STV7610A [STMICROELECTRONICS]
PLASMA DISPLAY PANEL DATA DRIVER; 等离子显示面板的数据驱动器![STV7610A](http://pdffile.icpdf.com/pdf1/p00064/img/icpdf/STV7610_338304_icpdf.jpg)
型号: | STV7610A |
厂家: | ![]() |
描述: | PLASMA DISPLAY PANEL DATA DRIVER |
文件: | 总17页 (文件大小:144K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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STV7610A
PLASMA DISPLAY PANEL DATA DRIVER
FEATURE
■ 96 OUTPUTS PLASMA DISPLAY DRIVER
■ 100 V ABSOLUTE MAXIMUM SUPPLY
■ 5 V SUPPLY FOR LOGIC
■ 60/50 mA SOURCE/SINK OUTPUT MOS
■ 60/50 mA SOURCE/SINK OUTPUT DIODE
■ 6 bit CASCADABLE DATA BUS (20 MHz)
■ BLANK, POLARITY CONTROL
■ BCD TECHNOLOGY
■ PACKAGING TQFP144 OR DICE
DIE
ORDER CODE: STV7610A/WAF(1)
(1): Unsawn tested wafer
DESCRIPTION
The STV7610A is a BCD data driver for Plasma
Display Panel (PDP). Using a 6-bit wide cascada-
ble data bus, it addresses 96 high current & high
voltage outputs. By serially connecting several
STV7610A, any horizontal pixel definition can be
performed. The 20 MHz shift clock gives an equiv-
alent 120 MHz shift register. The STV7610A is
supplied with a separated 90 V power output sup-
ply and a 5 V logic supply. All command inputs are
CMOS compatible.
TQFP144 (20 x 20 x 1.4 mm)
(Thin Plastic Quad Flat Pack)
ORDER CODE: STV7610A
Version 4.2
June 2000
1/17
This is preliminary information on a new product in development or undergoing evaluation. Details are subject to change without notice.
1
STV7610A
PIN CONNECTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
PIN CONNECTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
PIN LIST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
PAD COORDINATES (IN MM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
CIRCUIT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
NOTE 1 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
NOTE 4 THERMAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
NOTE 4 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
NOTE 5 AC TIMINGS REQUIREMENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
NOTE 5 AC TIMINGS CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
FIGURE 2. INPUT/OUTPUT SCHEMATICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
FIGURE 6. PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2/16
2
STV7610A
PIN CONNECTIONS
(DIE Pinout)
VSSP
VPP
VSSP
VPP
VPP
VPP
OUT64
OUT65
OUT66
OUT67
OUT68
OUT69
OUT70
OUT71
OUT72
OUT73
OUT74
OUT75
OUT76
OUT77
OUT78
OUT79
OUT80
OUT81
OUT82
OUT83
OUT84
OUT85
OUT86
OUT87
OUT88
OUT89
OUT90
OUT91
OUT92
OUT93
OUT94
OUT95
OUT96
OUT33
OUT32
OUT31
OUT30
OUT29
OUT28
OUT27
OUT26
OUT25
OUT24
OUT23
OUT22
OUT21
OUT20
OUT19
OUT18
OUT17
OUT16
OUT15
OUT14
OUT13
OUT12
OUT11
OUT10
OUT9
OUT8
OUT7
OUT6
OUT5
OUT4
OUT3
OUT2
OUT1
STV7610A
Bare Die
Y
(0,0)
X
3/17
3
STV7610A
PIN CONNECTIONS
(TQFP Pinout)
VPP
VPP
1
108
107
106
105
104
103
102
101
100
99
VPP
2
VPP
NC
3
NC
OUT64
OUT65
OUT66
OUT67
OUT68
OUT69
OUT70
OUT71
OUT72
OUT73
OUT74
OUT75
OUT76
OUT77
OUT78
OUT79
OUT80
OUT81
OUT82
OUT83
OUT84
OUT85
OUT86
OUT87
OUT88
OUT89
OUT90
OUT91
OUT92
OUT93
OUT94
OUT95
OUT96
4
OUT33
OUT32
OUT31
OUT30
OUT29
OUT28
OUT27
OUT26
OUT25
OUT24
OUT23
OUT22
OUT21
OUT20
OUT19
OUT18
OUT17
OUT16
OUT15
OUT14
OUT13
OUT12
OUT11
OUT10
OUT9
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
98
97
96
95
94
93
92
STV7610A
TQFP144
91
90
89
88
87
86
85
84
83
82
81
80
OUT8
79
OUT7
78
OUT6
77
OUT5
76
OUT4
75
OUT3
74
OUT2
73
OUT1
4/17
3
STV7610A
PIN LIST
(TQFP144)
Pin N°
Symbol
Type
Description
3-37-38-39-41-43-48-65-67-69-
70-71-72-106-110-111-142-143
NC
-
1-2-42-66-107-108
V
Supply
Ground
Ground
Ground
Output
Output
Input
High Voltage Supply of Power Outputs
5V Logic Supply
PP
53
40-68-109-144
54
V
CC
V
Ground of Power Outputs
Logic Ground
SSP
V
SSLOG
SSSUB
55
V
Substrate Ground
73 to 105
112 to 141
4 to 36
50
OUT 1 to OUT 33
OUT 34 to OUT 63
OUT 64 to OUT 96
BLK
Power Output
Power Output
Input
Power Output
Input
Blanking Input
51
POL
Input
Polarity Input
52
FOR/ REV
CLK
Input
Selection of Shift Direction
Clock of data Shift Register
Latch of data to Outputs
56
Input
57
STB
Input
59 to 64
44 to 49
A1 to A6
Input/Output Forward Shift Register Input
Input/Output Forward Shift Register Output
B6 to B1
PIN LIST
(Power outputs)
Output N°
Pin N°
Output N°
Pin N°
Output N°
Pin N°
Output N°
Pin N°
1
2
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
97
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
98
3
99
4
100
101
102
103
104
105
112
113
114
115
116
117
5
6
7
8
9
10
11
12
13
14
15
5/17
3
STV7610A
Output N°
Pin N°
Output N°
Pin N°
Output N°
Pin N°
Output N°
Pin N°
16
17
18
19
20
21
22
23
24
88
89
90
91
92
93
94
95
96
40
41
42
43
44
45
46
47
48
118
119
120
121
122
123
124
125
126
64
65
66
67
68
69
70
71
72
4
5
88
89
90
91
92
93
94
95
96
28
29
30
31
32
33
34
35
36
6
7
8
9
10
11
12
PAD COORDINATES (in ΜM)
Pad positions from the middle of the top side
Center
Size
Name
Center
Size
X
Y
X
Y
Name
X
Y
X
Y
OUT 33 2117.0
OUT 32 2117.0
OUT 31 2117.0
OUT 30 2117.0
OUT 29 2117.0
OUT 28 2117.0
OUT 27 2117.0
OUT 26 2117.0
OUT 25 2117.0
OUT 24 2117.0
OUT 23 2117.0
OUT 22 2117.0
OUT 21 2117.0
OUT 20 2117.0
OUT 19 2117.0
OUT 18 2117.0
OUT 17 2117.0
OUT 16 2117.0
OUT 15 2117.0
OUT 14 2117.0
OUT 13 2117.0
OUT 12 2117.0
OUT 11 2117.0
1580.0
1444.0
1308.0
1172.0
1036.0
900.0
90.0
90.0
90.0
90.0
90.0
90.0
90.0
90.0
90.0
90.0
90.0
90.0
90.0
90.0
90.0
90.0
90.0
90.0
90.0
90.0
90.0
90.0
90.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
OUT 48
OUT 47
OUT 46
OUT 45
OUT 44
OUT 43
OUT 42
OUT 41
OUT 40
OUT 39
OUT 38
OUT 37
OUT 36
OUT 35
OUT 34
74.0
3034.0
3034.0
3034.0
3034.0
3034.0
3034.0
3034.0
3034.0
3034.0
3034.0
3034.0
3034.0
3034.0
3034.0
3034.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
90.0
90.0
90.0
90.0
90.0
90.0
90.0
90.0
90.0
90.0
90.0
90.0
90.0
90.0
90.0
210.0
346.0
482.0
618.0
754.0
764.0
890.0
628.0
1026.0
1162.0
1298.0
1434.0
1570.0
1706.0
1842.0
1993.0
492.0
356.0
220.0
84.0
2117.0
2117.0
-324.0
-460.0
-596.0
-732.0
-868.0
-1004.0
-1140.0
-1276.0
-1412.0
Pad positions along the right side
Center
Name
Size
X
Y
X
Y
V
2116.0
2029.8
2041.5
2795.0
2496.5
1843.0
90.0
90.0
90.0
80.0
90.0
80.0
SSP
V
PP
PP
V
6/17
3
STV7610A
Center
Size
Center
Size
Y
Name
Name
X
Y
X
Y
X
Y
X
OUT 10
OUT 9
OUT 8
OUT 7
OUT 6
OUT 5
OUT 4
OUT 3
OUT 2
OUT 1
2117.0
2117.0
2117.0
2117.0
2117.0
2117.0
2117.0
2117.0
2117.0
2117.0
-1548.0
-1684.0
-1820.0
-1956.0
-2092.0
-2228.0
-2364.0
-2500.0
-2636.0
-2832.0
90.0
90.0
90.0
90.0
90.0
90.0
90.0
90.0
90.0
90.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
A3
A2
1049.0
899.0
749.0
449.0
299.0
156.5
3.0
-3034.0
-3034.0
-3034.0
-3034.0
-3034.0
-3034.0
-3034.0
-3034.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
90.0
90.0
90.0
90.0
90.0
90.0
90.0
90.0
A1
STB
CLK
GNDsub
GND
V
-158.0
CC
F/R
POL
BLK
B1
-299.0
-449.0
-3034.0
-3034.0
-3034.0
-3034.0
-3034.0
-3034.0
-3034.0
-3034.0
-3034.0
-3034.0
-3034.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
90.0
90.0
90.0
90.0
90.0
90.0
90.0
90.0
90.0
90.0
90.0
-599.0
Pad positions along the bottom side
-749.0
Center
Name
Size
B2
-899.0
X
Y
X
Y
B3
-1049.0
-1199.0
-1349.0
-1499.0
-1698.0
-1904.0
V
1904.0
1698.0
1499.0
1349.0
1199.0
-3034.0
-3034.0
-3034.0
-3034.0
-3034.0
80.0
80.0
80.0
80.0
80.0
90.0
90.0
90.0
90.0
90.0
SSP
B4
V
PP
B5
A6
B6
A5
A4
V
PP
V
SSP
7/17
3
STV7610A
Pad Positions along the left side
Center
Size
Name
Center
Name
Size
X
Y
X
Y
X
Y
X
Y
OUT 69 -2117.0
OUT 68 -2117.0
OUT 67 -2117.0
OUT 66 -2117.0
OUT 65 -2117.0
OUT 64 -2117.0
900.0
90.0
90.0
90.0
90.0
90.0
90.0
90.0
90.0
90.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
OUT 96 -2117.0
OUT 95 -2117.0
OUT 94 -2117.0
OUT 93 -2117.0
OUT 92 -2117.0
OUT 91 -2117.0
OUT 90 -2117.0
OUT 89 -2117.0
OUT 88 -2117.0
OUT 87 -2117.0
OUT 86 -2117.0
OUT 85 -2117.0
OUT 84 -2117.0
OUT 83 -2117.0
OUT 82 -2117.0
OUT 81 -2117.0
OUT 80 -2117.0
OUT 79 -2117.0
OUT 78 -2117.0
OUT 77 -2117.0
OUT 76 -2117.0
OUT 75 -2117.0
OUT 74 -2117.0
OUT 73 -2117.0
OUT 72 -2117.0
OUT 71 -2117.0
OUT 70 -2117.0
-2832.0
-2636.0
-2500.0
-2364.0
-2228.0
-2092.0
-1956.0
-1820.0
-1684.0
-1548.0
-1412.0
-1276.0
-1140.0
-1004.0
-868.0
-732.0
-596.0
-460.0
-324.0
-188.0
-52.0
90.0
90.0
90.0
90.0
90.0
90.0
90.0
90.0
90.0
90.0
90.0
90.0
90.0
90.0
90.0
90.0
90.0
90.0
90.0
90.0
90.0
90.0
90.0
90.0
90.0
90.0
90.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
1036.0
1172.0
1308.0
1444.0
1580.0
1843.0
2496.5
2795.5
V
V
-2041.5
-2029.8
2116.0
PP
PP
V
SSP
Pad Positions along the top side
Center
Name
Size
X
Y
X
Y
OUT 63 -1980.0
OUT 62 -1830.0
OUT 61 -1694.0
OUT 60 -1558.0
OUT 59 -1422.0
OUT 58 -1286.0
OUT 57 -1150.0
OUT 56 -1014.0
3034.0
3034.0
3034.0
3034.0
3034.0
3034.0
3034.0
3034.0
3034.0
3034.0
3034.0
3034.0
3034.0
3034.0
3034.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
80.0
90.0
90.0
90.0
90.0
90.0
90.0
90.0
90.0
90.0
90.0
90.0
90.0
90.0
90.0
90.0
OUT 55
OUT 54
OUT 53
OUT 52
OUT 51
OUT 50
OUT 49
-878.0
-742.0
-606.0
-470.0
-334.0
-198.0
-62.0
84.0
220.0
356.0
492.0
628.0
764.0
8/17
3
STV7610A
BLOCK DIAGRAM
CLK
56
FOR/REV
52
VCC
16-BIT SHIFT REGISTER
P1
P91
59
60
61
62
49
A1
A2
A3
A4
B1
B2
B3
B4
16-BIT SHIFT REGISTER
P2
P92
48
47
46
16-BIT SHIFT REGISTER
P3
P93
16-BIT SHIFT REGISTER
P4
P94
16-BIT SHIFT REGISTER
P5
P95
63
64
45
44
A5
A6
B5
B6
16-BIT SHIFT REGISTER
P6
P96
54
55
P1
P6
P95P96
Q95Q96
VSSLOG
VSSSUB
57
50
51
LATCH
STB
POL
BLK
Q1Q2
VCC
VCC
53
VCC
VSSP
LOGIC
Pins 40-68-109-144
VPP
Pins 1-2-42-66-107-108
STV7610A
73
36
OUT1
OUT96
9/17
3
STV7610A
CIRCUIT DESCRIPTION
The STV7610A contains all the logic and the pow-
er circuits necessary to drive the columns of a
Plasma Display Panel (P. D. P.). The binary value
of each pixel of the displayed line is loaded into the
shift register. Data are input in a 6-bit wide data
bus to A1 - A6 input (case of forward shift mode).
Data are shifted at each low to high transition of
the CLK shift clock. After 16 shifts the first data are
available on B1 - B6 outputs. These B1 - B6 out-
puts can be used to cascade several drivers to
perform any horizontal resolution. The forward/
reverse (FOR/REV ) input is used to select the
direction of the shift register, A1 - A6 and B1 - B6
data bus input/output status is set according to the
selected direction. FOR/REV = H, A is an input
and B is an output.
V
and V
must be connected as close
SSLOG
SSSUB
as possible to the logical reference ground of the
application.
Shift Register Truth Table
Shift Register
Input
Input/Outp ut
Function
FOR/ REV CLK
A
IN
IN
B
Output Q
H
H
L
Rise
OUT Forward shift
OUT Steady
H or L
Rise OUT
H or L OUT
IN
IN
Reverse shift
Steady
L
Power Output Truth Table
POL
Serial inputs, CLK, STB inputs are Smith trigger in-
puts. If not used in the application, Blanking
Driver
Output
Qn
STB BLK
Comments
POL
(BLK ), Polarity (
are internaly pulled to level
”H”. The maximum frequency of the shift clock is
20 MHz. This leads to an equivalent 120 MHz se-
rial shift register.
X
X
X
L
X
X
H
L
L
X
L
L
H
Output low
H
H
H
H
Output high
Data latched
Data copied
Data copied
On low level of STB, data is transferred from shift
register to the latch stage. Data will not be re-
freshed as long as STB is kept high.
H
H
H
Qn
L
Blanking input (BLK ) forces the power outputs to
low level when pulled low. All the power outputs
are set at high level when the Polarity command
H
L
H
Note 1 Qn+1 = A1, Qn + 2 = A2, Qn + 3 = A3, Qn + 4 =
POL
is at high level.
(
) is pulled low and the Blanking (BLK ) input
A4, Qn + 5 = A5, Qn + 6 = A6, n = [0,6,12,18,...,90]
10/17
3
STV7610A
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
V
Logic Supply Range (Pin 53)
-0.3, +7
V
V
CC
OUTi
VIN
Output Pins (4 to 36, 73 to 105, 112 to 141)
Logic Input Voltage (Pins 50, 51, 52, 56, 57, 59 to 64)
Logic Output Voltage (Pin 44 to 49)
Driver Output Current ( Note 2) ( Note 4)
Diode Output Current ( Note 3) ( Note 4)
Junction Temperature
-0.3, +100
-0.3, +V +0.3
V
CC
-0.3, +V + 0.3
VOUT
V
CC
I
-60/ +50
-50/ +60
+150
mA
mA
°C
°C
°C
POUT
I
DOUT
Tj
Toper
Tstg
Operating Temperature
-20, +85
-50, +150
Storage Temperature
Note 2 Through one power output (all power outputs).
Note 3 Through one power output for all power outputs (see Test Diagram) with Junction temperature lower or equal than
Tjmax.
Note 4 These parameters are measured during ST’s internal qualification which includes temperature characterisation
on standard batches and on corners batches of the process. These parameters are not tested on the parts.
THERMAL DATA
Symbol
Parameter
Value
Unit
Rth(j-a)
Junction-ambient Thermal Resistance
Typ.
41
°C/W
11/17
3
STV7610A
ELECTRICAL CHARACTERISTICS
(V
= 5 V, V = 90 V, V
= 0 V, V
= 0 V, V
= 0 V, T
= 25°C, f
= 20 MHz, unless
CLK
CC
PP
SSP
SSLOG
SSSUB
amb
otherwise specified)
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
SUPPLY
V
Logic Supply Voltage
4.5
5
-
5.5
100
-
V
µA
mA
V
CC
I
Logic Supply Current (all inputs high)
Logic Dynamic Supply Current
Power Output Supply Voltage
-
-
CCH
I
f
= 20 MHz
26
-
CCL
CLK
V
15
-
90
PP
Power Output Supply Current
(steady outputs)
-
100
µA
I
PPH
OUTPUT (V = 15 V to 90 V)
PP
OUT 1- OUT 96
Power Output Voltage Drop
(High Level) (versus V
I
= - 30 mA
= - 45mA
-
-
4.0
4.5
6.0
6.5
V
V
POUTH
V
POUTH
)
I
PP
POUTH
Power Output Voltage Drop
(Low Level)
V
V
I
= + 30 mA
-
1.6
4
V
POUTL
POUTL
Output Diode Voltage (High Level)
Output Diode Low Level
I
= +45 mA ( Note 5)
= - 30mA ( Note 5)
-
-
1.05
4
V
V
DOUTH
DOUTH
V
I
-0.95
-4
DOUTL
DOUTL
A1-A6, B1-B6
V
Logic Output (High Level)
Logic Output (Low Level)
I
= -1 mA
4
-
4.2
-
V
V
OH
OH
V
I
= +1 mA
0.12
0.4
OL
OL
INPUT
CLK, FOR/ REV , STB, POL , BLK , A1-A6, B1-B6
V
0.8 V
Input Voltage (High Level)
Input Voltage (Low Level)
High Level Input Current
-
-
-
-
V
V
IH
CC
V
I
0.2V
-
-
IL
CC
V
V
= V
10
µA
IH
IH
IL
CC
I
Low Level Input Current
CLK, A1-A6, B1-B6, STB,
FOR/ REV , BLK , POL
= 0 V
IL
-
-
-
-
-10
-40
µA
µA
Note 5 See test diagram page 14.
12/17
3
STV7610A
AC TIMINGS REQUIREMENTS
(V = 4.5 V to 5.5 V, T
= -20 to +85°C, input signals max leading edge & trailing edge (t , t ) = 10 ns)
R F
CC
amb
Symbol
Parameter
Min.
Typ.
Max.
Unit
t
Duration of clock (CLK) pulse at high level
15
15
10
10
-
-
-
-
-
-
-
-
ns
ns
ns
ns
WHCLK
t
Duration of clock (CLK) pulse at low level
WLCLK
t
Set-up Time of data input before clock (low to high) transition
Hold Time of data input after clock (low to high) transition
SDAT
t
HDAT
Forward/ reverse (FOR/ REV ) Set-up Time before clock (low to
high) transition
t
100
SFR
t
Minimum Delay to latch (STB) after clock (low to high) transition
Minimum Delay to latch (STB) before clock (low to high) transition
Latch (STB) Low Level Pulse Duration
10
10
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
DSTB
t
SSTB
t
20
STB
t
Blanking (BLK) Pulse Duration
500
500
BLK
t
Polarity (POL) Pulse Duration
POL
AC TIMINGS CHARACTERISTICS
(V = 5 V, V = 90 V V
= 0 V, V
= 0 V, V
= 0 V, T
= 25°C)
CC
PP
,
SPP
SSLOG
SSSUB
amb
(V
= 0.2 Vcc, V
= 0.8 V , V = 4.0V, V = 0.4 V, unless otherwise specified)
IL(Max.)
IH(Min.) CC OH OL
Symbol
Parameter
Min. Typ. Max. Unit
t
Data clock Period
50
-
-
-
ns
ns
ns
CLK
t
Logical Data Output Rise Time (CL=10pF)
Logical Data Output Fall Time (CL=10pF)
12
11
20
20
RDAT
t
-
FDAT
t
t
Delay of logic data output (high to low transition) after clock (CLK) transition
Delay of logic data output (low to high transition) after clock (CLK) transition
-
-
30
30
50
50
ns
ns
PHL1
PLH1
t
t
Delay of power output change (high to low transition) after clock (CLK) transition
Delay of power output change (low to high transition) after clock (CLK) transition
-
-
135 180 ns
80 180 ns
PHL2
PLH2
t
t
Delay of power output change (high to low transition) after Latch (STB) transition
Delay of power output change (low to high transition) after Latch (STB) transition
-
-
115 165 ns
70 165 ns
PHL3
PLH3
t
t
PHL4
PLH4
Delay of power output change (high to low transition) to Blank or Polarity
( BLK , POL ) transition
Delay of power output change (low to high transition) to Blank or Polarity
( BLK , POL ) transition
-
-
100 160 ns
55 160 ns
t
Power Output Rise Time ( Note 6)
Power Output Fall Time ( Note 6)
-
-
50 150 ns
80 200 ns
ROUT
t
FOUT
Note 6 One output among 96, loading capacitor C = 50pF, other outputs at low level.
L
13/17
3
STV7610A
Figure 1. : AC Characteristics Waveform
t
CLK
t
t
WHCLK
WLCLK
“1”
“0”
“1”
50%
CLK
50%
50%
t
HDAT
t
SDAT
50%
50%
A INPUT
“0”
“1”
t
t
FDAT
PHL1
90%
90%
10%
B OUTPUT
10%
“0”
t
RDAT
t
PLH1
t
t
STB
DSTB
“1”
“0”
STB
50%
50%
t
SSTB
t
SFR
“1”
“0”
“1”
F/R
t
t
PHL3
PHL2
90%
90%
10%
OUTn
10%
“0”
“1”
t
t
PLH2
PLH3
t
BLK
(POL=#0#)
50%
50%
BLK
“0”
“1”
t
t
PHL4
PLH4
OUTn
90%
90%
10%
10%
“0”
t
t
F OUT
R OUT
14/17
3
STV7610A
Figure 2. : Test Configuration
VPP=V
VPP=VSSP
SSP
VDOUTH
IDOUTH
VDOUTL
IDOUTL
VSSP
VSSP
Output sinking current as positive value, sourcing current as negative value
INPUT/OUTPUT SCHEMATICS
Figure 3. : POL , BLK , F/ R Input
Figure 5. : A1 to A6, B1 to B6
VCC
VCC
VCC
A1 to A6,
B1 to B6
VCC
Pins 59 to 64,
49 to 44
VCC
POL, BLK, F/R
Pins 51, 50, 52
GNDLOG
GNDLOG
GNDSUB
GNDSUB
Figure 4. : CLK, STB Input
Figure 6. : Power Output
VCC
VPP
VCC
CLK, STB
Pins 56, 57
OUT1 to OUT 96
Pins 73 to 105,
112 to 141, 4 to 36
GNDLOG
VSSP
GNDSUB
15/17
3
STV7610A
PACKAGE MECHANICAL DATA
144 PINS - THIN PLASTIC QUAD FLAT PACK (TQFP)
A
A2
A1
e
144
109
0,076 mm
0.03 inch
SEATING PLANE
1
108
36
73
37
72
D3
D1
D
0,25 mm
.010 inch
GAGE PLANE
K
Millimeters
Dimensions
Inches
Typ.
Min.
Typ.
Max.
1.60
0.15
1.45
0.27
0.20
Min.
Max.
0.063
0.006
0.057
0.011
0.008
A
A1
A2
B
0.05
1.35
0.17
0.09
0.002
0.053
1.40
0.22
0.055
0.0067
0.0035
0.0087
C
D
22.00
20.00
17.50
0.50
0.866
0.787
0.689
0.020
0.866
0.787
0.689
0.024
0.039
D1
D3
e
E
22.00
20.00
17.50
0.60
E1
E3
L
0.45
0.75
0.018
0.030
L1
K
1.00
0° (Min.), 7° (Max.)
16/17
STV7610A
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no respon-
sibility for the consequences of use of such information nor for any infringement of patents or other rights of
third parties which may result from its use. No license is granted by implication or otherwise under any patent
or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change with-
out notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics
products are not authorized for use as critical components in life support devices or systems without express
written approval of STMicroelectronics.
The ST logo is a trademark of STMicroelectronics.
2000 STMicroelectronics - All Rights Reserved
2
2
Purchase of I C Components of STMicroelectronics, conveys a license under the Philips I C Patent.
2
2
Rights to use these components in a I C system, is granted provided that the system conforms to the I C Stan-
dard Specifications as defined by Philips.
STMicroelectronics GROUP OF COMPANIES
Australia - Brazil - China - Finland - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Mexico - Morocco - The
Netherlands - Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A.
http://www .st.com
17/17
4
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