VNH5019A-E [STMICROELECTRONICS]
Automotive fully integrated H-bridge motor driver; 汽车完全集成H桥电机驱动器
| 型号： | VNH5019A-E |
| 厂家： | 
ST |
| 描述： | Automotive fully integrated H-bridge motor driver |
| 文件： | 总37页 (文件大小：514K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
VNH5019A-E
Automotive fully integrated
H-bridge motor driver
Features
Type
RDS(on)
Iout
Vccmax
MultiPowerSO-30™
18 mΩ typ
(per leg)
VNH5019A-E
30 A
41 V
Power MOSFET with an intelligent
signal/protection circuit.
■ ECOPACK®: lead free and RoHS compliant
The three dice are assembled in
MultiPowerSO-30 package on electrically isolated
lead-frames. This package, specifically designed
for the harsh automotive environment offers
improved thermal performance thanks to exposed
die pads. The input signals INA and INB can
directly interface to the microcontroller to select
the motor direction and the brake condition.
■ Automotive Grade: compliance with AEC
guidelines
■ Output current: 30 A
■ 3 V CMOS compatible inputs
■ Undervoltage and overvoltage shutdown
■ High-side and low-side thermal shutdown
■ Cross-conduction protection
■ Current limitation
The DIAGA/ENA or DIAGB/ENB, when connected
to an external pull-up resistor, enable one leg of
the bridge. They also provide a feedback digital
diagnostic signal. The CS pin allows to monitor
the motor current by delivering a current
proportional to its value when CS_DIS pin is
driven low or left open. The PWM, up to 20 KHz,
lets us to control the speed of the motor in all
possible conditions. In all cases, a low-level state
on the PWM pin turns-off both the LSA and LSB
switches. When PWM rises to a high-level, LSA or
LSB turn-on again depending on the input pin
state.
■ Very low standby power consumption
■ PWM operation up to 20 khz
■ Protection against:
– Loss of ground and loss of VCC
■ Current sense output proportional to motor
current
■ Charge pump output for reverse polarity
protection
■ Output protected against short to ground and
Output current limitation and thermal shutdown
protects the concerned high-side in short to
ground condition.
short to VCC
Description
The short to battery condition is revealed by the
overload detector or by thermal shutdown that
latches off the relevant low-side.
The VHN5019A-E is a full bridge motor driver
intended for a wide range of automotive
applications. The device incorporates a dual
monolithic high-side drivers and two low-side
switches. The high-side driver switch is designed
using STMicroelectronics’ well known and proven
proprietary VIPower® M0 technology that allows
to efficiently integrate on the same die a true
Active VCC pin voltage clamp protects the device
against low energy spikes in all configurations for
the motor.
CP pin provides the necessary gate drive for an
external n-channel PowerMOS used for reverse
polarity protection.
December 2011
Doc ID 15701 Rev 8
1/37
www.st.com
1
Contents
VNH5019A-E
Contents
1
2
Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.1
2.2
2.3
2.4
2.5
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Waveforms and truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Reverse battery protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3
4
Package and PCB thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.1
MultiPowerSO-30 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.1.1
Thermal calculation in clockwise and anti-clockwise operation in
steady-state mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.1.2
Thermal calculation in transient mode . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
®
4.1
4.2
4.3
4.4
ECOPACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
MultiPowerSO-30 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
MultiPowerSO-30 suggested land pattern . . . . . . . . . . . . . . . . . . . . . . . . 32
MultiPowerSO-30 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
5
6
Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
2/37
Doc ID 15701 Rev 8
VNH5019A-E
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Suggested connections for unused and not connected pins . . . . . . . . . . . . . . . . . . . . . . . . 6
Pin definitions and functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Block descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Absolute maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Logic inputs (INA, INB, ENA, ENB,PWM, CS_DIS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Switching (VCC = 13 V, RLOAD = 0.87 W, Tj = 25 °C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Protection and diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Current sense (8 V < VCC < 21 V). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Charge pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Truth table in normal operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Truth table in fault conditions (detected on OUTA). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Electrical transient requirements (part 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Electrical transient requirements (part 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Electrical transient requirements (part 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Thermal calculation in clockwise and anti-clockwise operation in steady-state mode . . . . 27
Thermal parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
MultiPowerSO-30 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Doc ID 15701 Rev 8
3/37
List of figures
VNH5019A-E
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Typical application circuit for DC to 20 kHz PWM operation with reverse battery protection
(option A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Typical application circuit for DC to 20 kHz PWM operation with reverse battery protection
(option B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Behavior in fault condition (how a fault can be cleared) . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Definition of the delay times measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Definition of the low-side switching times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Definition of the high-side switching times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10. Definition of dynamic cross conduction current during a PWM operation. . . . . . . . . . . . . . 21
Figure 11. Waveforms in full bridge operation (part 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 12. Waveforms in full bridge operation (part 2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 13. Definition of delay response time of sense current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 14. Half-bridge configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 15. Multi-motors configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 16. MultiPowerSO-30™ PC board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 17. Chipset configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 18. Auto and mutual Rthj-amb vs PCB copper area in open box free air condition . . . . . . . . . 26
Figure 19. Chipset configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 20. MultiPowerSO-30 HSD thermal impedance junction ambient single pulse . . . . . . . . . . . . 28
Figure 21. MultiPowerSO-30 LSD thermal impedance junction ambient single pulse. . . . . . . . . . . . . 28
Figure 22. Thermal fitting model of an H-bridge in MultiPowerSO-30 . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 23. MultiPowerSO-30 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 24. MultiPowerSO-30 suggested pad layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 25. MultiPowerSO-30 tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 26. MultiPowerSO-30 tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
4/37
Doc ID 15701 Rev 8
VNH5019A-E
Block diagram and pin description
1
Block diagram and pin description
Figure 1.
Block diagram
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Doc ID 15701 Rev 8
5/37
Block diagram and pin description
Figure 2. Configuration diagram (top view)
VNH5019A-E
1
30
OUTA
OUTA
N.C.
VCC
INA
N.C.
GNDA
GNDA
OUTA
Heat Slug2
ENA/DIAGA
CS_DIS
PWM
GNDA
OUTA
N.C.
VCC
Heat Slug1
CS
VCC
ENB/DIAGB
INB
N.C.
OUTB
CP
VBAT
GNDB
GNDB
GNDB
N.C.
OUTB
Heat Slug3
VCC
N.C.
15
16
OUTB
OUTB
Table 1.
Suggested connections for unused and not connected pins
INPUTx, PWM
Connection / pin
Current sense
N.C.
OUTx
DIAGx/ENx
CS_DIS
Floating
Not allowed
X
X
X
X
Through 10 kΩ
To ground
Through 1 kΩ resistor
Not allowed
resistor
Table 2.
Pin
Pin definitions and functions
Symbol
Function
OUTA,
Heat Slug2
Source of high-side switch A / drain of low-side switch A, power
connection to the motor
1, 25, 30
2,14,17, 22,
24,29
N.C.
Not connected
VCC
Heat Slug1
,
Drain of high-side switches and connection to the drain of the
external PowerMOS used for the reverse battery protection
3, 13, 23
12
Battery connection and connection to the source of the external
PowerMOS used for the reverse battery protection
VBAT
Status of high-side and low-side switches A; open drain output.
This pin must be connected to an external pull-up resistor. When
externally pulled low, it disables half-bridge A. In case of fault
detection (thermal shutdown of a high-side FET or excessive
ON-state voltage drop across a low-side FET), this pin is pulled
low by the device (see Table 13: Truth table in fault conditions
(detected on OUTA))
5
ENA/DIAGA
6/37
Doc ID 15701 Rev 8
VNH5019A-E
Block diagram and pin description
Pin definitions and functions (continued)
Table 2.
Pin
Symbol
Function
Active high CMOS compatible pin to disable the current sense
pin
6
CS_DIS
4
7
INA
Clockwise input. CMOS compatible
PWM input. CMOS compatible.
PWM
Output of current sense. This output delivers a current
proportional to the motor current, if CS_DIS is low or left open.
The information can be read back as an analog voltage across
an external resistor.
8
CS
Status of high-side and low-side switches B; Open drain output.
This pin must be connected to an external pull up resistor. When
externally pulled low, it disables half-bridge B. In case of fault
detection (thermal shutdown of a high-side FET or excessive
ON-state voltage drop across a low-side FET), this pin is pulled
low by the device (see Table 13: Truth table in fault conditions
(detected on OUTA).
9
ENB/DIAGB
10
11
INB
CP
Counter clockwise input. CMOS compatible
Connection to the gate of the external MOS used for the reverse
battery protection
OUTB,
Heat Slug3
Source of high-side switch B / drain of low-side switch B, power
connection to the motor
15, 16, 21
26, 27, 28
18, 19, 20
GNDA
GNDB
Source of low-side switch A and power ground(1)
Source of low-side switch B and power ground(1)
1. GNDA and GNDB must be externally connected together
)
Table 3.
Block descriptions(1)
Name
Description
Allows the turn-on and the turn-off of the high-side and the
low-side switches according to the Table 12.
Logic control
Shut down the device outside the range [4.5 V to 24 V] for the
battery voltage.
Overvoltage + undervoltage
High-side, low-side and clamp
voltage
Protect the high-side and the low-side switches from the
high-voltage on the battery line in all configuration for the motor.
Drive the gate of the concerned switch to allow a proper RDS(on)
for the leg of the bridge.
High-side and low-side driver
Linear current limiter
Limits the motor current, by reducing the high-side switch
gate-source voltage when short-circuit to ground occurs.
In case of short-circuit with the increase of the junction’s
temperature, it shuts down the concerned driver to prevent its
degradation and to protect the die.
High-side and low-side
overtemperature protection
Detects when low-side current exceeds shutdown current and
latches off the concerned low-side.
Low-side overload detector
Doc ID 15701 Rev 8
7/37
Block diagram and pin description
VNH5019A-E
Table 3.
Block descriptions(1) (continued)
Name
Description
Provides the voltage necessary to drive the gate of the external
PowerMOS used for the reverse polarity protection
Charge pump
Fault detection
Signalizes an abnormal condition of the switch (output
shorted to ground or output shorted to battery) by pulling
down the concerned ENx/DIAGx pin.
Limits the power dissipation of the high-side driver inside
safe range in case of short to ground condition.
Power limitation
1. See Figure 1
8/37
Doc ID 15701 Rev 8
VNH5019A-E
Electrical specifications
2
Electrical specifications
Figure 3.
Current and voltage conventions
ICP
IBAT
IS
VCP
VBAT
VCC
IINA
VCC
OUTA
CP
VBAT
IOUTA
INA
INB
IINB
VINA
IOUTB
OUTB
CS
VOUTA
IENA
VINB
ISENSE
ICSD
DIAGA/ENA
VOUTB
IENB
CS_DIS
VSENSE
DIAGB/ENB
PWM
VENA
VCSD
GNDA
GNDB
VENB
Ipw
GND
IGND
Vpw
2.1
Absolute maximum ratings
Stressing the device above the rating listed in the “absolute maximum ratings” table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the operating sections of
this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability. Refer also to the STMicroelectronics SURE
program and other relevant quality document.
Table 4.
Symbol
Absolute maximum rating
Parameter
Value
Unit
-16
V
V
VBAT
Maximum battery voltage(1)
+41
VCC
Imax
IR
Maximum bridge supply voltage
Maximum output current (continuous)
Reverse output current (continuous)
Input current (INA and INB pins)
Enable input current (DIAGA/ENA and DIAGB/ENB pins)
PWM input current
+ 41
30
V
A
-30
A
IIN
+/- 10
+/- 10
+/- 10
+/- 10
+/- 10
mA
mA
mA
mA
mA
IEN
Ipw
ICP
CP output current
ICS_DIS CS_DIS input current
Doc ID 15701 Rev 8
9/37
Electrical specifications
VNH5019A-E
Unit
Table 4.
Symbol
Absolute maximum rating (continued)
Parameter
Value
VCC - 41
+VCC
V
V
VCS
Current sense maximum voltage
Electrostatic discharge (human body model: R = 1.5 kΩ,
C = 100 pF)
VESD
2
kV
Tc
Case operating temperature
Storage temperature
-40 to 150
-55 to 150
°C
°C
TSTG
1. This applies with the n-channel MOSFET used for the reverse battery protection. Otherwise V
has to be
BAT
shorted to V
.
CC
2.2
Thermal data
Table 5.
Symbol
Thermal data
Parameter
Max. value
Unit
Thermal resistance junction-case HSD
Thermal resistance junction-case LSD
1.7
3.2
°C/W
°C/W
°C/W
Rthj-case
Rthj-amb Thermal resistance junction-ambient
See Figure 18
10/37
Doc ID 15701 Rev 8
VNH5019A-E
Electrical specifications
2.3
Electrical characteristics
Values specified in this section are for 8 V < VCC < 21 V, -40 °C < Tj < 150 °C, unless
otherwise specified.
Table 6.
Symbol
Power section
Parameter
Test conditions
Min.
Typ.
Max. Unit
Operating bridge supply
voltage
VCC
5.5
24
V
OFF-state with all fault cleared and ENx = 0 V
(standby):
INA = INB = PWM = 0; Tj = 25 °C; VCC = 13 V
INA = INB = PWM = 0
10
15
60
µA
µA
OFF-state (no standby):
IS
Supply current
INA = INB = PWM = 0; ENx = 5 V
6
mA
ON-state:
INA or INB = 5 V, no PWM
INA or INB = 5 V, PWM = 20 kHz
4
8
8
mA
mA
I
OUT = 15 A; Tj = 25 °C
12.0
Static high-side
resistance
RONHS
mΩ
mΩ
IOUT = 15 A; Tj = - 40 °C to 150 °C
IOUT = 15 A; Tj = 25 °C
26.5
6.0
0.6
Static low-side
resistance
RONLS
IOUT = 15 A; Tj = - 40 °C to 150 °C
11.5
0.8
High-side
free-wheeling diode
forward voltage
If = 15 A,
Tj = 150 °C
Vf
V
High-side OFF-state
output current (per
channel)
Tj = 25 °C; VOUTX = ENX = 0 V; VCC = 13 V
Tj = 125 °C; VOUTX = ENX = 0 V; VCC = 13 V
3
5
IL(off)
µA
Table 7.
Symbol
Logic inputs (INA, INB, ENA, ENB,PWM, CS_DIS)
Parameter
Test conditions
Min.
Typ.
Max. Unit
Normal operation (DIAGX/ENX pin
acts as an input pin)
VIL
Low-level input voltage
0.9
V
High-level input
voltage
Normal operation (DIAGX/ENX pin
acts as an input pin)
VIH
IINL
IINH
2.1
1
V
Low-level input current VIN = 0.9 V
High-level input
µA
µA
VIN = 2.1 V
10
current
Input hysteresis
voltage
Normal operation (DIAGX/ENX pin
acts as an input pin)
VIHYST
0.15
V
Doc ID 15701 Rev 8
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Electrical specifications
VNH5019A-E
Max. Unit
Table 7.
Symbol
Logic inputs (INA, INB, ENA, ENB,PWM, CS_DIS) (continued)
Parameter
Test conditions
IN = 1 mA
Min.
Typ.
I
5.5
6.3
7.5
V
-0.3
VICL
Input clamp voltage
IIN = -1 mA
-1.0
-0.7
Enable low-level
output voltage
Fault operation (DIAGX/ENX pin
acts as an output pin); IEN = 1 mA
VDIAG
0.4
V
Table 8.
Symbol
Switching (VCC = 13 V, RLOAD = 0.87 Ω, Tj = 25 °C)
Parameter
Test conditions
Min
Typ Max Unit
f
PWM frequency
0
20
kHz
µs
Input rise time < 1µs
(see Figure 9)
td(on)
HSD rise time
HSD fall time
250
Input rise time < 1µs
(see Figure 9)
td(off)
250
µs
tr
tf
LSD rise time
LSD fall time
(see Figure 8)
(see Figure 8)
1
1
2
2
µs
µs
Delay time during change of
operating mode
tDEL
trr
(see Figure 7)
(see Figure 10)
200
400 1600
µs
ns
A
High-side free wheeling
diode reverse recovery time
110
2
Dynamic cross-conduction
current
IOUT = 15 A
(see Figure 10)
IRM
Table 9.
Symbol
Protection and diagnostic
Parameter
Test conditions
Min Typ Max Unit
VCC undervoltage
shutdown
VUSD
4.5
0.5
5.5
V
V
VCC undervoltage
shutdown hysteresis
VUSDhyst
VOV
V
CC overvoltage shutdown
24
30
70
27
50
30
70
V
A
A
ILIM_H
ISD_LS
High-side current limitation
Low-side shutdown current
High-side clamp voltage
115 160
(1)
VCLPHS
IOUT = 15 A
43
48
30
54
33
V
(VCC to OUTA = 0 or
OUTB = 0)
Low-side clamp voltage
(1)
VCLPLS
IOUT = 15 A
VIN = 2.1 V
27
V
(OUTA = VCC or
OUTB = VCC to GND)
Thermal shutdown
temperature
(2)
TTSD
150
175 200
°C
12/37
Doc ID 15701 Rev 8
VNH5019A-E
Table 9.
Electrical specifications
Min Typ Max Unit
Protection and diagnostic (continued)
Symbol
Parameter
Test conditions
Low-side thermal
shutdown temperature
TTSD_LS
VIN = 0 V
150
175 200
°C
(3)
TTR
Thermal reset temperature
Thermal hysteresis
135
7
°C
°C
(3)
THYST
15
1. The device is able to pass the ESD and ISO pulse requirements as specified in the Table 15.
2. is the minimum threshold temperature between HS and LS
T
TSD
3. Valid for both HSD and LSD
Table 10. Current sense (8 V < VCC < 21 V)
Symbol
Parameter
Test conditions
Min
Typ
Max
Unit
IOUT = 3 A, VSENSE = 0.5 V,
Tj = - 40 °C to 150°C
K0
IOUT SENSE
/I
4670
7110 10110
19
Analog current sense ratio
drift
IOUT = 3 A; VSENSE = 0.5 V,
Tj = -40 °C to 150 °C
dK0/K0
K1
-19
6060
-14
%
IOUT = 8 A, VSENSE = 1.3V,
Tj = - 40 °C to 150°C
IOUT SENSE
/I
7030
6990
6940
8330
14
Analog current sense ratio
drift
IOUT = 8 A; VSENSE = 1.3V,
Tj = -40 °C to 150 °C
dK1/K1
K2
%
%
%
IOUT = 15 A, VSENSE = 2.4 V,
Tj = - 40 °C to 150°C
IOUT SENSE
/I
6070
-12
7810
12
Analog current sense ratio
drift
IOUT = 15 A; VSENSE = 2.4 V,
Tj = -40 °C to 150 °C
dK2/K2
K3
IOUT = 25 A, VSENSE = 4 V,
Tj = - 40 °C to 150°C
IOUT SENSE
/I
6000
-12
7650
12
Analog current sense ratio
drift
IOUT =25 A; VSENSE = 4 V,
Tj = -40 °C to 150 °C
dK3/K3
VSENSE
Max analog sense output
voltage
IOUT = 15 A, RSENSE = 1.1 kΩ
5
V
IOUT = 0 A, VSENSE = 0 V, VCSD = 5 V,
VIN = 0 V,
Tj = - 40 to 150°C
0
0
5
ISENSEO Analog sense leakage current
µA
IOUT = 0 A, VSENSE = 0 V, VCSD = 0 V,
VIN = 5 V,
Tj = - 40 to 150°C
100
50
VIN = 5 V, VSENSE < 4 V, IOUT = 8 A,
ISENSE = 90% of ISENSEmax
(see fig Figure 13)
Delay response time from
tDSENSEH
µs
µs
falling edge of CS_DIS pin
VIN = 5 V, VSENSE < 4 V, IOUT = 8 A,
Delay response time from
tDSENSEL
ISENSE = 10% of ISENSEmax
20
rising edge of CS_DIS pin
(see fig Figure 13)
Doc ID 15701 Rev 8
13/37
Electrical specifications
VNH5019A-E
Table 11. Charge pump
Symbol
Parameter
Test conditions
ENX = 5 V
Min
Typ
Max
Unit
VCC + 5
VCC + 10
Charge pump output
voltage
VCP
V
ENX = 5 V, VCC = 4.5 V
ENA = ENB = 0 V
10.5
200
Charge pump standby
current
IBAT
nA
2.4
Waveforms and truth table
In normal operating conditions the DIAGX/ENX pin is considered as an input pin by the
device. This pin must be externally pulled-high
PWM pin usage: in all cases, a “0” on the PWM pin turns-off both LSA and LSB switches.
When PWM rises back to “1”, LSA or LSB turn-on again depending on the input pin state.
Table 12. Truth table in normal operating conditions
INA
INB DIAGA/ENA DIAGB/ENB OUTA OUTB CS (VCSD = 0 V)
Operating mode
1
1
1
0
1
1
1
1
H
H
H
L
High imp.
Brake to VCC
ISENSE = IOUT/K Clockwise (CW)
Counterclockwise
ISENSE = IOUT/K
0
0
1
0
1
1
1
1
L
L
H
L
(CCW)
High imp.
Brake to GND
14/37
Doc ID 15701 Rev 8
VNH5019A-E
Electrical specifications
Figure 4.
Typical application circuit for DC to 20 kHz PWM operation with reverse battery
protection (option A)
VBAT
Reg 5V
+5V
+ 5V
3.3K
1K
3.3K
DIAG /EN
VCC
B
B
VBAT
CP
1K
DIAGA/ENA
1K
HSA
HSB
PWM
μC
OUT
A
OUTB
IN
B
INA
CS
1K
1K
LSA
LSB
10K
C
M
33nF
1.5K
GNDB
GNDA
Note:
The external N-channel Power MOSFET used for the reverse battery protection should have the following characteristics:
- BVdss > 20 V (for a reverse battery of -16 V);
- RDS(on) < 1/3 of H-bridge total RDS(on)
- Standard Logic Gate Driving
Doc ID 15701 Rev 8
15/37
Electrical specifications
VNH5019A-E
Figure 5.
Typical application circuit for DC to 20 kHz PWM operation with reverse battery
protection (option B)
VCC
+5V
Reg 5V
+ 5V
VCC
VBAT CP
3.3K
3.3K
1K
DIAG /EN
B
B
1K
DIAGA/ENA
1K
HSA
HSB
PWM
μC
OUT
A
OUTB
IN
A
1K
IN
B
1K
LSA
LSB
CS
10K
C
M
33nF
1.5K
GND
GND
B
A
S
100K
G
D
Note:
The value of the blocking capacitor (C) depends on the application conditions and defines voltage and current ripple onto supply line at PWM
operation. Stored energy of the motor inductance may flyback into the blocking capacitor, if the bridge driver goes into 3-state. This causes a
hazardous overvoltage if the capacitor is not big enough. As basic orientation, 500 µF per 10 A load current is recommended.
Table 13. Truth table in fault conditions (detected on OUTA)
INA
INB
DIAGA/ENA
DIAGB/ENB
OUTA
OUTB
CS (VCSD=0V)
1
0
1
0
X
H
High
impedance
1
L
H
1
0
0
OPEN
I
OUTB/K
High
0
L
impedance
X
OPEN
Fault Information
Protection Action
Note:
In normal operating conditions the DIAGX/ENX pin is considered as an input pin by the
device. This pin must be externally pulled high.
In case of a fault condition the DIAGX/ENX pin is considered as an output pin by the device.
16/37
Doc ID 15701 Rev 8
VNH5019A-E
The fault conditions are:
Electrical specifications
●
overtemperature on one or both high-sides (for example, if a short to ground occurs as
it could be the case described in line 1 and 2 in the Table 14);
●
Short to battery condition on the output (saturation detection on the low-side
Power MOSFET).
Possible origins of fault conditions may be:
●
OUTA is shorted to ground. It follows that, high-side A is in overtemperature state.
OUTA is shorted to VCC. It follow that, low-side Power MOSFET is in saturation state.
●
When a fault condition is detected, the user can know which power element is in fault by
monitoring the INA, INB, DIAGA/ENA and DIAGB/ENB pins.
In any case, when a fault is detected, the faulty leg of the bridge is latched off. To turn-on the
respective output (OUTX) again, the input signal must rise from low-level to high-level.
Figure 6.
Behavior in fault condition (how a fault can be cleared)
Note:
In case of the fault condition is not removed, the procedure for unlatching and sending the
device in Stby mode is:
- Clear the fault in the device (toggle: INA if ENA=0 or INB if ENB=0)
- Pull low all inputs, PWM and Diag/EN pins within tDEL.
If the Diag/En pins are already low, PWM=0, the fault can be cleared simply toggling the
input. The device enters in stby mode as soon as the fault is cleared.
Doc ID 15701 Rev 8
17/37
Electrical specifications
VNH5019A-E
Table 14. Electrical transient requirements (part 1)
ISO T/R
7637/1
Test level
I
II
III
IV
Delay and impedance
Test Pulse
1
2
-25 V
+25 V
-25 V
-50 V
+50 V
-50 V
-75 V
+75 V
-100 V
+75 V
-6 V
-100 V
+100 V
-150 V
+100 V
-7 V
2 ms, 10 Ω
0.2 ms, 10 Ω
0.1 μs, 50 Ω
0.1 μs, 50 Ω
100 ms, 0.01 Ω
400 ms, 2 Ω
3a
3b
4
+25 V
-4 V
+50 V
-5 V
5
+26.5 V
+46.5 V
+66.5 V
+86.5 V
Table 15. Electrical transient requirements (part 2)
ISO T/R
7637/1
Test levels
I
II
III
IV
Test Pulse
1
2
C
C
C
C
C
C
C
C
C
C
C
E
C
C
C
C
C
E
C
C
C
C
C
E
3a
3b
4
5
Table 16. Electrical transient requirements (part 3)
Class
Contents
All functions of the device are performed as designed after exposure to
disturbance.
C
One or more functions of the device are not performed as designed after
exposure to disturbance and cannot be returned to proper operation without
replacing the device.
E
18/37
Doc ID 15701 Rev 8
VNH5019A-E
Electrical specifications
2.5
Reverse battery protection
Against reverse battery condition the charge pump feature allows to use an external
N-channel MOSFET connected as shown in the typical application circuit (see Figure 4).
As alternative option, a N-channel MOSFET connected to GND pin can be used (see typical
application circuit in figure Figure 5).
With this configuration we recommend to short VBAT pin to VCC
.
The device sustains no more than -30 A in reverse battery conditions because of the two
body diodes of the Power MOSFETs. Additionally, in reverse battery condition the I/Os of
VNH5019A-E is pulled-down to the VCC line (approximately -1.5 V). Series resistor must be
inserted to limit the current sunk from the microcontroller I/Os. If IRmax is the maximum
target reverse current through microcontroller I/Os, series resistor is:
V
– V
IOs
I
CC
R = -------------------------------
Rmax
Figure 7.
Definition of the delay times measurement
VINA,
t
VINB
t
PWM
t
ILOAD
t
DEL
t
DEL
t
Doc ID 15701 Rev 8
19/37
Electrical specifications
Figure 8.
VNH5019A-E
Definition of the low-side switching times
PWM
t
V
OUTA, B
90%
80%
tf
tr
t
10%
20%
Figure 9.
Definition of the high-side switching times
VINA,
td(on)
td(off)
t
VOUTA
90%
10%
t
20/37
Doc ID 15701 Rev 8
VNH5019A-E
Electrical specifications
Figure 10. Definition of dynamic cross conduction current during a PWM operation
INA=1, IN =0
B
PWM
t
IMOTOR
t
VOUTB
t
ICC
IRM
t
trr
Doc ID 15701 Rev 8
21/37
Electrical specifications
VNH5019A-E
Figure 11. Waveforms in full bridge operation (part 1)
NORMAL OPERATION (DIAGA/ENA=1, DIAGB/ENB=1)
LOAD CONNECTED BETWEEN OUTA, OUTB
DIAGA/ENA
DIAGB/ENB
INA
INB
PWM
OUTA
OUTB
IOUTA->OUTB
CS (*)
tDEL
tDEL
CS_DIS
(*) CS BEHAVIOUR DURING PWM MODE DEPENDS ON PWM FREQUENCY AND DUTY CYCLE
NORMAL OPERATION (DIAGA/ENA=1, DIAGB/ENB=0 and DIAGA/ENA=0, DIAGB/ENB=1)
LOAD CONNECTED BETWEEN OUTA, OUTB
DIAGA/ENA
DIAGB/ENB
INA
INB
PWM
OUTA
OUTB
IOUTA->OUTB
CS
CS_DIS
CURRENT LIMITATION/THERMAL SHUTDOWN or OUTA SHORTED TO GROUND
INA
INB
ILIM
IOUTA->OUTB
TTSD_HSA
TTR_HSA
Tj =TTSD
Tj < TTSD
Tj > TTR
TjHSA
DIAGA/ENA
DIAGB/ENB
CS
CS_DIS
power limitation
current
limitation
normal operation
normal operation
OUTA shorted to ground
22/37
Doc ID 15701 Rev 8
VNH5019A-E
Figure 12. Waveforms in full bridge operation (part 2)
Electrical specifications
OUTA shorted to VCC (resistive short) and undervoltage shutdown
CS_DIS
INA
INB
OUTA
OUTB
IOUTA->OUTB
I
SD_LS
ILSA
T
TSD_LS
Tj_LSA
DIAGB/ENB
DIAGA/ENA
CS
V<nominal
normal operation OUTA softly shorted to VCC
normal operation
undervoltage shutdown
OUTA shorted to VCC (pure short) and undervoltage shutdown
CS_DIS
INA
INB
OUTA
OUTB
IOUTA->OUTB
I
SD_LS
ILSA
T
TSD_LS
Tj_LSA
DIAGB/ENB
DIAGA/ENA
CS
V<nominal
normal operation OUTA hardly shorted to VCC
normal operation
undervoltage shutdown
Doc ID 15701 Rev 8
23/37
Electrical specifications
Figure 13. Definition of delay response time of sense current
VNH5019A-E
INPUT
CS_DIS
LOAD CURRENT
CURRENT SENSE
t
t
DSENSEH
DSENSEL
The VNH5019A-E can be used as a high power half-bridge driver achieving an
on- resistance per leg of 9.5 mΩ. The figure below shows the suggested configuration:
Figure 14. Half-bridge configuration
V
CP
V
CC
CP
BAT
V
CC
IN
IN
IN
A
B
A
B
IN
V
DIAG /EN
DIAG /EN
BAT
A
A
A
B
A
B
DIAG /EN
DIAG /EN
B
B
PWM
PWM
CS_DIS
CS_DIS
OUT
A
OUT
OUT
B
OUT
M
B
A
GND
GND
B
GND
GND
B
A
A
The VNH5019A-E can easily be designed in multi-motors driving applications such as seat
positioning systems where only one motor must be driven at a time. DIAGX/ENX pins allow
to put unused half-bridges in high-impedance. The figure below shows the suggested
configuration:
24/37
Doc ID 15701 Rev 8
VNH5019A-E
Figure 15. Multi-motors configuration
Electrical specifications
V
CP
V
CC
CP
BAT
V
CC
IN
IN
IN
A
B
A
B
IN
V
BAT
DIAG /EN
DIAG /EN
A
A
B
A
B
A
B
DIAG /EN
DIAG /EN
B
PWM
PWM
CS_DIS
CS_DIS
OUT
A
OUT
OUT
OUT
B
M
2
B
A
GND
GND
B
GND
GND
B
A
A
M
M
1
3
Doc ID 15701 Rev 8
25/37
Package and PCB thermal data
VNH5019A-E
3
Package and PCB thermal data
3.1
MultiPowerSO-30 thermal data
Figure 16. MultiPowerSO-30™ PC board
Note:
Layout condition of Rth and Zth measurements (PCB FR4 area= 58 mm x 58 mm, PCB thickness=2 mm, Cu thickness=35 mm, Copper areas:
from minimum pad lay-out to 16 cm2).
Figure 17. Chipset configuration
CHIP 1
RthA
RthAB
RthAC
RthBC
CHIP 3
RthC
CHIP 2
RthB
Figure 18. Auto and mutual Rthj-amb vs PCB copper area in open box free air
condition
50
RthA
45
RthB = RthC
RthAB = RthAC
RthBC
40
35
30
25
20
15
10
5
0
0
2
4
6
8
10
12
14
16
18
cm2 of Cu Area (refer to PCB layout)
26/37
Doc ID 15701 Rev 8
VNH5019A-E
Package and PCB thermal data
3.1.1
Thermal calculation in clockwise and anti-clockwise operation in
steady-state mode
Table 17. Thermal calculation in clockwise and anti-clockwise operation in steady-state mode
Chip 1 Chip 2 Chip 3
Tjchip1
Tjchip2
Tjchip3
Pdchip1 • RthA + Pdchip3
RthAC + Tamb
•
•
Pdchip1 • RthAB + Pdchip3
RthBC + Tamb
•
Pdchip1 • RthAC + Pdchip3
RthC + Tamb
•
•
ON
OFF
ON
Pdchip1 • RthA + Pdchip2
Pdchip1 • RthAB + Pdchip2 • RthB
+ Tamb
Pdchip1 • RthAC + Pdchip2
ON
ON
ON
ON
OFF
ON
OFF
OFF
ON
RthAB + Tamb
RthBC + Tamb
Pdchip1 • RthA+ Tamb
dchip1 • RthA + (Pdchip2
Pdchip1 • RthAB + Tamb
Pdchip1 • RthAC + Tamb
P
+
Pdchip2 • RthB + Pdchip1
thAB + Pdchip3 • RthBC + Tamb
•
Pdchip1 • RthAB + Pdchip2
thBC + Pdchip3 • RthC + Tamb
•
Pdchip3) • RthAB + Tamb
R
R
3.1.2
Thermal calculation in transient mode
Ths= Pdhs • Zhs + Zhsls • (PdlsA + PdlsB) + Tamb
TlsA= PdlsA • Zls + Pdhs • Zhsls + PdlsB • Zhsls + Tamb
TlsB= PdlsB • Zls + Pdhs • Zhsls + PdlsA • Zhsls + Tamb
Figure 19. Chipset configuration
CHIP 1
Zls
Zhsls
Zhsls
Zlsls
CHIP 3
Zls
CHIP 2
Zls
Equation 1: pulse calculation formula
Z
= R
⋅ δ + Z
(1 – δ)
THtp
THδ
where
TH
δ = t ⁄ T
p
Doc ID 15701 Rev 8
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Package and PCB thermal data
VNH5019A-E
Figure 20. MultiPowerSO-30 HSD thermal impedance junction ambient single pulse
ZTH -HSD @ cu area
100
HSD-16 cm^2 Cu
HSD-8 cm^2 Cu
HSD-4 cm^2 Cu
HSD-footprint
HsLsD-16 cm^2 Cu
HsLsD-8 cm^2 Cu
HsLsD-4 cm^2 Cu
HsLsD-footprint
10
W
/
C°
1
0.1
0.001
0.01
0.1 time (sec)
1
10
100
1000
Figure 21. MultiPowerSO-30 LSD thermal impedance junction ambient single pulse
ZTH -LSD @ cu area
100
LSD-16 cm^2 Cu
LSD-8 cm^2 Cu
LSD-4 cm^2 Cu
LSD-footprint
LsLsD-16 cm^2 Cu
LsLsD-8 cm^2 Cu
LsLsD-4 cm^2 Cu
10
LsLsD-footprint
Z ls
W
/
C°
Z lsls
1
0.1
0.001
0.01
0.1
1
10
100
1000
time (sec)
28/37
Doc ID 15701 Rev 8
VNH5019A-E
Package and PCB thermal data
Figure 22. Thermal fitting model of an H-bridge in MultiPowerSO-30
Table 18. Thermal parameters(1)
Area/island (cm2)
Footprint
4
8
16
R1 = R7 (°C/W)
R2 = R8 (°C/W)
R3 = R10 = R16 (°C/W)
R4 (°C/W)
0.1
0.3
0.5
6
R5 (°C/W)
30
24
52
24
42
24
32
R6 (°C/W)
56
R9 = R15 (°C/W)
R11 = R17 (°C/W)
R12 = R18 (°C/W)
R13 = R19 (°C/W)
R14 = R20 (°C/W)
R21 = R22 (°C/W)
R23 (°C/W)
0.05
0.7
10
36
26
42
26
36
26
28
56
35
25
25
25
160
0.005
0.01
0.03
0.4
1.5
3
150
150
150
C1 = C7 = C9 = C15 (W.s/°C)
C2 = C8 (W.s/°C)
C3 (W.s/°C)
C4 (W.s/°C)
C5 (W.s/°C)
2
4
2
5
2
6
C6 (W.s/°C)
C10 = C16 (W.s/°C)
C11 = C17 (W.s/°C)
C12 = C18 (W.s/°C)
C13 = C19 (W.s/°C)
C14 = C20 (W.s/°C)
C21 = C22 = C23 (W.s/°C)
0.015
0.05
0.3
1.2
2.5
0.01
2
3
2
4
2
5
0.008
0.008
0.008
1. The blank space means that the value is the same as the previous one.
Doc ID 15701 Rev 8
29/37
Package and packing information
VNH5019A-E
4
Package and packing information
®
4.1
ECOPACK
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
4.2
MultiPowerSO-30 mechanical data
Figure 23. MultiPowerSO-30 package dimensions
N
S
L
BOTTOM VIEW
F1
F1
B
e
h x 45°
30
A
1
C
F3
D
30/37
Doc ID 15701 Rev 8
VNH5019A-E
Package and packing information
Table 19. MultiPowerSO-30 mechanical data
Data book mm
Typ.
Symbol
Min.
Max.
A
A2
A3
B
2.35
2.25
0.1
1.85
0
0.42
0.23
17.1
18.85
15.9
0.58
0.32
17.3
19.15
16.1
C
D
17.2
E
E1
e
16
1
F1
F2
F3
L
5.55
4.6
6.05
5.1
9.6
10.1
1.15
10°
7°
0.8
N
S
0°
Doc ID 15701 Rev 8
31/37
Package and packing information
VNH5019A-E
4.3
MultiPowerSO-30 suggested land pattern
Figure 24. MultiPowerSO-30 suggested pad layout
32/37
Doc ID 15701 Rev 8
VNH5019A-E
Package and packing information
4.4
MultiPowerSO-30 packing information
The devices can be packed in tube or tape and reel shipments (see Table 20: Device
summary for packaging quantities).
Figure 25. MultiPowerSO-30 tube shipment (no suffix)
Dimension
mm
29
Base q.ty
A
Bulk q.ty
435
532
3.82
23.6
0.8
Tube length ( 0.5)
C
B
A
B
C ( 0.13)
Figure 26. MultiPowerSO-30 tape and reel shipment (suffix “TR”)
Reel dimensions
SO-28 tube shipment (no suffix)
Dimension
mm
1000
Base q.ty
Bulk q.ty
A (max)
B (min)
1000
330
1.5
C ( 0.2)
D (min)
13
20.2
32
G (+ 2 / -0)
N (min)
100
38.4
T (max)
Tape dimensions
According to Electronic Industries Association
(EIA) Standard 481 rev. A, Feb 1986
Description
Dimension
mm
Tape width
W
32
4
Tape hole spacing
Component spacing
Hole diameter
P0 ( 0.1)
P
24
1.5
2
D ( 0.1/-0)
D1 (min)
F ( 0.1)
K (max)
P1 ( 0.1)
Hole diameter
Hole position
14.2
2.2
2
Compartment Depth
Hole Spacing
End
Start
Top
cover
tape
No components
500 mm min
Components
No components
500 mm min
Empty components pockets
User direction of feed
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Order codes
VNH5019A-E
5
Order codes
Table 20. Device summary
Package
Order codes
Tube
Tape and reel
VNH5019TR-E
MultiPowerSO-30
VNH5019A-E
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VNH5019A-E
Revision history
6
Revision history
Table 21. Document revision history
Date
Revision
Changes
22-Jan-2008
1
Initial release.
Uploaded corporate template by using V3 version
Added Table 5: Thermal data
Section 2.1: Absolute maximum ratings
– Added text
Table 6: Power section
– IS: added max value for INA = INB = PWM = 0; Tj = 25 °C;
VCC=13V in Test conditions, deleted INA = INB = PWM = 0
– Vf: changed Test conditions, changed typ/max value
– IRM: deleted and copied in Table 8: Switching (VCC = 13 V,
R
LOAD = 0.87 W, Tj = 25 °C) whole row
04-Nov-2009
2
Table 8: Switching (VCC = 13 V, RLOAD = 0.87 W, Tj = 25 °C)
– tDEL: changed min/typ/max value
– Copied IRM row by Table 6: Power section
Updated Table 10: Current sense (8 V < VCC < 21 V)
Table 11: Charge pump
– VCP: changed min/max value for ENX = 5 V, changed typ
value for ENX = 5 V, VCC = 4.5 V
Updated Figure 11: Waveforms in full bridge operation (part 1)
Updated Figure 12: Waveforms in full bridge operation (part 2)
Added Chapter 4
Updated following tables:
– Table 6: Power section
– Table 9: Protection and diagnostic
– Table 10: Current sense (8 V < VCC < 21 V)
16-Dec-2009
3
Added Figure 6: Behavior in fault condition (how a fault can be
cleared)
Added Chapter 3: Package and PCB thermal data
Updated Table 5: Thermal data.
Table 6: Power section:
– IS: updated test condition and max value
Updated table notes on Table 9: Protection and diagnostic.
Table 10: Current sense (8 V < VCC < 21 V):
06-Apr-2010
4
– dK0/k0, dK1/k1, dK3/k3: updated minimum end maximum
values.
19-Apr-2010
25-May-2010
5
6
Updated Table 10: Current sense (8 V < VCC < 21 V).
Updated Features list.
Updated Table 6: Power section.
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Revision history
Table 21. Document revision history (continued)
VNH5019A-E
Date
Revision
Changes
Updated Table 5: Thermal data.
Updated Figure 1: Block diagram
02-Sep-2010
7
Added Table 1: Suggested connections for unused and not
connected pins
Updated Table 3: Block descriptions
Table 8: Switching (VCC = 13 V, RLOAD = 0.87 W, Tj = 25 °C):
22-Dec-2011
8
– TTSD, TTR, THYST: added note
– TTSD_LS: added row
Updated Table 13: Truth table in fault conditions (detected on
OUTA)
Updated Figure 11: Waveforms in full bridge operation (part 1)
and Figure 12: Waveforms in full bridge operation (part 2)
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VNH5019A-E
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