ADS54J40IRMP_技术文档

ADS54J40

ZHCSEA4C – MAY 2015 – REVISED DECEMBER 2020

ADS54J40 双通道 14 位 1.0GSPS 模数转换器

1 特性

3 说明

• 14 位分辨率、双通道、1GSPS ADC

ADS54J40 是一款低功耗、高带宽、14 位、1.0GSPS

双通道模数转换器 (ADC)。该器件具有高信噪比

(SNR)，可为需要在高瞬时带宽内实现超高动态范围的

应用提供 -158dBFS/Hz 的本底噪声。该器件支持

JESD204B 串行接口，数据传输速率高达 10.0Gbps，

每个 ADC 可支持双通道或四通道。经缓冲的模拟输入

可在较宽频率范围内提供统一的输入阻抗，并尽可能降

低采样和保持毛刺脉冲能量。可选择将每个 ADC 通道

连接至数字下变频器 (DDC) 模块。ADS54J40 以超低

功耗在宽输入频率范围内提供出色的无杂散动态范围

(SFDR)。

•

本底噪声：-158dBFS/Hz

频谱性能（f_IN= 170MHz，–1dBFS）：

– SNR：69.0dBFS

– NSD：-155.9dBFS/Hz

– SFDR：86dBc（包括交错音调）

– SFDR：89dBc（不包括 HD2、HD3 和交错音

调）

•

频谱性能（f_IN= 350MHz，–1dBFS）：

– SNR：66.3dBFS

– NSD：-153.3dBFS/Hz

– SFDR：75dBc

JESD204B 接口减少了接口线路数，从而实现高系统

集成度。内部锁相环 (PLL) 会将 ADC 采样时钟加倍，

以获得对各通道的 14 位数据进行串行化所使用的位时

钟。

– SFDR：85dBc（不包括 HD2、HD3 和交错音

调）

通道隔离：f_IN= 170MHz 时为 100dBc

满量程输入：1.9V V_PP

输入带宽 (3dB)：1.2GHz

片上抖动

•

器件信息

封装⁽¹⁾

封装尺寸（标称值）

器件型号

ADS54J40

VQFNP (72)

10.00mm x 10.00mm

集成宽带 DDC 块

支持子类 1 的 JESD204B 接口：

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

– 10.0Gbps 时每个 ADC 具有 2 条信道

– 5.0Gbps 时每个 ADC 具有 4 条信道

– 支持多芯片同步

空白

•

功率耗散：1GSPS 时为每通道 1.35W

封装：72 引脚 VQFNP (10mm × 10mm)

0

-20

-40

2 应用

•

雷达和天线阵列

无线宽带

电缆 CMTS、DOCSIS 3.1 接收器

通信测试设备

微波接收器

软件定义无线电 (SDR)

数字转换器

医疗成像和诊断

-60

-80

-100

-120

0

100

200 300

Input Frequency (MHz)

400

500

D003

（SNR = 69dBFS；SFDR = 86dBc；f_IN= 170MHz，IL 毛刺 =

84dBc；非 HD2、HD3 毛刺 = 89dBc）

用于 170MHz 输入信号的 FFT

本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问

www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SBAS714

ADS54J40

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ZHCSEA4C – MAY 2015 – REVISED DECEMBER 2020

Table of Contents

8.3 Feature Description...................................................28

8.4 Device Functional Modes..........................................36

8.5 Register Maps...........................................................48

9 Application Information Disclaimer.............................85

9.1 Application Information............................................. 85

9.2 Typical Application.................................................. 103

10 Power Supply Recommendations............................106

10.1 Power Sequencing and Initialization.....................106

11 Layout.........................................................................107

11.1 Layout Guidelines................................................. 107

11.2 Layout Example.................................................... 107

12 Device and Documentation Support........................108

12.1 Documentation Support........................................ 108

12.2 Receiving Notification of Documentation Updates108

12.3 支持资源................................................................108

12.4 Trademarks...........................................................108

12.5 静电放电警告........................................................ 108

12.6 术语表................................................................... 108

1 特性................................................................................... 1

2 应用................................................................................... 1

3 说明................................................................................... 1

4 Revision History.............................................................. 2

5 ADS54J40 Comparison...................................................5

6 Pin Configuration and Functions...................................6

7 Specifications.................................................................. 8

7.1 Absolute Maximum Ratings........................................ 8

7.2 ESD Ratings............................................................... 8

7.3 Recommended Operating Conditions.........................9

7.4 Thermal Information....................................................9

7.5 Electrical Characteristics...........................................10

7.6 AC Characteristics.................................................... 11

7.7 Digital Characteristics............................................... 15

7.8 Timing Requirements................................................16

7.9 Typical Characteristics..............................................18

8 Detailed Description......................................................27

8.1 Overview...................................................................27

8.2 Functional Block Diagram.........................................27

4 Revision History

注：以前版本的页码可能与当前版本的页码不同

Changes from Revision B (January 2017) to Revision C (December 2020)

Page

•

向特性要点添加了文本“（包括交错音调）”...................................................................................................1

• Added ADS54J40 Comparison section, moved Device Comparison Table to this section.................................5

• Changed the description of SYSREFM, SYSREFP, and PDN pins in Pin Functions table ............................... 6

• Changed f_IN= 470 MHz test conditions and typical values across parameters in AC Characteristics table.... 11

• Added f_IN= 720 MHz test conditions across parameters in AC Characteristics table...................................... 11

• Changed ENOB unit from dBFS to Bits in AC Characteristics table.................................................................11

• Changed typical values of SFDR_IL parameter ...............................................................................................11

• Changed first IMD3 typical value from –85 dBFS to –89 dBFS ....................................................................11

• Changed first footnote in Timing Characteristics table..................................................................................... 16

• Changed typical value of FOVR latency from 18 + 4 ns to 18 .........................................................................16

• Changed t_PDparameter name to t_PDIin Timing Characteristics table.............................................................. 16

• Changed FFT for 470-MHz Input Signal at –3 dBFS figure, title, and conditions........................................... 18

• Added FFT for 720-MHz Input Signal at –6 dBFS figure................................................................................ 18

• Changed Spurious-Free Dynamic Range vs Input Frequency figure............................................................... 18

• Changed IL Spur vs Input Frequency figure.....................................................................................................18

• Changed 16-bit to 14-bit in first sentence of Overview section.........................................................................27

• Added DDC Block section ............................................................................................................................... 30

• Changed 表 8-6 ............................................................................................................................................... 36

• Added last sentence to Step 4 in Serial Register Readout: Analog Bank section............................................39

• Added last sentence to Step 4 in Serial Register Readout: JESD Bank section..............................................40

• Added SDOUT Timing Diagram figure............................................................................................................. 40

• Changed the JESD204B Test Patterns section ............................................................................................... 43

• Changed Serial Interface Registers diagram....................................................................................................48

• Added register addresses 1 and 2 to GENERAL REGISTERS in Register Map section ................................ 48

• Changed the name of JESD ANALOG PAGE (6A00h) to JESD ANALOG PAGE (JESD BANK PAGE

SEL=6A00h) in Register Map table ................................................................................................................. 48

• Changed bit 1, register 12 of JESD ANALOG PAGE (6A00h) from 0 to ALWAYS WRITE 1 .......................... 48

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• Added OFFSET READ Page and OFFSET LOAD Page registers to Register Map table .............................. 48

• Added ADS54J40 Access Type Codes table....................................................................................................52

• Deleted legends from bit registers in Register Descriptions section.................................................................53

• Added register 1h and 2h to Register Descriptions section .............................................................................53

• Added text '6100h = OFFSET READ or LOAD Page' to the JESD BANK PAGE SEL[7:0] bit description.......53

• Changed description of Registers 3h and 4h (address = 3h and 4h)in General Registers Page. ................... 54

• Changed description of bit 0 in Register 4Fh (address = 4Fh), Master Page (080h)....................................... 58

• Changed Register 53H .................................................................................................................................... 59

• Changed Register 54H .................................................................................................................................... 59

• Changed Register 55H .................................................................................................................................... 60

• Added Register 40h .........................................................................................................................................62

• Changed Register 4Eh .................................................................................................................................... 67

• Changed Register 52h .....................................................................................................................................67

• Added Register 68h .........................................................................................................................................68

• Changed the Register ABh description.............................................................................................................69

• Changed bit 1 from 0 to ALWAYS WRITE 1 in Register 12h (address = 12h), JESD Analog Page (6A00h)...76

• Changed Register 1Ah .................................................................................................................................... 79

• Added Offset Read Page Register and Offset Load Page Register sections to Register Descriptions section...

81

• Changed Register 075h, 077h, 079h, 7Bh (address = 075h, 077h, 079h, 7Bh ...............................................82

• Changed Register 00h, 04h, 08h, 0Ch ............................................................................................................ 83

• Changed Register 01h, 05h, 09h, 0Dh ............................................................................................................ 83

• Added Register 78h .........................................................................................................................................84

• Added DC Offset Correction Block in the ADS54J40 section...........................................................................89

• Added Idle Channel Histogram section............................................................................................................ 93

• Added the Interleaving (IL) Mismatch Compensation section.......................................................................... 94

• Changed the description in Transformer-Coupled Circuits section.................................................................104

• Changed the Layout Guidelines .................................................................................................................... 107

Changes from Revision A (October 2015) to Revision B (January 2017)

Page

• Added the Device Comparison Table ................................................................................................................ 5

• Added CDM row to ESD Ratings table...............................................................................................................8

• Changed the minimum value for the input clock frequency in the Recommended Operating Conditions table ..

9

• Changed Sample Timing, Aperture jitter parameter typical specification in Timing Characteristics section.....16

• Added the FOVR latency parameter to the Timing Characteristics table......................................................... 16

• Changed Overview section ..............................................................................................................................27

• Changed Functional Block Diagram section: changed Control and SPI block and added dashed outline to

FOVR traces.....................................................................................................................................................27

• Changed SYSREF Signal section: changed 表 8-4 and added last paragraph................................................34

• Added SYSREF Not Present (Subclass 0, 2) section.......................................................................................34

• Changed the number of clock cycles in the Fast OVR section.........................................................................35

• Deleted Lane Enable with Decimation subsection ...........................................................................................45

• Added the Program Summary of DDC Modes and JESD Link Configuration table..........................................45

• Added 图 8-27 to Register Maps section..........................................................................................................48

• Changed the Register Map ..............................................................................................................................48

• Deleted register 39h, 3Ah, and 56h .................................................................................................................48

• Added 表 8-63 ..................................................................................................................................................71

• Changed Power Supply Recommendations section ......................................................................................106

• Added the Power Sequencing and Initialization section.................................................................................106

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• Added the Receiving Notification of Documentation Updates section............................................................108

Changes from Revision * (May 2015) to Revision A (October 2015)

Page

•

已投入量产..........................................................................................................................................................1

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5 ADS54J40 Comparison

表 5-1 lists companion devices to the ADS54J40 .(TBD: Why has it been shifted to this place? )

表 5-1. Device Comparison Table

PART NUMBER

ADS54J20

ADS54J42

ADS54J40

ADS54J60

ADS54J66

ADS54J69

SPEED GRADE (MSPS)

RESOLUTION (Bits)

CHANNEL

1000

625

12

14

16

14

16

2

4

2

1000

500

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6 Pin Configuration and Functions

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

1

2

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

DB3M

DB3P

DA3M

DA3P

DGND

IOVDD

PDN

3

DGND

IOVDD

SDIN

4

5

6

SCLK

RES

7

SEN

RESET

DVDD

AVDD

AVDD3V

AVDD

INAP

8

DVDD

AVDD

AVDD3V

SDOUT

AVDD

INBP

9

GND Pad

(Back Side)

10

11

12

13

14

15

16

17

18

INBM

INAM

AVDD

AVDD3V

AVDD

AGND

AVDD

AVDD3V

AVDD

AGND

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

图 6-1. RMP Package, 72-Pin VQFNP, Top View

表 6-1. Pin Functions

I/O

DESCRIPTION

NAME

NO.

CLOCK, SYSREF

CLKINM

28

27

34

33

I

Negative differential clock input for the ADC.

Positive differential clock input for the ADC.

CLKINP

SYSREFM

SYSREFP

Negative external SYSREF input. Connect this pin to GND if not used.

Positive external SYSREF input. Connect this pin to 1.8 V if not used.

CONTROL, SERIAL

Power down, active low pin. Can be configured via an SPI register setting.

Can be configured to fast overrange output for channel A through the SPI. This pin

has an internal 20kΩ pulldown resistor.

PDN

50

I/O

RESET

SCLK

48

6

I

Hardware reset; active high. This pin has an internal 20-kΩ pulldown resistor.

Serial interface clock input

6

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表 6-1. Pin Functions (continued)

I/O

DESCRIPTION

NAME

NO.

SDIN

5

I

Serial interface data input

Serial interface data output.

SDOUT

SEN

11

7

O

I

Can be configured to fast overrange output for channel B through the SPI.

Serial interface enable

DATA INTERFACE

DA0M

DA1M

DA2M

DA3M

DA0P

62

59

56

54

61

58

55

53

65

68

71

1

O

JESD204B serial data negative outputs for channel A

JESD204B serial data positive outputs for channel A

JESD204B serial data negative outputs for channel B

DA1P

DA2P

DA3P

DB0M

DB1M

DB2M

DB3M

DB0P

66

69

72

2

DB1P

O

I

JESD204B serial data positive outputs for channel B

Synchronization input for the JESD204B port

DB2P

DB3P

SYNC

63

INPUT, COMMON MODE

INAM

INAP

INBM

INBP

41

42

14

13

I

Differential analog negative input for channel A

Differential analog positive input for channel A

Differential analog negative input for channel B

Differential analog positive input for channel B

Common-mode voltage, 2.1 V.

VCM

22

O

Note that analog inputs are internally biased to this pin through 600 Ω (effective),

no external connection from the VCM pin to the INxP or INxM pin is required.

POWER SUPPLY

AGND

AVDD

18, 23, 26, 29, 32, 36, 37

I

Analog ground

9, 12, 15, 17, 25, 30, 35, 38,

40, 43, 44, 46

Analog 1.9-V power supply

AVDD3V

DGND

DVDD

IOVDD

NC, RES

NC

10, 16, 24, 31, 39, 45

3, 52, 60, 67

8, 47

I

Analog 3.0-V power supply for the analog buffer

Digital ground

Digital 1.9-V power supply

4, 51, 57, 64, 70

Digital 1.15-V power supply for the JESD204B transmitter

19-21

49

Unused pins, do not connect

—

RES

I

Reserved pin. Connect to DGND.

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7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

MAX

UNIT

V

AVDD3V

3.6

–0.3

–0.2

–0.3

–0.2

–65

AVDD

Supply voltage range

DVDD

2.1

IOVDD

Voltage between AGND and DGND

INAP, INBP, INAM, INBM

1.4

0.3

3

V

CLKINP, CLKINM

Voltage applied to input pins

AVDD + 0.3

2.1

V

SYSREFP, SYSREFM

SCLK, SEN, SDIN, RESET, SYNC, PDN

Storage temperature, T_stg

150

°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under

Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device

reliability.

7.2 ESD Ratings

VALUE

±1000

±500

UNIT

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

V_(ESD)

Electrostatic discharge

V

Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V HBM allows safe manufacturing with a standard ESD control process.

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7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)^{(2) (3)}

MIN

2.85

1.8

NOM

3

MAX

3.6

UNIT

AVDD3V

AVDD

Supply voltage range

DVDD

1.9

1.15

1.9

2

2.0

V

1.7

2.0

IOVDD

1.1

1.2

Differential input voltage range

V_PP

V

Analog inputs

Input common-mode voltage

Maximum analog input frequency for 1.9-V_PPinput amplitude^{(4) (5)}

400

MHz

V_PP

Input clock frequency, device clock frequency

250⁽⁶⁾

0.75

0.8

1000

Input clock amplitude differential

(V_CLKP– V_CLKM

Sine wave, ac-coupled

LVPECL, ac-coupled

LVDS, ac-coupled

1.5

1.6

)

Clock inputs

Temperature

0.7

Input device clock duty cycle

Operating free-air, T_A

45%

50%

55%

85

–40

°C

Operating junction, T_J

105⁽¹⁾

125

(1) Prolonged use above the nominal junction temperature can increase the device failure-in-time (FIT) rate.

(2) SYSREF must be applied for the device to initialize; see the SYSREF Signal section for details.

(3) After power-up, always use a hardware reset to reset the device for the first time; see 表 9-1 for details.

(4) Operating 0.5 dB below the maximum-supported amplitude is recommended to accommodate gain mismatch in interleaving ADCs.

(5) At high frequencies, the maximum supported input amplitude reduces; see 图 7-37 for details.

(6) See 表 8-10.

7.4 Thermal Information

ADS54J40

THERMAL METRIC⁽¹⁾

RMP (VQFNP)

UNIT

72 PINS

22.3

5.1

R_θJA

Junction-to-ambient thermal resistance

°C/W

R_θJC(top)

R_θJB

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

2.4

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

0.1

ψ_JT

2.3

ψ_JB

R_θJC(bot)

0.4

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report (SPRA953).

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7.5 Electrical Characteristics

Typical values are at T_A= 25°C, full temperature range is from T_MIN= –40°C to T_MAX= 85°C, ADC sampling rate = 1 GSPS,

50% clock duty cycle, AVDD3V = 3 V, AVDD = DVDD = 1.9 V, IOVDD = 1.15 V, –1-dBFS differential input, and 0-dB digital

gain (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

GENERAL

ADC sampling rate

Resolution

250

14

1000 MSPS

Bits

POWER SUPPLIES

AVDD3V

AVDD

DVDD

IOVDD

I_AVDD3V

I_AVDD

3.0-V analog supply

2.85

1.8

1.7

1.1

3.0

1.9

3.6

2.0

V

1.9-V analog supply

1.9-V digital supply

1.9

2.0

V

1.15-V SERDES supply

3.0-V analog supply current

1.9-V analog supply current

1.9-V digital supply current

1.15-V SERDES supply current

Total power dissipation

1.15

334

359

197

566

2.71

211

618

2.80

1.2

V

V_IN= full-scale on both channels

Eight lanes active (LMFS = 8224)

Four lanes active (LMFS = 4244)

360

510

260

920

3.1

mA

W

I_DVDD

I_IOVDD

P_dis

I_DVDD

I_IOVDD

P_dis

1.9-V digital supply current

1.15-V SERDES supply current

Total power dissipation

mA

W

Four lanes active (LMFS = 4222),

2X decimation

I_DVDD

I_IOVDD

P_dis

1.9-V digital supply current

1.15-V SERDES supply current

Total power dissipation

197

593

2.74

176

562

mA

W

Four lanes active (LMFS = 4222),

2X decimation

Four lanes active (LMFS = 4222),

2X decimation

Two lanes active (LMFS = 2221),

4X decimation

I_DVDD

I_IOVDD

1.9-V digital supply current

1.15-V SERDES supply current

mA

Two lanes active (LMFS = 2221),

4X decimation

Two lanes active (LMFS = 2221),

4X decimation

(1)

P_dis

Total power dissipation

2.66

139

W

Global power-down power dissipation

315

mW

ANALOG INPUTS (INAP, INAM, INBP, INBM)

Differential input full-scale voltage

1.9

2.0

0.6

4.7

V_PP

V

V_IC

R_IN

C_IN

Common-mode input voltage

Differential input resistance

Differential input capacitance

At 170-MHz input frequency

kΩ

pF

50-Ω source driving ADC inputs

terminated with 50 Ω

Analog input bandwidth (3 dB)

1.2

GHz

CLOCK INPUT (CLKINP, CLKINM)

CLKINP and CLKINM are

connected to internal biasing

voltage through 400 Ω

Internal clock biasing

1.15

V

(1) See the Power-down Mode section for details.

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7.6 AC Characteristics

Typical values are at T_A= 25°C, full temperature range is from T_MIN= –40°C to T_MAX= 85°C, ADC sampling rate = 1 GSPS,

50% clock duty cycle, AVDD3V = 3 V, AVDD = DVDD = 1.9 V, IOVDD = 1.15 V, –1-dBFS differential input, and 0-dB digital

gain (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN TYP

MAX

UNIT

69.7

69.5

68.9

68.4

67.9

67.5

66.5

64.9

f_IN= 10 MHz, A_IN= –1 dBFS

f_IN= 100 MHz, A_IN= –1 dBFS

f_IN= 170 MHz, A_IN= –1 dBFS

f_IN= 230 MHz, A_IN= –1 dBFS

f_IN= 270 MHz, A_IN= –1 dBFS

f_IN= 300 MHz, A_IN= –1 dBFS

f_IN= 370 MHz, A_IN= –1 dBFS

f_IN= 470 MHz, A_IN= –3 dBFS

f_IN= 720 MHz, A_IN= –6 dBFS

66.2

SNR

Signal-to-noise ratio

dBFS

f_IN= 720 MHz, A_IN= –6 dBFS,

gain = 5 dB

63.3

f_IN= 10 MHz, A_IN= -1 dBFS

f_IN= 100 MHz, A_IN= –1 dBFS

f_IN= 170 MHz, A_IN= –1 dBFS

f_IN= 230 MHz, A_IN= –1 dBFS

f_IN= 270 MHz, A_IN= –1 dBFS

f_IN= 300 MHz, A_IN= –1 dBFS

f_IN= 370 MHz, A_IN= –1 dBFS

f_IN= 470 MHz, A_IN= –3 dBFS

f_IN= 720 MHz, A_IN= –6 dBFS

156.7

156.5

155.9

155.4

154.9

154.5

153.5

151.9

153.2

NSD

Noise spectral density

dBFS/Hz

f_IN= 720 MHz, A_IN= –6 dBFS,

gain = 5 dB

150.3

69.6

69.3

68.8

68.3

67.6

67

f_IN= 10 MHz, A_IN= –1 dBFS

f_IN= 100 MHz, A_IN= –1 dBFS

f_IN= 170 MHz, A_IN= –1 dBFS

f_IN= 230 MHz, A_IN= –1 dBFS

f_IN= 270 MHz, A_IN= –1 dBFS

f_IN= 300 MHz, A_IN= –1 dBFS

f_IN= 370 MHz, A_IN= –1 dBFS

f_IN= 470 MHz, A_IN= –3 dBFS

f_IN= 720 MHz, A_IN= –6 dBFS

65.2

SINAD

Signal-to-noise and distortion ratio

dBFS

65.5

65.7

64.1

f_IN= 720 MHz, A_IN= –6 dBFS,

gain = 5 dB

63.2

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7.6 AC Characteristics (continued)

Typical values are at T_A= 25°C, full temperature range is from T_MIN= –40°C to T_MAX= 85°C, ADC sampling rate = 1 GSPS,

50% clock duty cycle, AVDD3V = 3 V, AVDD = DVDD = 1.9 V, IOVDD = 1.15 V, –1-dBFS differential input, and 0-dB digital

gain (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN TYP

MAX

UNIT

83

86

85

81

78

73

71

67

f_IN= 100 MHz, A_IN= –1 dBFS

76

f_IN= 170 MHz, A_IN= –1 dBFS

f_IN= 230 MHz, A_IN= –1 dBFS

f_IN= 270 MHz, A_IN= –1 dBFS

f_IN= 300 MHz, A_IN= –1 dBFS

f_IN= 370 MHz, A_IN= –1 dBFS

f_IN= 470 MHz, A_IN= –3 dBFS

f_IN= 720 MHz, A_IN= –6 dBFS

Spurious free dynamic range

(excluding IL spurs

SFDR

dBc

f_IN= 720 MHz, A_IN= –6 dBFS,

gain = 5 dB

71

85

90

92

85

81

76

71

67

f_IN= 10 MHz, A_IN= –1 dBFS

f_IN= 100 MHz, A_IN= –1 dBFS

f_IN= 170 MHz, A_IN= –1 dBFS

f_IN= 230 MHz, A_IN= –1 dBFS

f_IN= 270 MHz, A_IN= –1 dBFS

f_IN= 300 MHz, A_IN= –1 dBFS

f_IN= 370 MHz, A_IN= –1 dBFS

f_IN= 470 MHz, A_IN= –3 dBFS

f_IN= 720 MHz, A_IN= –6 dBFS

76

HD2

Second-order harmonic distortion

dBc

f_IN= 720 MHz, A_IN= –6 dBFS,

gain = 5 dB

71

85

83

86

87

81

78

73

71

74

f_IN= 10 MHz, A_IN= –1 dBFS

f_IN= 100 MHz, A_IN= –1 dBFS

f_IN= 170 MHz, A_IN= –1 dBFS

f_IN= 230 MHz, A_IN= –1 dBFS

f_IN= 270 MHz, A_IN= –1 dBFS

f_IN= 300 MHz, A_IN= –1 dBFS

f_IN= 370 MHz, A_IN= –1 dBFS

f_IN= 470 MHz, A_IN= –3 dBFS

f_IN= 720 MHz, A_IN= –6 dBFS

76

HD3

Third-order harmonic distortio

dBc

f_IN= 720 MHz, A_IN= –6 dBFS,

gain = 5 dB

83

12

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7.6 AC Characteristics (continued)

Typical values are at T_A= 25°C, full temperature range is from T_MIN= –40°C to T_MAX= 85°C, ADC sampling rate = 1 GSPS,

50% clock duty cycle, AVDD3V = 3 V, AVDD = DVDD = 1.9 V, IOVDD = 1.15 V, –1-dBFS differential input, and 0-dB digital

gain (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN TYP

MAX

UNIT

94

97

93

95

91

85

89

f_IN= 10 MHz, A_IN= –1 dBFS

f_IN= 100 MHz, A_IN= –1 dBFS

f_IN= 170 MHz, A_IN= –1 dBFS

f_IN= 230 MHz, A_IN= –1 dBFS

f_IN= 270 MHz, A_IN= –1 dBFS

f_IN= 300 MHz, A_IN= –1 dBFS

f_IN= 370 MHz, A_IN= –1 dBFS

f_IN= 470 MHz, A_IN= –3 dBFS

f_IN= 720 MHz, A_IN= –6 dBFS

79

Non

Spurious-free dynamic range

dBFS

HD2, HD3 (excluding HD2, HD3, and IL spur)

f_IN= 720 MHz, A_IN= –6 dBFS,

gain = 5 dB

93

11.3

11.2

11.1

10.9

10.8

10.6

10.4

f_IN= 10 MHz, A_IN= –1 dBFS

f_IN= 100 MHz, A_IN= –1 dBFS

f_IN= 170 MHz, A_IN= –1 dBFS

f_IN= 230 MHz, A_IN= –1 dBFS

f_IN= 270 MHz, A_IN= –1 dBFS

f_IN= 300 MHz, A_IN= –1 dBFS

f_IN= 370 MHz, A_IN= –1 dBFS

f_IN= 470 MHz, A_IN= –3 dBFS

f_IN= 720 MHz, A_IN= –6 dBFS

10.5

ENOB

Effective number of bits

Bits

f_IN= 720 MHz, A_IN= –6 dBFS,

gain = 5 dB

10.2

82

80

83

82

78

75

70

66

f_IN= 10 MHz, A_IN= –1 dBFS

f_IN= 100 MHz, A_IN= –1 dBFS

f_IN= 170 MHz, A_IN= –1 dBFS

f_IN= 230 MHz, A_IN= –1 dBFS

f_IN= 270 MHz, A_IN= –1 dBFS

f_IN= 300 MHz, A_IN= –1 dBFS

f_IN= 370 MHz, A_IN= –1 dBFS

f_IN= 470 MHz, A_IN= –3 dBFS

f_IN= 720 MHz, A_IN= –6 dBFS

73

THD

Total harmonic distortion

dBc

f_IN= 720 MHz, A_IN= –6 dBFS,

gain = 5 dB

70

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7.6 AC Characteristics (continued)

Typical values are at T_A= 25°C, full temperature range is from T_MIN= –40°C to T_MAX= 85°C, ADC sampling rate = 1 GSPS,

50% clock duty cycle, AVDD3V = 3 V, AVDD = DVDD = 1.9 V, IOVDD = 1.15 V, –1-dBFS differential input, and 0-dB digital

gain (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN TYP

MAX

UNIT

85

84

83

82

81

77

78

f_IN= 10 MHz, A_IN= –1 dBFS

f_IN= 100 MHz, A_IN= –1 dBFS

f_IN= 170 MHz, A_IN= –1 dBFS

f_IN= 230 MHz, A_IN= –1 dBFS

f_IN= 270 MHz, A_IN= –1 dBFS

f_IN= 300 MHz, A_IN= –1 dBFS

f_IN= 370 MHz, A_IN= –1 dBFS

f_IN= 470 MHz, A_IN= –3 dBFS

f_IN= 720 MHz, A_IN= –6 dBFS

69

SFDR_IL

Interleaving spur

dBc

f_IN= 720 MHz, A_IN= –6 dBFS,

gain = 5 dB

74

f_IN1= 185 MHz, f_IN2= 190 MHz,

A_IN= –7 dBFS

–89

–79

–75

100

f_IN1= 365 MHz, f_IN2= 370 MHz,

A_IN= –7 dBFS

Two-tone, third-order intermodulation

distortion

IMD3

dBFS

dB

f_IN1= 465 MHz, f_IN2= 470 MHz,

A_IN= –7 dBFS

Full-scale, 170-MHz signal on

aggressor; idle channel is victim

Crosstalk Isolation between channel A and B

14

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7.7 Digital Characteristics

Typical values are at T_A= 25°C, full temperature range is from T_MIN= –40°C to T_MAX= 85°C, ADC sampling rate = 1 GSPS,

50% clock duty cycle, AVDD3V = 3 V, AVDD = DVDD = 1.9 V, IOVDD = 1.15 V, –1-dBFS differential input, and 0-dB digital

gain (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNITS

DIGITAL INPUTS (RESET, SCLK, SEN, SDIN, SYNC, PDN)⁽¹⁾

V_IH

V_IL

High-level input voltage

Low-level input voltage

All digital inputs support 1.2-V and 1.8-V logic levels

SEN

0.8

V

0.4

0

50

0

I_IH

High-level input current

Low-level input current

µA

RESET, SCLK, SDIN, PDN, SYNC

SEN

I_IL

RESET, SCLK, SDIN, PDN, SYNC

DIGITAL INPUTS (SYSREFP, SYSREFM)

V_D

Differential input voltage

0.35

0.45

1.3

1.4

V

V_{(CM_DIG)}

Common-mode voltage for SYSREF

DIGITAL OUTPUTS (SDOUT, PDN⁽³⁾

)

DVDD –

V_OH

High-level output voltage

DVDD

V

0.1

V_OL

Low-level output voltage

0.1

DIGITAL OUTPUTS (JESD204B Interface: DxP, DxM)⁽²⁾

V_OD

V_OC

Output differential voltage

With default swing setting

700

450

mV_PP

mV

Output common-mode voltage

Transmitter pins shorted to any voltage between –

0.25 V and 1.45 V

Transmitter short-circuit current

Single-ended output impedance

Output capacitance

100

mA

–100

z_os

50

2

Ω

Output capacitance inside the device,

from either output to ground

pF

(1) The RESET, SCLK, SDIN, and PDN pins have a 20-kΩ (typical) internal pulldown resistor to ground, and the SEN pin has a 20-kΩ

(typical) pullup resistor to IOVDD.

(2) 100-Ω differential termination.

(3) When functioning as an OVR pin for channel B.

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7.8 Timing Requirements

Typical values are at T_A= 25°C, full temperature range is from T_MIN= –40°C to T_MAX= 85°C, ADC sampling rate = 1.0

GSPS, 50% clock duty cycle, AVDD3V = 3.0 V, AVDD = DVDD = 1.9 V, IOVDD = 1.15 V, and –1-dBFS differential input,

unless otherwise noted.

MIN

TYP

MAX

UNITS

SAMPLE TIMING (TBD are any of these Switching Characteristics?TBD: No)

Aperture delay

0.75

1.6

ns

ps

Aperture delay matching between two channels on the same device

±70

±270

120

Aperture delay matching between two devices at the same temperature and supply voltage

ps

Aperture jitter

f_Srms

WAKE-UP TIMING

Wake-up time to valid data after coming out of global power-down

150

µs

LATENCY ⁽¹⁾

Input clock

cycles

Data latency: ADC sample to digital output

OVR latency: ADC sample to OVR bit

134

62

Input clock

cycles

Input clock

cycles

FOVR latency: ADC sample to FOVR signal on pin

18

4

t_PDI

Propagation delay: logic gates and output buffers delay (does not change with f_S)

ns

SYSREF TIMING

t_{SU_SYSREF}Setup time for SYSREF, referenced to the input clock falling edge

t_{H_SYSREF}Hold time for SYSREF, referenced to the input clock falling edge

JESD OUTPUT INTERFACE TIMING CHARACTERISTICS

Unit interval

300

100

900

ps

100

2.5

400

10

ps

Gbps

ps

Serial output data rate

Total jitter for BER of 1E-15 and lane rate = 10 Gbps

Random jitter for BER of 1E-15 and lane rate = 10 Gbps

Deterministic jitter for BER of 1E-15 and lane rate = 10 Gbps

26

0.75

12

ps rms

ps, pk-pk

Data rise time, data fall time: rise and fall times are measured from 20% to 80%,

differential output waveform, 2.5 Gbps ≤ bit rate ≤ 10 Gbps

t_R, t_F

35

ps

(1) Overall latency = latency + t_PDI

.

Sample N

t_{s_min}

t_{s_max}

CLKIN

1.0 GSPS

SYSREF

图 7-1. SYSREF Timing

16

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N+1

N+2

N

N+3

Sample

t_PD

Data Latency: 134 Clock Cycles

CLKINM

CLKINP

D

20

D

11

D

20

D

11

D

20

DA0P, DA0M,

DB0P, DB0M

Sample N-1

Sample N

Sample N+1

Sample N+2

D

10

D

1

D

10

D

1

D

10

DA1P, DA1M,

DB1P, DB1M

Sample N-1

Sample N

Sample N+1

Sample N+2

图 7-2. Sample Timing Requirements

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7.9 Typical Characteristics

Typical values are at T_A= 25°C, full temperature range is from T_MIN= –40°C to T_MAX= 85°C, ADC sampling

rate = 1.0 GSPS, 50% clock duty cycle, AVDD3V = 3.0 V, AVDD = DVDD = 1.9 V, IOVDD = 1.15 V, and –1-

dBFS differential input, unless otherwise noted.

0

-20

0

-20

-40

-60

-80

-100

-120

-100

-120

0

100

200 300

Input Frequency (MHz)

400

500

0

100

200 300

Input Frequency (MHz)

400

500

D001

D002

SNR = 69.7 dBFS; SFDR = 85 dBc; IL spur = 86 dBc; non

HD2, HD3 spur = 89 dBc

SNR = 69.2 dBFS; SFDR = 86 dBc; IL spur = 85 dBc; non

HD2, HD3 spur = 94 dBc

图 7-3. FFT for 10-MHz Input Signal

图 7-4. FFT for 140-MHz Input Signal

0

-20

-40

-20

-40

-60

-80

-100

-120

-100

-120

0

100

200 300

Input Frequency (MHz)

400

500

0

100

200 300

Input Frequency (MHz)

400

500

D003

D004

SNR = 68.9 dBFS; SFDR = 86 dBc; IL spur = 84 dBc; non

HD2, HD3 spur = 89 dBc

SNR = 68.1 dBFS; SFDR = 84 dBc; IL spur = 86 dBc; non

HD2, HD3 spur = 86 dBc

图 7-5. FFT for 170-MHz Input Signal

图 7-6. FFT for 230-MHz Input Signal

0

-20

-40

-20

-40

-60

-80

-100

-120

-100

-120

0

100

200 300

Input Frequency (MHz)

400

500

0

100

200 300

Input Frequency (MHz)

400

500

D005

D006

SNR = 67.4 dBFS; SFDR = 77 dBc; IL spur = 83 dBc; non

HD2, HD3 spur = 85 dBc

SNR = 66.2 dBFS; SFDR = 72 dBc; IL spur = 84 dBc; non

HD2, HD3 spur = 78 dBc

图 7-7. FFT for 300-MHz Input Signal

图 7-8. FFT for 370-MHz Input Signal

18

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0

-20

-40

-60

-80

-100

-120

0

100

200 300

Input Frequency (MHz)

400

500

0

100

200 300

Input Frequency (MHz)

400

500

D007

D070

SNR = 66.5 dBFS; SFDR = 73 dBc; IL spur = 81 dBc; non

HD2, HD3 spur = 88 dBc

SNR = 65.3 dBFS; SFDR = 71 dBc; IL spur = 83 dBc; non

HD2, HD3 spur = 89 dBFS

图 7-9. FFT for 470-MHz Input Signal at –3 dBFS

图 7-10. FFT for 720-MHz Input Signal at –6 dBFS

0

-20

-40

-20

-40

-60

-80

-100

-120

-100

-120

0

100

200 300

Input Frequency (MHz)

400

500

0

100

200 300

Input Frequency (MHz)

400

500

D008

D009

f_IN1= 185 MHz, f_IN2= 190 MHz, each tone at –7 dBFS, IMD3

f_IN1= 185 MHz, f_IN2= 190 MHz, each tone at –36 dBFS,

= 85 dBFS

IMD3 = 103 dBFS

图 7-11. FFT for Two-Tone Input Signal (–7 dBFS) 图 7-12. FFT for Two-Tone Input Signal (–36 dBFS)

0

-20

-40

-60

-80

-100

-120

-100

-120

0

100

200 300

Input Frequency (MHz)

400

500

0

100

200 300

Input Frequency (MHz)

400

500

D010

D011

f_IN1= 370 MHz, f_IN2= 365 MHz, each tone at –7 dBFS, IMD3

f_IN1= 370 MHz, f_IN2= 365 MHz, each tone at –36 dBFS,

= 80 dBFS

IMD3 = 109 dBFS

图 7-13. FFT for Two-Tone Input Signal (–7 dBFS) 图 7-14. FFT for Two-Tone Input Signal (–36 dBFS)

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0

-20

0

-20

-40

-60

-80

-100

-120

-100

-120

0

100

200 300

Input Frequency (MHz)

400

500

0

100

200 300

Input Frequency (MHz)

400

500

D012

D013

f_IN1= 470 MHz, f_IN2= 465 MHz, each tone at –7 dBFS, IMD3

f_IN1= 470 MHz, f_IN2= 465 MHz, each tone at –36 dBFS,

= 74.9 dBFS

IMD3 = 109.2 dBFS

图 7-15. FFT for Two-Tone Input Signal (–7 dBFS) 图 7-16. FFT for Two-Tone Input Signal (–36 dBFS)

-82

-76

-80

-86

-84

-90

-88

-94

-92

-98

-96

-102

-106

-110

-100

-104

-108

-35

-31

-27

Each Tone Amplitude (dBFS)

-23

-19

-15

-11

-7

-35

-31

-27

Each Tone Amplitude (dBFS)

-23

-19

-15

-11

-7

D014

D015

f_IN1= 185 MHz, f_IN2= 190 MHz

f_IN1= 365 MHz, f_IN2= 370 MHz

图 7-17. Intermodulation Distortion vs Input Tone

图 7-18. Intermodulation Distortion vs Input Tone

Amplitude

-70

-74

90

A_IN= -6 dBFS

Ain = -3 dBFS

A_IN= -1 dBFS

85

80

75

70

65

60

-78

-82

-86

-90

-94

-98

-102

-106

-35

-31

-27

-23

-19

-15

Each Tone Amplitude (dBFS)

-11

-7

0

100

200

300

400

Input Frequency (MHz)

500

600

700

D016

D017

f_IN1= 465 MHz, f_IN2= 470 MHz

图 7-20. Spurious-Free Dynamic Range vs Input

Frequency

图 7-19. Intermodulation Distortion vs Input Tone

Amplitude

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90

60

56

52

48

44

40

71

70

69

68

67

66

65

IL Enable

IL Disable

A_IN= -6 dBFS

A_IN= -3 dBFS

A_IN= -1 dBFS

86

82

78

74

70

0

40 80 120 160 200 240 280 320 360 400 440 480

Input Frequency (MHz)

0

100

200

300

400

Input Frequency (MHz)

500

600

700

D500

D042

图 7-21. IL Spur vs Input Frequency

图 7-22. Signal-to-Noise Ratio vs Input Frequency

71

70.5

70

94

AVDD = 1.8 V

AVDD = 1.85 V

AVDD = 1.9 V

AVDD = 1.95 V

AVDD = 2 V

AVDD = 1.8 V

AVDD = 1.85 V

AVDD = 1.9 V

AVDD = 1.95 V

AVDD = 2 V

92

90

88

86

84

82

80

78

69.5

69

68.5

68

67.5

67

-40

-15

10 35

Temperature (°C)

60

85

-40

-15

10 35

Temperature (°C)

60

85

D020

D021

f_IN= 170 MHz

图 7-23. Signal-to-Noise Ratio vs AVDD Supply and

图 7-24. Spurious-Free Dynamic Range vs AVDD

Temperature

Supply and Temperature

72

79

AVDD = 1.8 V

AVDD = 1.85 V

AVDD = 1.9 V

AVDD = 1.95 V

AVDD = 2 V

AVDD = 1.8 V

AVDD = 1.85 V

AVDD = 1.9 V

AVDD = 1.95 V

AVDD = 2 V

71

70

69

68

67

66

65

64

78

77

76

75

74

73

-40

-15

10 35

Temperature (°C)

60

85

-40

-15

10 35

Temperature (°C)

60

85

D022

D023

f_IN= 350 MHz

图 7-25. Signal-to-Noise Ratio vs AVDD Supply and 图 7-26. Spurious-Free Dynamic Range vs AVDD

Temperature

Supply and Temperature

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71

92

90

88

86

84

82

DVDD = 1.75 V

DVDD = 1.8 V

DVDD = 1.85 V

DVDD = 1.9 V

DVDD = 1.95 V

DVDD = 2 V

DVDD = 1.75 V

DVDD = 1.8 V

DVDD = 1.85 V

DVDD = 1.9 V

DVDD = 1.95 V

DVDD = 2 V

70.2

69.4

68.6

67.8

67

-40

-15

10 35

Temperature (°C)

60

85

-40

-15

10 35

Temperature (°C)

60

85

D024

D025

f_IN= 170 MHz

图 7-27. Signal-to-Noise Ratio vs DVDD Supply and 图 7-28. Spurious-Free Dynamic Range vs DVDD

Temperature

Supply and Temperature

70

69

68

67

66

65

64

82

80

78

76

74

72

DVDD = 1.75 V

DVDD = 1.8 V

DVDD = 1.85 V

DVDD = 1.9 V

DVDD = 1.95 V

DVDD = 2 V

DVDD = 1.75 V

DVDD = 1.8 V

DVDD = 1.85 V

DVDD = 1.9 V

DVDD = 1.95 V

DVDD = 2 V

-40

-15

10 35

Temperature (°C)

60

85

-40

-15

10 35

Temperature (°C)

60

85

D026

D027

f_IN= 350 MHz

图 7-29. Signal-to-Noise Ratio vs DVDD Supply and 图 7-30. Spurious-Free Dynamic Range vs DVDD

Temperature

Supply and Temperature

71

70.5

70

94

92

90

88

86

84

82

80

AVDD3V = 2.85 V

AVDD3V = 3 V

AVDD3V = 3.1 V

AVDD3V = 3.2 V

AVDD3V = 3.3 V

AVDD3V = 3.4 V

AVDD3V = 3.5 V

AVDD3V = 3.6 V

AVDD3V = 2.85 V

AVDD3V = 3 V

AVDD3V = 3.1 V

AVDD3V = 3.2 V

AVDD3V = 3.3 V

AVDD3V = 3.4 V

AVDD3V = 3.5 V

AVDD3V = 3.6 V

69.5

69

68.5

68

-40

-15

10 35

Temperature (°C)

60

85

-40

-15

10 35

Temperature (°C)

60

85

D028

D029

f_IN= 170 MHz

图 7-31. Signal-to-Noise Ratio vs AVDD3V Supply 图 7-32. Spurious-Free Dynamic Range vs AVDD3V

and Temperature Supply and Temperature

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71

70

69

68

67

66

65

82

80

78

76

74

72

AVDD3V = 2.85 V

AVDD3V = 3 V

AVDD3V = 3.1 V

AVDD3V = 3.2 V

AVDD3V = 3.3 V

AVDD3V = 3.4 V

AVDD3V = 3.5 V

AVDD3V = 3.6 V

AVDD3V = 2.85 V

AVDD3V = 3 V

AVDD3V = 3.1 V

AVDD3V = 3.2 V

AVDD3V = 3.3 V

AVDD3V = 3.4 V

AVDD3V = 3.5 V

AVDD3V = 3.6 V

64

-40

-15

10 35

Temperature (°C)

60

85

-40

-15

10 35

Temperature (°C)

60

85

D030

D031

f_IN= 350 MHz

图 7-33. Signal-to-Noise Ratio vs AVDD3V Supply

图 7-34. Spurious-Free Dynamic Range vs AVDD3V

and Temperature

Supply and Temperature

79

110

Gain = 0 dB

Gain = 2 dB

Gain = 4 dB

Gain = 6 dB

Gain = 8 dB

Gain = 10 dB

Gain = 12 dB

Gain = 0 dB

Gain = 2 dB

Gain = 4 dB

Gain = 6 dB

Gain = 8 dB

Gain = 10 dB

Gain = 12 dB

105

100

95

76

73

70

67

64

61

58

55

90

85

80

75

70

65

0

80

160

Input Frequency (MHz)

240

320

400

480

0

80

160

Input Frequency (MHz)

240

320

400

480

D053

D054

图 7-35. Signal-to-Noise Ratio vs Gain and Input

图 7-36. Spurious-Free Dynamic Range vs Gain

Frequency

and Input Frequency

2

0

75

73

71

69

67

65

200

160

120

80

SNR (dBFS)

SFDR (dBc)

SFDR (dBFS)

-2

-4

-6

40

-8

-10

0

100 200 300 400 500 600 700 800 900 1000

Input Frequency (MHz)

-70

-60

-50

-40 -30

Amplitude (dBFS)

-20

-10

0

D046

D032

f_IN= 170 MHz

图 7-37. Maximum Supported Amplitude vs

Frequency

图 7-38. Performance vs Input Amplitude

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74

180

150

120

90

76

74

72

70

68

66

110

SNR (dBFS)

SFDR (dBc)

SFDR (dBFS)

SNR

SFDR

72.5

71

100

90

69.5

68

80

60

70

66.5

30

65

0

60

-70

-60

-50

-40 -30

Amplitude (dBFS)

-20

-10

0

0.2

0.6

1

Differential Clock Amplitude (Vpp)

1.4

1.8

2.2

D033

D034

f_IN= 350 MHz

f_IN= 170 MHz

图 7-39. Performance vs Input Amplitude

图 7-40. Performance vs Sampling Clock Amplitude

75

72

69

66

63

60

125

100

75

50

25

0

73

72

71

70

69

68

100

95

90

85

80

75

SNR

SFDR

SNR

SFDR

0.2

0.6

1

Differential Clock Amplitude (Vpp)

1.4

1.8

2.2

30

35

40

45

50

Input Clock Duty Cycle (%)

55

60

65

70

D035

D036

f_IN= 350 MHz

f_IN= 170 MHz

图 7-41. Performance vs Sampling Clock Amplitude

图 7-42. Performance vs Input Clock Duty Cycle

72

71

70

69

68

67

66

65

88

84

80

76

72

68

64

60

-10

SNR

SFDR

PSRR with 25-mV_ppSignal on AVDD

PSRR with 50-mV_ppSignal on AVDD3V

-15

-20

-25

-30

-35

-40

-45

-50

-55

-60

30

35

40

45

Input Clock Duty Cycle (%)

50

55

60

65

70

0

50

100

Frequency of Signal on Supply (MHz)

150

200

250

300

D037

D038

f_IN= 350 MHz

f_IN= 170 MHz

图 7-43. Performance vs Input Clock Duty Cycle

图 7-44. Power-Supply Rejection Ratio vs Test

Signal Frequency

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0

-20

-25

-30

-35

-40

-45

-50

-55

-40

-60

-80

-100

-120

0

100

200 300

Input Frequency (MHz)

400

500

0

50

100

150

Frequency of Input Common-Mode Signal (MHz)

200

250

300

D039

D040

f_IN= 170 MHz

f_IN= 170 MHz , A_IN= –1 dBFS, SINAD = 65.7 dBFS, SFDR =

79 dBc, f_PSRR= 5 MHz, A_PSRR= 25 mV_PP, amplitude of f_IN

–

图 7-46. Common-Mode Rejection Ratio vs Test

f_PSRR= –74 dBFS, amplitude of f_IN+ f_PSRR= –76 dBFS

Signal Frequency

图 7-45. Power-Supply Rejection Ratio FFT for Test

Signals on the AVDD Supply

0

-20

4

3.5

3

-40

-60

2.5

2

-80

-100

-120

1.5

1

0

100

200 300

Input Frequency (MHz)

400

500

500 550 600 650 700 750 800 850 900 950 1000

Sampling Speed (MSPS)

D041

D042

f_IN= 170.1 MHz , A_IN= –1 dBFS, f_CMRR= 5 MHz, A_CMRR= 50

图 7-48. Power Consumption vs Sampling Speed

mV_PP, SINAD = 67.3 dBFS, SFDR = 85 dBc, amplitude of f_IN

±

f_CMRR= –80 dBFS

图 7-47. Common-Mode Rejection Ratio FFT

800

700

600

500

400

300

200

100

2.78

2.76

2.74

2.72

2.7

0

-20

I _DVDD(mA)

I _AVDD(mA)

I _IOVDD(mA)

I _AVDD3(mA)

Total Power (W)

-40

-60

-80

2.68

2.66

2.64

-100

-120

-40

-15

10 35

Temperature (°C)

60

85

0

25

50 75

Input Frequency (MHz)

100

125

D045

D047

SNR = 73.1 dBFS, SFDR = 88.6 dBc

图 7-49. Power vs Temperature

图 7-50. FFT for 60-MHz Input Signal in Decimate-

by-4 Mode

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0

-20

0

-20

-40

-60

-80

-100

-120

-100

-120

0

25

50 75

Input Frequency (MHz)

100

125

0

25

50 75

Input Frequency (MHz)

100

125

D048

D049

SNR = 72.5 dBFS, SFDR = 87 dBc

SNR = 71.1 dBFS, SFDR = 86 dBc

图 7-51. FFT for 170-MHz Input Signal in Decimate- 图 7-52. FFT for 300-MHz Input Signal in Decimate-

by-4 Mode

0

-20

-40

-60

-80

-100

-120

-100

-120

0

25

50 75

Input Frequency (MHz)

100

125

0

50

100 150

Input Frequency (MHz)

200

250

D050

D051

SNR = 68.7 dBFS, SFDR = 83 dBc

SNR = 70.5 dBFS, SFDR = 86 dBc

图 7-53. FFT for 450-MHz Input Signal in Decimate- 图 7-54. FFT for 170-MHz Input Signal in Decimate-

by-4 Mode by-2 Mode

0

-20

-40

-60

-80

-100

-120

0

50

100 150

Input Frequency (MHz)

200

250

D052

SNR = 67.6 dBFS, SFDR = 80 dBc

图 7-55. FFT for 350-MHz Input Signal in Decimate-by-2 Mode

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8 Detailed Description

8.1 Overview

The ADS54J40 is a low-power, wide-bandwidth, 14-bit, 1.0-GSPS, dual-channel, analog-to-digital converter

(ADC). The ADS54J40 employs four interleaving ADCs for each channel to achieve a noise floor of –

159 dBFS/Hz. The ADS54J40 uses TI's proprietary interleaving and dither algorithms to achieve a clean

spectrum with a high spurious-free dynamic range (SFDR). The device also offers various programmable

decimation filtering options for systems requiring higher signal-to-noise ratio (SNR) and SFDR over a wide range

of frequencies.

Analog input buffers isolate the ADC driver from glitch energy generated from sampling process, thereby simplify

the driving network on-board. The JESD204B interface reduces the number of interface lines with two-lane and

four-lane options, allowing a high system integration density. The JESD204B interface operates in subclass 1,

enabling multi-chip synchronization with the SYSREF input.

8.2 Functional Block Diagram

DA0P, DA0M,

DA1P, DA1M

DDC Block:

2x, 4x Decimation

Mixer: f_S/ 16, f_S/ 4

Buffer

Digital Block

ADC

Interleaving

Correction

INAP, INAM

DA2P, DA2M,

DA3P, DA3M

PLL:

x20

x40

Divide-by-

4

CLKINP,

CLKINM

SYNC

SYSREFP,

SYSREFM

DDC Block:

2X, 4X Decimation

Mixer: f_S/ 16, f_S/ 4

DB0P, DB0M,

DB1P, DB1M

Buffer

Digital Block

ADC

Interleaving

Correction

INBP, INBM

DB2P, DB2M,

DB3P, DB3M

FOVR

Control and SPI

Common

Mode

VCM

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8.3 Feature Description

8.3.1 Analog Inputs

The ADS54J40 analog signal inputs are designed to be driven differentially. The analog input pins have internal

analog buffers that drive the sampling circuit. As a result of the analog buffer, the input pins present a high

impedance input across a very wide frequency range to the external driving source that enables great flexibility

in the external analog filter design as well as excellent 50-Ω matching for RF applications. The buffer also helps

isolate the external driving circuit from the internal switching currents of the sampling circuit, resulting in a more

constant SFDR performance across input frequencies.

The common-mode voltage of the signal inputs is internally biased to VCM using 600-Ω resistors, allowing for

ac-coupling of the input drive network. Each input pin (INP, INM) must swing symmetrically between (VCM +

0.475 V) and (VCM – 0.475 V), resulting in a 1.9-V_PP(default) differential input swing. The input sampling circuit

has a 3-dB bandwidth that extends up to 1.2 GHz. An equivalent analog input network diagram is shown in 图

8-1.

0.77 W

1 W

3.3 W

2 nH

0.6 W

150 fF

200 fF

3 pF

375 fF

INP

40 W

500 fF

150 fF

0.77 W

1 W

3.3 W

600 W

150 fF

200 fF

3 pF

VCM

40 W

600 W

0.77 W

1 W

3.3 W

150 fF

200 fF

3 pF

2 nH

0.6 W

INM

40 W

500 fF

150 fF

0.77 W

1 W

3.3 W

150 fF

200 fF

3 pF

40 W

图 8-1. Analog Input Network

28

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The input bandwidth shown in 图 8-2 is measured with respect to a 50-Ω differential input termination at the

ADC input pins. Figure x shows the signal processing done inside the DDC block of the ADS54J40.

0

-3

-6

-9

-12

-15

-18

0

200 400 600 800 1000 1200 1400 1600 1800 2000

Input Frequency (MHz)

D056

图 8-2. Transfer Function vs Frequency

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8.3.2 DDC Block

The ADS54J40 has an optional DDC block that can be enabled via an SPI register write. Each ADC channel is

followed by a DDC block consisting of three different decimate-by-2 and decimate-by-4 finite impulse response

(FIR) half-band filter options. The different decimation filter options can be selected through SPI programming.图

8-3 shows the signal processing done inside the DDC block of the ADS54J40

Default 14-Bit Data (At 1 GSPS)

Decimate-by-2 Data (At 500 MSPS)

LPF

BPF

2

4

Decimate-by-4 Data (At 250 MSPS)

Interleaving

Engine,

Digital

Features

Ch X

1 GSPS Data,

x(n)

To JESD

Encoder

4

LPF

Decimate-by-4, I-Data (At 250 MSPS)

cos(2 n Œ f_mix/ f_S)⁽¹⁾

sin(2 n Œ f_mix/ f_S)⁽¹⁾

Decimate-by-4 Q-Data (At 250 MSPS)

4

LPF

Mode Selection Using DECFIL

MODE[3:0] Register Bits

A. In IQ decimate-by-4 mode, the mixer frequency is fixed at f_mix= f_S/ 4. For f_S= 1 GSPS and f_mix= 250 MHz.

图 8-3. DDC Block

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8.3.2.1 Decimate-by-2 Filter

This decimation filter has 41 taps. The stop-band attenuation is approximately 90 dB and the pass-band flatness

is ±0.05 dB. 表 8-1 shows corner frequencies for low-pass and high-pass filter options.

表 8-1. Corner Frequencies for the Decimate-by-2 Filter

CORNERS (dB)

LOW PASS

0.202 × f_S

0.210 × f_S

0.215 × f_S

0.227 × f_S

HIGH PASS

0.298 × f_S

0.290 × f_S

0.285 × f_S

0.273 × f_S

–0.1

–0.5

–1

–3

图 8-4 and 图 8-5 show the frequency response of decimate-by-2 filter from dc to f_S/ 2.

5

0.5

0

-20

-0.5

-1

-45

-1.5

-2

-70

-95

-2.5

-3

-120

0

0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5

Frequency Response

0

0.05

0.1 0.15

Frequency Response

0.2

0.25

D013

D014

图 8-4. Decimate-by-2 Filter Response

图 8-5. Decimate-by-2 Filter Response (Zoomed)

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8.3.2.2 Decimate-by-4 Filter Using a Digital Mixer

This band-pass decimation filter consists of a digital mixer and three concatenated FIR filters with a combined

latency of approximately 28 output clock cycles. The alias band attenuation is approximately

55 dB and the pass-band flatness is ±0.1 dB. By default after reset, the band-pass filter is centered at f_S/ 16.

Using the SPI, the center frequency can be programmed at N × f_S/ 16 (where N = 1, 3, 5, or 7). 表 8-2 shows

corner frequencies for two extreme options.

表 8-2. Corner frequencies for the Decimate-by-4 Filter

CORNER FREQUENCY AT LOWER SIDE

(Center Frequency f_S/ 16)

CORNER FREQUENCY AT HIGHER SIDE

(Center Frequency f_S/ 16)

CORNERS (dB)

0.011 × f_S

0.010 × f_S

0.008 × f_S

0.006 × f_S

0.114 × f_S

0.116 × f_S

0.117 × f_S

0.120 × f_S

–0.1

–0.5

–1

–3

图 8-6 and 图 8-7 show the frequency response of the decimate-by-4 filter for center frequencies f_S/ 16 and 3 ×

f_S/ 16 (N = 1 and N = 3, respectively).

10

0

0.2

0.1

0

-10

-20

-30

-40

-50

-60

-70

-80

-0.1

-0.2

-0.3

-0.4

-0.5

-0.6

-0.7

-0.8

-0.9

-1

0

0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5

Frequency Response

0

0.05

0.1 0.15

Frequency Response

0.2

0.25

D015

D016

图 8-6. Decimate-by-4 Filter Response

图 8-7. Decimate-by-4 Filter Response (Zoomed)

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8.3.2.3 Decimate-by-4 Filter with IQ Outputs

In this configuration, the DDC block includes a fixed digital f_S/ 4 mixer. Thus, the IQ pass band is approximately

±110 MHz, centered at f_S/ 4. This decimation filter has 41 taps with a latency of approximately ten output clock

cycles. The stop-band attenuation is approximately 90 dB and the pass-band flatness is ±0.05 dB. 表 8-3 shows

the corner frequencies for a low-pass, decimate-by-4 IQ filter.

表 8-3. Corner Frequencies for a Decimate-by-4 IQ Output Filter

CORNERS (dB)

LOW PASS

0.107 × f_S

0.112 × f_S

0.115 × f_S

0.120 × f_S

–0.1

–0.5

–1

–3

图 8-8 and 图 8-9 show the frequency response of a decimate-by-4 IQ output filter from dc to f_S/ 2.

5

0.5

0

-20

-0.5

-1

-45

-1.5

-2

-70

-95

-2.5

-3

-120

0

0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5

Frequency Response

0

0.025

0.05 0.075

Frequency Response

0.1

0.125

D012

D011

图 8-8. Decimate-by-4 IQ Output Filter Response

图 8-9. Decimate-by-4 IQ Output Filter Response

(Zoomed)

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8.3.3 SYSREF Signal

The SYSREF signal is a periodic signal that is sampled by the ADS54J40 device clock and used to align the

boundary of the local multi-frame clock inside the data converter. SYSREF is required to be a sub-harmonic of

the local multiframe clock (LMFC) internal timing. To meet this requirement, the timing of SYSREF is dependent

on the device clock frequency and the LMFC frequency, as determined by the selected DDC decimation and

frames per multi-frame settings. The SYSREF signal is recommended to be a low-frequency signal in the range

of 1 MHz to 5 MHz to reduce coupling to the signal path both on the printed circuit board (PCB) as well as

internal in the device.

The external SYSREF signal must be a sub-harmonic of the internal LMFC clock, as shown in 方程式 1 and 表

8-4.

SYSREF = LMFC / 2^N

(1)

where

• N = 0, 1, 2, and so forth.

表 8-4. Local Multi-Frame Clock Frequency

LMFS CONFIGURATION

DECIMATION

LMFC CLOCK^{(1) (2)}

f_S/ K

4211

4244

8224

4222

2242

2221

2441

4421

1241

—

(f_S/ 4) / K

—

2X

4X

4X (IQ)

4X

(1) K = Number of frames per multi frame (JESD digital page 6900h, address 06h, bits 4-0).

(2) f_S= sampling (device) clock frequency.

For example, if LMFS = 8224 then the programmed value of K is 9 (the actual value is 9 + 1 = 10 because the

actual value for K = the value set in the SPI register +1). If the device clock frequency is f_S= 1000 MSPS, then

the local multi-frame clock frequency becomes (1000 / 4) / 10 = 25 MHz. The SYSREF signal frequency can be

chosen as the LMFC frequency / 8 = 3.125 MHz.

8.3.3.1 SYSREF Not Present (Subclass 0, 2)

A SYSREF pulse is required by the ADS54J40 to reset internal counters. If SYSREF is not present, as can be

the case in subclass 0 or 2, this pulse can be done by doing the following register writes shown in 表 8-5.

表 8-5. Internally Pulsing SYSREF Twice Using Register Writes

ADDRESS (Hex)

DATA (Hex)

COMMENT

Set the master page

Enable manual SYSREF

Set SYSREF high

Set SYSREF low

0-011h

80h

0-054h

80h

0-053h

01h

0-053h

00h

0-053h

01h

Set SYSREF high

Set SYSREF low

0-053h

00h

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8.3.4 Overrange Indication

The ADS54J40 provides a fast overrange indication that can be presented in the digital output data stream via

SPI configuration. Alternatively, if not used, the SDOUT (pin 11) and PDN (pin 50) pins can be configured

through the SPI to output the fast OVR indicator.

JESD 8b/10b encoder receives 16-bit data that is formed by 14-bit ADC data padded with two 0s as LSBs. When

the FOVR indication is embedded in the output data stream, it replaces the LSB of the 16-bit data stream going

to the 8b/10b encoder, as shown in 图 8-10.

16-Bit Data Output (14-Bit ADC Data Padded with Two 0s)

0,

OVR

D13 D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

0

16-Bit Data Going to the 8b, 10b Encoder

图 8-10. Overrange Indication in a Data Stream

8.3.4.1 Fast OVR

The fast OVR is triggered if the input voltage exceeds the programmable overrange threshold and is presented

after only 18 clock cycles + t_PD(t_PDof the gates and buffers is approximately 4 ns), thus enabling a quicker

reaction to an overrange event.

The input voltage level that the overload is detected at is referred to as the threshold. The threshold is

programmable using the FOVR THRESHOLD bits, as shown in 图 8-11. The FOVR is triggered 18 clock cycles +

t_PD(t_PDof the gates and buffers is approximately 4 ns) after the overload condition occurs.

0

-5

-10

-15

-20

-25

-30

-35

-40

-45

-50

0

32

64

96

128

160

Threshold Decimal Value

192

224

255

D055

图 8-11. Programming Fast OVR Thresholds

The input voltage level that the fast OVR is triggered at is defined by 方程式 2:

Full-Scale × [Decimal Value of the FOVR Threshold Bits] / 255)

(2)

(3)

The default threshold is E3h (227d), corresponding to a threshold of –1 dBFS.

In terms of full-scale input, the fast OVR threshold can be calculated as 方程式 3:

20log (FOVR Threshold / 255)

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8.4 Device Functional Modes

8.4.1 Power-Down Mode

The ADS54J40 provides a highly-configurable power-down mode. Power-down can be enabled using the PDN

pin or SPI register writes.

A power-down mask can be configured that allows a trade-off between wake-up time and power consumption in

power-down mode. Two independent power-down masks can be configured: MASK 1 and MASK 2, as shown in

表 8-6. See the master page registers in Register Maps for further details.

表 8-6. Register Address for Power-Down Modes

REGISTER

ADDRESS

REGISTER DATA

COMMENT

A[7:0] (Hex)

MASTER PAGE (80h)

20

7

6

5

4

3

2

1

0

PDN ADC CHA

PDN BUFFER CHB

PDN ADC CHA

PDN BUFFER CHB

PDN ADC CHB

MASK 1

21

23

24

PDN BUFFER CHA

0

PDN ADC CHB

MASK 2

CONFIG

0

OVERRIDE

PDN PIN

PDN MASK

26

55

GLOBAL PDN

0

SEL

0

PDN MASK

To save power, the device can be put in complete power-down by using the GLOBAL PDN register bit. However,

when JESD must remain linked up when putting the device in power-down, the ADC and analog buffer can be

powered down by using the PDN ADC CHx and PDN BUFFER CHx register bits after enabling the PDN MASK

register bit. The PDN MASK SEL register bit can be used to select between MASK 1 or MASK 2. 表 8-7 shows

power consumption for different combinations of the GLOBAL PDN, PDN ADC CHx, and PDN BUFF CHx

register bits.

表 8-7. Power Consumption in Different Power-Down Settings

I_AVDD3V

(mA)

TOTAL

REGISTER BIT

Default

COMMENT

I_AVDD(mA) I_DVDD(mA) I_IOVDD(mA) POWER (W)

After reset, with a full-scale input signal

to both channels

336

2

358

6

198

22

533

199

2.68

0.29

The device is in complete power-down

state

GBL PDN = 1

GBL PDN = 0,

PDN ADC CHx = 1

(x = A or B)

The ADC of one channel is powered

down

274

262

223

352

135

194

512

545

2.09

2.45

GBL PDN = 0,

PDN BUFF CHx = 1

(x = A or B)

The input buffer of one channel is

powered down

GBL PDN = 0,

PDN ADC CHx = 1, PDN The ADC and input buffer of one

198

60

222

85

132

66

508

484

1.85

1.02

BUFF CHx = 1

(x = A or B)

channel is powered down

GBL PDN = 0,

PDN ADC CHx = 1, PDN The ADC and input buffer of both

BUFF CHx = 1

(x = A and B)

channels are powered down

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8.4.2 Device Configuration

The ADS54J40 can be configured by using a serial programming interface, as described in the Serial Interface

section. In addition, the device has one dedicated parallel pin (PDN) for controlling the power-down mode.

The ADS54J40 supports a 24-bit (16-bit address, 8-bit data) SPI operation and uses paging (see the Register

Maps section) to access all register bits.

8.4.2.1 Serial Interface

The ADC has a set of internal registers that can be accessed by the serial interface formed by the SEN (serial

interface enable), SCLK (serial interface clock), and SDIN (serial interface data) pins, as shown in 图 8-12.

Legends used in 图 8-12 are explained in 表 8-8. Serially shifting bits into the device is enabled when SEN is

low. Serial data on SDIN are latched at every SCLK rising edge when SEN is active (low). The interface can

function with SCLK frequencies from 2 MHz down to very low speeds (of a few Hertz) and also with a non-50%

SCLK duty cycle.

Register Address[11:0]

Register Data[7:0]

SDIN

R/W

M

P

CH

A11

A10

A9

A8

A7

A6

A5

A4

A3

A2

A1

A0

D7

D6

D5

D4

D3

D2

D1

t_DH

D0

t_SCLK

t_DSU

SCLK

SEN

t_SLOADS

t_SLOADH

RESET

图 8-12. SPI Timing Diagram

表 8-8. SPI Timing Diagram Legend

SPI BITS

DESCRIPTION

BIT SETTINGS

0 = SPI write

1 = SPI read back

R/W

M

Read/write bit

0 = Analog SPI bank (master and ADC pages)

1 = JESD SPI bank (main digital, JESD analog, and

JESD digital pages)

SPI bank access

JESD page selection bit

0 = Page access

1 = Register access

P

0 = Channel A

1 = Channel B

By default, both channels are being addressed.

SPI access for a specific channel of the JESD SPI

bank

CH

A[11:0]

D[7:0]

SPI address bits

SPI data bits

—

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表 8-9 shows the timing requirements for the serial interface signals in 图 8-12.

表 8-9. SPI Timing Requirements

MIN

TYP

MAX

UNIT

MHz

ns

f_SCLK

t_SLOADS

t_SLOADH

t_DSU

SCLK frequency (equal to 1 / t_SCLK

SEN to SCLK setup time

SCLK to SEN hold time

SDIN setup time

)

> dc

100

2

ns

t_DH

SDIN hold time

ns

8.4.2.2 Serial Register Write: Analog Bank

The analog SPI bank contains of two pages (the master and ADC page). The internal register of the ADS54J40

analog SPI bank can be programmed by:

1. Driving the SEN pin low.

2. Initiating a serial interface cycle specifying the page address of the register whose content must be written.

• Master page: write address 0011h with 80h.

• ADC page: write address 0011h with 0Fh.

3. Writing the register content as shown in 图 8-13. When a page is selected, multiple writes into the same

page can be done.

Register Address[11:0]

Register Data[7:0]

0

SDIN

SCLK

R/W

M

P

CH A11 A10

A9

A8

A7

A6

A5

A4

A3

A2

A1

A0

D7

D6

D5

D4

D3

D2

D1

D0

SEN

RESET

图 8-13. Serial Register Write Timing Diagram

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8.4.2.3 Serial Register Readout: Analog Bank

The content from one of the two analog banks can be read out by:

1. Driving the SEN pin low.

2. Selecting the page address of the register whose content must be read.

• Master page: write address 0011h with 80h.

• ADC page: write address 0011h with 0Fh.

3. Setting the R/W bit to 1 and writing the address to be read back.

4. Reading back the register content on the SDOUT pin, as shown in 图 8-14. When a page is selected,

multiple read backs from the same page can be done. SDOUT comes out at the SCLK falling edge with an

approximate delay (t_{SD_DELAY}) of 68 ns; see 图 8-18.

Register Address[11:0]

Register Data[7:0] = XX

1

0

SDIN

SCLK

R/W

M

P

CH

A11

A10

A9

A8

A7

A6

A5

A4

A3

A2

A1

A0

D7

D6

D5

D4

D3

D2

D1

D0

SEN

RESET

SDOUT

D7

D6

D5

D4

D3

D2

D1

D0

SDOUT[7:0]

图 8-14. Serial Register Read Timing Diagram

8.4.2.4 JESD Bank SPI Page Selection

The JESD SPI bank contains four pages (main digital, JESD digital, and JESD analog pages). The individual

pages can be selected by:

1. Driving the SEN pin low.

2. Setting the M bit to 1 and specifying the page with two register writes. Note that the P bit must be set to 0, as

shown in 图 8-15.

• Write address 4003h with 00h (LSB byte of the page address).

• Write address 4004h with the MSB byte of the page address.

– For the main digital page: write address 4004h with 68h.

– For the JESD digital page: write address 4004h with 69h.

– For the JESD analog page: write address 4004h with 6Ah.

Register Address[11:0]

Register Data[7:0]

0

1

0

SDIN

SCLK

R/W

M

P

CH A11 A10 A9

A8

A7

A6

A5

A4

A3

A2

A1

A0

D7

D6

D5

D4

D3

D2

D1

D0

SEN

RESET

图 8-15. SPI Page Selection

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8.4.2.5 Serial Register Write: JESD Bank

The ADS54J40 is a dual-channel device and the JESD204B portion is configured individually for each channel

by using the CH bit. Note that the P bit must be set to 1 for register writes.

1. Drive the SEN pin low.

2. Select the JESD bank page. Note that the M bit = 1 and the P bit = 0.

• Write address 4003h with 00h.

• Write address 4005h with 01h to enable separate control for both channels.

– For the main digital page: write address 4004h with 68h.

– For the JESD digital page: write address 4004h with 69h.

– For the JESD analog page: write address 4004h with 6Ah.

3. Set the M and P bits to 1, select channel A (CH = 0) or channel B (CH = 1), and write the register content as

shown in 图 8-16. When a page is selected, multiple writes into the same page can be done.

Register Address[11:0]

Register Data[7:0]

0

1

0

SDIN

SCLK

R/W

M

P

CH A11 A10

A9

A8

A7

A6

A5

A4

A3

A2

A1

A0

D7

D6

D5

D4

D3

D2

D1

D0

SEN

RESET

图 8-16. JESD Serial Register Write Timing Diagram

8.4.2.5.1 Individual Channel Programming

By default, register writes are applied to both channels. To enable individual channel writes, write address 4005h

with 01h (default is 00h).

8.4.2.6 Serial Register Readout: JESD Bank

The content from one of the pages of the JESD bank can be read out by:

1. Driving the SEN pin low.

2. Selecting the JESD bank page. Note that the M bit = 1 and the P bit = 0.

• Write address 4003h with 00h.

• Write address 4005h with 01h to enable separate control for both channels.

– For the main digital page: write address 4004h with 68h.

– For the JESD digital page: write address 4004h with 69h.

– For the JESD analog page: write address 4004h with 6Ah.

3. Setting the R/W, M, and P bits to 1, selecting channel A or channel B, and writing the address to be read

back.

4. Reading back the register content on the SDOUT pin; see 图 8-17. When a page is selected, multiple read

backs from the same page can be done. SDOUT comes out at the SCLK falling edge with an approximate

delay (t_{SD_DELAY}) of 68 ns; see 图 8-18.

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Register Address[11:0]

Register Data[7:0] = XX

1

0

SDIN

SCLK

R/W

M

P

CH A11 A10 A9

A8

A7

A6

A5

A4

A3

A2

A1

A0

D7

D6

D5

D4

D3

D2

D1

D0

SEN

RESET

SDOUT

D7

D6

D5

D4

D3

D2

D1

D0

SDOUT[7:0]

图 8-17. JESD Serial Register Read Timing Diagram

SCLK

t_{SD_DELAY}

SDOUT

图 8-18. SDOUT Timing Diagram

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8.4.3 JESD204B Interface

The ADS54J40 supports device subclass 1 with a maximum output data rate of 10.0 Gbps for each serial

transmitter.

An external SYSREF signal is used to align all internal clock phases and the local multi-frame clock to a specific

sampling clock edge, allowing synchronization of multiple devices in a system and minimizing timing and

alignment uncertainty. The SYNC input is used to control the JESD204B SERDES blocks.

Depending on the ADC output data rate, the JESD204B output interface can be operated with either two or four

lanes per single ADC, as shown in 图 8-19. The JESD204B setup and configuration of the frame assembly

parameters is controlled through the SPI interface.

SYSREF

SYNC

JESD204B

DA[3:0]

INA

INB

JESD204B

DB[3:0]

Sample Clock

图 8-19. ADS54J40 Block Diagram

The JESD204B transmitter block shown in 图 8-20 consists of the transport layer, the data scrambler, and the

link layer. The transport layer maps the ADC output data into the selected JESD204B frame data format. The link

layer performs the 8b/10b data encoding as well as the synchronization and initial lane alignment using the

SYNC input signal. Optionally, data from the transport layer can be scrambled.

JESD204B Block

Transport Layer

Link Layer

8b, 10b

Encoding

Frame Data

Mapping

Scrambler

1 + x¹⁴+ x¹⁵

D[3:0]

Comma Characters,

Initial Lane Alignment

SYNC

图 8-20. JESD204B Transmitter Block

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8.4.3.1 JESD204B Initial Lane Alignment (ILA)

The initial lane alignment process is started when the receiving device de-asserts the SYNC signal, as shown in

图 8-21. When a logic low is detected on the SYNC input pin, the ADS54J40 starts transmitting comma (K28.5)

characters to establish a code group synchronization.

When synchronization is complete, the receiving device asserts the SYNC signal and the ADS54J40 starts the

initial lane alignment sequence with the next local multi-frame clock boundary. The ADS54J40 transmits four

multi-frames, each containing K frames (K is SPI programmable). Each of the multi-frames contains the frame

start and end symbols and the second multi-frame also contains the JESD204 link configuration data.

SYSREF

LMFC Clock

LMFC Boundary

Multi

Frame

SYNC

Transmit Data

xxx

K28.5

ILA

DATA

Code Group

Synchronization

Initial Lane

Alignment

Data Transmission

图 8-21. Lane Alignment Sequence

8.4.3.2 JESD204B Test Patterns

There are three different test patterns available in the transport layer of the JESD204B interface. The ADS54J40

supports a clock output-encoded test pattern, and a 12-octet RPAT. These test patterns can be enabled via an

SPI register write and are located in the JESD digital page of the JESD bank.

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8.4.3.3 JESD204B Frame

The JESD204B standard defines the following parameters:

• L is the number of lanes per link.

• M is the number of converters per device.

• F is the number of octets per frame clock period, per lane.

• S is the number of samples per frame per converter.

表 8-10 lists the available JESD204B formats and valid ranges for the ADS54J40 when the decimation filter is

not used. The ranges are limited by the SERDES lane rate and the maximum ADC sample frequency.

Note

16-bit data going to JESD 8b/10b encoder is formed by padding two 0s as LSBs into the 14-bit ADC

data.

表 8-10. Default Interface Rates

MINIMUM RATES

MAXIMUM RATES

L

M

F

S

DECIMATION

SAMPLING RATE

SERDES BIT

RATE (Gbps)

SAMPLING RATE

SERDES BIT

RATE (Gbps)

(MSPS)

4

8

2

1

4

2

1

4

Not used

250

2.5

1000

10.0

5.0

250

1000

500

1000

Note

In the LMFS = 8224 row of 表 8-10, the sample order in lane DA2 and DA3 are swapped.

The detailed frame assembly is shown in 表 8-11.

表 8-11. Default Frame Assembly

DA0

DA1

DA2

DA3

DB0

DB1

DB2

DB3

LMFS = 4211

LMFS = 4244

LMFS = 8224

A₃[15:8]

A₂[15:8]

A₀[15:8]

A₁[15:8]

B₃[15:8]

B₂[15:8]

B₀[15:8]

B₁[15:8]

A₃[7:0]

A₂[7:0]

A₀[7:0]

A₁[7:0]

B₃[7:0]

B₂[7:0]

B₀[7:0]

B₁[7:0]

A₀[7:0]

A₂[15:8]

A₀[15:8]

A₂[7:0]

A₃[15:8]

A₁[15:8]

A₃[7:0]

A₁[7:0]

A₀[15:8]

A₀[7:0]

B₀[7:0]

B₂[15:8]

B₀[15:8]

B₂[7:0]

B₀[7:0]

B₃[15:8]

B₁[15:8]

B₃[7:0]

B₁[7:0]

B₀[15:8]

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8.4.3.4 JESD204B Frame Assembly with Decimation

表 8-12 lists the available JESD204B formats and valid ranges for the ADS54J40 when enabling the decimation

filter. The ranges are limited by the SERDES line rate and the maximum ADC sample frequency.

表 8-13 lists the detailed frame assembly with different decimation options.

表 8-12. Interface Rates with Decimation Filter

MINIMUM RATES

MAXIMUM RATES

DEVICE

CLOCK

FREQUENCY

(MSPS)

DEVICE

CLOCK

FREQUENCY

(MSPS)

OUTPUT

SAMPLE RATE

(MSPS)

OUTPUT

SAMPLE RATE

(MSPS)

L

M

F

S

DECIMATION

SERDES BIT

RATE (Gbps)

SERDES BIT

RATE (Gbps)

4

2

1

4

2

4

2

4

2

4

1

2

1

4X (IQ)

2X

500

300

500

300

125

250

150

125

75

2.5

3

1000

250

500

250

5.0

2X

10.0

5.0

4X

2.5

3

4X (IQ)

4X

10.0

75

3

表 8-13. Frame Assembly with Decimation Filter

LMFS = 4222, 2X

DECIMATION

LMFS = 2242, 2X

DECIMATION

LMFS = 2221, 4X

DECIMATION

LMFS = 2441, 4X

DECIMATION (IQ)

LMFS = 4421, 4X

DECIMATION (IQ)

LMFS = 1241, 4X

DECIMATION

DA0

DA1

A1

AQ0

[15:8]

AQ0

[7:0]

[15:8]

[7:0]

A0

A1

A0

AI0

AI0 AQ0 AQ0

AI0

A0

B0

[15:8]

[7:0]

[15:8] [7:0] [15:8] [7:0]

[15:8]

[7:0]

[15:8] [7:0] [15:8] [7:0]

[15:8]

[7:0]

[15:8] [7:0] [15:8] [7:0]

DA2

DA3

B1

[15:8]

B1

[7:0]

BQ0

[15:8]

BQ0

[7:0]

DB0

DB1

B0

[15:8]

B0

[7:0]

B0

B1

B0

[15:8]

B0

[7:0]

BI0

BI0 BQ0 BQ0

BI0

[15:8]

BI0

[7:0]

[15:8] [7:0] [15:8] [7:0]

DB2

DB3

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表 8-14. Program Summary of DDC Modes and JESD Link Configuration

LMFS

OPTIONS

DDC MODES PROGRAMMING

JESD LINK (LMFS) PROGRAMMING

DEC

DECIMATI

ON

OPTIONS

DA_BUS_ DB_BUS_ BUS_REO BUS_REO

MODE EN,

DECFIL

EN⁽¹⁾

DECFIL

JESD

JESD PLL

MODE⁽⁵⁾

LANE

L

M

F

S

REORDER REORDER

RDER

MODE[3:0]⁽²⁾

FILTER⁽³⁾

MODE⁽⁴⁾

SHARE⁽⁶⁾

(7)

(8)

EN1⁽⁹⁾

EN2⁽¹⁰⁾

No

decimation

4

2

1

4

1

4

00

000

100

010

10

0

00h

0

No

decimation

No

decimation

(default

8

2

4

00

000

001

00

0

00h

0

after reset)

0011 (LPF with

f_S/ 4 mixer)

4

2

4

2

4

1

2

4X (IQ)

2X

11

111

110

001

010

00

10

0

0Ah

1

0010 (LPF) or

0110 (HPF)

0010 (LPF) or

0110 (HPF)

2X

0000, 0100,

1000, or 1100 (all

BPFs with

different center

frequencies).

2

1

2

4

2

4

1

4X

4X (IQ)

4X

11

100

111

100

001

010

00

10

0

1

0Ah

1

0011 (LPF with

an f_S/ 4 mixer)

0000, 0100,

1000, or 1100 (all

BPFs with

different center

frequencies)

(1) The DEC MODE EN and DECFIL EN register bits are located in the main digital page, register 04Dh (bit 3) and register 041h (bit 4).

(2) The DECFIL MODE[3:0] register bits are located in the main digital page, register 041h (bits 5 and 2-0).

(3) The JESD FILTER register bits are located in the JESD digital page, register 001h (bits 5-3).

(4) The JESD MODE register bits are located in the JESD digital page, register 001h (bits 2:0).

(5) The JESD PLL MODE register bits are located in the JESD analog page, register 016h (bits 1-0).

(6) The LANE SHARE register bit is located in the JESD digital page, register 016h (bit 4).

(7) The DA_BUS_REORDER register bits are located in the JESD digital page, register 031h (bits 7-0).

(8) The DB_BUS_REORDER register bits are located in the JESD digital page, register 032h (bits 7-0).

(9) The BUS_REORDER EN1 register bit is located in the main digital page, register 052h (bit 7).

(10) The BUS_REORDER EN2 register bit is located in the main digital page, register 072h (bit 3).

8.4.3.4.1 JESD Transmitter Interface

Each of the 10-Gbps SERDES JESD transmitter outputs requires ac coupling between the transmitter and

receiver. The differential pair must be terminated with 100-Ω resistors as close to the receiving device as

possible to avoid unwanted reflections and signal degradation, as shown in 图 8-22.

0.1 mF

DA[3:0]P,

DB[3:0]P

R_t= Z_O

Transmission Line, Zo

VCM

Receiver

R_t= Z_O

DA[3:0]M,

DB[3:0]M

0.1 mF

图 8-22. Output Connection to Receiver

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8.4.3.4.2 Eye Diagrams

图 8-23 to 图 8-26 show the serial output eye diagrams of the ADS54J40 at 5.0 Gbps and 10 Gbps with default

and increased output voltage swing against the JESD204B mask.

图 8-23. Eye at 5-Gbps Bit Rate with Default Output

图 8-24. Eye at 5-Gbps Bit Rate with Increased

Swing

Output Swing

图 8-26. Eye at 10-Gbps Bit Rate with Increased

图 8-25. Eye at 10-Gbps Bit Rate with Default

Output Swing

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8.5.1 Example Register Writes

This section provides three different example register writes. 表 8-16 describes a global power-down register

write, 表 8-17 describes the register writes when the default lane setting (eight active lanes per device) is

changed to four active lanes (LMFS = 4211), and 表 8-18 describes the register writes for 2X decimation with

four active lanes (LMFS = 4222).

表 8-16. Global Power Down

ADDRESS (Hex)

0-011h

DATA (Hex)

80h

COMMENT

Set the master page

0-026h

C0h

Set the global power-down

表 8-17. Two Lanes per Channel Mode (LMFS = 4211)

ADDRESS (Hex)

4-004h

DATA (Hex)

COMMENT

69h

Select the JESD digital page

Select the digital to 40X mode

Select the JESD analog page

Set the SERDES PLL to 40X mode

4-003h

00h

6-001h

02h

4-004h

6Ah

6-016h

02h

表 8-18. 2X Decimation (LPF for Both Channels) with Four Active Lanes (LMFS = 4222)

ADDRESS (Hex)

DATA (Hex)

COMMENT

4-004h

68h

Select the main digital page (6800h)

Set decimate-by-2 (low-pass filter)

Enable decimation filter control

BUS_REORDER EN2

4-003h

00h

6-041h

12h

6-04Dh

6-072h

08h

6-052h

80h

BUS_REORDER EN1

6-000h

01h

Pulse the PULSE RESET bit (so that register writes to the main digital page go into effect).

6-000h

00h

4-004h

69h

Select the JESD digital page (6900h)

4-003h

00h

Select the JESD digital page (6900h)

6-031h

0Ah

31h

Output bus reorder for channel A

6-032h

Output bus reorder for channel B

6-001h

Program the JESD MODE and JESD FILTER register bits for LMFS = 4222.

表 8-19 lists the access codes for the ADS54J40 registers.

表 8-19. ADS54J40 Access Type Codes

Access Type

Code

Description

R

Read

R-W

W

R/W

W

Read or write

Write

-n

Value after reset or the default

value

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8.5.2 Register Descriptions

8.5.2.1 General Registers

8.5.2.1.1 Register 0h (address = 0h)

图 8-22. Register 0h

7

6

0

5

0

4

3

2

0

1

0

RESET

W-0h

0

RESET

W-0h

表 8-20. Register 0h Field Descriptions

Bit

Field

Type

Reset

Description

7

RESET

W

0h

0 = Normal operation

1 = Internal software reset, clears back to 0

6-1

0

W

0h

Must write 0

RESET

0 = Normal operation

1 = Internal software reset, clears back to 0

8.5.2.1.2 Register 1h (address = 1h)

图 8-23. Register 1h

7

6

5

4

3

2

1

0

JESD BANK PAGE SEL1[7:0]

R/W-0h

表 8-21. Register 1h Field Descriptions

Bit

Field

JESD BANK PAGE SEL1[7:0]

Type

Reset

Description

7-0

R/W

0h

Program these bits to access the desired page in the JESD

bank.

0000h = OFFSET READ Page

0500h = OFFSET LOAD Page

8.5.2.1.3 Register 2h (address = 2h)

图 8-24. Register 2h

7

6

5

4

3

2

1

0

JESD BANK PAGE SEL1[15:8]

R/W-0h

表 8-22. Register 2h Field Descriptions

Bit

Field

JESD BANK PAGE SEL1[15:8]

Type

Reset

Description

7-0

R/W

0h

Program these bits to access the desired page in the JESD

bank.

0000h = OFFSET READ Page

0500h = OFFSET LOAD Page

8.5.2.1.4 Register 3h (address = 3h)

图 8-25. Register 3h

7

6

5

4

3

2

1

0

JESD BANK PAGE SEL[7:0]

R/W-0h

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表 8-23. Register 3h Field Descriptions

Bit

Field

Type

Reset

Description

7-0

JESD BANK PAGE SEL[7:0]

R/W

0h

Program these bits to access the desired page in the JESD

bank.

6800h = Main digital page selected

6900h = JESD digital page selected

6A00h = JESD analog page selected

6100h = OFFSET READ or LOAD Page

8.5.2.1.5 Register 4h (address = 4h)

图 8-26. Register 4h

7

6

5

4

3

2

1

0

JESD BANK PAGE SEL[15:8]

R/W-0h

表 8-24. Register 4h Field Descriptions

Bit

Field

JESD BANK PAGE SEL[15:8]

Type

Reset

Description

7-0

R/W

0h

Program these bits to access the desired page in the JESD

bank.

6800h = Main digital page selected

6900h = JESD digital page selected

6A00h = JESD analog page selected

6100h = OFFSET READ or LOAD Page

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8.5.2.1.6 Register 5h (address = 5h)

图 8-27. Register 5h

7

0

6

0

5

0

4

0

3

2

0

1

0

DISABLE BROADCAST

R/W-0h

W-0h

表 8-25. Register 5h Field Descriptions

Bit

Field

Type

Reset

Description

7-1

0

W

0h

Must write 0

DISABLE BROADCAST

R/W

0h

0 = Normal operation. Channel A and B are programmed as a pair.

1 = Channel A and B can be individually programmed based on the

CH bit.

8.5.2.1.7 Register 11h (address = 11h)

图 8-28. Register 11h

7

6

5

4

3

2

1

0

ANALOG PAGE SELECTION

R/W-0h

表 8-26. Register 11h Field Descriptions

Bit

Field

ANALOG BANK PAGE SEL

Type

Reset

Description

7-0

R/W

0h

Program these bits to access the desired page in the analog bank.

Master page = 80h

ADC page = 0Fh

8.5.2.2 Master Page (080h) Registers

8.5.2.2.1 Register 20h (address = 20h), Master Page (080h)

图 8-29. Register 20h

7

6

5

4

3

2

1

0

PDN ADC CHA

R/W-0h

PDN ADC CHB

R/W-0h

表 8-27. Registers 20h Field Descriptions

Bit

7-4

3-0

Field

Type

R/W

Reset

Description

PDN ADC CHA

PDN ADC CHB

0h

There are two power-down masks that are controlled through

the PDN mask register bit in address 55h. The power-down

mask 1 or mask 2 are selected via register bit 5 in address 26h.

Power-down mask 1: addresses 20h and 21h.

Power-down mask 2: addresses 23h and 24h.

0Fh = Power-down CHB only.

0h

F0h = Power-down CHA only.

FFh = Power-down both.

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8.5.2.2.2 Register 21h (address = 21h), Master Page (080h)

图 8-30. Register 21h

7

6

5

4

3

2

0

1

0

PDN BUFFER CHB

R/W-0h

PDN BUFFER CHA

R/W-0h

0

W-0h

表 8-28. Register 21h Field Descriptions

Bit

Field

Type

R/W

Reset

Description

7-6

5-4

PDN BUFFER CHB

PDN BUFFER CHA

0h

There are two power-down masks that are controlled through

the PDN mask register bit in address 55h. The power-down

mask 1 or mask 2 are selected via register address 26h, bit 5.

Power-down mask 1: addresses 20h and 21h.

Power-down mask 2: addresses 23h and 24h.

There are two buffers per channel. One buffer drives two ADC

cores.

0h

PDN BUFFER CHx:

00 = Both buffers of a channel are active.

11 = Both buffers are powered down.

01–10 = Do not use.

3-0

0

W

0h

Must write 0.

8.5.2.2.3 Register 23h (address = 23h), Master Page (080h)

图 8-31. Register 23h

7

6

5

4

3

2

1

0

PDN ADC CHA

R/W-0h

PDN ADC CHB

R/W-0h

表 8-29. Register 23h Field Descriptions

Bit

7-4

3-0

Field

Type

R/W

Reset

Description

PDN ADC CHA

PDN ADC CHB

0h

There are two power-down masks that are controlled through

the PDN mask register bit in address 55h. The power-down

mask 1 or mask 2 are selected via register address 26h, bit 5.

Power-down mask 1: addresses 20h and 21h.

Power-down mask 2: addresses 23h and 24h.

0Fh = Power-down CHB only.

0h

F0h = Power-down CHA only.

FFh = Power-down both.

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8.5.2.2.4 Register 24h (address = 24h), Master Page (080h)

图 8-32. Register 24h

7

6

5

4

3

2

0

1

0

PDN BUFFER CHB

R/W-0h

PDN BUFFER CHA

R/W-0h

0

W-0h

表 8-30. Register 24h Field Descriptions

Bit

Field

Type

R/W

Reset

Description

7-6

5-4

PDN BUFFER CHB

PDN BUFFER CHA

0h

There are two power-down masks that are controlled through

the PDN mask register bit in address 55h. The power-down

mask 1 or mask 2 are selected via register address 26h, bit 5.

Power-down mask 1: addresses 20h and 21h.

Power-down mask 2: addresses 23h and 24h.

There are two buffers per channel. One buffer drives two ADC

cores.

0h

PDN BUFFER CHx:

00 = Both buffers of a channel are active.

11 = Both buffers are powered down.

01–10 = Do not use.

3-0

0

W

0h

Must write 0.

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8.5.2.2.5 Register 26h (address = 26h), Master Page (080h)

表 8-31. Register 26h

7

6

5

4

3

2

0

1

0

OVERRIDE

PDN PIN

PDN MASK

SEL

GLOBAL PDN

R/W-0h

0

R/W-0h

W-0h

表 8-32. Register 26h Field Descriptions

Bit

Field

GLOBAL PDN

Type

Reset

Description

7

R/W

0h

Bit 6 (OVERRIDE PDN PIN) must be set before this bit can be

programmed.

0 = Normal operation

1 = Global power-down through the SPI

6

5

OVERRIDE PDN PIN

R/W

W

0h

This bit ignores the power-down pin control.

0 = Normal operation

1 = Ignores inputs on the power-down pin

PDN MASK SEL

0

This bit selects power-down mask 1 or mask 2.

0 = Power-down mask 1

1 = Power-down mask 2

4-0

Must write 0

8.5.2.2.6 Register 4Fh (address = 4Fh), Master Page (080h)

表 8-33. Register 4Fh

7

0

6

0

5

0

4

0

3

2

0

1

0

EN INPUT DC COUPLING

R/W-0h

W-0h

表 8-34. Register 4Fh Field Descriptions

Bit

7-1

0

Field

Type

Reset

Description

0

W

0h

Must write 0

EN INPUT DC COUPLING

R/W

0h

The device has an internal biassing resistor of 600 Ω from VCM

to the INP and INM pins. A small common-mode current flows

through these resistors causing approximately a 100-mV drop.

To compenste for the drop, the device raises the VCM voltage

by 100-mV by default. This compensation is particularly helpful

in AC-coupling applications where the common-mode voltage on

the INP and INM pins is established by internal biasing resistors.

In DC-coupling applications, because the common-mode

voltage is established by an external circuit, there is no need to

raise VCM by 100-mV.

0 = Device raises VCM voltage by 100 mV, useful in AC-

coupling applications

1 = Device does not raise the VCM voltage, useful in DC-

coupling applications.

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8.5.2.2.7 Register 53h (address = 53h), Master Page (080h)

表 8-35. Register 53h

7

0

6

0

5

0

4

3

2

0

1

0

EN SYSREF

DC COUPLING

0

SET SYSREF

R/W-0h

W-0h

R/W-0h

表 8-36. Register 53h Field Descriptions

Bit

Field

Type

Reset

Description

7:2

1

0

W

0h

Must write 0

EN SYSREF DC COUPLING

R/W

0h

This bit enables a higher common-mode voltage input on the

SYSREF signal (up to 1.6 V).

0 = Normal operation

1 = Enables a higher SYSREF common-mode voltage support

0

MANUAL SYSREF

R/W

0h

The device has a feature to apply the SYSREF signal manually

through the serial interface instead of the SYSREFP, SYSREFM

pins. This application can be done by first setting the ENABLE

MANUAL SYSREF register bit, then using the MANUAL

SYSREF bit to set the SYSREF signal high or low.0 = Set

SYSREF low

1 = Set SYSREF high

8.5.2.2.8 Register 54h (address = 54h), Master Page (080h)

图 8-33. Register 54h

7

6

0

5

4

3

2

0

1

0

ENABLE

MANUAL

SYSREF

MASK SYSREF MASK SYSREF

0

R/W-0h

W-0h

R/W-0h

W-0h

表 8-37. Register 54h Field Descriptions

Bit

7

Field

Type

R/W

W

Reset

Description

ENABLE MANUAL SYSREF

0h

This bit enables manual SYSREF

Must write 0

6

0

0h

5-4

MASK SYSREF

R/W

0h

00 = Normal operation

11 = The SYSREF signal is ignored by the device irrespective of

how the signal was applied (through a pin or manually by the

serial interface)

01 and 10 = Not applicable

3-0

0

W

0h

Must write 0

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8.5.2.2.9 Register 55h (address = 55h), Master Page (080h)

表 8-38. Register 55h

7

0

6

0

5

0

4

3

2

0

1

0

PDN MASK

R/W-0h

0

W-0h

表 8-39. Register 55h Field Descriptions

Bit

Field

Type

Reset

Description

7-5

4

0

W

0h

Must write 0

PDN MASK

R/W

0h

This bit enables power-down via a register bit.

0 = Normal operation

1 = Power-down is enabled by powering down the internal

blocks as specified in the selected power-down mask

3-0

0

W

0h

Must write 0

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8.5.2.2.10 Register 59h (address = 59h), Master Page (080h)

图 8-34. Register 59h

7

6

0

5

4

3

0

2

0

1

0

FOVR CHB

W-0h

ALWAYS WRITE 1

R/W-0h

0

W-0h

表 8-40. Register 59h Field Descriptions

Bit

Field

FOVR CHB

Type

Reset

Description

7

W

0h

This bit outputs the FOVR signal for channel B on the SDOUT

pin.

0 = Normal operation

1 = The FOVR signal is available on the SDOUT pin

6

5

0

W

0h

Must write 0

Must write 1

Must write 0

ALWAYS WRITE 1

0

R/W

W

4-0

8.5.2.3 ADC Page (0Fh) Register

8.5.2.3.1 Register 5F (addresses = 5F), ADC Page (0Fh)

图 8-35. Register 5F

7

6

5

4

3

2

1

0

FOVR THRESHOLD PROG

R/W-E3h

表 8-41. Register 5F Field Descriptions

Bit

Field

FOVR THRESHOLD PROG

Type

Reset

Description

7-0

R/W

E3h

Program the fast OVR thresholds together for channel A and B,

as described in the Overrange Indication section.

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8.5.2.4 Main Digital Page (6800h) Registers

8.5.2.4.1 Register 0h (address = 0h), Main Digital Page (6800h)

表 8-42. Register 0h

7

0

6

0

5

0

4

3

2

0

1

0

PULSE RESET

R/W-0h

W-0h

表 8-43. Register 0h Field Descriptions

Bit

Field

Type

Reset

Description

7-1

0

W

0h

Must write 0

PULSE RESET

R/W

0h

This bit must be pulsed after power-up or after configuring

registers in the main digital page of the JESD bank. Any register

bits in the main digital page (6800h) take effect only after this bit

is pulsed; see the Start-Up Sequence section for the correct

sequence.

0 = Normal operation

0 → 1 → 0 = This bit is pulsed

8.5.2.4.2 Register 40h (address = 40h), Main Digital Page (6800h)

表 8-44. Register 40h

7

6

5

4

3

2

1

0

IL ENGINE MODE

W-0h

表 8-45. Register 40h Field Descriptions

Bit

Field

IL ENGINE MODE

Type

Reset

Description

7-0

W

0h

Specifies the Interleaving Engine Mode

0 = Interleaving Engine is enabled

8 = Interleaving Engine is disabled

Other Values = Reserved

Note that for this register setting to take effect, CTRL IL ENGINE

field should be set to 1

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8.5.2.4.3 Register 41h (address = 41h), Main Digital Page (6800h)

图 8-36. Register 41h

7

0

6

0

5

4

3

0

2

1

0

DECFIL MODE[3]

R/W-0h

DECFIL EN

R/W-0h

DECFIL MODE[2:0]

R/W-0h

W-0h

表 8-46. Register 41h Field Descriptions

Bit

Field

Type

Reset

Description

7-6

5

0

W

0h

Must write 0

DECFIL MODE[3]

R/W

0h

This bit selects the decimation filter mode. 表 8-47 lists the bit settings.

The decimation filter control (DEC MODE EN, register 4Dh, bit 3) and

decimation filter enable (DECFIL EN, register 41h, bit 4) must be enabled.

4

DECFIL EN

R/W

0h

This bit enables the digital decimation filter.

0 = Normal operation, full rate output

1 = Digital decimation enabled

3

0

W

0h

Must write 0

2-0

DECFIL MODE[2:0]

R/W

These bits select the decimation filter mode. 表 8-47 lists the bit settings.

The decimation filter control (DEC MODE EN, register 4Dh, bit 3) and

decimation filter enable (DECFIL EN, register 41h, bit 4) must be enabled.

表 8-47. DECFIL MODE Bit Settings

BITS (5, 2-0)

FILTER MODE

DECIMATION

0000

0100

1000

1100

0010

0110

0011

Band-pass filter centered on 3 × f_S/ 16

4X

Band-pass filter centered on 5 × f_S/ 16

Band-pass filter centered on 1 × f_S/ 16

Band-pass filter centered on 7 × f_S/ 16

Low-pass filter

4X

2X

High-pass filter

2X

Low-pass filter with f_S/4 mixer

4X (IQ)

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8.5.2.4.4 Register 42h (address = 42h), Main Digital Page (6800h)

表 8-48. Register 42h

7

0

6

0

5

0

4

3

2

1

0

NYQUIST ZONE

R/W-0h

W-0h

表 8-49. Register 42h Field Descriptions

Bit

Field

Type

Reset

Description

7-3

2-0

0

W

0h

Must write 0

NYQUIST ZONE

R/W

0h

The Nyquist zone must be selected for proper interleaving

correction. The CONTROL NYQUIST register bit (register 4Eh,

bit 7) must be enabled to use these bits.

000 = 1st Nyquist zone (0 MHz to 500 MHz)

001 = 2nd Nyquist zone (500 MHz to 1000 MHz)

010 = 3rd Nyquist zone (1000 MHz to 1500 MHz)

All others = Not used

8.5.2.4.5 Register 43h (address = 43h), Main Digital Page (6800h)

图 8-37. Register 43h

7

0

6

0

5

0

4

3

2

0

1

0

FORMAT SEL

R/W-0h

W-0h

表 8-50. Register 43h Field Descriptions

Bit

Field

Type

Reset

Description

7-1

0

W

0h

Must write 0

FORMAT SEL

R/W

0h

This bit changes the output format. Set the FORMAT EN bit to

enable control using this bit.

0 = Twos complement

1 = Offset binary

8.5.2.4.6 Register 44h (address = 44h), Main Digital Page (6800h)

图 8-38. Register 44h

7

0

6

5

4

3

2

1

0

DIGITAL GAIN

R/W-0h

表 8-51. Register 44h Field Descriptions

Bit

7

Field

Type

R/W

Reset

Description

0

0h

Must write 0

6-0

DIGITAL GAIN

0h

These bits set the digital gain setting. The DIG GAIN EN register

bit (register 52h, bit 0) must be enabled to use these bits.

Gain in dB = 20log (digital gain / 32)

7Fh = 127 equals a digital gain of 9.5 dB

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8.5.2.4.7 Register 4Bh (address = 4Bh), Main Digital Page (6800h)

图 8-39. Register 4Bh

7

0

6

0

5

4

3

2

1

0

FORMAT EN

0

CTRL IL

ENGINE MODE

W-0h

R/W-0h

W-0h

R/W-0h

W-0h

表 8-52. Register 4Bh Field Descriptions

Bit

Field

Type

Reset

Description

7-6

5

0

W

0h

Must write 0

FORMAT EN

R/W

0h

This bit enables control for data format selection using the

FORMAT SEL register bit.

0 = Default, output is in twos complement format

1 = Output is in offset binary format after the FORMAT SEL bit is

set

4-3

2

W

oh

0h

Must write 0

0

CTRL IL ENGINE MODE

R/W

This bit enables control of interleaving engine mode selection

using the IL ENGINE Mode register field.

0 = Default. IL Engine Mode (IL Engine enabled)

1 = IL Engine Mode is determined from IL ENGINE MODE field

setting.

1-0

0

W

0h

Must write 0

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8.5.2.4.8 Register 4Dh (address = 4Dh), Main Digital Page (6800h)

图 8-40. Register 4Dh

7

0

6

0

5

0

4

3

2

0

1

0

CTRL FREEZE

IL ENGINE

0

DEC MOD EN

R/W-0h

W-0h

R/W-0h

表 8-53. Register 4Dh Field Descriptions

Bit

Field

Type

Reset

Description

7-4

3

0

W

0h

Must write 0

DEC MOD EN

R/W

0h

This bit enables control of decimation filter mode through the

DECFIL MODE[3:0] register bits.

0 = Default

1 = Decimation mode control is enabled

2-1

0

W

0h

Must write 0

R/W

This bit enables control of interleaving engine freeze/unfreeze

state using the FREEZE IL ENGINE register field.

0 = IL Engine continues in its current state (either frozen or

unfrozen).

CTRL FREEZE IL ENGINE

1 = IL Engine state enters a frozen or unfrozen state base on

FREEZE IL ENGINE register field setting.

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8.5.2.4.9 Register 4Eh (address = 4Eh), Main Digital Page (6800h)

图 8-41. Register 4Eh

7

6

0

5

4

3

0

2

0

1

0

IMPROVE IL

PERF

CTRL NYQUIST

R/W-0h

0

W-0h

R/W-0h

W-0h

表 8-54. Register 4Eh Field Descriptions

Bit

Field

Type

Reset

Description

7

CTRL NYQUIST

R/W

0h

This bit enables selecting the Nyquist zone using register 42h,

bits 2-0.

0 = Selection disabled

1 = Selection enabled

6

5

0

W

0h

Must write 0

IMPROVE IL PERF

R/W

Improves interleaving performance. Effective only for input

frequencies that are within +/- fs / 64 band centered at n * fs / 8

(n = 1, 2, 3 or 4). For example, at a 1-Gsps sampling rate, this

bit may improve IL performance when the input frequencies fall

within +/- 15.625 MHz band located at 125 MHz, 250 MHz, 375

MHz and 500 MHz.

0 = Default

1 = Improves IL performance for certain input frequenies

6-0

0

W

0h

Must write 0

8.5.2.4.10 Register 52h (address = 52h), Main Digital Page (6800h)

图 8-42. Register 52h

7

6

0

5

0

4

3

2

0

1

0

DIG GAIN EN

BUS_REORD

ER_EN1

R/W-0h

W-0h

R/W-0h

表 8-55. Register 52h Field Descriptions

Bit

7

Field

Type

R/W

W

Reset

Description

BUS_REORDER_EN1

0h

Must write 1 in DDC mode only

Must write 0

6-1

0

0h

DIG GAIN EN

R/W

0h

Enables selecting the digital gain for register 44h.

0 = Digital gain disabled

1 = Digital gain enabled

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8.5.2.4.11 Register 68h (address = 68h), Main Digital Page (6800h)

图 8-43. Register 68h

7

6

5

0

4

3

2

1

0

FREEZE IL ENGINE

W-0h

0

W-0h

表 8-56. Register 68h Field Descriptions

Bit

Field

Type

Reset

Description

7-3

2

0

W

0h

Must write 0

FREEZE IL ENGINE

W

0h

IL Engine Freeze/Unfreeze Configuration.

0 = IL Engine is unfrozen (i.e. Interleaving Mismatch estimation

is resumed)

1 = IL Engine is frozen (i.e. Interleaving Mismatch estimation is

frozen, correction continues with estimates computed prior to

freeze)

Note -

1. Value specified here takes effect when CTRL FREEZE IL

ENGINE is 1.

2. For IL Engine to be frozen, register field IL ENGINE

FREEZE SECONDARY CONTROL should be set to 0

3. Unlike other register fields in the Main Digital Page,

FREEZE IL ENGINE does not need a PULSE RESET to

take effect. FREEZE IL ENGINE can be asserted/de-

asserted at any time and the setting takes effect immediatel

.

1-0

0

W

0h

Must write 0

8.5.2.4.12 Register 72h (address = 72h), Main Digital Page (6800h)

图 8-44. Register 72h

7

0

6

0

5

0

4

0

3

2

0

1

0

BUS_REORDER_EN2

W-0h

R/W-0h

W-0h

表 8-57. Register 72h Field Descriptions

Bit

7-4

3

Field

Type

Reset

Description

0

W

0h

Must write 0

BUS_REORDER_EN2

0

R/W

W

0h

Must write a 1 in DDC mode only

Must write 0

2-0

0h

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8.5.2.4.13 Register ABh (address = ABh), Main Digital Page (6800h)

图 8-45. Register ABh

7

0

6

0

5

0

4

3

2

0

1

0

LSB SEL EN

R/W-0h

W-0h

表 8-58. Register ABh Field Descriptions

Bit

Field

Type

Reset

Description

7-1

0

W

0h

Must write 0

LSB SEL EN

R/W

0h

Enable control for the LSB SELECT register bit.

0 = Default

1 = LSB of the 16-bit data (14-bit ADC data padded with two 0s

as the LSBs) can be programmed as fast OVR using the LSB

SELECT register bit.

8.5.2.4.14 Register ADh (address = ADh), Main Digital Page (6800h)

图 8-46. Register ADh

7

0

6

0

5

0

4

3

2

0

1

0

LSB SELECT

R/W-0h

W-0h

表 8-59. Register ADh Field Descriptions

Bit

Field

Type

Reset

Description

7-2

1-0

0

W

0h

Must write 0

LSB SELECT

R/W

0h

These bits enable the output of the FOVR flag instead of the

output data LSB. Ensure that LSB SEL EN register bit is set to

1.

00 = Output is 16-bit data (14-bit ADC data padded with two 0s

as LSBs)

11 = LSB of 16-bit output data is replaced by the FOVR

information for each channel.

8.5.2.4.15 Register F7h (address = F7h), Main Digital Page (6800h)

图 8-47. Register F7h

7

0

6

0

5

0

4

3

2

0

1

0

DIG RESET

W-0h

表 8-60. Register F7h Field Descriptions

Bit

Field

Type

Reset

Description

7-1

0

W

0h

Must write 0

DIG RESET

W

0h

This bit is the self-clearing reset for the digital block and does

not include interleaving correction.

0 = Normal operation

1 = Digital reset

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8.5.2.5 JESD Digital Page (6900h) Registers

8.5.2.5.1 Register 0h (address = 0h), JESD Digital Page (6900h)

图 8-48. Register 0h

7

6

0

5

0

4

3

2

1

0

TESTMODE EN

FLIP ADC

DATA

CTRL K

R/W-0h

LANE ALIGN FRAME ALIGN

R/W-0h R/W-0h

TX LINK DIS

R/W-0h

W-0h

R/W-0h

表 8-61. Register 0h Field Descriptions

Bit

Field

Type

Reset

Description

7

CTRL K

R/W

0h

Thib bit is the enable bit for a number of frames per multi frame.

0 = Default is five frames per multi frame

1 = Frames per multi frame can be set in register 06h

6-5

4

0

W

0h

Must write 0

TESTMODE EN

R/W

This bit generates the long transport layer test pattern mode, as

per section 5.1.6.3 of the JESD204B specification.

0 = Test mode disabled

1 = Test mode enabled

3

2

FLIP ADC DATA

LANE ALIGN

R/W

0h

0 = Normal operation

1 = Output data order is reversed: MSB to LSB.

This bit inserts the lane alignment character (K28.3) for the

receiver to align to lane boundary, as per section 5.3.3.5 of the

JESD204B specification.

0 = Normal operation

1 = Inserts lane alignment characters

1

0

FRAME ALIGN

TX LINK DIS

R/W

0h

This bit inserts the lane alignment character (K28.7) for the

receiver to align to lane boundary, as per section 5.3.3.5 of the

JESD204B specification.

0 = Normal operation

1 = Inserts frame alignment characters

This bit disables sending the initial link alignment (ILA)

sequence when SYNC is de-asserted.

0 = Normal operation

1 = ILA disabled

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8.5.2.5.2 Register 1h (address = 1h), JESD Digital Page (6900h)

图 8-49. Register 1h

7

6

5

4

3

2

1

0

SYNC REG

R/W-0h

SYNC REG EN

R/W-0h

JESD FILTER

R/W-0h

JESD MODE

R/W-01h

表 8-62. Register 1h Field Descriptions

Bit

Field

SYNC REG

Type

Reset

Description

7

R/W

0h

This bit is the register control for the sync request.

0 = Normal operation

1 = ADC output data are replaced with K28.5 characters; the

SYNC REG EN register bit must also be set to 1

6

SYNC REG EN

JESD FILTER

R/W

0h

This bit enables register control for the sync request.

0 = Use the SYNC pin for sync requests

1 = Use the SYNC REG register bit for sync requests

5-3

These bits and the JESD MODE bits set the correct LMFS

configuration for the JESD interface. The JESD FILTER setting

must match the configuration in the decimation filter page.

000 = Filter bypass mode

See 表 8-63 for valid combinations for register bits JESD FILTER

along with JESD MODE.

2-0

JESD MODE

R/W

01h

These bits select the number of serial JESD output lanes per ADC.

The JESD PLL MODE register bit located in the JESD analog page

must also be set accordingly.

001 = Default after reset(Eight active lanes)

See 表 8-63 for valid combinations for register bits JESD FILTER

along with JESD MODE.

表 8-63. Valid Combinations for JESD FILTER and JESD MODE Bits

NUMBER OF ACTIVE LANES

PER DEVICE

REGISTER BIT JESD FILTER

REGISTER BIT JESD MODE

DECIMATION FACTOR

000

100

010

No decimation

Four lanes are active

No decimation

(default after reset)

000

001

Eight lanes are active

111

110

100

111

100

001

010

001

010

4X (IQ)

2X

Four lanes are active

Two lanes are active

One lane is active

2X

4X

4X (IQ)

4X

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8.5.2.5.3 Register 2h (address = 2h), JESD Digital Page (6900h)

图 8-50. Register 2h

7

6

5

4

3

2

0

1

0

LINK LAYER TESTMODE

R/W-0h

LINK LAYER RPAT

R/W-0h

LMFC MASK RESET

R/W-0h

W-0h

表 8-64. Register 2h Field Descriptions

Bit

Field

Type

Reset

Description

7-5

LINK LAYER TESTMODE

R/W

0h

These bits generate a pattern as per section 5.3.3.8.2 of the

JESD204B document.

000 = Normal ADC data

001 = D21.5 (high-frequency jitter pattern)

010 = K28.5 (mixed-frequency jitter pattern)

011 = Repeat initial lane alignment (generates a K28.5 character

and continuously repeats lane alignment sequences)

100 = 12-octet RPAT jitter pattern

All others = Not used

4

LINK LAYER RPAT

R/W

0h

This bit changes the running disparity in the modified RPAT pattern

test mode (only when the link layer test mode = 100).

0 = Normal operation

1 = Changes disparity

3

LMFC MASK RESET

0

R/W

W

0h

This bit masks the LMFC reset coming to the digital block.

0 = LMFC reset is not masked

1 = Ignore the LMFC reset request

2-0

Must write 0

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8.5.2.5.4 Register 3h (address = 3h), JESD Digital Page (6900h)

图 8-51. Register 3h

7

6

5

4

3

2

1

0

FORCE LMFC COUNT

R/W-0h

LMFC COUNT INIT

R/W-0h

RELEASE ILANE SEQ

R/W-0h

表 8-65. Register 3h Field Descriptions

Bit

Field

Type

Reset

Description

7

FORCE LMFC COUNT

R/W

0h

This bit forces the LMFC count.

0 = Normal operation

1 = Enables using a different starting value for the LMFC

counter

6-2

1-0

LMFC COUNT INIT

R/W

0h

When SYSREF transmits to the digital block, the LMFC count

resets to 0 and K28.5 stops transmitting when the LMFC count

reaches 31. The initial value that the LMFC count resets to can

be set using LMFC COUNT INIT. In this manner, the receiver

can be synchronized early because it receives the LANE

ALIGNMENT SEQUENCE early. The FORCE LMFC COUNT

register bit must be enabled.

RELEASE ILANE SEQ

These bits delay the generation of the lane alignment sequence

by 0, 1, 2, or 3 multi frames after the code group

synchronization.

00 = 0

01 = 1

10 = 2

11 = 3

8.5.2.5.5 Register 5h (address = 5h), JESD Digital Page (6900h)

图 8-52. Register 5h

7

6

0

5

0

4

3

0

2

0

1

0

SCRAMBLE EN

R/W-0h

0

W-0h

表 8-66. Register 5h Field Descriptions

Bit

Field

Type

Reset

Description

7

SCRAMBLE EN

R/W

This bit is the scramble enable bit in the JESD204B interface.

0 = Scrambling disabled

0h

1 = Scrambling enabled

6-0

0

W

0h

Must write 0

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8.5.2.5.6 Register 6h (address = 6h), JESD Digital Page (6900h)

图 8-53. Register 6h

7

0

6

0

5

0

4

3

2

1

0

FRAMES PER MULTI FRAME (K)

R/W-8h

W-0h

表 8-67. Register 6h Field Descriptions

Bit

Field

Type

Reset

Description

7-5

4-0

0

W

0h

Must write 0

FRAMES PER MULTI FRAME (K)

R/W

8h

These bits set the number of multi frames.

Actual K is the value in hex + 1 (that is, 0Fh is K = 16).

8.5.2.5.7 Register 7h (address = 7h), JESD Digital Page (6900h)

图 8-54. Register 7h

7

0

6

0

5

0

4

3

2

0

1

0

SUBCLASS

R/W-1h

W-0h

表 8-68. Register 7h Field Descriptions

Bit

Field

Type

Reset

Description

7-4

3

0

W

0h

Must write 0

SUBCLASS

R/W

1h

This bit sets the JESD204B subclass.

000 = Subclass 0 is backward compatible with JESD204A

001 = Subclass 1 deterministic latency using the SYSREF signal

2-0

0

W

0h

Must write 0

8.5.2.5.8 Register 16h (address = 16h), JESD Digital Page (6900h)

图 8-55. Register 16h

7

1

6

0

5

0

4

3

2

0

1

0

LANE SHARE

R/W-0h

0

W-1h

W-0h

表 8-69. Register 16h Field Descriptions

Bit

Field

Type

Reset

Description

Must write 1

Must write 0

7

6-5

4

1

0

W

1h

W

0h

LANE SHARE

R/W

0h

When using decimate-by-4, the data of both channels are output

over one lane (LMFS = 1241).

0 = Normal operation (each channel uses one lane)

1 = Lane sharing is enabled, both channels share one lane

(LMFS = 1241)

3-0

0

W

0h

Must write 0

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8.5.2.5.9 Register 31h (address = 31h), JESD Digital Page (6900h)

图 8-56. Register 31h

7

6

5

4

3

2

1

0

DA_BUS_REORDER[7:0]

R/W-0h

表 8-70. Register 31h Field Descriptions

Bit

Field

DA_BUS_REORDER[7:0]

Type

Reset

Description

7-0

R/W

0h

Use these bits to program output connections between data

streams and output lanes in decimate-by-2 and decimate-by-4

mode. 表 8-14 lists the supported combinations of these bits.

8.5.2.5.10 Register 32h (address = 32h), JESD Digital Page (6900h)

图 8-57. Register 32h

7

6

5

4

3

2

1

0

DB_BUS_REORDER[7:0]

R/W-0h

表 8-71. Register 32h Field Descriptions

Bit

Field

DB_BUS_REORDER[7:0]

Type

Reset

Description

7-0

R/W

0h

Use these bits to program output connections between data

streams and output lanes in decimate-by-2 and decimate-by-4

mode. 表 8-14 lists the supported combinations of these bits.

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8.5.2.6 JESD Analog Page (6A00h) Registers

8.5.2.6.1 Register 12h (address = 12h), JESD Analog Page (6A00h)

TBD I separated this register since it is now different from the rest

图 8-58. Register 12h

7

6

5

4

3

2

1

0

SEL EMP LANE 1

R/W-0h

ALWAYS

WRITE 1

W-0h

表 8-72. Register 12h Field Descriptions

Bit

Field

Type

Reset

Description

7-2

SEL EMP LANE 1, 0, 2, or 3

R/W

0h

These bits select the amount of de-emphasis for the JESD

output transmitter. The de-emphasis value in dB is measured as

the ratio between the peak value after the signal transition to the

settled value of the voltage in one bit period.

000000 = 0 dB

000001 = –1 dB

000011 = –2 dB

000111 = –4.1 dB

001111 = –6.2 dB

011111 = –8.2 dB

111111 = –11.5 dB

1

0

ALWAYS WRITE 1

0

W

0h

1 = Always write 1

0 = Must write 0

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8.5.2.6.2 Registers 13h-15h (addresses = 13h-5h), JESD Analog Page (6A00h)

图 8-59. Register 13h

7

6

5

4

3

2

1

0

SEL EMP LANE 0

R/W-0h

W-0h

图 8-60. Register 14h

5

4

3

1

0

SEL EMP LANE 2

R/W-0h

W-0h

图 8-61. Register 15h

5

4

3

1

0

SEL EMP LANE 3

R/W-0h

W-0h

表 8-73. Registers 13h-15h Field Descriptions

Bit

Field

Type

Reset

Description

7-2

SEL EMP LANE x (where x = 1, 0, 2, R/W

or 3)

0h

These bits select the amount of de-emphasis for the JESD

output transmitter. The de-emphasis value in dB is measured as

the ratio between the peak value after the signal transition to the

settled value of the voltage in one bit period.

000000 = 0 dB

000001 = –1 dB

000011 = –2 dB

000111 = –4.1 dB

001111 = –6.2 dB

011111 = –8.2 dB

111111 = –11.5 dB

1-0

0

W

0h

Must write 0

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8.5.2.6.3 Register 16h (address = 16h), JESD Analog Page (6A00h)

图 8-62. Register 16h

7

0

6

0

5

0

4

3

2

0

1

0

JESD PLL MODE

R/W-0h

W-0h

表 8-74. Register 16h Field Descriptions

Bit

Field

Type

Reset

Description

7-2

1-0

0

W

0h

Must write 0

JESD PLL MODE

R/W

0h

These bits select the JESD PLL multiplication factor and must

match the JESD MODE setting.

00 = 20X mode, four lanes per ADC

01 = Not used

10 = 40X mode, two lanes per ADC

11 = Not used

表 8-14 lists a programming summary of the DDC modes and

JESD link configuration.

8.5.2.6.4 Register 17h (address = 17h), JESD Analog Page (6A00h)

图 8-63. Register 17h

7

0

6

5

4

3

2

0

1

0

PLL RESET

R/W-0h

LANE PDN 1

R/W-0h

0

LANE PDN 0

R/W-0h

W-0h

表 8-75. Register 17h Field Descriptions

Bit

Field

Type

Reset

Description

7

6

0

W

0h

Must write 0

PLL RESET

R/W

0h

Pulse this bit after powering up the device; see 表 9-1.

0 = Default

0 → 1 → 0 = The PLL RESET bit is pulsed.

5

LANE PDN 1

R/W

0h

This bit powers down unused SERDES lanes DA0, DA3, DB0,

and DB3 in certain LMFS settings (applicable for LMFS = 4244,

2242, 2441, 4211, and 2221). Powering down unused lanes puts

the SERDES buffers in tri-state moe and saves approximately

15-mA current on the IOVDD supply. This bit must be used with

LANE PDN 0 to take effect.

0 = Default

1 = DA0, DB0, DA3 and DB3 are powered down4

4

3

0

W

0h

Must write 0

LANE PDN 0

R/W

This bit powers down unused SERDES lanes DA0, DA3, DB0,

and DB3 in certain LMFS settings (applicable for LMFS = 4244,

2242, 2441, 4211, and 2221). Powering down unused lanes puts

the SERDES buffers in tri-state moe and saves approximately

15-mA current on the IOVDD supply.This bit must be used with

LANE PDN 1 to take effect.

0 = Dafult

1 = DA0, DB0, DA3 and DB3 are powered down4

2-0

0

W

0h

Must write 0

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8.5.2.6.5 Register 1Ah (address = 1Ah), JESD Analog Page (6A00h)

图 8-64. Register 1Ah

7

0

6

0

5

0

4

3

2

0

1

0

FOVR CHA

R/W-0h

W-0h

表 8-76. Register 1Ah Field Descriptions

Bit

Field

Type

Reset

Description

7-2

1

0

W

0h

Must write 0

FOVR CHA

R/W

0h

This bit outputs the FOVR signal for channel A on the PDN pin.

FOVR CHA EN (register 1Bh, bit 3) must be enabled for this bit

to function.

0 = Normal operation

1 = The FOVR signal of channel A is available on the PDN pin

0

W

0h

Must write 0

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8.5.2.6.6 Register 1Bh (address = 1Bh), JESD Analog Page (6A00h)

图 8-65. Register 1Bh

7

6

5

4

3

2

0

1

0

JESD SWING

R/W-0h

0

FOVR CHA EN

R/W-0h

W-0h

表 8-77. Register 1Bh Field Descriptions

Bit

Field

Type

Reset

Description

7-5

JESD SWING

R/W

0h

These bits select the output amplitude V_OD(mV_PP) of the JESD

transmitter (for all lanes).

0 = 860 mV_PP

1 = 810 mV_PP

2 = 770 mV_PP

3 = 745 mV_PP

4 = 960 mV_PP

5 = 930 mV_PP

6 = 905 mV_PP

7 = 880 mV_PP

4

3

0

W

0h

Must write 0

FOVR CHA EN

R/W

This bit enables overwrites of the PDN pin with the FOVR signal

from channel A.

0 = Normal operation

1 = PDN is overwritten

2-0

0

R/W

0h

Must write 0

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8.5.2.7 Offset Read Page (JESD BANK PAGE SEL = 6100h, JESD BANK PAGE SEL1 = 0000h) Registers

8.5.2.7.1 Register 068h (address = 068h), Offset Read Page

图 8-66. Register 068h

7

6

5

4

3

2

1

0

FREEZE CORR DC OFFSET

CORR BW

DC OFFSET

CORR BW

DC OFFSET

CORR BW

DC OFFSET BYPASS CORR

CORR BW

ALWAYS

WRITE 1

R/W-0h

W-0h

表 8-78. Register 068h Field Descriptions

Bit

Field

Type Reset Description

Offset correction block is enabled by default. Set this bit to freeze the block.

0 = Default after reset

1 = Offset correction block is frozen

7

FREEZE CORR

R/W 0h

See the DC Offset Correction Block in the ADS54J40ADS54J40W section for details.

DC OFFSET CORR BW

These bits allow the user to program the 3-dB bandwidth of the notch filter centered

around k x fs4/ 4 (k = 0, 1, 2). The notch filter is a first-order digital filter with 3-dB

bandwidth:

3-dB bandwidth normalized to fs

0 = 2.99479E-07

1 = 1.4974E-07

2 = 7.48698E-08

3 = 3.74349E-08

4 = 1.87174E-08

5 = 9.35872E-09

6-3

R/W 0h

6 = 4.67936E-09

7 = 2.33968E-09

8 = 1.16984E-09

9 = 5.8492E-10

10 = 2.9246E-10

11 = 1.4623E-10

For example, at fs = 1 GSPS,if DC OFFSET CORR BW is set to 1, the notch filter has

a 3-dB bandwidth of 149.74 Hz.

0 = Default after reset

2

BYPASS CORR

R/W 0h

1 = Offset correction block is bypassed

See the DC Offset Correction Block in the ADS54J40ADS54J40W section for details.

1

0

ALWAYS WRITE 1

0

Always write 1

Must write 0

W

0h

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8.5.2.7.2 Register 069h (address = 069h), Offset Read Page

图 8-67. Register 069h

7

0

6

0

5

0

4

3

2

0

1

0

EXT CORR EN

R/W-0h

W-0h

表 8-79. Register 069h Field Descriptions

Bit

Field

Type

Reset

Description

7-1

0

W

0h

Must write 0

Enables loading of external estimate into offset correction block.

0 = Default after reset (device uses internal estimate for offset

correction)

0

EXT CORR EN

R/W

0h

1 = External estimate can be loaded by using the

ADCx_LOAD_EXT_EST register bits

See the DC Offset Correction Block in the

ADS54J40ADS54J40W section for details.

8.5.2.7.3 Registers 074h, 076h, 078h, 7Ah (address = 074h, 076h, 078h, 7Ah), Offset Read Page

图 8-68. Registers 074h, 076h, 078h, 7Ah

7

6

5

4

3

2

1

X

0

X

ADCx_CORR_INT_EST[5:0]

R/W-0h

n/a

表 8-80. Registers 074h, 076h, 078h, 7Ah Field Descriptions

Bit

7-2

1-0

Field

Type

R/W

n/a

Reset

Description

Internal estimate for all four interleaving ADC cores of the dc

offset corrector block can be read from these bits.

Keep the R/W bit set to 1 when reading from these registers.

See the DC Offset Correction Block in the

ADCx_CORR_INT_EST[5:0]

X

0h

ADS54J40ADS54J40W section for details.

n/a

Don't care

8.5.2.7.4 Registers 075h, 077h, 079h, 7Bh (address = 075h, 077h, 079h, 7Bh), Offset Read Page

图 8-69. Registers 075h, 077h, 079h, 7Bh

7

0

6

0

5

4

3

2

1

0

ADCx_CORR_INT_EST[8:6]

R/W-0h

W-0h

表 8-81. Registers 075h, 077h, 079h, 7Bh Field Descriptions

Bit

Field

Type

Reset

Description

7-3

0

W

0h

Must write 0

Internal estimate for all four interleaving ADC cores of the dc

offset corrector block can be read from these bits.

Keep the R/W bit set to 1 when reading from these registers.

See the DC Offset Correction Block in the

2-0

ADCx_CORR_INT_EST[8:6]

R/W

0h

ADS54J40ADS54J40W section for details.

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8.5.2.8 Offset Load Page (JESD BANK PAGE SEL= 6100h, JESD BANK PAGE SEL1 = 0500h) Registers

8.5.2.8.1 Registers 00h, 04h, 08h, 0Ch (address = 00h, 04h, 08h, 0Ch), Offset Load Page

图 8-70. Registers 00h, 04h, 08h, 0Ch

7

6

5

4

3

2

1

X

0

X

ADCx_LOAD_EXT_EST[5:0]

R/W-0h

n/a

表 8-82. Registers 00h, 04h, 08h, 0Ch Field Descriptions

Bit

5-0

1-0

Field

Type

R/W

n/a

Reset

Description

External estimate can be loaded into the dc offset corrector

blocks for all four interleaving ADC cores.

See the DC Offset Correction Block in the

ADCx_LOAD_EXT_EST[5:0]

X

0h

ADS54J40ADS54J40W section for details.

n/a

Don't care

8.5.2.8.2 Registers 01h, 05h, 09h, 0Dh (address = 01h, 05h, 09h, 0Dh), Offset Load Page

图 8-71. Registers 01h, 05h, 09h, 0Dh

7

0

6

0

5

0

4

3

2

1

0

ADCx_LOAD_EXT_EST[8:6]

R/W-0h

W-0h

表 8-83. Registers 01h, 05h, 09h, 0Dh Field Descriptions

Bit

Field

Type

Reset

Description

7-3

0

W

0h

Must write 0

External estimate can be loaded into the dc offset corrector

blocks for all four interleaving ADC cores.

See the DC Offset Correction Block in the

2-0

ADCx_CORR_INT_EST[8:6]

R/W

0h

ADS54J40ADS54J40W section for details.

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8.5.2.8.3 Registers 78h (address = 78h), Offset Load Page

图 8-72. Registers 078h

7

0

6

0

5

0

4

3

2

1

0

IL ENGINE FREEZE

SECONDARY CONTROL

W

R/W

表 8-84. Registers 078h Field Descriptions

Bit

Field

Type

Reset

Description

7-1

0

W

0h

Must write 0

IL ENGINE FREEZE SECONDARY

CONTROL

Whenever IL ENGINE freeze is required, this bit needs to be set

to 0.

R/W

0h

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9 Application Information Disclaimer

Note

Information in the following applications sections is not part of the TI component specification, and TI

does not warrant its accuracy or completeness. TI’s customers are responsible for determining

suitability of components for their purposes, as well as validating and testing their design

implementation to confirm system functionality.

9.1 Application Information

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9.1.2 Hardware Reset

图 9-1 and 表 9-2 show the timing for a hardware reset.

Power Supplies

t₁

RESET

t₂

t₃

SEN

图 9-1. Hardware Reset Timing Diagram

表 9-2. Timing Requirements

MIN

TYP

MAX

UNIT

ms

ns

t₁

t₂

t₃

Power-on delay: delay from power-up to an active high RESET pulse

Reset pulse duration: active high RESET pulse duration

1

10

Register write delay: delay from RESET disable to SEN active

100

ns

9.1.3 SNR and Clock Jitter

The signal-to-noise ratio (SNR) of the ADC is limited by three different factors: quantization noise, thermal noise,

and jitter, as shown in 方程式 4. The quantization noise is typically not noticeable in pipeline converters and is 86

dBFS for a 14-bit ADC. The thermal noise limits SNR at low input frequencies and the clock jitter sets SNR for

higher input frequencies.

(4)

The SNR limitation resulting from sample clock jitter can be calculated by 方程式 5:

(5)

The total clock jitter (T_Jitter) has two components: the internal aperture jitter (130 fs) is set by the noise of the

clock input buffer and the external clock jitter. T_Jittercan be calculated by 方程式 6:

(6)

External clock jitter can be minimized by using high-quality clock sources and jitter cleaners as well as band-

pass filters at the clock input. A faster clock slew rate also improves the ADC aperture jitter.

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The ADS54J40 has a thermal noise of approximately 71.1 dBFS and an internal aperture jitter of 120 f_S. SNR,

depending on the amount of external jitter for different input frequencies, is shown in 图 9-2.

75

35 f_S

50 f_S

100 f_S

150 f_S

200 f_S

73

71

69

67

65

10

100

Input Frequency (MHz)

D052

图 9-2. SNR versus Input Frequency and External Clock Jitter

9.1.4 DC Offset Correction Block in the ADS54J40

The ADS54J40 employs eight dc offset correction blocks (four per channel, one per interleaving core). 图 9-3

shows a dc correction block diagram.

Input data, x(n)

(250 MSPS data from each interleaving core)

0

Output data, y(n)

at 250 MSPS

1

+

œ

DC Corrected data

ALWAYS WRITE 1

(Reg 68h, bit 1)

0

DC Correction

Engine

BYPASS CORR

1

FREEZE CORR

ADCx_LOAD_EXT_EST[8:0]

Internal Estimate

Read back path

EXT CORR EN

ADCx_CORR_INT_EST[8:0]

图 9-3. DC Offset Correction Block Diagram

The purpose of the dc offset correction block is to correct the dc offset of interleaving cores that mainly arise the

from amplifier in the first pipeline stage. Any mismatch in dc offset among interleaving cores results in spurs at

f_S/ 4 and f_S/ 2. The dc offset correction blocks estimate and correct the dc offset of the individual core, to an

ideal mid-code value, and thereby remove the effect of offset mismatch.

The dc offset correction block can correct the dc offset of individual core up to ±1024 codes.

In applications involving dc-coupling between the ADC and the driver, the dc offset correction block can either be

bypassed or frozen because the block cannot distinguish the external dc signal from the internal dc offset. 图 9-4

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shows that when bypassed, the internal dc mismatch appears at dc, and the f_S/ 4 and f_S/ 2 frequency points

and can be as big as –40 dBFS.

0

-20

-40

-60

-80

-100

-120

0

100

200 300

Frequency (MHz)

400

500

D001

图 9-4. FFT After Bypassing the DC Offset Correction Block

9.1.4.1 Freezing the DC Offset Correction Block

After the device is powered up, the dc offset correction block estimates the internal dc offset with the idle

channel input before the block is frozen. When frozen, the correction block holds the last estimated value that

belongs to the internal dc offset. After the correction block is frozen, an external signal can be applied.

9.1.4.2 Effect of Temperature

The internal dc offset of the individual cores changes with temperature, resulting in f_S/ 4 and f_S/ 2 spurs

appearing again in the spectrum at a different temperature.

图 9-5 shows the variation of the f_S/ 4 spur over temperature for a typical device.

-40

-50

-60

-70

-80

-90

-40

-15

10 35

Temperature (°C)

60

85

D068

The offset correction block was frozen at room temperature, then the temperature was varied from –40°C to +85°C.

图 9-5. Variation of the f_S/ 4 Spur Over Temperature

Although some systems can accept such a variation in the f_S/ 4 and f_S/ 2 spurs across temperature, other

systems may require the internal dc offset profile to be calibrated with temperature. To achieve the calibration of

internal dc offset, the device provides an option to read the internal estimate values from the correction block for

each of the interleaving cores and also to load the values back to the correction block. For calibration, after

power up, a temperature sweep can be performed with the idle channel input and the internal dc offset can be

read back using the ADCx_CORR_INT_EST register bits for salient temperature points. Then during operation,

when the temperature changes, corresponding estimates can be externally loaded to the correction block using

the ADCx_LOAD_EXT_EST register bits.

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The dc offset corrector block is enabled by default. For a given channel, the device can disable and freeze the

block, read the block estimate, and load the external estimate.

表 9-3 lists an example of the required SPI writes for reading an internal estimate of the dc offset correction

block, and then loading the estimate back to the corrector.

表 9-3. Format (16-Bit Address, 8-Bit Data)

ADDRESS

STEP

DATA (Hex)

COMMENT

(Hex)⁽¹⁾

This setting disables broadcast mode (channel A and B can be individually

programmed)

4-005

01

4-004

4-003

4-002

4-001

61

00

Select the offset read page (61000000h)

Data from offset read page can be read as below (keep the R/W bit = 1)

E-074

E-075

E-076

E-077

E-078

E-079

E-07A

E-07B

F-074

F-075

F-076

F-077

F-078

F-079

F-07A

F-07B

xx

Reading the internal estimate [5:0] for core 0, channel A on the SDOUT pin

Reading the internal estimate [8:6] for core 0, channel A on the SDOUT pin

Reading the internal estimate [5:0] for core 1, channel A on the SDOUT pin

Reading the internal estimate [8:6] for core 1, channel A on the SDOUT pin

Reading the internal estimate [5:0] for core 2, channel A on the SDOUT pin

Reading the internal estimate [8:6] for core 2, channel A on the SDOUT pin

Reading the internal estimate [5:0] for core 3, channel A on the SDOUT pin

Reading the internal estimate [8:6] for core 3, channel A on the SDOUT pin

Reading the internal estimate [5:0] for core 0, channel B on the SDOUT pin

Reading the internal estimate [8:6] for core 0, channel B on the SDOUT pin

Reading the internal estimate [5:0] for core 1, channel B on the SDOUT pin

Reading the internal estimate [8:6] for core 1, channel B on the SDOUT pin

Reading the internal estimate [5:0] for core 2, channel B on the SDOUT pin

Reading the internal estimate [8:6] for core 2, channel B on the SDOUT pin

Reading the internal estimate [5:0] for core 3, channel B on the SDOUT pin

Reading the internal estimate [8:6] for core 3, channel B on the SDOUT pin

Reading an internal

estimate from both

channels

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表 9-3. Format (16-Bit Address, 8-Bit Data) (continued)

ADDRESS

(Hex)⁽¹⁾

STEP

DATA (Hex)

COMMENT

6-069

7-069

4-004

4-003

4-002

4-001

6-000

6-001

6-004

6-005

6-008

6-009

6-00C

6-00D

7-000

7-001

7-004

7-005

7-008

7-009

7-00C

7-00D

01

61

00

05

00

xx

Enables the external correction bit located in the offset read page for channel A

Enables the external correction bit located in the offset read page for channel B

Change the page to the offset load page (61000500h)

Loading the external estimate [5:0] for core 0, channel A through SPI writes

Loading the external estimate [8:6] for core 0, channel A through SPI writes

Loading the external estimate [5:0] for core 1, channel A through SPI writes

Loading the external estimate [8:6] for core 1, channel A through SPI writes

Loading the external estimate [5:0] for core 2, channel A through SPI writes

Loading the external estimate [8:6] for core 2, channel A through SPI writes

Loading the external estimate [5:0] for core 3, channel A through SPI writes

Loading the external estimate [8:6] for core 3, channel A through SPI writes

Loading the external estimate [5:0] for core 0, channel B through SPI writes

Loading the external estimate [8:6] for core 0, channel B through SPI writes

Loading the external estimate [5:0] for core 1, channel B through SPI writes

Loading the external estimate [8:6] for core 1, channel B through SPI writes

Loading the external estimate [5:0] for core 2, channel B through SPI writes

Loading the external estimate [8:6] for core 2, channel B through SPI writes

Loading the external estimate [5:0] for core 3, channel B through SPI writes

Loading the external estimate [8:6] for core 3, channel B through SPI writes

Loading an external

estimate to both

channels

(1) The address field is represented in four hex bits in a-bcd format, where a contains information about the R/W, M, P, and CH bits, and

bcd contains the actual address of the register.

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9.1.5 Idle Channel Histogram

图 9-6 shows a histogram of output codes for when no signal is applied at the analog inputs of the ADS54J40 .

图 9-7 shows that when the dc offset correction block of the device is bypassed, the output code histogram

becomes multi-modal with as many as four peaks because the ADS54J40 is a 4-way interleaved ADC with each

ADC core having a different internal dc offset.

7000

6000

5000

4000

3000

2000

1000

0

2800

2400

2000

1600

1200

800

400

0

8184

8187

8190

8193

Output Code

8196

8199

8202

8080 8100 8120 8140 8160 8180 8200 8220 8240 8260 8280

Output Code

D060

D061

图 9-6. Idle Channel Histogram (No Signal at

图 9-7. Idle Channel Histogram (No Signal at

Analog Inputs, DC Offset Correction is On)

Analog Inputs, DC Offset Correction is Off)

图 9-8 shows that when the dc offset correction block is frozen (instead of bypassed), the output code histogram

improves (compared to when bypassed). However, when the temperature changes, the dc offset difference

among interleaving cores may increase resulting in increased spacing between peaks in the histogram.

8000

7000

6000

5000

4000

3000

2000

1000

0

8180 8182 8184 8186 8188 8190 8192 8194 8196 8198 8200

Output Code

D062

D107

图 9-8. Idle Channel Histogram (No Signal at Analog Inputs, DC Offset Correction is Frozen)

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9.1.6 Interleaving (IL) Mismatch Compensation

9.1.6.1 Introduction

The ADC in ADS54J40 is an interleaved ADC, which is realized by interleaving the outputs of 4 component

ADCs running at one-fourth of the final rate. Gain/timing mismatches between the 4 component ADCs give rise

to images in the spectrum, located at Fin + kFs/4, k = 1,2,3, where Fin is the input frequency and Fs is the

overall ADC sampling frequency. Note that the frequencies Fin + kFs/4 will alias and fall within [-Fs/2,Fs/2] when

the ADC out is observed. The Interleaving (IL) mismatch corrector module in ADS54J40 compensates for these

images.

Digital Data To

DDC/Output

IL Mismatch Corrector

ADC

Input Analog Signal

Digital Correction

Parameters

IL Mismatch Parameters

Estimator

Analog Correction Parameters

图 9-9. Block diagram of Interleaving mismatch Compensation

9.1.6.2 Features

1. IL mismatch correction has 2 components – Analog Correction component and Digital Correction

component. The correction parameters are provided by the ‘IL Mismatch Parameters Estimator’ block

shown in Fig 1.

2. Tracking of IL mismatch parameters happens continuously in the background, based on incoming data

(except under certain specific conditions listed in item 5).

3. IL mismatch estimation uses Nyquist band information programmed by the user, for proper estimation from

the input signals. Note that for higher Nyquist signals, the IL spurs are at Fin_alias + kFs/4 (k = 1,2,3) where

Fin_alias is the aliased input frequency between [-Fs/2,Fs/2]. This effectively gives the location of IL spurs at

the ADC output.

a. Any change in Nyquist band should be succeeded by a “pulse reset”. A pulse reset signal resets the

internal IL mismatch estimation and correction and the JESD link. However; all other registers written

into the IL engine or the status of the rest of the system is unaffected by a pulse reset. The IL mismatch

parameters would be reestimated for the new Nyquist band after a pulse reset

b. In typical use cases, signals would be present only within one Nyquist band. However, if there are

signals across multiple Nyquist bands (for eg the desired bands in multiple Nyquist bands may not alias

after sampling enabling them to be separated later), it is possible that IL performance may be degraded.

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So it is advisable to disable IL engine to get raw IL performance. The typical raw IL performance is

shown in 图 9-10.

Typical raw IL Performance

90

86

82

78

74

70

60

56

52

48

44

40

IL Enable

IL Disable

0

40 80 120 160 200 240 280 320 360 400 440 480

Input Frequency (MHz)

D500

图 9-10. Typical raw IL Performance

4. IL image performance starts to degrade gracefully for signal frequency components > 0.9 x Fs/2, for 1st

Nyquist signals, as digital correction cannot accurately correct for signals very close to Nyquist band edge .

a. For signals in higher Nyquist bands, the performance degrades gracefully for aliased frequency

components <0.1Fs/2 or >0.9Fs/2

5. IL correction accuracy will continue to be maintained unless any of the following conditions are hit:

a. Persistent Signal absence: The IL estimator works on the input signals to estimate and track IL

mismatch parameters over time. So if no input signal is present, then IL mismatch estimation is not

possible. See item 5f for further details.

No Estimation

Signal not present

OFF

Time

b. Persistent very weak signal only: As IL estimator works on input signals, it needs reasonable-powered

signals present for some continuous period of time to get IL estimates properly. The signal power in

atleast one frequency band of width Fs/256 has to be > -35 dBFs for proper IL estimation. Further such

signal needs to be present in chunks of atleast 100 µs for an integrated ON period of at least 10 ms over

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a total time of 100 ms for proper IL estimation. See item 5f for further details.

Estimation Valid

Signal ON time >

10ms

Signal OFF time

ON

OFF

100 ms

0 ms

Time

No Estimation

Signal ON time <

10ms

Signal OFF time

OFF

ON

0 ms

100 ms

Time

Estimation Valid

Integrated Signal ON time > 10ms, with individual ON times > 100us

ON

0 ms

OFF

ON

OFF

ON

OFF

ON

OFF

ON

OFF

ON

OFF

ON

OFF

100 ms

Time

No Estimation

Integrated Signal ON time > 10ms, BUT individual ON times < 100us

O OF O OF O OF O OF O OF O OF O OF O OF O OF O OF O OF O OF O OF O OF

N

F

N

F

N

F

N

F

N

F

N

F

N

F

N

F

N

F

N

F

N

F

N

F

N

F

0 ms

100 ms

Time

c. Consistent Signal saturation: Whenever signal is saturated, signal gets distorted and IL estimation is no

longer possible. IL estimation is possible if signal amplitude is < -0.5 dBFs for more than 100 µs in one

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chunk and such chunks make up atleast 10 ms in a 100 ms window. See item 5f for further details.

No Estimation

Signal not saturated for >

10ms

Signal Saturated

Normal

Sat

0 ms

100 ms

Time

No Estimation

Signal not saturated for <

10ms

Signal Saturated

Normal

Sat

0 ms

100 ms

Time

Estimation Valid

Non-saturated(normal) time blocks > 100us with total normal block time > 10ms

Nor

mal

Nor

mal

Nor

mal

Nor

mal

Nor

mal

Nor

mal

Nor

mal

Nor

mal

Sat

0 ms

100 ms

Time

No Estimation

Non-saturated(normal) time blocks < 100us with total normal block time > 10ms

No

rm Sat

al

No

rm Sat rm Sat

al al

No

rm Sat

al

No

rm Sat

al

No No

rm Sat rm Sat

No

rm Sat

al

No

rm Sat

al

No

rm Sat rm Sat

al al

No

rm Sat

al

0 ms

100 ms

Time

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d. Signal presence in a very small band only around kfs/8: If input signal is present only within 5e-7 x Fs of

kFs/8 (k = 0,1,2,3), then no IL estimation is possible as the IL signal and IL image are not separable.

No Estimation

Signal only

around kfs/8

+/-500Hz around fs/4

Fs/4

Fs/2 = 512 MHz

See item 5f for further details.

e. Presence of high power signal component in the IL image band: In some cases, the signal component

(such as Sig1) may be present in the IL image band of other components of the signal (such as Sig0).

This signal component in IL image band (Sig1) acts as an interferer for IL estimation of the first

component (Sig0). If the ratio of the power of the signal component causing IL mismatch (power of Sig0)

to the power of the signal component in the IL image band (power of Sig1) is less than 25 dB, then IL

estimation cannot be done for that signal component (Sig0). See item 5f for further details

No Estimation

Estimation Valid

Sig0

Pwr_diff_dB <

25 dB

Sig0

Pwr_diff_dB >

25 dB

Sig1

IL image

Sig1

IL image

of Sig1

IL image of

Sig0

IL image of

Sig0

IL image of

Sig1

Frequency

f. In the normal course of operation, old IL mismatch estimates are retained and used for correction even if

there are no current IL mismatch estimates due to any of the conditions listed in 5a – 5e. This enables

good performance when any of the conditions in 5a-5e are present for a short duration. However if any

of the conditions that prevent estimation listed in 5a – 5e persist for a large time (>40s), then the

estimated digital IL mismatch parameters are reset and the digital IL mismatch parameters are re-

estimated when the conditions for estimation becomes favorable again.

• If the user knows apriori that such a condition will occur and would like the old IL correction to be

retained, then a good option is to freeze the IL engine as in item 6. This freeze stops the IL engine

and so the old IL estimates are not discarded.

Digital IL mismatch estimates

are reset

IL mismatch estimates not available continuously for a long period

No Estimation

…….

No Estimation

40s

0

Time

g. Signal and IL image overlap: If signal component is present around kfs/8 (k = 0,1,2,3), then the IL image

band will also overlap with the signal making it difficult to estimate IL mismatch parameters. Overlap of

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signal and IL image bands around kfs/8 should be < Fs/256 MHz for 90% of the time for proper IL

estimation. Note that if this condition cannot be ensured, then IL performance will be degraded. If this

condition is violated in a known period, then the user can freeze IL engine when this condition occurs as

described in section 6. Otherwise, user has to switch to options in items 6 or 7 to avoid performance

Estimation Valid

No Estimation

Nonoverlap

> 4 MHz

Nonoverlap

< 4 MHz

IL

image

IL image

kfs/8, k=1/

2/3

kfs/8, k=1/

2/3

Frequency

degradation

6. Freezing the IL Engine: If the user knows apriori that any of the conditions in item 5f occurs and would like

the old IL correction to be retained, then a good option is to freeze the IL engine. Or, if the user knows that

condition in 5g is violated at a known time, then also freezing the IL engine is a good option. Once IL engine

is frozen, all past IL estimates/correction are retained and no updates are done to the IL estimates. Once the

conditions described above are no longer present, then the IL engine can be unfrozen. The IL engine then

starts updating the estimates as though the entire period for which it was frozen did not exist at all.

表 9-4. IL Freeze

SPI Address

SPI Data

Comments

0x4005

0x1

Enable per channel writes

Page Select

0x4004

0x68

0x00

0x01

0x4003

Page Select

0x4002

Page Select

0x4001

Page Select

0x604D

Validity for IL Freeze/Unfreeze for

CHA

0x704D

0x01

Validity for IL Freeze/Unfreeze for

CHB

0x6068

0x7068

0x4004

0x4003

0x4002

0x4001

0x6078

0x04

0x61

0x00

0x05

0x00

Freeze IL Engine for CHA

Freeze IL Engine for CHB

Page Select

IL Engine Freeze Secondary

Control for CHA

0x7078

0x00

IL Engine Freeze Secondary

Control for CHB

0x4004

0x4003

0x68

0x00

Page Select

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表 9-4. IL Freeze (continued)

SPI Address

0x4002

SPI Data

Comments

0x00

Page Select

0x4001

0x00

表 9-5. IL Unfreeze

SPI Address

0x4005

SPI Data

Comments

0x00

Enable per channel writes

Page Select

0x4004

0x68

0x4003

0x00

Page Select

0x4002

0x00

Page Select

0x4001

0x00

Page Select

0x604D

0x01

Validity for IL Freeze/Unfreeze for

CHA

0x704D

0x01

Validity for IL Freeze/Unfreeze for

CHB

0x6068

0x7068

0x00

Unfreeze IL Engine for CHA

Unfreeze IL Engine for CHB

7. In case the limitations in items 5 cannot be worked around in the user system and the limitations are

permanent (eg a system where the entire band from [0,fs/2) is nearly fully occupied or signals present

around kfs/8 with overlap < Fs/256), then there are 2 options

a. Power up/Temp based IL calibration - Do calibration using a single tone (single tone frequency in

[0.77fs/2, 0.9 x fs/2], single tone power in [-0.5, -25] dBFs), either one-time or whenever temperature

changes by more than a desired threshold, and then freeze IL estimation module. During calibration, the

normal input should be bypassed and the calibration signal should be input to ADS54J40 for 100 ms for

high power signals (≥ - 3 dBFs) and 500 ms for lower powered signals. Once the calibration time is

complete, IL estimation should be frozen and normal signal may be input to ADS54J40. To determine the

temperature change for which calibration needs to be done, the user can refer to typical variation of IL

spur with temperature, under freeze conditions, as shown in 图 9-11 .

Power Up Device

Load Default Config

Freeze IL Calibration

Provide calib signal: Single

tone @ Fin in [0.77fs/2,0.9fs/

2]. Power in [-0.5,-25] dBFS

Wait for calibration to

complete: 100ms for high

powers (>=-3dBFs) and

500ms for lower powers

Connect Regular Input Signal

Flowchart For Powerup IL calibration

图 9-11. Flowchart for Powerup IL Calibratuion

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Replace regular input signal with

calibration signal: Single tone @

Fin in [0.77fs/2,0.9fs/2]. Power in

[-0.5,-25] dBFS

Freeze IL Calibration

Unfreeze IL Calibration

Wait for calibration to complete:

100ms for high powers (>=-

3dBFs) and 500ms for lower

powers

Connect Regular Input Signal

Flowchart For IL Calibration whenever temperature changes

significantly

图 9-12. Flow chart for intermittent IL calibration

b. Disable IL correction – IL performance would be limited to raw IL performance as shown in figure in the

data sheet. Note that the disable IL correction sequence includes “pulse reset”. A pulse reset signal

resets the internal IL mismatch estimation and correction and the JESD link. Therefore, in case IL

correction disable is desired, it is preferable to insert this sequence within the device bring up sequence,

just before the final pulse reset is issued.

表 9-6. IL Disable

SPI Address

0x4005

SPI Data

Comments

0x0

Enable single channel writes

Selecting page

0x4004

0x68

0x00

0x04

0x4003

Selecting page

0x4002

Selecting page

0x4001

Selecting page

0x604B

Validity for IL Correction Disable

for CHA

0x704B

0x04

Validity for IL Correction Disable

for CHB

0x6040

0x7040

0x6000

0x08

0x01

0x00

Disable IL Correction for CHA

Disable IL Correction for CHB

Pulse reset assert

Pulse reset de-assert

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9.1.6.3 Temperature variation

IL mismatch parameters estimator tracks IL mismatch variations across temperature and gives good

performance under normal conditions. However if IL mismatch estimation is frozen, the residual IL mismatch

seen would vary with temperature as shown in 图 9-13. To reduce the residual IL mismatch below this level,

customer may put the system in calibration mode whenever significant temperature change is detected or based

on a certain time lapse from the last calibration.

-50

-55

-60

-65

-70

-75

-80

-85

-90

f_IN+3f_S/4

f_IN+f_S/2

f_IN+f_S/4

-95

-100

-40 -30 -20 -10

0

10 20 30 40 50 60 70 80 90

Temperature (C)

D501

图 9-13. Residual IL Spur for signal at 400 Mhz vs Temperature after freezing IL calibration at 25°C

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9.2 Typical Application

The ADS54J40 is designed for wideband receiver applications demanding excellent dynamic range over a large

input frequency range. A typical schematic for an ac-coupled receiver is shown in 图 9-14.

DVDD

10 kꢀ

5 W

50 W

Driver

0.1 mF

2 pF

0.1 mF

SPI Master

GND

IOVDD

0.1 mF

GND

0.1 mF

10nF

GND

AVDD3V

AVDD

AVDD3V

DVDD

100-W Differential

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

10 nF

DB2P

DB2M

IOVDD

DB1P

DB1M

DGND

DB0P

DB0M

IOVDD

SYNC

DA0M

DA0P

DGND

DA1M

DA1P

IOVDD

DA2M

DA2P

NC

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

IOVDD

10 nF

GND

NC

10 nF

VCM

0.1 mF

AGND

AVDD3V

AVDD

AGND

CLKINP

CLKINM

AGND

AVDD

AVDD3V

AGND

GND

0.1 mF

AVDD3V

10 nF

GND

AVDD

0.1 mF

GND

10 nF

IOVDD

0.1 mF

GND

GND Pad

(Back Side)

GND

0.1 mF

FPGA

Low-Jitter Clock

Generator

10 nF

AVDD3V

0.1 mF

GND

SYSREFP

SYSREFM

AVDD

100 W

IOVDD

10 nF

GND

AVDD

AGND

GND

10 nF

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

100-W Differential

AVDD3V

DVDD

AVDD

AVDD3V

0.1 mF

GND

0.1 mF

GND

IOVDD

0.1 mF

GND

5 W

50 W

Driver

0.1 mF

2 pF

GND

NOTE: GND = AGND and DGND connected in the PCB layout.

图 9-14. AC-Coupled Receiver

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9.2.1 Design Requirements

9.2.1.1 Transformer-Coupled Circuits

Transformer-Coupled Circuits

Typical applications involving transformer-coupled circuits are discussed in this section. To achieve good phase

and amplitude balances at the ADC input, surface-mount transformers can be used (for example transformers

such as ADT1-1WT or WBC1-1 can be used for frequencies up to 300 MHz and TC1-1-13M+ for higher

frequencies) to achieve good phase and amplitude balances at the ADC inputs. When designing dc-driving

circuits, the ADC input impedance must be considered. 图 9-15 and 图 9-16 show the impedance (Z_IN= R_IN||

C_IN) across the ADC input pins.

1.4

1.2

1

5

4.75

4.5

4.25

4

0.8

0.6

0.4

0.2

0

3.75

3.5

3.25

3

2.75

2.5

2.25

0

100 200 300 400 500 600 700 800 900 1000

Frequency (MHz)

0

100 200 300 400 500 600 700 800 900 1000

Frequency (MHz)

D102

D103

图 9-16. C_INvs Input Frequency

图 9-15. R_INvs Input Frequency

By using the simple drive circuit of 图 9-17, uniform performance can be obtained over a wide frequency range.

The buffers present at the analog inputs of the device help isolate the external drive source from the switching

currents of the sampling circuit.

0.1 ꢁF

T2

CHx_INP

T1

5 ꢀ

0.1 ꢁF

25 ꢀ

0.1 ꢁF

R_IN

C_IN

25 ꢀ

5 ꢀ

0.1 ꢁF

CHx_INM

1:1

Device

图 9-17. Input Drive Circuit

9.2.2 Detailed Design Procedure

For optimum performance, the analog inputs must be driven differentially. This architecture improves common-

mode noise immunity and even-order harmonic rejection. A small resistor (5 Ω to 10 Ω) in series with each input

pin is recommended to damp out ringing caused by package parasitics, as shown in 图 9-17.

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9.2.3 Application Curves

图 9-18 and 图 9-19 show the typical performance at 170 MHz and 230 MHz, respectively.

0

-20

0

-20

-40

-60

-80

-100

-120

-100

-120

0

100

200 300

Input Frequency (MHz)

400

500

0

100

200 300

Input Frequency (MHz)

400

500

D003

D004

SNR = 68.9 dBFS; SFDR = 86 dBc; IL spur = 84 dBc; non

HD2, HD3 spur = 89 dBc

SNR = 68.1 dBFS; SFDR = 84 dBc; IL spur = 86 dBc; non

HD2, HD3 spur = 86 dBc

图 9-18. FFT for 170-MHz Input Signal

图 9-19. FFT for 230-MHz Input Signal

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10 Power Supply Recommendations

The device requires a 1.15-V nominal supply for IOVDD, a 1.9-V nominal supply for DVDD, a 1.9-V nominal

supply for AVDD, and a 3.0-V nominal supply for AVDD3V. For detailed information regarding the operating

voltage minimum and maximum specifications of different supplies, see the Recommended Operating

Conditions table.

10.1 Power Sequencing and Initialization

图 10-1 shows the suggested power-up sequencing for the device. Note that the 1.15-V IOVDD supply must rise

before the 1.9-V DVDD supply. If the 1.9-V DVDD supply rises before the 1.15-V IOVDD supply, then the internal

default register settings may not load properly. The other supplies (the 3-V AVDD3V and the 1.9-V AVDD), can

come up in any order during the power sequence. The power supplies can ramp up at any rate and there is no

hard requirement for the time delay between IOVDD ramp up to DVDD ramp-up (can be in orders of

microseconds but is recommend to be a few milliseconds).

IOVDD = 1.15 V

DVDD = 1.9 V

AVDD = 1.9 V

AVDD = 3 V

图 10-1. Power Sequencing for the ADS54Jxx Family of Devices

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11 Layout

11.1 Layout Guidelines

The device evaluation module (EVM) layout can be used as a reference layout to obtain the best performance. A

layout diagram of the EVM top layer is provided in 图 11-1. The ADS54J40 EVM User's Guide, SLAU652,

provides a complete layout of the EVM. Some important points to remember during board layout are:

• Analog inputs are located on opposite sides of the device pinout to ensure minimum crosstalk on the package

level. To minimize crosstalk onboard, the analog inputs must exit the pinout in opposite directions, as

illustrated in the reference layout of 图 11-1 as much as possible.

• In the device pinout, the sampling clock is located on a side perpendicular to the analog inputs in order to

minimize coupling between them. This configuration is also maintained on the reference layout of 图 11-1 as

much as possible.

• Keep digital outputs away from the analog inputs. When these digital outputs exit the pinout, the digital output

traces must not be kept parallel to the analog input traces because this configuration can result in coupling

from the digital outputs to the analog inputs and degrade performance. All digital output traces to the receiver

[such as a field-programmable gate arrays (FPGAs) or an application-specific integrated circuits (ASICs)]

must be matched in length to avoid skew among outputs.

• At each power-supply pin (AVDD, DVDD, or AVDDD3V), keep a 0.1-µF decoupling capacitor close to the

device. A separate decoupling capacitor group consisting of a parallel combination of 10-µF, 1-µF, and 0.1-µF

capacitors can be kept close to the supply source.

• The PDN and SDOUT traces must be routed away from the analog input traces. When the PDN and SDOUT

pins are programmed to carry OVR information, the proximity of these pins to the analog traces may result in

degradation of the ADC performance because of coupling. For best performance, the PDN and SDOUT

traces must not overlap or cross the path of the analog input traces even if routed on different layers of the

PCB.

11.2 Layout Example

图 11-1. ADS54J40 EVM Layout

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12 Device and Documentation Support

12.1 Documentation Support

12.1.1 Related Documentation

For related documentation see the following:

• ADS54J20 Dual-Channel, 12-Bit, 1.0-GSPS, Analog-to-Digital Converter

• ADS54J42 Dual-Channel, 14-Bit, 625-MSPS, Analog-to-Digital Converter

• ADS54J60 Dual-Channel, 16-Bit, 1.0-GSPS Analog-to-Digital Converter

• ADS54J66 Quad-Channel, 14-Bit, 500-MSPS ADC with Integrated DDC

• ADS54J69 Dual-Channel, 16-Bit, 500-MSPS, Analog-to-Digital Converter

• ADS54J40EVM User's Guide

12.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper

right corner, click on Alert me to register and receive a weekly digest of any product information that has

changed. For change details, review the revision history included in any revised document.

12.3 支持资源

TI E2E^™支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解

答或提出自己的问题可获得所需的快速设计帮助。

链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅

TI 的《使用条款》。

12.4 Trademarks

TI E2E^™is a trademark of Texas Instruments.

所有商标均为其各自所有者的财产。

12.5 静电放电警告

静电放电 (ESD) 会损坏这个集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理

和安装程序，可能会损坏集成电路。

ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参

数更改都可能会导致器件与其发布的规格不相符。

12.6 术语表

TI 术语表

本术语表列出并解释了术语、首字母缩略词和定义。

Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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PACKAGE MATERIALS INFORMATION

www.ti.com

4-Jan-2022

TRAY

Chamfer on Tray corner indicates Pin 1 orientation of packed units.

*All dimensions are nominal

Device

Package Package Pins SPQ Unit array

Max

matrix temperature

(°C)

L (mm)

W

K0

P1

CL

CW

Name

Type

(mm) (µm) (mm) (mm) (mm)

ADS54J40IRMP

RMP

VQFNP

72

168

8 X 21

150

315 135.9 7620 14.65

11

11.95

Pack Materials-Page 1

PACKAGE OUTLINE

RMP0072A

VQFN - 0.9 mm max height

SCALE 1.700

VQFN

10.1

9.9

A

B

PIN 1 ID

10.1

9.9

0.9 MAX

0.05

0.00

C

SEATING PLANE

0.08 C

(0.2)

4X (45 X0.42)

19

36

18

37

SYMM

4X

8.5

8.5 0.1

PIN 1 ID

(R0.2)

1

54

0.30

0.18

72X

72

55

68X 0.5

SYMM

0.5

0.3

0.1

C B

A

72X

0.05

C

4221047/B 02/2014

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

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EXAMPLE BOARD LAYOUT

RMP0072A

VQFN - 0.9 mm max height

VQFN

(

8.5)

SYMM

72X (0.6)

SEE DETAILS

55

72

1

54

72X (0.24)

(0.25) TYP

SYMM

(9.8)

(1.315) TYP

68X (0.5)

(

0.2) TYP

VIA

37

18

19

36

(1.315) TYP

(9.8)

LAND PATTERN EXAMPLE

SCALE:8X

0.07 MAX

ALL AROUND

0.07 MIN

ALL AROUND

SOLDER MASK

OPENING

METAL

SOLDER MASK

OPENING

METAL

NON SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4221047/B 02/2014

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see QFN/SON PCB application report

in literature No. SLUA271 (www.ti.com/lit/slua271).

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EXAMPLE STENCIL DESIGN

RMP0072A

VQFN - 0.9 mm max height

VQFN

(9.8)

72X (0.6)

(1.315) TYP

72

55

1

54

72X (0.24)

(1.315)

TYP

(0.25) TYP

SYMM

(9.8)

(1.315)

TYP

68X (0.5)

METAL

TYP

37

18

(

0.2) TYP

VIA

19

36

36X ( 1.115)

(1.315) TYP

SYMM

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD

62% PRINTED SOLDER COVERAGE BY AREA

SCALE:8X

4221047/B 02/2014

NOTES: (continued)

5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

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邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	ADS54J40IRMP
厂家：	TEXAS INSTRUMENTS
描述：	双通道、14 位、1.0GSPS 模数转换器 (ADC) \| RMP \| 72 \| -40 to 85 转换器模数转换器
文件：	总115页 (文件大小：5989K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ADS54J40IRMP [TI]

相关型号：

ADS54J40IRMPT

ADS54J42

ADS54J42IRMP

ADS54J42IRMPT

ADS54J54

ADS54J54IRGCR

ADS54J54IRGCT

ADS54J60

ADS54J60IRMP

ADS54J60IRMPT

ADS54J64

ADS54J64IRMP