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ADS54J60

ZHCSE42D –APRIL 2015–REVISED APRIL 2019

ADS54J60 双通道 16 位 1.0GSPS 模数转换器

1 特性

3 说明

1

•

16 位分辨率、双通道、1GSPS ADC

ADS54J60 是一款低功耗、高带宽 16 位、1.0GSPS

双通道模数转换器 (ADC)。该器件经设计具有高信噪

比 (SNR)，可提供 -159dBFS/Hz 的噪底，从而协助应

用在宽瞬时带宽内实现最高动态范围。该器件支持

JESD204B 串行接口，数据传输速率高达 10Gbps，每

个 ADC 可支持 2 或 4 条通道。已缓冲模拟输入在大

大减少采样保持毛刺脉冲能量的同时，在宽频率范围内

提供统一的输入阻抗。可选择将每个 ADC 通道连接至

数字下变频器 (DDC) 模块。ADS54J60 以超低功耗在

宽输入频率范围内提供出色的无杂散动态范围

(SFDR)。

本底噪声：–159dBFS/Hz

频谱性能（f_IN= 170MHz，–1dBFS）：

–

信噪比 (SNR)：70dBFS

噪声频谱密度 (NSD)：–157dBFS/Hz

SFDR：86dBc（包括交错音调）

SFDR：89dBc（不包括 HD2、HD3 和交错音

调）

•

频谱性能（f_IN= 350MHz，–1dBFS）：

–

SNR：67.5dBFS

NSD：–154.5dBFS/Hz

SFDR：75dBc

JESD204B 接口减少了接口线路数，从而实现高系统

集成度。内部锁相环 (PLL) 会将 ADC 采样时钟加倍，

以获得串行化各通道的 16 位数据时所使用的位时钟。

SFDR：85dBc（不包括 HD2、HD3 和交错音

调）

•

通道隔离：f_IN= 170MHz 时为 100dBc

输入满标度：1.9V_PP

器件信息

器件型号

ADS54J60

封装

封装尺寸（标称值）

输入带宽 (3dB)：1.2GHz

片上抖动

VQFNP (72)

10.00mm x 10.00mm

(1) 如需了解所有可用封装，请参阅产品说明书末尾的可订购产品

附录。

集成宽带 DDC 块

支持子类 1 的 JESD204B 接口：

–

10.0Gbps 时每个 ADC 具有 2 条信道

5.0Gbps 时每个 ADC 具有 4 条信道

支持多芯片同步

170MHz 输入信号的 FFT

0

•

功耗：1GSPS 时为 1.35W/通道

SNR = 70 dBFS

SFDR = 86 dBc

Non HD2,HD3 = 89 dBc

封装：72 引脚 VQFNP (10mm × 10mm)

-20

2 应用

-40

-60

•

雷达和天线阵列

无线宽带

电缆 CMTS、DOCSIS 3.1 接收器

通信测试设备

-80

-100

-120

微波接收器

软件定义无线电 (SDR)

数字转换器

0

100

200

300

400

500

Input Frequency (MHz)

D000

医疗成像和诊断

1

本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确

性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SBAS706

ADS54J60

ZHCSE42D –APRIL 2015–REVISED APRIL 2019

www.ti.com.cn

8.3 Feature Description................................................. 26

8.4 Device Functional Modes........................................ 34

8.5 Register Maps......................................................... 45

Application and Implementation ........................ 74

9.1 Application Information............................................ 74

9.2 Typical Application .................................................. 83

1

2

3

4

5

6

7

特性.......................................................................... 1

应用.......................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 2

Device Comparison Table..................................... 5

Pin Configuration and Functions......................... 5

Specifications......................................................... 7

7.1 Absolute Maximum Ratings ...................................... 7

7.2 ESD Ratings.............................................................. 7

7.3 Recommended Operating Conditions....................... 7

7.4 Thermal Information.................................................. 8

7.5 Electrical Characteristics........................................... 8

7.6 AC Characteristics .................................................... 9

7.7 Digital Characteristics ............................................. 12

7.8 Timing Requirements.............................................. 13

7.9 Typical Characteristics............................................ 15

7.10 Typical Characteristics: Contour ........................... 24

Detailed Description ............................................ 25

8.1 Overview ................................................................. 25

8.2 Functional Block Diagram ....................................... 25

9

10 Power Supply Recommendations ..................... 85

10.1 Power Sequencing and Initialization..................... 86

11 Layout................................................................... 87

11.1 Layout Guidelines ................................................. 87

11.2 Layout Example .................................................... 88

12 器件和文档支持 ..................................................... 89

12.1 文档支持................................................................ 89

12.2 接收文档更新通知 ................................................. 89

12.3 社区资源................................................................ 89

12.4 商标....................................................................... 89

12.5 静电放电警告......................................................... 89

12.6 术语表 ................................................................... 89

13 机械、封装和可订购信息....................................... 89

8

4 修订历史记录

注：之前版本的页码可能与当前版本有所不同。

Changes from Revision C (January 2017) to Revision D

Page

•

已更改 170MHz 输入信号的 FFT 图 ....................................................................................................................................... 1

Changed the description of the CLKINM, CLKINP, SYSREFM, SYSREFP, and PDN pins in Pin Functions table .............. 6

Changed typical values across parameters in AC Characteristics table................................................................................ 9

Changed value of A_INfrom –1 dBFS to –3 dBFS in 470 MHz test condition across all parameters in AC

Characteristics table ............................................................................................................................................................... 9

•

Added ENOB parameter to AC Characteristics table .......................................................................................................... 11

Changed the first footnote in Timing Characteristics table................................................................................................... 13

Changed the typical value of FOVR latency from 18 + 4 ns to 18 in Timing Characteristics table ..................................... 13

Changed parameter name from t_PDto t_PDIin Timing Characteristics table .......................................................................... 13

Changed FFT for 170-MHz Input Signal figure .................................................................................................................... 15

Changed FFT for 470-MHz Input Signal at –3 dBFS figure, title, and conditions ................................................................ 16

Changed conditions of FFT for 720-MHz Input Signal at –6 dBFS figure............................................................................ 16

Changed Spurious-Free Dynamic Range vs Input Frequency figure................................................................................... 17

Changed DDC Block figure .................................................................................................................................................. 27

Deleted register address 53 from Register Address for Power-Down Modes table............................................................. 33

Added last sentence to Step 4 in Serial Register Readout: Analog Bank section ............................................................... 36

Added last sentence to Step 4 in Serial Register Readout: JESD Bank section ................................................................ 37

Added SDOUT Timing Diagram figure ................................................................................................................................. 38

Deleted unrelated patterns in in JESD204B Test Patterns section...................................................................................... 40

Changed Serial Interface Registers figure............................................................................................................................ 45

Added register addresses 1h and 2h and their descriptions to GENERAL REGISTERS in Register Map section............. 46

Changed the name of MASTER PAGE (80h) to MASTER PAGE (ANALOG BANK PAGE SEL= 80h in Register Map

table...................................................................................................................................................................................... 46

•

Changed register 53h and 54h, and their descriptions to MASTER PAGE (ANALOG BANK PAGE SEL = 80h) in

2

ADS54J60

www.ti.com.cn

ZHCSE42D –APRIL 2015–REVISED APRIL 2019

修订历史记录 (接下页)

Register Map section............................................................................................................................................................ 46

Changed the name of ADC PAGE (0Fh) to ADC PAGE (ANALOG BANK PAGE SEL= 0Fh) in Register Map table......... 46

•

Changed the name of MAIN DIGITAL PAGE (6800h) to MAIN DIGITAL PAGE (JESD BANK PAGE SEL=6800h) in

Register Map table ............................................................................................................................................................... 46

•

Changed bit 5, register 4E of MAIN DIGITAL PAGE (JESD BANK PAGE SEL = 6800h) from 0 to IMPROVE IL

PERF ................................................................................................................................................................................... 46

Changed the name of JESD DIGITAL PAGE (6900h) to JESD DIGITAL PAGE (JESD BANK PAGE SEL=6900h) in

Register Map table ............................................................................................................................................................... 47

Changed the name of JESD ANALOG PAGE (6A00h) to JESD ANALOG PAGE (JESD BANK PAGE SEL=6A00h)

in Register Map table............................................................................................................................................................ 47

•

Changed bit 1, register 12 of JESD ANALOG PAGE (6A00h) from 0 to ALWAYS WRITE 1 ............................................. 47

Changed bits 5 and 3, register 17 of JESD ANALOG PAGE (JESD BANK PAGE SEL = 6A00h) from 0 to LANE

PDN 1 and from 0 to LANE PDN 0 respectively .................................................................................................................. 47

•

Added OFFSET READ Page and OFFSET LOAD Page registers to Register Map table................................................... 47

Added ADS54J60 Access Type Codes table, deleted legends from Register Descriptions section ................................... 49

Added register 1h and 2h to Register Descriptions section ................................................................................................ 50

Changed description of Registers 3h and 4h (address = 3h and 4h) in General Registers Page....................................... 51

Changed description of bit 0 in Register 4Fh (address = 4Fh), Master Page (080h) .......................................................... 55

Changed the description of registers 53h and 54h .............................................................................................................. 56

Changed 9.5 dB to 12 dB in description of bits 6-0 in Register 44h (address = 44h), Main Digital Page (6800h).............. 59

Changed bit 5 from 0 the IMPROVE IL PERF and changed Register 4Eh Field Descriptions table in Register 4Eh

(address = 4Eh), Main Digital Page (6800h) ........................................................................................................................ 61

•

Changed bit 1 from 0 to ALWAYS WRITE 1 in Register 12h (address = 12h), JESD Analog Page (6A00h) ..................... 68

Changed bit 1 from ALWAYS WRITE 1 to 0 in register 15h bit register ............................................................................. 69

Added x (where x = 0, 2, or 3) to bits 7-2 in Register 13h-15h Field Descriptions table of Registers 13h-15h

(address = 13h-15h), JESD Analog Page (6A00h) .............................................................................................................. 69

•

Changed bit 6 from W to R/W, bit 5 from 0 to LANE PDN 1 and from W to R/W, and changed bit 3 from 0 to LANE

PDN 0 and from W to R/W in Register 17h bit register table of Register 17h (address = 17h), JESD Analog Page

(6A00h)................................................................................................................................................................................. 70

Changed bits 5-0 of Register 17h Field Descriptions table in Register 17h (address = 17h), JESD Analog Page

(6A00h)................................................................................................................................................................................. 70

•

Added Offset Read Page Register and Offset Load Page Register sections to Register Descriptions section .................. 72

Added DC Offset Correction Block in the ADS54J60 section .............................................................................................. 78

Changed ±512 codes to ±1024 codes in DC Offset Correction Block in the ADS54J60 section......................................... 78

Added Idle Channel Histogram section ................................................................................................................................ 82

Added transformer TC1-1-13M+ to Transformer-Coupled Circuits section.......................................................................... 84

Added note to Layout Guidelines section............................................................................................................................. 87

Changes from Revision B (August 2015) to Revision C

Page

•

已更改频谱性能特性要点的最后一个子要点中的 SFDR 值.................................................................................................. 1

已更改器件信息表.................................................................................................................................................................. 1

Added CDM row to ESD Ratings table................................................................................................................................... 7

Changed the minimum value for the input clock frequency in the Recommended Operating Conditions table ................... 7

Added minimum value to the ADC sampling rate parameter in the Electrical Characteristics table...................................... 8

Added 720 -MHz test condition rows to SNR, NSD, SINAD, SFDR, HD2, HD3, Non HD2, HD3, THD, and SFDR_IL

parameters of AC Characteristics table.................................................................................................................................. 9

•

Changed typical specification of SFDR parameter in AC Characteristics table................................................................... 10

3

ADS54J60

ZHCSE42D –APRIL 2015–REVISED APRIL 2019

www.ti.com.cn

•

Changed Sample Timing, Aperture jitter parameter typical specification in Timing Characteristics section........................ 13

Added the FOVR latency parameter to the Timing Characteristics table............................................................................. 13

Added FFT for 720-MHz Input Signal at –6 dBFS figure ..................................................................................................... 16

Added Typical Characteristics: Contour section................................................................................................................... 24

Changed Overview section .................................................................................................................................................. 25

Changed Functional Block Diagram section: changed Control and SPI block and added dashed outline to FOVR traces 25

Added Figure 60 and text reference to Analog Inputs section ............................................................................................. 27

Changed SYSREF Signal section: changed Table 4 and added last paragraph................................................................. 30

Added SYSREF Not Present (Subclass 0, 2) section .......................................................................................................... 31

Changed the number of clock cycles in the Fast OVR section ............................................................................................ 32

Changed Table 10 and Table 11.......................................................................................................................................... 41

Changed Table 12 and Table 13.......................................................................................................................................... 42

Deleted Lane Enable with Decimation subsection .............................................................................................................. 42

Added the Program Summary of DDC Modes and JESD Link Configuration table............................................................. 43

Added Figure 84 to Register Maps section .......................................................................................................................... 45

Changed Table 15 ................................................................................................................................................................ 46

Deleted register 39h, 3Ah, and 56h ..................................................................................................................................... 46

Changed Example Register Writes section.......................................................................................................................... 49

Updated register descriptions .............................................................................................................................................. 50

Added Table 54 .................................................................................................................................................................... 64

Deleted row for bit 1 in Table 64 as bit 1 is included in last table row ................................................................................ 69

Changed Table 75 ................................................................................................................................................................ 75

Changed internal aperture jitter value in SNR and Clock Jitter section ............................................................................... 78

Changed Figure 141............................................................................................................................................................. 78

Changed Power Supply Recommendations section ........................................................................................................... 85

Added the Power Sequencing and Initialization section....................................................................................................... 86

已添加文档支持和接收文档更新通知部分.......................................................................................................................... 89

Changes from Revision A (May 2015) to Revision B

Page

•

已投入量产.............................................................................................................................................................................. 1

4

ADS54J60

www.ti.com.cn

ZHCSE42D –APRIL 2015–REVISED APRIL 2019

5 Device Comparison Table

PART NUMBER

ADS54J20

ADS54J42

ADS54J40

ADS54J60

ADS54J66

ADS54J69

SPEED GRADE (MSPS)

RESOLUTION (Bits)

CHANNEL

1000

625

12

14

16

14

16

2

4

2

1000

500

6 Pin Configuration and Functions

RMP Package

72-Pin VQFNP

Top View

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

1

2

54

DB3M

DB3P

DA3M

DA3P

DGND

IOVDD

PDN

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

3

DGND

IOVDD

SDIN

4

5

6

SCLK

RES

7

SEN

RESET

DVDD

AVDD

AVDD3V

AVDD

INAP

8

DVDD

AVDD

AVDD3V

SDOUT

AVDD

INBP

9

GND Pad

(Back Side)

10

11

12

13

14

15

16

17

18

INBM

INAM

AVDD

AVDD3V

AVDD

AGND

AVDD

AVDD3V

AVDD

AGND

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

5

ADS54J60

ZHCSE42D –APRIL 2015–REVISED APRIL 2019

www.ti.com.cn

Pin Functions

I/O

DESCRIPTION

NAME

NO.

CLOCK, SYSREF

Negative differential clock input for the ADC. The device has an internal 100-Ω termination

resistor between the CLKINP and CLKINM pins.

CLKINM

CLKINP

28

27

I

Positive differential clock input for the ADC. The device has an internal 100-Ω termination

resistor between the CLKINP and CLKINM pins.

SYSREFM

34

33

I

Negative external SYSREF input. Connect this pin to GND if not used.

Positive external SYSREF input. Connect this pin to 1.8 V if not used.

SYSREFP

CONTROL, SERIAL

Power down, active low pin. Can be configured via an SPI register setting.

Can be configured to fast overrange output for channel A via the SPI.

PDN

50

I/O

RESET

SCLK

SDIN

48

6

I

Hardware reset; active high. This pin has an internal 20-kΩ pulldown resistor.

Serial interface clock input

5

Serial interface data input

Serial interface data output.

Can be configured to fast overrange output for channel B via the SPI.

SDOUT

11

7

O

I

SEN

Serial interface enable

DATA INTERFACE

DA0M

DA1M

DA2M

DA3M

DA0P

62

59

56

54

61

58

55

53

65

68

71

1

O

JESD204B serial data negative outputs for channel A

DA1P

JESD204B serial data positive outputs for channel A

JESD204B serial data negative outputs for channel B

DA2P

DA3P

DB0M

DB1M

DB2M

DB3M

DB0P

66

69

72

2

DB1P

O

I

JESD204B serial data positive outputs for channel B

Synchronization input for JESD204B port

DB2P

DB3P

SYNC

INPUT, COMMON MODE

INAM

63

41

42

14

13

I

Differential analog negative input for channel A

Differential analog positive input for channel A

Differential analog negative input for channel B

Differential analog positive input for channel B

INAP

INBM

INBP

Common-mode voltage, 2.1 V.

VCM

22

O

Note that analog inputs are internally biased to this pin through 600 Ω (effective), no external

connection from the VCM pin to the INxP or INxM pin is required.

POWER SUPPLY

AGND

AVDD

18, 23, 26, 29, 32, 36, 37

I

Analog ground

9, 12, 15, 17, 25, 30, 35, 38,

40, 43, 44, 46

Analog 1.9-V power supply

AVDD3V

DGND

DVDD

IOVDD

NC, RES

NC

10, 16, 24, 31, 39, 45

3, 52, 60, 67

8, 47

I

Analog 3.0-V power supply for the analog buffer

Digital ground

Digital 1.9-V power supply

4, 51, 57, 64, 70

Digital 1.15-V power supply for the JESD204B transmitter

19-21

49

—

I

Unused pins, do not connect

RES

Reserved pin. Connect to DGND.

6

ADS54J60

www.ti.com.cn

ZHCSE42D –APRIL 2015–REVISED APRIL 2019

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

–0.3

–0.2

–0.3

–0.2

–65

MAX

UNIT

V

AVDD3V

3.6

AVDD

Supply voltage range

DVDD

2.1

IOVDD

Voltage between AGND and DGND

INAP, INBP, INAM, INBM

1.4

0.3

3

V

CLKINP, CLKINM

Voltage applied to input pins

AVDD + 0.3

2.1

V

SYSREFP, SYSREFM

SCLK, SEN, SDIN, RESET, SYNC, PDN

Storage temperature, T_stg

150

°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

7.2 ESD Ratings

VALUE

±1000

±500

UNIT

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾

V_(ESD)

Electrostatic discharge

V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V HBM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)⁽¹⁾⁽²⁾

MIN

2.85

1.8

NOM

3.0

MAX

3.6

UNIT

AVDD3V

AVDD

1.9

2.0

Supply voltage range

Analog inputs

V

DVDD

1.7

1.9

2.0

IOVDD

1.1

1.15

1.9

1.2

Differential input voltage range

Input common-mode voltage

V_PP

V

2.0

Maximum analog input frequency for 1.9-V_PPinput amplitude⁽³⁾⁽⁴⁾

Input clock frequency, device clock frequency

Sine wave, ac-coupled

400

MHz

250⁽⁵⁾

0.75

0.8

1000

1.5

1.6

Input clock amplitude differential

Clock inputs

Temperature

LVPECL, ac-coupled

V_PP

(V_CLKP– V_CLKM

)

LVDS, ac-coupled

0.7

Input device clock duty cycle

Operating free-air, T_A

45%

–40

50%

55%

85

ºC

Operating junction, T_J

105⁽⁶⁾

125

(1) SYSREF must be applied for the device to initialize; see the SYSREF Signal section for details.

(2) After power-up, always use a hardware reset to reset the device for the first time; see Table 75 for details.

(3) Operating 0.5 dB below the maximum-supported amplitude is recommended to accommodate gain mismatch in interleaving ADCs.

(4) At high frequencies, the maximum supported input amplitude reduces; see Figure 37 for details.

(5) See Table 10.

(6) Prolonged use above the nominal junction temperature can increase the device failure-in-time (FIT) rate.

7

ADS54J60

ZHCSE42D –APRIL 2015–REVISED APRIL 2019

www.ti.com.cn

7.4 Thermal Information

ADS54J60

THERMAL METRIC⁽¹⁾

RMP (VQFNP)

UNIT

72 PINS

22.3

5.1

R_θJA

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

°C/W

R_θJC(top)

R_θJB

2.4

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

0.1

ψ_JB

2.3

R_θJC(bot)

0.4

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

7.5 Electrical Characteristics

typical values are at T_A= 25°C, full temperature range is from T_MIN= –40°C to T_MAX= 85°C, ADC sampling rate = 1.0 GSPS,

50% clock duty cycle, AVDD3V = 3.0 V, AVDD = DVDD = 1.9 V, IOVDD = 1.15 V, –1-dBFS differential input, and 0-dB digital

gain (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

GENERAL

ADC sampling rate

Resolution

250

16

1000 MSPS

Bits

POWER SUPPLIES

AVDD3V

AVDD

DVDD

IOVDD

I_AVDD3V

I_AVDD

3.0-V analog supply

2.85

1.8

3.0

1.9

3.6

2.0

V

1.9-V analog supply

1.9-V digital supply

1.7

1.9

2.0

V

1.15-V SERDES supply

3.0-V analog supply current

1.9-V analog supply current

1.9-V digital supply current

1.15-V SERDES supply current

Total power dissipation

1.1

1.15

334

359

197

566

2.71

211

618

2.80

1.2

V

V_IN= full-scale on both channels

Eight lanes active (LMFS = 8224)

Four lanes active (LMFS = 4244)

360

510

260

920

3.1

mA

W

I_DVDD

I_IOVDD

P_dis

I_DVDD

1.9-V digital supply current

1.15-V SERDES supply current

Total power dissipation

mA

W

I_IOVDD

P_dis

Four lanes active (LMFS = 4222),

2X decimation

I_DVDD

I_IOVDD

P_dis

1.9-V digital supply current

1.15-V SERDES supply current

Total power dissipation

197

593

2.74

176

562

mA

W

Four lanes active (LMFS = 4222),

2X decimation

Four lanes active (LMFS = 4222),

2X decimation

Two lanes active (LMFS = 2221),

4X decimation

I_DVDD

I_IOVDD

1.9-V digital supply current

1.15-V SERDES supply current

mA

Two lanes active (LMFS = 2221),

4X decimation

Two lanes active (LMFS = 2221),

4X decimation

(1)

P_dis

Total power dissipation

2.66

139

W

Global power-down power dissipation

315

mW

(1) See the Power-Down Mode section for details.

8

ADS54J60

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ZHCSE42D –APRIL 2015–REVISED APRIL 2019

Electrical Characteristics (continued)

typical values are at T_A= 25°C, full temperature range is from T_MIN= –40°C to T_MAX= 85°C, ADC sampling rate = 1.0 GSPS,

50% clock duty cycle, AVDD3V = 3.0 V, AVDD = DVDD = 1.9 V, IOVDD = 1.15 V, –1-dBFS differential input, and 0-dB digital

gain (unless otherwise noted)

PARAMETER

ANALOG INPUTS (INAP, INAM, INBP, INBM)

Differential input full-scale voltage

TEST CONDITIONS

MIN

TYP

MAX

UNIT

1.9

2.0

0.6

4.7

V_PP

V

V_IC

R_IN

C_IN

Common-mode input voltage

Differential input resistance

Differential input capacitance

At 170-MHz input frequency

kΩ

pF

50-Ω source driving ADC inputs

terminated with 50-Ω

Analog input bandwidth (3 dB)

1.2

GHz

CLOCK INPUT (CLKINP, CLKINM)

CLKINP and CLKINM are

connected to internal biasing

voltage through 400-Ω

Internal clock biasing

1.15

V

7.6 AC Characteristics

typical values are at T_A= 25°C, full temperature range is from T_MIN= –40°C to T_MAX= 85°C, ADC sampling rate = 1.0 GSPS,

50% clock duty cycle, AVDD3V = 3.0 V, AVDD = DVDD = 1.9 V, IOVDD = 1.15 V, –1-dBFS differential input, and 0-dB digital

gain (unless otherwise noted)

PARAMETER

TEST CONDITIONS

f_IN= 10 MHz, A_IN= –1 dBFS

f_IN= 100 MHz, A_IN= –1 dBFS

f_IN= 170 MHz, A_IN= –1 dBFS

f_IN= 230 MHz, A_IN= –1 dBFS

f_IN= 270 MHz, A_IN= –1 dBFS

f_IN= 300 MHz, A_IN= –1 dBFS

f_IN= 370 MHz, A_IN= –1 dBFS

f_IN= 470 MHz, A_IN= –3 dBFS

f_IN= 720 MHz, A_IN= –6 dBFS

MIN

TYP

70.9

70.6

70

MAX

UNIT

67.2

69.2

68.7

68.1

67.1

67.6

66

SNR

Signal-to-noise ratio

dBFS

f_IN= 720 MHz, A_IN= –6 dBFS,

gain = 5 dB

64.4

f_IN= 10 MHz, A_IN= –1 dBFS

f_IN= 100 MHz, A_IN= –1 dBFS

f_IN= 170 MHz, A_IN= –1 dBFS

f_IN= 230 MHz, A_IN= –1 dBFS

f_IN= 270 MHz, A_IN= –1 dBFS

f_IN= 300 MHz, A_IN= –1 dBFS

f_IN= 370 MHz, A_IN= –1 dBFS

f_IN= 470 MHz, A_IN= –3 dBFS

f_IN= 720 MHz, A_IN= –6 dBFS

157.9

157.6

157

154.2

156.2

155.7

155.1

154.1

154.6

153

NSD

Noise spectral density

dBFS/Hz

f_IN= 720 MHz, A_IN= –6 dBFS,

gain = 5 dB

151.4

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AC Characteristics (continued)

typical values are at T_A= 25°C, full temperature range is from T_MIN= –40°C to T_MAX= 85°C, ADC sampling rate = 1.0 GSPS,

50% clock duty cycle, AVDD3V = 3.0 V, AVDD = DVDD = 1.9 V, IOVDD = 1.15 V, –1-dBFS differential input, and 0-dB digital

gain (unless otherwise noted)

PARAMETER

TEST CONDITIONS

f_IN= 10 MHz, A_IN= –1 dBFS

f_IN= 100 MHz, A_IN= –1 dBFS

f_IN= 170 MHz, A_IN= –1 dBFS

f_IN= 230 MHz, A_IN= –1 dBFS

f_IN= 270 MHz, A_IN= –1 dBFS

f_IN= 300 MHz, A_IN= –1 dBFS

f_IN= 370 MHz, A_IN= –1 dBFS

f_IN= 470 MHz, A_IN= –3 dBFS

f_IN= 720 MHz, A_IN= –6 dBFS

MIN

TYP

70.7

70.4

69.8

69.1

68.3

67.6

66

MAX

UNIT

67

SINAD

SFDR

HD2

Signal-to-noise and distortion ratio

dBFS

66.8

65.2

f_IN= 720 MHz, A_IN= –6 dBFS,

gain = 5 dB

64.3

f_IN= 10 MHz, A_IN= –1 dBFS

f_IN= 100 MHz, A_IN= –1 dBFS

f_IN= 170 MHz, A_IN= –1 dBFS

f_IN= 230 MHz, A_IN= –1 dBFS

f_IN= 270 MHz, A_IN= –1 dBFS

f_IN= 300 MHz, A_IN= –1 dBFS

f_IN= 370 MHz, A_IN= –1 dBFS

f_IN= 470 MHz, A_IN= –3 dBFS

f_IN= 720 MHz, A_IN= –6 dBFS

85

84

88

86

81

78

73

72

68

78

79

82

Spurious-free dynamic range

(excluding IL spurs)

dBc

f_IN= 720 MHz, A_IN= –6 dBFS,

gain = 5 dB

72

f_IN= 10 MHz, A_IN= –1 dBFS

f_IN= 100 MHz, A_IN= –1 dBFS

f_IN= 170 MHz, A_IN= –1 dBFS

f_IN= 230 MHz, A_IN= –1 dBFS

f_IN= 270 MHz, A_IN= –1 dBFS

f_IN= 300 MHz, A_IN= –1 dBFS

f_IN= 370 MHz, A_IN= –1 dBFS

f_IN= 470 MHz, A_IN= –3 dBFS

f_IN= 720 MHz, A_IN= –6 dBFS

85

92

95

86

81

76

72

68

Second-order harmonic distortion

f_IN= 720 MHz, A_IN= –6 dBFS,

gain = 5 dB

72

f_IN= 10 MHz, A_IN= –1 dBFS

f_IN= 100 MHz, A_IN= –1 dBFS

f_IN= 170 MHz, A_IN= –1 dBFS

f_IN= 230 MHz, A_IN= –1 dBFS

f_IN= 270 MHz, A_IN= –1 dBFS

f_IN= 300 MHz, A_IN= –1 dBFS

f_IN= 370 MHz, A_IN= –1 dBFS

f_IN= 470 MHz, A_IN= –3 dBFS

f_IN= 720 MHz, A_IN= –6 dBFS

87

84

89

92

82

78

73

70

75

HD3

Third-order harmonic distortion

f_IN= 720 MHz, A_IN= –6 dBFS,

gain = 5 dB

84

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AC Characteristics (continued)

typical values are at T_A= 25°C, full temperature range is from T_MIN= –40°C to T_MAX= 85°C, ADC sampling rate = 1.0 GSPS,

50% clock duty cycle, AVDD3V = 3.0 V, AVDD = DVDD = 1.9 V, IOVDD = 1.15 V, –1-dBFS differential input, and 0-dB digital

gain (unless otherwise noted)

PARAMETER

TEST CONDITIONS

f_IN= 10 MHz, A_IN= –1 dBFS

f_IN= 100 MHz, A_IN= –1 dBFS

f_IN= 170 MHz, A_IN= –1 dBFS

f_IN= 230 MHz, A_IN= –1 dBFS

f_IN= 270 MHz, A_IN= –1 dBFS

f_IN= 300 MHz, A_IN= –1 dBFS

f_IN= 370 MHz, A_IN= –1 dBFS

f_IN= 470 MHz, A_IN= –3 dBFS

f_IN= 720 MHz, A_IN= –6 dBFS

MIN

TYP

94

97

93

95

91

85

90

MAX

UNIT

79

Non HD2, Spurious-free dynamic range

dBFS

HD3

(excluding HD2, HD3, and IL spur)

f_IN= 720 MHz, A_IN= –6 dBFS,

gain = 5 dB

96

f_IN= 10 MHz, A_IN= –1 dBFS

f_IN= 100 MHz, A_IN= –1 dBFS

f_IN= 170 MHz, A_IN= –1 dBFS

f_IN= 230 MHz, A_IN= –1 dBFS

f_IN= 270 MHz, A_IN= –1 dBFS

f_IN= 300 MHz, A_IN= –1 dBFS

f_IN= 370 MHz, A_IN= –1 dBFS

f_IN= 470 MHz, A_IN= –3 dBFS

f_IN= 720 MHz, A_IN= –6 dBFS

83

87

84

78

76

71

67

74

THD

Total harmonic distortion

dBc

Bits

dBc

f_IN= 720 MHz, A_IN= –6 dBFS,

gain = 5 dB

71

f_IN= 10 MHz, A_IN= –1 dBFS

f_IN= 100 MHz, A_IN= –1 dBFS

f_IN= 170 MHz, A_IN= –1 dBFS

f_IN= 230 MHz, A_IN= –1 dBFS

f_IN= 270 MHz, A_IN= –1 dBFS

f_IN= 300 MHz, A_IN= –1 dBFS

f_IN= 370 MHz, A_IN= –1 dBFS

f_IN= 470 MHz, A_IN= –3 dBFS

f_IN= 720 MHz, A_IN= –6 dBFS

11.5

11.4

11.3

11.2

11.0

10.9

10.7

10.8

10.5

ENOB

Effective number of bits

f_IN= 720 MHz, A_IN= –6 dBFS,

gain = 5 dB

10.4

f_IN= 10 MHz, A_IN= –1 dBFS

f_IN= 100 MHz, A_IN= –1 dBFS

f_IN= 170 MHz, A_IN= –1 dBFS

f_IN= 230 MHz, A_IN= –1 dBFS

f_IN= 270 MHz, A_IN= –1 dBFS

f_IN= 300 MHz, A_IN= –1 dBFS

f_IN= 370 MHz, A_IN= –1 dBFS

f_IN= 470 MHz, A_IN= –3 dBFS

f_IN= 720 MHz, A_IN= –6 dBFS

88

90

87

85

84

82

79

69

SFDR_IL

Interleaving spur

f_IN= 720 MHz, A_IN= –6 dBFS,

gain = 5 dB

75

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AC Characteristics (continued)

typical values are at T_A= 25°C, full temperature range is from T_MIN= –40°C to T_MAX= 85°C, ADC sampling rate = 1.0 GSPS,

50% clock duty cycle, AVDD3V = 3.0 V, AVDD = DVDD = 1.9 V, IOVDD = 1.15 V, –1-dBFS differential input, and 0-dB digital

gain (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

f_IN1= 185 MHz, f_IN2= 190 MHz,

A_IN= –7 dBFS

–88

Two-tone, third-order

intermodulation distortion

f_IN1= 365 MHz, f_IN2= 370 MHz,

A_IN= –7 dBFS

IMD3

–79

–75

100

dBFS

f_IN1= 465 MHz, f_IN2= 470 MHz,

A_IN= –7 dBFS

Crosstalk isolation between channel Full-scale, 170-MHz signal on

A and B aggressor; idle channel is victim

dB

7.7 Digital Characteristics

typical values are at T_A= 25°C, full temperature range is from T_MIN= –40°C to T_MAX= 85°C, ADC sampling rate = 1.0 GSPS,

50% clock duty cycle, AVDD3V = 3.0 V, AVDD = DVDD = 1.9 V, IOVDD = 1.15 V, –1-dBFS differential input, and 0-dB digital

gain (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNITS

DIGITAL INPUTS (RESET, SCLK, SEN, SDIN, SYNC, PDN)⁽¹⁾

V_IH

V_IL

High-level input voltage

Low-level input voltage

All digital inputs support 1.2-V and 1.8-V logic levels

SEN

0.8

V

0.4

0

50

0

I_IH

High-level input current

Low-level input current

µA

RESET, SCLK, SDIN, PDN, SYNC

SEN

I_IL

RESET, SCLK, SDIN, PDN, SYNC

DIGITAL INPUTS (SYSREFP, SYSREFM)

V_D

Differential input voltage

0.35

0.45

1.3

1.4

V

V_{(CM_DIG)}

Common-mode voltage for SYSREF

DIGITAL OUTPUTS (SDOUT, PDN⁽²⁾

)

DVDD –

0.1

V_OH

V_OL

High-level output voltage

Low-level output voltage

DVDD

V

0.1

DIGITAL OUTPUTS (JESD204B Interface: DxP, DxM)⁽³⁾

V_OD

V_OC

Output differential voltage

With default swing setting

700

450

mV_PP

mV

Output common-mode voltage

Transmitter pins shorted to any voltage between

–0.25 V and 1.45 V

Transmitter short-circuit current

Single-ended output impedance

Output capacitance

–100

100

mA

Ω

z_os

50

2

Output capacitance inside the device,

from either output to ground

pF

(1) The RESET, SCLK, SDIN, and PDN pins have a 20-kΩ (typical) internal pulldown resistor to ground, and the SEN pin has a 20-kΩ

(typical) pullup resistor to IOVDD.

(2) When functioning as an OVR pin for channel B.

(3) 100-Ω differential termination.

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7.8 Timing Requirements

typical values are at T_A= 25°C, full temperature range is from T_MIN= –40°C to T_MAX= 85°C, ADC sampling rate = 1.0 GSPS,

50% clock duty cycle, AVDD3V = 3.0 V, AVDD = DVDD = 1.9 V, IOVDD = 1.15 V, and –1-dBFS differential input (unless

otherwise noted)

MIN

TYP

MAX

UNITS

SAMPLE TIMING

Aperture delay

0.75

1.6

ns

ps

Aperture delay matching between two channels on the same device

Aperture delay matching between two devices at the same temperature and supply voltage

Aperture jitter

±70

±270

120

ps

f_Srms

WAKE-UP TIMING

Wake-up time to valid data after coming out of global power-down

150

µs

(1)

LATENCY

Input

clock

cycles

Data latency: ADC sample to digital output

OVR latency: ADC sample to OVR bit

134

62

Input

clock

cycles

Input

clock

cycles

FOVR latency: ADC sample to FOVR signal on pin

18

4

t_PDI

Propagation delay: logic gates and output buffers delay (does not change with f_S)

ns

SYSREF TIMING

t_{SU_SYSREF}Setup time for SYSREF, referenced to the input clock falling edge

300

100

900

ps

t_{H_SYSREF}

Hold time for SYSREF, referenced to the input clock falling edge

JESD OUTPUT INTERFACE TIMING CHARACTERISTICS

Unit interval

100

2.5

400

10

ps

Gbps

ps

Serial output data rate

Total jitter for BER of 1E-15 and lane rate = 10 Gbps

Random jitter for BER of 1E-15 and lane rate = 10 Gbps

Deterministic jitter for BER of 1E-15 and lane rate = 10 Gbps

26

0.75

12

ps rms

ps, pk-pk

Data rise time, data fall time: rise and fall times are measured from 20% to 80%,

differential output waveform, 2.5 Gbps ≤ bit rate ≤ 10 Gbps

t_R, t_F

35

ps

(1) Overall latency = latency + t_PDI

.

Sample N

t_{s_min}

t_{s_max}

CLKIN

1.0 GSPS

SYSREF

Figure 1. SYSREF Timing

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N+1

N+2

N

N+3

Sample

t_PD

Data Latency: 134 Clock Cycles

CLKINM

CLKINP

D

20

D

11

D

20

D

11

D

20

DA0P, DA0M,

DB0P, DB0M

Sample N-1

Sample N

Sample N+1

Sample N+2

D

10

D

1

D

10

D

1

D

10

DA1P, DA1M,

DB1P, DB1M

Sample N-1

Sample N

Sample N+1

Sample N+2

Figure 2. Sample Timing Requirements Diagram

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7.9 Typical Characteristics

typical values are at T_A= 25°C, full temperature range is from T_MIN= –40°C to T_MAX= 85°C, ADC sampling rate = 1.0 GSPS,

50% clock duty cycle, AVDD3V = 3.0 V, AVDD = DVDD = 1.9 V, IOVDD = 1.15 V, and –1-dBFS differential input (unless

otherwise noted)

0

-20

0

-20

-40

-60

-80

-100

-120

-100

-120

0

100

200

300

400

500

0

100

200

300

400

500

Input Frequency (MHz)

D001

D002

SNR = 71 dBFS; SFDR = 86 dBc;

SNR = 70.3 dBFS; SFDR = 90 dBc;

IL spur = 94 dBc; non HD2, HD3 spur = 89 dBc

IL spur = 95 dBc; non HD2, HD3 spur = 94 dBc

Figure 3. FFT for 10-MHz Input Signal

Figure 4. FFT for 140-MHz Input Signal

0

-20

-40

-60

-40

-60

-80

-100

-120

-100

-120

0

100

200

300

400

500

0

100

200

300

400

500

Input Frequency (MHz)

D003

D004

SNR = 69.8 dBFS; SFDR = 88 dBc;

SNR = 68.9 dBFS; SFDR = 85 dBc;

IL spur = 86 dBc; non HD2, HD3 spur = 89 dBc

IL spur = 85 dBc; non HD2, HD3 spur = 86 dBc

Figure 5. FFT for 170-MHz Input Signal

Figure 6. FFT for 230-MHz Input Signal

0

-20

-40

-60

-40

-60

-80

-100

-120

-100

-120

0

100

200

300

400

500

0

100

200

300

400

500

Input Frequency (MHz)

D005

D006

SNR = 68 dBFS; SFDR = 77 dBc;

SNR = 66.7 dBFS; SFDR = 71 dBc;

IL spur = 84 dBc; non HD2, HD3 spur = 85 dBc

IL spur = 87 dBc; non HD2, HD3 spur = 78 dBc

Figure 7. FFT for 300-MHz Input Signal

Figure 8. FFT for 370-MHz Input Signal

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Typical Characteristics (continued)

typical values are at T_A= 25°C, full temperature range is from T_MIN= –40°C to T_MAX= 85°C, ADC sampling rate = 1.0 GSPS,

50% clock duty cycle, AVDD3V = 3.0 V, AVDD = DVDD = 1.9 V, IOVDD = 1.15 V, and –1-dBFS differential input (unless

otherwise noted)

0

-20

-40

-60

-80

-100

-120

-100

-120

0

100

200

300

400

500

0

100

200

300

400

500

Input Frequency (MHz)

D058

D007

SNR = 66.3 dBFS, SINAD = 65.3 dBFS, THD = 70 dBc,

IL spur = 84 dBc, SFDR = 73 dBc, non HD2, HD3 spur = 90 dBFS

SNR = 67.9 dBFS; SFDR = 74 dBc;

IL spur = 82 dBc; non HD2, HD3 spur = 89 dBc

Figure 10. FFT for 720-MHz Input Signal at –6 dBFS

Figure 9. FFT for 470-MHz Input Signal at –3 dBFS

0

-20

-40

-60

-80

-100

-120

-100

-120

0

100

200

300

400

500

0

100

200

300

400

500

Input Frequency (MHz)

D008

D009

f_IN1= 185 MHz, f_IN2= 190 MHz, each tone at –7 dBFS,

IMD3 = 88 dBFS

f_IN1= 185 MHz, f_IN2= 190 MHz, each tone at –36 dBFS,

IMD3 = 106 dBFS

Figure 11. FFT for Two-Tone Input Signal (–7 dBFS)

Figure 12. FFT for Two-Tone Input Signal (–36 dBFS)

0

-20

-40

-20

-40

-60

-80

-100

-120

-100

-120

0

100

200

300

400

500

0

100

200

300

400

500

Input Frequency (MHz)

D010

D011

f_IN1= 365 MHz, f_IN2= 370 MHz, each tone at –7 dBFS,

IMD3 = 80 dBFS

f_IN1= 365 MHz, f_IN2= 370 MHz, each tone at –36 dBFS,

IMD3 = 105 dBFS

Figure 13. FFT for Two-Tone Input Signal (–7 dBFS)

Figure 14. FFT for Two-Tone Input Signal (–36 dBFS)

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Typical Characteristics (continued)

typical values are at T_A= 25°C, full temperature range is from T_MIN= –40°C to T_MAX= 85°C, ADC sampling rate = 1.0 GSPS,

50% clock duty cycle, AVDD3V = 3.0 V, AVDD = DVDD = 1.9 V, IOVDD = 1.15 V, and –1-dBFS differential input (unless

otherwise noted)

0

-20

-40

-60

-80

-100

-120

-100

-120

0

100

200

300

400

500

0

100

200

300

400

500

Input Frequency (MHz)

D012

D013

f_IN1= 465 MHz, f_IN2= 470 MHz, each tone at –7 dBFS,

IMD3 = 75 dBFS

f_IN1= 465 MHz, f_IN2= 470 MHz, each tone at –36 dBFS,

IMD3 = 106 dBFS

Figure 15. FFT for Two-Tone Input Signal (–7 dBFS)

Figure 16. FFT for Two-Tone Input Signal (–36 dBFS)

-82

-76

-80

-84

-86

-90

-88

-94

-92

-98

-96

-102

-106

-110

-100

-104

-108

-35

-31

-27

-23

-19

-15

-11

-7

-35

-31

-27

-23

-19

-15

-11

-7

Each Tone Amplitude (dBFS)

D014

D015

f_IN1= 185 MHz, f_IN2= 190 MHz

f_IN1= 365 MHz, f_IN2= 370 MHz

Figure 17. Intermodulation Distortion vs

Input Tone Amplitude

Figure 18. Intermodulation Distortion vs

Input Tone Amplitude

-70

95

90

85

80

75

70

65

60

55

A_IN= -6 dBFS

A_IN= -3 dBFS

A_IN= -1 dBFS

-74

-78

-82

-86

-90

-94

-98

-102

-106

0

100

200

300

400

500

600

700

-35

-31

-27

-23

-19

-15

-11

-7

Input Frequency (MHz)

Each Tone Amplitude (dBFS)

D043

D016

f_IN1= 465 MHz, f_IN2= 470 MHz

Figure 20. Spurious-Free Dynamic Range vs

Input Frequency

Figure 19. Intermodulation Distortion vs

Input Tone Amplitude

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Typical Characteristics (continued)

typical values are at T_A= 25°C, full temperature range is from T_MIN= –40°C to T_MAX= 85°C, ADC sampling rate = 1.0 GSPS,

50% clock duty cycle, AVDD3V = 3.0 V, AVDD = DVDD = 1.9 V, IOVDD = 1.15 V, and –1-dBFS differential input (unless

otherwise noted)

72

71

70

69

68

67

66

95

91

87

83

79

75

A_IN= -6 dBFS

A_IN= -3 dBFS

A_IN= -1 dBFS

0

100

200

300

400

500

600

700

0

40 80 120 160 200 240 280 320 360 400 440 480

Input Frequency (MHz)

D042

D018

Figure 22. Signal-to-Noise Ratio vs Input Frequency

Figure 21. IL Spur vs Input Frequency

72

96

AVDD = 1.8 V

AVDD = 1.85 V

AVDD = 1.9 V

AVDD = 1.95 V

AVDD = 2 V

AVDD = 1.8 V

AVDD = 1.85 V

AVDD = 1.9 V

AVDD = 1.95 V

AVDD = 2 V

71.5

71

94

92

90

88

86

84

82

80

70.5

70

69.5

69

68.5

68

-40

-15

10

35

60

85

-40

-15

10

35

60

85

Temperature (°C)

D020

D021

f_IN= 170 MHz

Figure 23. Signal-to-Noise Ratio vs

AVDD Supply and Temperature

Figure 24. Spurious-Free Dynamic Range vs

AVDD Supply and Temperature

72

71

70

69

68

67

66

65

64

78

77

76

75

74

73

72

AVDD = 1.8 V

AVDD = 1.85 V

AVDD = 1.9 V

AVDD = 1.95 V

AVDD = 2 V

AVDD = 1.8 V

AVDD = 1.85 V

AVDD = 1.9 V

AVDD = 1.95 V

AVDD = 2 V

-40

-15

10

35

60

85

-40

-15

10

35

60

85

Temperature (°C)

D022

D023

f_IN= 350 MHz

Figure 25. Signal-to-Noise Ratio vs

AVDD Supply and Temperature

Figure 26. Spurious-Free Dynamic Range vs

AVDD Supply and Temperature

18

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Typical Characteristics (continued)

typical values are at T_A= 25°C, full temperature range is from T_MIN= –40°C to T_MAX= 85°C, ADC sampling rate = 1.0 GSPS,

50% clock duty cycle, AVDD3V = 3.0 V, AVDD = DVDD = 1.9 V, IOVDD = 1.15 V, and –1-dBFS differential input (unless

otherwise noted)

72

71.2

70.4

69.6

68.8

68

94

92

90

88

86

84

DVDD = 1.75 V

DVDD = 1.8 V

DVDD = 1.85 V

DVDD = 1.9 V

DVDD = 1.95 V

DVDD = 2 V

DVDD = 1.75 V

DVDD = 1.8 V

DVDD = 1.85 V

DVDD = 1.9 V

DVDD = 1.95 V

DVDD = 2 V

-40

-15

10

35

60

85

-40

-15

10

35

60

85

Temperature (°C)

D024

D025

f_IN= 170 MHz

Figure 27. Signal-to-Noise Ratio vs

DVDD Supply and Temperature

Figure 28. Spurious-Free Dynamic Range vs

DVDD Supply and Temperature

72

71

70

69

68

67

66

82

80

78

76

74

72

DVDD = 1.75 V

DVDD = 1.8 V

DVDD = 1.85 V

DVDD = 1.9 V

DVDD = 1.95 V

DVDD = 2 V

DVDD = 1.75 V

DVDD = 1.8 V

DVDD = 1.85 V

DVDD = 1.9 V

DVDD = 1.95 V

DVDD = 2 V

-40

-15

10

35

60

85

-40

-15

10

35

60

85

Temperature (°C)

D026

D027

f_IN= 350 MHz

Figure 29. Signal-to-Noise Ratio vs

DVDD Supply and Temperature

Figure 30. Spurious-Free Dynamic Range vs

DVDD Supply and Temperature

72

97

95

93

91

89

87

85

83

AVDD3V = 2.85 V

AVDD3V = 3 V

AVDD3V = 3.1 V

AVDD3V = 3.2 V

AVDD3V = 3.3 V

AVDD3V = 2.85 V

AVDD3V = 3 V

AVDD3V = 3.1 V

AVDD3V = 3.2 V

AVDD3V = 3.3 V

AVDD3V = 3.4 V

AVDD3V = 3.5 V

AVDD3V = 3.6 V

AVDD3V = 3.4 V

AVDD3V = 3.5 V

AVDD3V = 3.6 V

71.5

71

70.5

70

69.5

69

-40

-15

10

35

60

85

-40

-15

10

35

60

85

Temperature (°C)

D028

D029

f_IN= 170 MHz

Figure 31. Signal-to-Noise Ratio vs

AVDD3V Supply and Temperature

Figure 32. Spurious-Free Dynamic Range vs

AVDD3V Supply and Temperature

19

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Typical Characteristics (continued)

typical values are at T_A= 25°C, full temperature range is from T_MIN= –40°C to T_MAX= 85°C, ADC sampling rate = 1.0 GSPS,

50% clock duty cycle, AVDD3V = 3.0 V, AVDD = DVDD = 1.9 V, IOVDD = 1.15 V, and –1-dBFS differential input (unless

otherwise noted)

72

71

70

69

68

67

66

65

82

80

78

76

74

72

AVDD3V = 2.85 V

AVDD3V = 3 V

AVDD3V = 3.1 V

AVDD3V = 3.2 V

AVDD3V = 3.3 V

AVDD3V = 3.4 V

AVDD3V = 3.5 V

AVDD3V = 3.6 V

AVDD3V = 2.85 V

AVDD3V = 3 V

AVDD3V = 3.1 V

AVDD3V = 3.2 V

AVDD3V = 3.3 V

AVDD3V = 3.4 V

AVDD3V = 3.5 V

AVDD3V = 3.6 V

-40

-15

10

35

60

85

-40

-15

10

35

60

85

Temperature (°C)

D030

D031

f_IN= 350 MHz

Figure 33. Signal-to-Noise Ratio vs

AVDD3V Supply and Temperature

Figure 34. Spurious-Free Dynamic Range vs

AVDD3V Supply and Temperature

110

105

100

95

85

80

75

70

65

60

55

Gain = 0 dB

Gain = 2 dB

Gain = 4 dB

Gain = 6 dB

Gain = 8 dB

Gain = 10 dB

Gain = 12 dB

Gain = 0 dB

Gain = 2 dB

Gain = 4 dB

Gain = 6 dB

Gain = 8 dB

Gain = 10 dB

Gain = 12 dB

90

85

80

75

70

65

0

80

160

240

320

400

480

0

80

160

240

320

400

480

Input Frequency (MHz)

D053

D054

Figure 35. Signal-to-Noise Ratio vs

Gain and Input Frequency

Figure 36. Spurious-Free Dynamic Range vs

Gain and Input Frequency

75

200

2

SNR (dBFS)

SFDR (dBc)

SFDR (dBFS)

0

-2

73

71

69

67

65

160

120

80

-4

-6

40

-8

-10

0

100 200 300 400 500 600 700 800 900 1000

-70

-60

-50

-40

-30

-20

-10

0

Input Frequency (MHz)

Amplitude (dBFS)

D046

D032

f_IN= 170 MHz

Figure 37. Maximum Supported Amplitude vs Frequency

Figure 38. Performance vs Input Amplitude

20

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Typical Characteristics (continued)

typical values are at T_A= 25°C, full temperature range is from T_MIN= –40°C to T_MAX= 85°C, ADC sampling rate = 1.0 GSPS,

50% clock duty cycle, AVDD3V = 3.0 V, AVDD = DVDD = 1.9 V, IOVDD = 1.15 V, and –1-dBFS differential input (unless

otherwise noted)

76

74

72

70

68

66

110

100

90

75

73.5

72

180

150

120

90

SNR

SFDR

SNR (dBFS)

SFDR (dBc)

SFDR (dBFS)

70.5

69

80

60

70

67.5

30

66

0

60

-70

-60

-50

-40

-30

-20

-10

0

0.2

0.6

1

1.4

1.8

2.2

Amplitude (dBFS)

Differential Clock Amplitude (Vpp)

D033

D034

f_IN= 350 MHz

f_IN= 170 MHz

Figure 39. Performance vs Input Amplitude

Figure 40. Performance vs Sampling Clock Amplitude

75

72

69

66

63

60

125

73

100

95

90

85

80

75

SNR

SFDR

SNR

SFDR

100

75

50

25

0

72

71

70

69

68

0.2

0.6

1

1.4

1.8

2.2

30

35

40

45

50

55

60

65

70

Differential Clock Amplitude (Vpp)

Input Clock Duty Cycle (%)

D035

D036

f_IN= 350 MHz

f_IN= 170 MHz

Figure 41. Performance vs Sampling Clock Amplitude

Figure 42. Performance vs Clock Duty Cycle

-10

-15

-20

-25

-30

-35

-40

-45

-50

-55

-60

72

88

84

80

76

72

68

64

60

PSRR with 50-mVPP Signal on AVDD

PSRR with 50-mVPP Signal on AVDD3V

SNR

SFDR

71

70

69

68

67

66

65

30

35

40

45

50

55

60

65

70

0

50

100

150

200

250

300

Input Clock Duty Cycle (%)

Frequency of Signal on Supply (MHz)

D037

D038

f_IN= 350 MHz

f_IN= 170 MHz

Figure 43. Performance vs Clock Duty Cycle

Figure 44. Power-Supply Rejection Ratio vs

Test Signal Frequency

21

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Typical Characteristics (continued)

typical values are at T_A= 25°C, full temperature range is from T_MIN= –40°C to T_MAX= 85°C, ADC sampling rate = 1.0 GSPS,

50% clock duty cycle, AVDD3V = 3.0 V, AVDD = DVDD = 1.9 V, IOVDD = 1.15 V, and –1-dBFS differential input (unless

otherwise noted)

0

-20

-25

-30

-35

-40

-45

-50

-55

-20

-40

-60

-80

-100

-120

0

100

200

300

400

500

Input Frequency (MHz)

D039

0

50

100

150

200

250

300

f_IN= 170 MHz , A_IN= –1 dBFS, SINAD = 67 dBFS,

Frequency of Input Common-Mode Signal (MHz)

D040

SFDR = 79 dBc, f_PSRR= 5 MHz, A_PSRR= 25 mV_PP

,

f_IN= 170 MHz

amplitude of f_IN– f_PSRR= –74 dBFS,

amplitude of f_IN+ f_PSRR= –76 dBFS

Figure 46. Common-Mode Rejection Ratio vs

Test Signal Frequency

Figure 45. Power-Supply Rejection Ratio FFT for

Test Signals on the AVDD Supply

0

-20

-40

-60

-80

4

3.5

3

2.5

2

-100

1.5

-120

0

100

200

300

400

500

1

Input Frequency (MHz)

D041

500 550 600 650 700 750 800 850 900 950 1000

f_IN= 170 MHz , A_IN= –1 dBFS, f_CMRR= 5 MHz, A_CMRR= 50 mV_PP

,

Sampling Speed (MSPS)

D042

SINAD = 69.1 dBFS, SFDR = 86 dBc,

amplitude of f_IN± f_CMRR= –80 dBFS

Figure 48. Power vs Sampling Speed

Figure 47. Common-Mode Rejection Ratio FFT

0

800

700

600

500

400

300

200

100

2.78

2.76

2.74

2.72

2.7

I _DVDD(mA)

I _AVDD(mA)

I _IOVDD(mA)

I _AVDD3(mA)

Total Power (W)

-20

-40

-60

-80

2.68

2.66

2.64

-100

-120

-40

-15

10

35

60

85

0

25

50

75

100

125

Temperature (°C)

Input Frequency (MHz)

D045

D047

SNR = 76.4 dBFS, SFDR = 99 dBc

Figure 49. Power vs Temperature

Figure 50. FFT for 60-MHz Input Signal in

Decimate-by-4 Mode

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Typical Characteristics (continued)

typical values are at T_A= 25°C, full temperature range is from T_MIN= –40°C to T_MAX= 85°C, ADC sampling rate = 1.0 GSPS,

50% clock duty cycle, AVDD3V = 3.0 V, AVDD = DVDD = 1.9 V, IOVDD = 1.15 V, and –1-dBFS differential input (unless

otherwise noted)

0

-20

-40

-60

-80

-100

-120

-100

-120

0

25

50

75

100

125

0

25

50

75

100

125

Input Frequency (MHz)

D048

D049

SNR = 75.2 dBFS, SFDR = 90 dBc

SNR = 72.8 dBFS, SFDR = 91 dBc

Figure 51. FFT for 170-MHz Input Signal in

Decimate-by-4 Mode

Figure 52. FFT for 300-MHz Input Signal in

Decimate-by-4 Mode

0

-20

0

-20

-40

-60

-80

-100

-120

-100

-120

0

25

50

75

100

125

0

50

100

150

200

250

Input Frequency (MHz)

D050

D051

SNR = 69.6 dBFS, SFDR = 84 dBc

SNR = 71.9 dBFS, SFDR = 89 dBc

Figure 53. FFT for 450-MHz Input Signal in

Decimate-by-4 Mode

Figure 54. FFT for 170-MHz Input Signal in

Decimate-by-2 Mode

0

-20

-40

-60

-80

-100

-120

0

50

100

150

200

250

Input Frequency (MHz)

D052

SNR = 68.3 dBFS, SFDR = 80 dBc

Figure 55. FFT for 350-MHz Input Signal in

Decimate-by-2 Mode

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7.10 Typical Characteristics: Contour

typical values are at T_A= 25°C, full temperature range is from T_MIN= –40°C to T_MAX= 85°C, ADC sampling rate = 1.0 GSPS,

50% clock duty cycle, AVDD3V = 3.0 V, AVDD = DVDD = 1.9 V, IOVDD = 1.15 V, –1-dBFS differential input, and 0-dB digital

gain (unless otherwise noted)

1000

950

1000

950

66.4

68

88

8484

88 88

84

80

76

72

71.2

70.4

69.6

68.8

68.0 67.2

900

850

800

900

850

800

71.2

70.8

70.4

69.6 69.2 68.8 68.4

70

68

71.2

70.4

69.6

68.8

68.0

67.2

92

88

88 88 84

80

76

72

750

700

750

700

71.2

150

70.4

69.6

68.8

350

67.2

450

71.2

70.8

70.4

84

69.6 69.2 68.8 68.4

76

68

70

92 88

50

80

72

400

50

100

200 250

Input Frequency (MHz)

300

400

100

150

200 300

Input Frequency (MHz)

250

350

450

69.6

65.6

66.4

67.2

68.0

68.8

70.4

71.2

72.0

88

68

72

76

80

84

92

96

Figure 57. Signal-to-Noise-Ratio

Figure 56. Spurious Free Dynamic Range

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8 Detailed Description

8.1 Overview

The ADS54J60 is a low-power, wide-bandwidth, 16-bit, 1.0-GSPS, dual-channel, analog-to-digital converter

(ADC). The ADS54J60 employs four interleaving ADCs for each channel to achieve a noise floor of

–159 dBFS/Hz. The ADS54J60 uses TI's proprietary interleaving and dither algorithms to achieve a clean

spectrum with a high spurious-free dynamic range (SFDR). The device also offers various programmable

decimation filtering options for systems requiring higher signal-to-noise ratio (SNR) and SFDR over a wide range

of frequencies.

Analog input buffers isolate the ADC driver from glitch energy generated from sampling process, thereby simplify

the driving network on-board. The JESD204B interface reduces the number of interface lines with two-lane and

four-lane options, allowing a high system integration density. The JESD204B interface operates in subclass 1,

enabling multi-chip synchronization with the SYSREF input.

8.2 Functional Block Diagram

DA0P, DA0M,

DA1P, DA1M

DDC Block:

2x, 4x Decimation

Mixer: f_S/ 16, f_S/ 4

Buffer

Digital Block

ADC

Interleaving

Correction

INAP, INAM

DA2P, DA2M,

DA3P, DA3M

PLL:

x20

x40

Divide-by-

4

CLKINP,

CLKINM

SYNC

SYSREFP,

SYSREFM

DDC Block:

2X, 4X Decimation

Mixer: f_S/ 16, f_S/ 4

DB0P, DB0M,

DB1P, DB1M

Buffer

Digital Block

ADC

Interleaving

Correction

INBP, INBM

DB2P, DB2M,

DB3P, DB3M

FOVR

Control and SPI

Common

Mode

VCM

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8.3 Feature Description

8.3.1 Analog Inputs

The ADS54J60 analog signal inputs are designed to be driven differentially. The analog input pins have internal

analog buffers that drive the sampling circuit. As a result of the analog buffer, the input pins present a high

impedance input across a very wide frequency range to the external driving source, which enables great flexibility

in the external analog filter design as well as excellent 50-Ω matching for RF applications. The buffer also helps

isolate the external driving circuit from the internal switching currents of the sampling circuit, resulting in a more

constant SFDR performance across input frequencies.

The common-mode voltage of the signal inputs is internally biased to VCM using 600-Ω resistors, allowing for ac-

coupling of the input drive network. Each input pin (INP, INM) must swing symmetrically between (VCM +

0.475 V) and (VCM – 0.475 V), resulting in a 1.9-V_PP(default) differential input swing. The input sampling circuit

has a 3-dB bandwidth that extends up to 1.2 GHz. An equivalent analog input network diagram is shown in

Figure 58.

0.77 W

1 W

3.3 W

2 nH

0.6 W

150 fF

200 fF

3 pF

375 fF

INP

40 W

500 fF

150 fF

0.77 W

1 W

3.3 W

600 W

150 fF

200 fF

3 pF

VCM

40 W

600 W

0.77 W

1 W

3.3 W

150 fF

200 fF

3 pF

2 nH

0.6 W

INM

40 W

500 fF

150 fF

0.77 W

1 W

3.3 W

150 fF

200 fF

3 pF

40 W

Figure 58. Analog Input Network

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Feature Description (continued)

The input bandwidth shown in Figure 59 is measured with respect to a 50-Ω differential input termination at the

ADC input pins. Figure 60 shows the signal processing done inside the DDC block of the ADS54J60.

0

-3

-6

-9

-12

-15

-18

0

200 400 600 800 1000 1200 1400 1600 1800 2000

Input Frequency (MHz)

D056

Figure 59. Transfer Function versus Frequency

Default 14-Bit Data (At 1 GSPS)

Decimate-by-2 Data (At 500 MSPS)

LPF

BPF

2

4

Decimate-by-4 Data (At 250 MSPS)

Interleaving

Engine,

Digital

Features

Ch X

1 GSPS Data,

x(n)

To JESD

Encoder

4

LPF

Decimate-by-4, I-Data (At 250 MSPS)

(1)

cos(2 n Œ f_mix/ f_S

)

(1)

sin(2 n Œ f_mix/ f_S

)

Decimate-by-4 Q-Data (At 250 MSPS)

4

LPF

Mode Selection Using DECFIL

MODE[3:0] Register Bits

(1) In IQ decimate-by-4 mode, the mixer frequency is fixed at f_mix= f_S/ 4. For f_S= 1 GSPS and f_mix= 250 MHz.

Figure 60. DDC Block

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Feature Description (continued)

8.3.2 DDC Block

The ADS54J60 has an optional DDC block that can be enabled via an SPI register write. Each ADC channel is

followed by a DDC block consisting of three different decimate-by-2 and by-4 finite impulse response (FIR) half-

band filter options. The different decimation filter options can be selected via SPI programming.

8.3.2.1 Decimate-by-2 Filter

This decimation filter has 41 taps. The stop-band attenuation is approximately 90 dB and the pass-band flatness

is ±0.05 dB. Table 1 shows corner frequencies for low-pass and high-pass filter options.

Table 1. Corner Frequencies for the Decimate-by-2 Filter

CORNERS (dB)

LOW PASS

0.202 × f_S

0.210 × f_S

0.215 × f_S

0.227 × f_S

HIGH PASS

0.298 × f_S

0.290 × f_S

0.285 × f_S

0.273 × f_S

–0.1

–0.5

–1

–3

Figure 61 and Figure 62 show the frequency response of decimate-by-2 filter from dc to f_S/ 2.

5

-20

0.5

0

-0.5

-1

-45

-1.5

-2

-70

-95

-2.5

-3

-120

0

0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5

Frequency Response

0

0.05

0.1

0.15

0.2

0.25

Frequency Response

D013

D014

Figure 61. Decimate-by-2 Filter Response

Figure 62. Decimate-by-2 Filter Response (Zoomed)

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ZHCSE42D –APRIL 2015–REVISED APRIL 2019

8.3.2.2 Decimate-by-4 Filter Using a Digital Mixer

This band-pass decimation filter consists of a digital mixer and three concatenated FIR filters with a combined

latency of approximately 28 output clock cycles. The alias band attenuation is approximately

55 dB and the pass-band flatness is ±0.1 dB. By default after reset, the band-pass filter is centered at f_S/ 16.

Using the SPI, the center frequency can be programmed at N × f_S/ 16 (where N = 1, 3, 5, or 7). Table 2 shows

corner frequencies for two extreme options. Figure 63 and Figure 64 show frequency response of decimate-by-4

filter for center frequencies f_S/16 and 3 × f_S/16 (N =1 and 3).

Table 2. Corner frequencies for the Decimate-by-4 Filter

CORNER FREQUENCY AT LOWER SIDE

(Center Frequency f_S/ 16)

CORNER FREQUENCY AT HIGHER SIDE

(Center Frequency f_S/ 16)

CORNERS (dB)

–0.1

–0.5

–1

0.011 × f_S

0.010 × f_S

0.008 × f_S

0.006 × f_S

0.114 × f_S

0.116 × f_S

0.117 × f_S

0.120 × f_S

–3

Figure 63 and Figure 64 show the frequency response of a decimate-by-4 filter from dc to f_S/ 2.

10

0

0.2

0.1

0

-10

-20

-30

-40

-50

-60

-70

-80

-0.1

-0.2

-0.3

-0.4

-0.5

-0.6

-0.7

-0.8

-0.9

-1

0

0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5

Frequency Response

0

0.05

0.1

0.15

0.2

0.25

Frequency Response

D015

D016

Figure 63. Decimate-by-4 Filter Response

Figure 64. Decimate-by-4 Filter Response (Zoomed)

8.3.2.3 Decimate-by-4 Filter with IQ Outputs

In this configuration, the DDC block includes a fixed digital f_S/ 4 mixer. Thus, the IQ pass band is approximately

±110 MHz, centered at f_S/ 4. This decimation filter has 41 taps with a latency of approximately ten output clock

cycles. The stop-band attenuation is approximately 90 dB and the pass-band flatness is ±0.05 dB. Table 3 shows

the corner frequencies for a low-pass decimate-by-4 with IQ filter.

Table 3. Corner Frequencies for a Decimate-by-4 IQ Output Filter

CORNERS (dB)

LOW PASS

0.107 × f_S

0.112 × f_S

0.115 × f_S

0.120 × f_S

–0.1

–0.5

–1

–3

29

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Figure 65 and Figure 66 show the frequency response of a decimate-by-4 IQ output filter from dc to f_S/ 2.

5

-20

0.5

0

-0.5

-1

-45

-1.5

-2

-70

-95

-2.5

-3

-120

0

0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5

Frequency Response

0

0.025

0.05

0.075

0.1

0.125

D012

Frequency Response

D011

Figure 65. Decimate-by-4 with IQ Outputs Filter Response

Figure 66. Decimate-by-4 with IQ Outputs Filter Response

(Zoomed)

8.3.3 SYSREF Signal

The SYSREF signal is a periodic signal that is sampled by the ADS54J60 device clock and used to align the

boundary of the local multi-frame clock inside the data converter. SYSREF is required to be a sub-harmonic of

the local multiframe clock (LMFC) internal timing. To meet this requirement, the timing of SYSREF is dependent

on the device clock frequency and the LMFC frequency, as determined by the selected DDC decimation and

frames per multi-frame settings. TI recommends that the SYSREF signal be a low-frequency signal in the range

of 1 MHz to 5 MHz in order to reduce coupling to the signal path both on the printed circuit board (PCB) as well

as internal in the device.

The external SYSREF signal must be a sub-harmonic of the internal LMFC clock, as shown in Equation 1 and

Table 4.

SYSREF = LMFC / 2^N

where

•

N = 0, 1, 2, and so forth.

(1)

Table 4. Local Multi-Frame Clock Frequency

LMFS CONFIGURATION

DECIMATION

LMFC CLOCK⁽¹⁾⁽²⁾

f_S/ K

4211

4244

8224

4222

2242

2221

2441

4421

1241

—

(f_S/ 4) / K

—

2X

4X

4X (IQ)

4X

(1) K = Number of frames per multi frame (JESD digital page 6900h, address 06h, bits 4-0).

(2) f_S= sampling (device) clock frequency.

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For example, if LMFS = 8224 then the programmed value of K is 9 (the actual value is 9 + 1 = 10 because the

actual value for K = the value set in the SPI register +1). If the device clock frequency is f_S= 1000 MSPS, then

the local multi-frame clock frequency becomes (1000 / 4) / 10 = 25 MHz. The SYSREF signal frequency can be

chosen as the LMFC frequency / 8 = 3.125 MHz.

8.3.3.1 SYSREF Not Present (Subclass 0, 2)

A SYSREF pulse is required by the ADS54J60 to reset internal counters. If SYSREF is not present, as can be

the case in subclass 0 or 2, this pulse can be done by doing the following register writes shown in Table 5.

Table 5. Internally Pulsing SYSREF Twice Using Register Writes

ADDRESS (Hex)

0-011h

DATA (Hex)

80h

COMMENT

Set the master page

Enable manual SYSREF

Set SYSREF high

Set SYSREF low

0-054h

80h

0-053h

01h

0-053h

00h

0-053h

01h

Set SYSREF high

Set SYSREF low

0-053h

00h

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8.3.4 Overrange Indication

The ADS54J60 provides a fast overrange indication that can be presented in the digital output data stream via

SPI configuration. Alternatively, if not used, the SDOUT (pin 11) and PDN (pin 50) pins can be configured via the

SPI to output the fast OVR indicator.

When the FOVR indication is embedded in the output data stream, it replaces the LSB of the 16-bit data stream

going to the 8b/10b encoder, as shown in Figure 67.

16-Bit Data Output

D0/

OVR

D15

D14

D13 D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

16-Bit Data Going to 8b/10b Encoder

Figure 67. Overrange Indication in a Data Stream

8.3.4.1 Fast OVR

The fast OVR is triggered if the input voltage exceeds the programmable overrange threshold and is presented

after only 18 clock cycles + t_PD(t_PDof the gates and buffers is approximately 4 ns), thus enabling a quicker

reaction to an overrange event.

The input voltage level at which the overload is detected is referred to as the threshold. The threshold is

programmable using the FOVR THRESHOLD bits, as shown in Figure 68. The FOVR is triggered 18 clock cycles

+ t_PD(t_PDof the gates and buffers is approximately 4 ns) after the overload condition occurs.

0

-5

-10

-15

-20

-25

-30

-35

-40

-45

-50

0

32

64

96

128

160

192

224

255

Threshold Decimal Value

D055

Figure 68. Programming Fast OVR Thresholds

The input voltage level at which the fast OVR is triggered is defined by Equation 2:

Full-Scale × [Decimal Value of the FOVR Threshold Bits] / 255)

(2)

(3)

The default threshold is E3h (227d), corresponding to a threshold of –1 dBFS.

In terms of full-scale input, the fast OVR threshold can be calculated as Equation 3:

20log (FOVR Threshold / 255)

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8.3.5 Power-Down Mode

The ADS54J60 provides a highly-configurable power-down mode. Power-down can be enabled using the PDN

pin or SPI register writes.

A power-down mask can be configured, which allows a trade-off between wake-up time and power consumption

in power-down mode. Two independent power-down masks can be configured: MASK 1 and MASK 2 as shown

in Table 6. See the master page registers in Table 15 for further details.

Table 6. Register Address for Power-Down Modes

REGISTER

ADDRESS

REGISTER DATA

COMMENT

A[7:0] (Hex)

MASTER PAGE (80h)

20

7

6

5

4

3

2

1

0

PDN ADC CHA

PDN BUFFER CHB

PDN ADC CHA

PDN BUFFER CHB

GLOBAL OVERRIDE

PDN ADC CHB

MASK 1

21

23

24

PDN BUFFER CHA

0

PDN ADC CHB

MASK 2

CONFIG

0

PDN MASK

26

55

0

PDN

PDN PIN

SEL

0

PDN MASK

To save power, the device can be put in complete power down by using the GLOBAL PDN register bit. However,

when JESD must remain linked up while putting the device in power down, the ADC and analog buffer can be

powered down by using the PDN ADC CHx and PDN BUFFER CHx register bits after enabling the PDN MASK

register bit. The PDN MASK SEL register bit can be used to select between MASK 1 or MASK 2. Table 7 shows

power consumption for different combinations of the GLOBAL PDN, PDN ADC CHx, and PDN BUFF CHx

register bits.

Table 7. Power Consumption in Different Power-Down Settings

TOTAL

I_AVDD3V

(mA)

POWER

(W)

REGISTER BIT

Default

COMMENT

I_AVDD(mA) I_DVDD(mA) I_IOVDD(mA)

After reset, with a full-scale input signal to

both channels

336

2

358

6

198

22

533

199

2.68

0.29

The device is in complete power-down

state

GBL PDN = 1

GBL PDN = 0,

PDN ADC CHx = 1

(x = A or B)

The ADC of one channel is powered down

274

262

223

352

135

194

512

545

2.09

2.45

GBL PDN = 0,

PDN BUFF CHx = 1

(x = A or B)

The input buffer of one channel is powered

down

GBL PDN = 0,

PDN ADC CHx = 1,

PDN BUFF CHx = 1

(x = A or B)

The ADC and input buffer of one channel

is powered down

198

60

222

85

132

66

508

484

1.85

1.02

GBL PDN = 0,

PDN ADC CHx = 1,

PDN BUFF CHx = 1

(x = A and B)

The ADC and input buffer of both channels

are powered down

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8.4 Device Functional Modes

8.4.1 Device Configuration

The ADS54J60 can be configured by using a serial programming interface, as described in the Serial Interface

section. In addition, the device has one dedicated parallel pin (PDN) for controlling the power-down mode.

The ADS54J60 supports a 24-bit (16-bit address, 8-bit data) SPI operation and uses paging (see the Register

Maps section) to access all register bits.

8.4.1.1 Serial Interface

The ADC has a set of internal registers that can be accessed by the serial interface formed by the SEN (serial

interface enable), SCLK (serial interface clock), and SDIN (serial interface data) pins, as shown in Figure 69.

Legends used in Figure 69 are explained in Table 8. Serially shifting bits into the device is enabled when SEN is

low. Serial data on SDIN are latched at every SCLK rising edge when SEN is active (low). The interface can

function with SCLK frequencies from 2 MHz down to very low speeds (of a few Hertz) and also with a non-50%

SCLK duty cycle.

Register Address[11:0]

Register Data[7:0]

SDIN

R/W

M

P

CH

A11

A10

A9

A8

A7

A6

A5

A4

A3

A2

A1

A0

D7

D6

D5

D4

D3

D2

D1

t_DH

D0

t_SCLK

t_DSU

SCLK

SEN

t_SLOADS

t_SLOADH

RESET

Figure 69. SPI Timing Diagram

Table 8. SPI Timing Diagram Legend

SPI BITS

DESCRIPTION

BIT SETTINGS

0 = SPI write

1 = SPI read back

R/W

Read/write bit

0 = Analog SPI bank (master and ADC pages)

1 = JESD SPI bank (main digital, JESD analog, and

JESD digital pages)

M

SPI bank access

JESD page selection bit

0 = Page access

1 = Register access

P

0 = Channel A

1 = Channel B

By default, both channels are being addressed.

SPI access for a specific channel of the JESD SPI

bank

CH

A[11:0]

D[7:0]

SPI address bits

SPI data bits

—

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Table 9 shows the timing requirements for the serial interface signals in Figure 69.

Table 9. SPI Timing Requirements

MIN

TYP

MAX

UNIT

MHz

ns

f_SCLK

t_SLOADS

t_SLOADH

t_DSU

SCLK frequency (equal to 1 / t_SCLK

SEN to SCLK setup time

SCLK to SEN hold time

SDIN setup time

)

> dc

100

2

ns

t_DH

SDIN hold time

ns

8.4.1.2 Serial Register Write: Analog Bank

The analog SPI bank contains of two pages (the master and ADC page). The internal register of the ADS54J60

analog SPI bank can be programmed by:

1. Driving the SEN pin low.

2. Initiating a serial interface cycle specifying the page address of the register whose content must be written.

–

Master page: write address 0011h with 80h.

ADC page: write address 0011h with 0Fh.

3. Writing the register content as shown in Figure 70. When a page is selected, multiple writes into the same

page can be done.

Register Address[11:0]

Register Data[7:0]

0

SDIN

SCLK

R/W

M

P

CH A11 A10

A9

A8

A7 A6 A5 A4

A3

A2

A1

A0

D7

D6

D5 D4 D3 D2

D1

D0

SEN

RESET

Figure 70. Serial Register Write Timing Diagram

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8.4.1.3 Serial Register Readout: Analog Bank

The content from one of the two analog banks can be read out by:

1. Driving the SEN pin low.

2. Selecting the page address of the register whose content must be read.

–

Master page: write address 0011h with 80h.

ADC page: write address 0011h with 0Fh.

3. Setting the R/W bit to 1 and write the address to be read back.

4. Reading back the register content on the SDOUT pin, as shown in Figure 71. When a page is selected,

multiple read backs from the same page can be done. SDOUT comes out at the SCLK falling edge with an

approximate delay (t_{SD_DELAY}) of 68 ns; see Figure 75.

Register Address[11:0]

Register Data[7:0] = XX

1

0

SDIN

SCLK

R/W

M

P

CH

A11

A10

A9

A8

A7

A6

A5

A4

A3

A2

A1

A0

D7

D6

D5

D4

D3

D2

D1

D0

SEN

RESET

SDOUT

D7

D6

D5

D4

D3

D2

D1

D0

SDOUT[7:0]

Figure 71. Serial Register Read Timing Diagram

8.4.1.4 JESD Bank SPI Page Selection

The JESD SPI bank contains four pages (main digital, JESD digital, and JESD analog pages). The individual

pages can be selected by:

1. Driving the SEN pin low.

2. Setting the M bit to 1 and specifying the page with two register writes. Note that the P bit must be set to 0, as

shown in Figure 72.

–

Write address 4003h with 00h (LSB byte of the page address).

Write address 4004h with the MSB byte of the page address.

–

For the main digital page: write address 4004h with 68h.

For the JESD digital page: write address 4004h with 69h.

For the JESD analog page: write address 4004h with 6Ah.

Register Address[11:0]

Register Data[7:0]

D5 D4 D3 D2

0

1

0

SDIN

R/W

M

P

CH A11 A10 A9

A8

A7

A6

A5

A4

A3

A2

A1

A0

D7

D6

D1

D0

SCLK

SEN

RESET

Figure 72. SPI Page Selection

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8.4.1.5 Serial Register Write: JESD Bank

The ADS54J60 is a dual-channel device and the JESD204B portion is configured individually for each channel by

using the CH bit. Note that the P bit must be set to 1 for register writes.

1. Drive the SEN pin low.

2. Select the JESD bank page. Note that the M bit = 1 and the P bit = 0.

–

Write address 4003h with 00h.

Write address 4005h with 01h to enable separate control for both channels.

–

For the main digital page: write address 4004h with 68h.

For the JESD digital page: write address 4004h with 69h.

For the JESD analog page: write address 4004h with 6Ah.

3. Set the M and P bits to 1, select channel A (CH = 0) or channel B (CH = 1), and write the register content as

shown in Figure 73. When a page is selected, multiple writes into the same page can be done.

Register Address[11:0]

Register Data[7:0]

0

1

0

SDIN

SCLK

R/W

M

P

CH A11 A10

A9

A8

A7 A6 A5 A4

A3

A2

A1

A0

D7

D6

D5 D4 D3 D2

D1

D0

SEN

RESET

Figure 73. JESD Serial Register Write Timing Diagram

8.4.1.5.1 Individual Channel Programming

By default, register writes are applied to both channels. To enable individual channel writes, write address 4005h

with 01h (default is 00h).

8.4.1.6 Serial Register Readout: JESD Bank

The content from one of the pages of the JESD bank can be read out by:

1. Driving the SEN pin low.

2. Selecting the JESD bank page. Note that the M bit = 1 and the P bit = 0.

–

Write address 4003h with 00h.

Write address 4005h with 01h to enable separate control for both channels.

–

For the main digital page: write address 4004h with 68h.

For the JESD digital page: write address 4004h with 69h.

For the JESD analog page: write address 4004h with 6Ah.

3. Setting the R/W, M, and P bits to 1, selecting channel A or channel B, and writing the address to be read

back.

4. Reading back the register content on the SDOUT pin; see Figure 74. When a page is selected, multiple read

backs from the same page can be done. SDOUT comes out at the SCLK falling edge with an approximate

delay (t_{SD_DELAY}) of 68 ns; see Figure 75.

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Register Address[11:0]

A7 A6 A5 A4

Register Data[7:0] = XX

D5 D4 D3 D2

1

0

SDIN

SCLK

R/W

M

P

CH A11 A10 A9

A8

A3

A2

A1

A0

D7

D6

D1

D0

SEN

RESET

SDOUT

D7

D6

D5

D4

D3

D2

D1

D0

SDOUT[7:0]

Figure 74. JESD Serial Register Read Timing Diagram

SCLK

t_{SD_DELAY}

SDOUT

Figure 75. SDOUT Timing Diagram

8.4.2 JESD204B Interface

The ADS54J60 supports device subclass 1 with a maximum output data rate of 10.0 Gbps for each serial

transmitter.

An external SYSREF signal is used to align all internal clock phases and the local multi-frame clock to a specific

sampling clock edge, allowing synchronization of multiple devices in a system and minimizing timing and

alignment uncertainty. The SYNC input is used to control the JESD204B SERDES blocks.

Depending on the ADC output data rate, the JESD204B output interface can be operated with either two or four

lanes per single ADC; see Figure 76. The JESD204B setup and configuration of the frame assembly parameters

is controlled via the SPI interface.

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SYSREF

SYNC

JESD204B

DA[3:0]

INA

INB

JESD204B

DB[3:0]

Sample Clock

Figure 76. ADS54J60 Block Diagram

The JESD204B transmitter block shown in Figure 77 consists of the transport layer, the data scrambler, and the

link layer. The transport layer maps the ADC output data into the selected JESD204B frame data format. The link

layer performs the 8b/10b data encoding as well as the synchronization and initial lane alignment using the

SYNC input signal. Optionally, data from the transport layer can be scrambled.

JESD204B Block

Transport Layer

Link Layer

8b, 10b

Encoding

Frame Data

Mapping

Scrambler

1 + x¹⁴+ x¹⁵

D[3:0]

Comma Characters,

Initial Lane Alignment

SYNC

Figure 77. JESD204B Transmitter Block

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8.4.2.1 JESD204B Initial Lane Alignment (ILA)

The initial lane alignment process is started when the receiving device de-asserts the SYNC signal, as shown in

Figure 78. When a logic low is detected on the SYNC input pin, the ADS54J60 starts transmitting comma (K28.5)

characters to establish a code group synchronization.

When synchronization is complete, the receiving device asserts the SYNC signal and the ADS54J60 starts the

initial lane alignment sequence with the next local multi-frame clock boundary. The ADS54J60 transmits four

multi-frames, each containing K frames (K is SPI programmable). Each of the multi-frames contains the frame

start and end symbols and the second multi-frame also contains the JESD204 link configuration data.

SYSREF

LMFC Clock

LMFC Boundary

Multi

Frame

SYNC

Transmit Data

xxx

K28.5

Code Group

K28.5

Initial Lane

ILA

DATA

Data Transmission

Synchronization

Alignment

Figure 78. Lane Alignment Sequence

8.4.2.2 JESD204B Test Patterns

There are three different test patterns available in the transport layer of the JESD204B interface. The ADS54J60

supports a clock output, encoded test pattern, and an 12-octet RPAT pattern. These test patterns can be

enabled via an SPI register write and are located in the JESD digital page of the JESD bank.

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8.4.2.3 JESD204B Frame

The JESD204B standard defines the following parameters:

•

L is the number of lanes per link.

M is the number of converters per device.

F is the number of octets per frame clock period, per lane.

S is the number of samples per frame per converter.

8.4.2.4 JESD204B Frame

Table 10 lists the available JESD204B formats and valid ranges for the ADS54J60 when the decimation filter is

not used. The ranges are limited by the SERDES lane rate and the maximum ADC sample frequency.

Table 10. Default Interface Rates

MINIMUM RATES

MAXIMUM RATES

L

M

F

S

DECIMATION

SAMPLING

RATE (MSPS)

SERDES BIT

RATE (Gbps)

SAMPLING

RATE (MSPS)

SERDES BIT

RATE (Gbps)

4

8

2

1

4

2

1

4

Not used

250

500

2.5

1000

10.0

5.0

1000

NOTE

In the LMFS = 8224 row of Table 10, the sample order in lane DA2 and DA3 are

swapped.

The detailed frame assembly is shown in Table 11.

Table 11. Default Frame Assembly

DA0

DA1

DA2

DA3

DB0

DB1

DB2

DB3

LMFS = 4211

LMFS = 4244

LMFS = 8224

A₃[15:8]

A₃[7:0]

A₂[7:0]

A₀[7:0]

A₁[7:0]

B₃[7:0]

B₂[7:0]

B₀[7:0]

B₁[7:0]

A₀[7:0]

A₂[15:8]

A₀[15:8]

A₂[7:0]

A₃[15:8]

A₁[15:8]

A₃[7:0]

A₁[7:0]

A₂[15:8]

A₀[15:8]

A₁[15:8]

B₃[15:8]

B₂[15:8]

B₀[15:8]

B₁[15:8]

A₀[15:8]

A₀[7:0]

B₀[7:0]

B₂[15:8]

B₀[15:8]

B₂[7:0]

B₀[7:0]

B₃[15:8]

B₁[15:8]

B₃[7:0]

B₁[7:0]

B₀[15:8]

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8.4.2.5 JESD204B Frame Assembly with Decimation

Table 12 lists the available JESD204B formats and valid ranges for the ADS54J60 when enabling the decimation

filter. The ranges are limited by the SERDES line rate and the maximum ADC sample frequency.

Table 13 lists the detailed frame assembly with different decimation options.

Table 12. Interface Rates with Decimation Filter

MINIMUM RATES

MAXIMUM RATES

DEVICE

CLOCK

FREQUENCY

(MSPS)

DEVICE

CLOCK

FREQUENCY

(MSPS)

OUTPUT

SAMPLE

RATE (MSPS)

OUTPUT

SAMPLE

RATE (MSPS)

L

M

F

S

DECIMATION

SERDES BIT

RATE (Gbps)

SERDES BIT

RATE (Gbps)

4

2

1

4

2

4

2

4

2

4

1

2

1

4X (IQ)

2X

500

300

500

300

125

250

150

125

75

2.5

3

1000

250

500

250

5.0

2X

10.0

5.0

4X

2.5

3

4X (IQ)

4X

10.0

75

3

Table 13. Frame Assembly with Decimation Filter

LMFS = 4222, 2X

DECIMATION

LMFS = 2242, 2X

DECIMATION

LMFS = 2221, 4X

DECIMATION

LMFS = 2441, 4X

DECIMATION (IQ)

LMFS = 4421, 4X

DECIMATION (IQ)

LMFS = 1241, 4X

DECIMATION

DA0

DA1

A1

AQ0

[15:8]

AQ0

[7:0]

[15:8]

[7:0]

A0

A1

A0

AI0

AQ0 AQ0

AI0

A0

B0

[15:8]

[7:0]

[15:8] [7:0] [15:8] [7:0]

[15:8]

[7:0]

[15:8] [7:0] [15:8] [7:0]

[15:8]

[7:0]

[15:8] [7:0] [15:8] [7:0]

DA2

DA3

B1

[15:8]

B1

[7:0]

BQ0

[15:8]

BQ0

[7:0]

DB0

DB1

B0

[15:8]

B0

[7:0]

B0

B1

B0

[15:8]

B0

[7:0]

BI0

BQ0 BQ0

BI0

[15:8]

BI0

[7:0]

[15:8] [7:0] [15:8] [7:0]

DB2

DB3

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8.4.2.5.1 JESD Transmitter Interface

Each of the 10.0-Gbps SERDES JESD transmitter outputs requires ac coupling between the transmitter and

receiver. The differential pair must be terminated with 100-Ω resistors as close to the receiving device as

possible to avoid unwanted reflections and signal degradation, as shown in Figure 79.

0.1 mF

DA[3:0]P,

DB[3:0]P

R_t= Z_O

Transmission Line, Zo

VCM

Receiver

R_t= Z_O

DA[3:0]M,

DB[3:0]M

0.1 mF

Figure 79. Output Connection to Receiver

8.4.2.5.2 Eye Diagram

Figure 80 to Figure 83 show the serial output eye diagrams of the ADS54J60 at 5.0 Gbps and 10 Gbps with

default and increased output voltage swing against the JESD204B mask.

Figure 80. Eye at 5-Gbps Bit Rate with

Default Output Swing

Figure 81. Eye at 5-Gbps Bit Rate with

Increased Output Swing

Figure 83. Eye at 10-Gbps Bit Rate with

Increased Output Swing

Figure 82. Eye at 10-Gbps Bit Rate with

Default Output Swing

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8.5.1 Example Register Writes

This section provides three different example register writes. Table 16 describes a global power-down register

write, Table 17 describes the register writes when the default lane setting (eight active lanes per device) is

changed to four active lanes (LMFS = 4211), and Table 18 describes the register writes for 2X decimation with

four active lanes (LMFS = 4222).

Table 16. Global Power Down

ADDRESS (Hex)

0-011h

DATA (Hex)

80h

COMMENT

Set the master page

0-026h

C0h

Set the global power-down

Table 17. Two Lanes per Channel Mode (LMFS = 4211)

ADDRESS (Hex)

4-004h

DATA (Hex)

69h

COMMENT

Select the JESD digital page

Select the digital to 40X mode

Select the JESD analog page

Set the SERDES PLL to 40X mode

4-003h

00h

6-001h

02h

4-004h

6Ah

6-016h

02h

Table 18. 2X Decimation (LPF for Both Channels) with Four Active Lanes (LMFS = 4222)

ADDRESS (Hex)

4-004h

DATA (Hex)

68h

COMMENT

Select the main digital page (6800h)

Set decimate-by-2 (low-pass filter)

Enable decimation filter control

BUS_REORDER EN2

4-003h

00h

6-041h

12h

6-04Dh

6-072h

08h

6-052h

80h

BUS_REORDER EN1

6-000h

01h

Pulse the PULSE RESET bit (so that register writes to the main digital page go into effect).

6-000h

00h

4-004h

69h

Select the JESD digital page (6900h)

4-003h

00h

Select the JESD digital page (6900h)

6-031h

0Ah

Output bus reorder for channel A

6-032h

0Ah

Output bus reorder for channel B

6-001h

31h

Program the JESD MODE and JESD FILTER register bits for LMFS = 4222.

Table 19 lists the access codes for the ADS54J60 registers.

Table 19. ADS54J60 Access Type Codes

Access Type

Code

Description

Read Type

R

Read

R/W

R-W

Read or write

Write Type

W

Write

Reset or Default Value

-n

Value after reset or the default value

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8.5.2 Register Descriptions

8.5.2.1 General Registers

8.5.2.1.1 Register 0h (address = 0h)

Figure 85. Register 0h

7

6

0

5

0

4

0

3

0

2

0

1

0

RESET

W-0h

RESET

W-0h

Table 20. Register 0h Field Descriptions

Bit

Field

Type

Reset

Description

7

RESET

W

0h

0 = Normal operation

1 = Internal software reset, clears back to 0

6-1

0

W

0h

Must write 0

RESET

0 = Normal operation

1 = Internal software reset, clears back to 0

8.5.2.1.2 Register 1h (address = 1h)

Figure 86. Register 1h

7

6

5

4

3

2

1

0

JESD BANK PAGE SEL1[7:0]

R/W-0h

Table 21. Register 1h Field Descriptions

Bit

Field

JESD BANK PAGE SEL1[7:0]

Type

Reset

Description

7-0

R/W

0h

Program these bits to access the desired page in the JESD

bank.

0000h = OFFSET READ Page

0500h = OFFSET LOAD Page

8.5.2.1.3 Register 2h (address = 2h)

Figure 87. Register 2h

7

6

5

4

3

2

1

0

JESD BANK PAGE SEL1[15:8]

R/W-0h

Table 22. Register 2h Field Descriptions

Bit

Field

JESD BANK PAGE SEL1[15:8]

Type

Reset

Description

7-0

R/W

0h

Program these bits to access the desired page in the JESD

bank.

0000h = OFFSET READ Page

0500h = OFFSET LOAD Page

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8.5.2.1.4 Register 3h (address = 3h)

Figure 88. Register 3h

7

6

5

4

3

2

1

0

JESD BANK PAGE SEL[7:0]

R/W-0h

Table 23. Register 3h Field Descriptions

Bit

Field

JESD BANK PAGE SEL[7:0]

Type

Reset

Description

7-0

R/W

0h

Program these bits to access the desired page in the JESD

bank.

6800h = Main digital page selected

6900h = JESD digital page selected

6A00h = JESD analog page selected

6100h = OFFSET READ or LOAD Page

8.5.2.1.5 Register 4h (address = 4h)

Figure 89. Register 4h

7

6

5

4

3

2

1

0

JESD BANK PAGE SEL[15:8]

R/W-0h

Table 24. Register 4h Field Descriptions

Bit

Field

JESD BANK PAGE SEL[15:8]

Type

Reset

Description

7-0

R/W

0h

Program these bits to access the desired page in the JESD

bank.

6800h = Main digital page selected

6900h = JESD digital page selected

6A00h = JESD analog page selected

6100h = OFFSET READ or LOAD Page

8.5.2.1.6 Register 5h (address = 5h)

Figure 90. Register 5h

7

0

6

0

5

0

4

3

0

2

1

0

DISABLE BROADCAST

R/W-0h

W-0h

Table 25. Register 5h Field Descriptions

Bit

Field

Type

W

Reset

0h

Description

7-1

0

Must write 0

DISABLE BROADCAST

R/W

0h

0 = Normal operation. Channel A and B are programmed as a pair.

1 = Channel A and B can be individually programmed based on the

CH bit.

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8.5.2.1.7 Register 11h (address = 11h)

Figure 91. Register 11h

7

6

5

4

3

2

1

0

ANALOG PAGE SEL

R/W-0h

Table 26. Register 11h Field Descriptions

Bit

Field

ANALOG BANK PAGE SEL

Type

Reset

Description

7-0

R/W

0h

Program these bits to access the desired page in the analog bank.

Master page = 80h

ADC page = 0Fh

8.5.2.2 Master Page (080h) Registers

8.5.2.2.1 Register 20h (address = 20h), Master Page (080h)

Figure 92. Register 20h

7

6

5

4

3

2

1

0

PDN ADC CHA

R/W-0h

PDN ADC CHB

R/W-0h

Table 27. Registers 20h Field Descriptions

Bit

7-4

3-0

Field

Type

R/W

Reset

0h

Description

PDN ADC CHA

PDN ADC CHB

There are two power-down masks that are controlled via the

PDN mask register bit in address 55h. The power-down mask 1

or mask 2 are selected via register bit 5 in address 26h.

Power-down mask 1: addresses 20h and 21h.

Power-down mask 2: addresses 23h and 24h.

0Fh = Power-down CHB only.

0h

F0h = Power-down CHA only.

FFh = Power-down both.

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8.5.2.2.2 Register 21h (address = 21h), Master Page (080h)

Figure 93. Register 21h

7

6

5

4

3

0

2

0

1

0

PDN BUFFER CHB

R/W-0h

PDN BUFFER CHA

R/W-0h

W-0h

Table 28. Register 21h Field Descriptions

Bit

Field

Type

R/W

Reset

0h

Description

7-6

5-4

PDN BUFFER CHB

PDN BUFFER CHA

There are two power-down masks that are controlled via the

PDN mask register bit in address 55h. The power-down mask 1

or mask 2 are selected via register address 26h, bit 5.

Power-down mask 1: addresses 20h and 21h.

Power-down mask 2: addresses 23h and 24h.

There are two buffers per channel. One buffer drives two ADC

cores.

0h

PDN BUFFER CHx:

00 = Both buffers of a channel are active.

11 = Both buffers are powered down.

01–10 = Do not use.

3-0

0

W

0h

Must write 0.

8.5.2.2.3 Register 23h (address = 23h), Master Page (080h)

Figure 94. Register 23h

7

6

5

4

3

2

1

0

PDN ADC CHA

R/W-0h

PDN ADC CHB

R/W-0h

Table 29. Register 23h Field Descriptions

Bit

7-4

3-0

Field

Type

R/W

Reset

0h

Description

PDN ADC CHA

PDN ADC CHB

There are two power-down masks that are controlled via the

PDN mask register bit in address 55h. The power-down mask 1

or mask 2 are selected via register address 26h, bit 5.

Power-down mask 1: addresses 20h and 21h.

Power-down mask 2: addresses 23h and 24h.

0Fh = Power-down CHB only.

0h

F0h = Power-down CHA only.

FFh = Power-down both.

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8.5.2.2.4 Register 24h (address = 24h), Master Page (080h)

Figure 95. Register 24h

7

6

5

4

3

0

2

0

1

0

PDN BUFFER CHB

R/W-0h

PDN BUFFER CHA

R/W-0h

W-0h

Table 30. Register 24h Field Descriptions

Bit

Field

Type

R/W

Reset

0h

Description

7-6

5-4

PDN BUFFER CHB

PDN BUFFER CHA

There are two power-down masks that are controlled via the

PDN mask register bit in address 55h. The power-down mask 1

or mask 2 are selected via register address 26h, bit 5.

Power-down mask 1: addresses 20h and 21h.

Power-down mask 2: addresses 23h and 24h.

There are two buffers per channel. One buffer drives two ADC

cores.

0h

PDN BUFFER CHx:

00 = Both buffers of a channel are active.

11 = Both buffers are powered down.

01–10 = Do not use.

3-0

0

W

0h

Must write 0.

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8.5.2.2.5 Register 26h (address = 26h), Master Page (080h)

Figure 96. Register 26h

7

6

5

4

0

3

0

2

0

1

0

OVERRIDE

PDN PIN

PDN MASK

SEL

GLOBAL PDN

R/W-0h

W-0h

Table 31. Register 26h Field Descriptions

Bit

Field

GLOBAL PDN

Type

Reset

Description

7

R/W

0h

Bit 6 (OVERRIDE PDN PIN) must be set before this bit can be

programmed.

0 = Normal operation

1 = Global power-down via the SPI

6

5

OVERRIDE PDN PIN

R/W

W

0h

This bit ignores the power-down pin control.

0 = Normal operation

1 = Ignores inputs on the power-down pin

PDN MASK SEL

0

This bit selects power-down mask 1 or mask 2.

0 = Power-down mask 1

1 = Power-down mask 2

4-0

Must write 0

8.5.2.2.6 Register 4Fh (address = 4Fh), Master Page (080h)

Figure 97. Register 4Fh

7

0

6

0

5

0

4

3

2

1

0

EN INPUT DC COUPLING

R/W-0h

W-0h

Table 32. Register 4Fh Field Descriptions

Bit

7-1

0

Field

Type

W

Reset

0h

Description

0

Must write 0

EN INPUT DC COUPLING

R/W

0h

The device has an internal biasing resistor of 600 Ω from VCM

to the INP and INM pins. A small common-mode current flows

through these resistors causing approximately a 100-mV drop.

To compensate for the drop, the device raises the VCM voltage

by 100 mV by default. This compensation is particularly helpful

in AC-coupling applications where the common-mode voltage on

the INP and INM pins is established by internal biasing resistors.

In DC-coupling applications, because the common-mode voltage

is established by external circuit, there is no need to raise VCM

by 100 mV.

0 = Device raises VCM voltage by 100 mV, useful in AC-

coupling applications

1 = Device does not raise the VCM voltage, useful in DC-

coupling applications

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8.5.2.2.7 Register 53h (address = 53h), Master Page (080h)

Figure 98. Register 53h

7

0

6

0

5

0

4

0

3

0

2

0

1

0

EN SYSREF

DC COUPLING

MANUAL

SYSREF

W-0h

R/W-0h

W-0h

R/W-0h

Table 33. Register 53h Field Descriptions

Bit

Field

Type

W

Reset

0h

Description

7-2

1

0

Must write 0

EN SYSREF DC COUPLING

R/W

0h

Enables a higher common-mode voltage input on the SYSREF

signal (up to 1.6 V).

0 = Normal operation

1 = Enables a higher SYSREF common-mode voltage support

0

MANUAL SYSREF

R/W

0h

The device has a feature to apply the SYSREF signal manually

through the serial interface instead of the SYREFP, SYREFM

pins. This application can be done by first setting the ENABLE

MANUAL SYSREF register bit, then using the MANUAL

SYSREF bit to set the SYSREF signal high or low.

0 = Set SYSREF low

1 = Set SYSREF high

8.5.2.2.8 Register 54h (address = 54h), Master Page (080h)

Figure 99. Register 54h

7

6

0

5

4

3

2

0

1

0

ENABLE

MANUAL

SYSREF

MASK SYSREF

R/W-0h

0

R/W-0h

W-0h

Table 34. Register 54h Field Descriptions

Bit

Field

Type

Reset

Description

7

ENABLE MANUAL SYSREF

R/W

0h

Enables the SYSREF input from the serial interface, thus

disabling pin control. Use the MANUAL SYSREF register bit to

apply SYSREF manually.

6

0

W

0h

Must write 0

5-4

MASK SYSREF

R/W

00 = Normal operation

11 = The SYSREF signal is ignored by the device irrespective of

how the signal was applied (through a pin or manually by the

serial interface)

3-0

0

W

0h

Must write 0

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8.5.2.2.9 Register 55h (address = 55h), Master Page (080h)

Figure 100. Register 55h

7

0

6

0

5

0

4

3

0

2

0

1

0

PDN MASK

R/W-0h

W-0h

Table 35. Register 55h Field Descriptions

Bit

Field

Type

W

Reset

0h

Description

7-5

4

0

Must write 0

PDN MASK

R/W

0h

This bit enables power-down via a register bit.

0 = Normal operation

1 = Power-down is enabled by powering down internal blocks as

specified in the selected power-down mask

3-0

0

W

0h

Must write 0

8.5.2.2.10 Register 59h (address = 59h), Master Page (080h)

Figure 101. Register 59h

7

6

0

5

4

0

3

0

2

0

1

0

FOVR CHB

W-0h

ALWAYS WRITE 1

R/W-0h

W-0h

Table 36. Register 59h Field Descriptions

Bit

Field

Type

Reset

Description

7

FOVR CHB

W

0h

Outputs FOVR signal for channel B on the SDOUT pin.

0 = normal operation

1 = FOVR on SDOUT pin

6

5

0

W

0h

Must write 0

Must write 1

Must write 0

ALWAYS WRITE 1

0

R/W

W

4-0

8.5.2.3 ADC Page (0Fh) Register

8.5.2.3.1 Register 5F (address = 5F), ADC Page (0Fh)

Figure 102. Register 5F

7

6

5

4

3

2

1

0

FOVR THRESHOLD PROG

R/W-E3h

Table 37. Register 5F Field Descriptions

Bit

Field

FOVR THRESHOLD PROG

Type

Reset

Description

7-0

R/W

E3h

Program the fast OVR thresholds together for channel A and B,

as described in the Overrange Indication section.

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8.5.2.4 Main Digital Page (6800h) Registers

8.5.2.4.1 Register 0h (address = 0h), Main Digital Page (6800h)

Figure 103. Register 0h

7

0

6

0

5

0

4

0

3

0

2

0

1

0

PULSE RESET

R/W-0h

W-0h

Table 38. Register 0h Field Descriptions

Bit

Field

Type

W

Reset

0h

Description

7-1

0

Must write 0

PULSE RESET

R/W

0h

Must be pulsed after power-up or after configuring registers in

the main digital page of the JESD bank. Any register bits in the

main digital page (6800h) take effect only after this bit is pulsed;

see the Start-Up Sequence section for the correct sequence.

0 = Normal operation

0 → 1 → 0 = Bit is pulsed

8.5.2.4.2 Register 41h (address = 41h), Main Digital Page (6800h)

Figure 104. Register 41h

7

0

6

0

5

4

3

2

1

0

DECFIL MODE[3]

R/W-0h

DECFIL EN

R/W-0h

0

DECFIL MODE[2:0]

R/W-0h

W-0h

Table 39. Register 41h Field Descriptions

Bit

Field

Type

W

Reset

0h

Description

7-6

5

0

Must write 0

DECFIL MODE[3]

R/W

0h

This bit selects the decimation filter mode. Table 40 lists the bit

settings.

The decimation filter control (DEC MODE EN, register 4Dh, bit 3) and

decimation filter enable (DECFIL EN, register 41h, bit 4) must be

enabled.

4

DECFIL EN

R/W

0h

Enables the digital decimation filter

0 = Normal operation, full rate output

1 = Digital decimation enabled

3

0

W

0h

Must write 0

2-0

DECFIL MODE[2:0]

R/W

These bits select the decimation filter mode. Table 40 lists the bit

settings.

The decimation filter control (DEC MODE EN, register 4Dh, bit 3) and

decimation filter enable (DECFIL EN, register 41h, bit 4) must be

enabled.

Table 40. DECFIL MODE Bit Settings

BITS (5, 2-0)

FILTER MODE

DECIMATION

0000

0100

1000

1100

0010

0110

0011

Band-pass filter centered on 3 × f_S/ 16

4X

Band-pass filter centered on 5 × f_S/ 16

Band-pass filter centered on 1 × f_S/ 16

Band-pass filter centered on 7 × f_S/ 16

Low-pass filter

4X

2X

High-pass filter

2X

Low-pass filter with f_S/ 4 mixer

4X (IQ)

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8.5.2.4.3 Register 42h (address = 42h), Main Digital Page (6800h)

Figure 105. Register 42h

7

0

6

0

5

0

4

0

3

0

2

1

0

NYQUIST ZONE

R/W-0h

W-0h

Table 41. Register 42h Field Descriptions

Bit

Field

Type

W

Reset

0h

Description

7-3

2-0

0

Must write 0

NYQUIST ZONE

R/W

0h

The Nyquist zone must be selected for proper interleaving

correction. Control must be enabled (register 4Eh, bit 7).

000 = 1st Nyquist zone (0 MHz to 500 MHz)

001 = 2nd Nyquist zone (500 MHz to 1000 MHz)

010 = 3rd Nyquist zone (1000 MHz to 1500 MHz)

All others = Not used

8.5.2.4.4 Register 43h (address = 43h), Main Digital Page (6800h)

Figure 106. Register 43h

7

0

6

0

5

0

4

0

3

0

2

0

1

0

FORMAT SEL

R/W-0h

W-0h

Table 42. Register 43h Field Descriptions

Bit

Field

Type

W

Reset

0h

Description

7-1

0

Must write 0

FORMAT SEL

R/W

0h

Changes the output format. Set the FORMAT EN bit to enable

control using this bit.

0 = Twos complement

1 = Offset binary

8.5.2.4.5 Register 44h (address = 44h), Main Digital Page (6800h)

Figure 107. Register 44h

7

0

6

5

4

3

2

1

0

DIGITAL GAIN

R/W-0h

Table 43. Register 44h Field Descriptions

Bit

7

Field

Type

R/W

Reset

0h

Description

0

Must write 0

6-0

DIGITAL GAIN

0h

Digital gain setting. Digital gain must be enabled (register 52h,

bit 0).

Gain in dB = 20log (digital gain / 32)

7Fh = 127 which equals digital gain of 12 dB

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8.5.2.4.6 Register 4Bh (address = 4Bh), Main Digital Page (6800h)

Figure 108. Register 4Bh

7

0

6

0

5

4

0

3

0

2

0

1

0

FORMAT EN

R/W-0h

W-0h

Table 44. Register 4Bh Field Descriptions

Bit

Field

Type

W

Reset

0h

Description

7-6

5

0

Must write 0

FORMAT EN

R/W

0h

This bit enables control for data format selection using the

FORMAT SEL register bit.

0 = Default, output is in twos complement format

1 = Output is in offset binary format after FORMAT SEL bit is

also set

4-0

0

W

0h

Must write 0

8.5.2.4.7 Register 4Dh (address = 4Dh), Main Digital Page (6800h)

Figure 109. Register 4Dh

7

0

6

0

5

0

4

0

3

2

0

1

0

DEC MOD EN

R/W-0h

W-0h

Table 45. Register 4Dh Field Descriptions

Bit

Field

Type

W

Reset

0h

Description

7-4

3

0

Must write 0

DEC MOD EN

R/W

0h

This bit enables control of decimation filter mode via the DECFIL

MODE[3:0] register bits.

0 = Default

1 = Decimation modes control is enabled

2-0

0

W

0h

Must write 0

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8.5.2.4.8 Register 4Eh (address = 4Eh), Main Digital Page (6800h)

Figure 110. Register 4Eh

7

6

0

5

4

0

3

0

2

0

1

0

CTRL NYQUIST

IMPROVE IL

PERF

R/W-0h

W-0h

Table 46. Register 4Eh Field Descriptions

Bit

Field

Type

Reset

Description

7

CTRL NYQUIST

R/W

0h

This bit enables selecting the Nyquist zone using register 42h,

bits 2-0.

0 = Selection disabled

1 = Selection enabled

6

5

0

W

0h

Must write 0

IMPROVE IL PERF

R/W

Improves interleaving performance. Effective only for input

frequencies that are within ± f_S/ 64 band centered at n × f_S/ 8

(n = 1, 2, 3, or 4). For example, at a 1-Gsps sampling rate, this

bit may improve IL performance when input frequencies fall

within the ±15.625-MHz band located at 125 MHz, 250 MHz,

375 MHz, and 500 MHz.

0 = Default

1 = Improves IL performance for certain input frequencies

4-0

0

W

0h

Must write 0

8.5.2.4.9 Register 52h (address = 52h), Main Digital Page (6800h)

Figure 111. Register 52h

7

6

0

5

0

4

3

2

0

1

0

BUS_REORDER_EN1

W-0h

0

DIG GAIN EN

R/W-0h

W-0h

Table 47. Register 52h Field Descriptions

Bit

7

Field

Type

R/W

W

Reset

0h

Description

BUS_REORDER_EN1

Must write 1 in DDC mode only

Must write 0

6-1

0

0h

DIG GAIN EN

R/W

0h

Enables selecting the digital gain for register 44h.

0 = Digital gain disabled

1 = Digital gain enabled

8.5.2.4.10 Register 72h (address = 72h), Main Digital Page (6800h)

Figure 112. Register 72h

7

0

6

0

5

0

4

0

3

2

0

1

0

BUS_REORDER_EN2

R/W-0h

W-0h

Table 48. Register 72h Field Descriptions

Bit

7-4

3

Field

Type

W

Reset

0h

Description

0

Must write 0

BUS_REORDER_EN2

0

R/W

W

0h

Must write a 1 in DDC mode only

Must write 0

2-0

0h

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8.5.2.4.11 Register ABh (address = ABh), Main Digital Page (6800h)

Figure 113. Register ABh

7

0

6

0

5

0

4

0

3

0

2

0

1

0

LSB SEL EN

R/W-0h

W-0h

Table 49. Register ABh Field Descriptions

Bit

Field

Type

W

Reset

0h

Description

7-1

0

Must write 0

LSB SEL EN

R/W

0h

Enable control for the LSB SELECT register bit.

0 = Default

1 = The LSB of 16-bit ADC data can be programmed as fast

OVR using the LSB SELECT bit.

8.5.2.4.12 Register ADh (address = ADh), Main Digital Page (6800h)

Figure 114. Register ADh

7

0

6

0

5

0

4

0

3

0

2

0

1

0

LSB SELECT

R/W-0h

W-0h

Table 50. Register ADh Field Descriptions

Bit

Field

Type

W

Reset

0h

Description

7-2

1-0

0

Must write 0

LSB SELECT

R/W

0h

Enables output of the FOVR flag instead of the output data LSB.

00 = Output is 16-bit data

11 = Output data LSB is replaced by the FOVR information for

each channel

8.5.2.4.13 Register F7h (address = F7h), Main Digital Page (6800h)

Figure 115. Register F7h

7

0

6

0

5

0

4

0

3

0

2

0

1

0

DIG RESET

W-0h

Table 51. Register F7h Field Descriptions

Bit

Field

Type

W

Reset

0h

Description

7-1

0

Must write 0

DIG RESET

W

0h

Self-clearing reset for the digital block. Does not include the

interleaving correction.

0 = Normal operation

1 = Digital reset

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8.5.2.5 JESD Digital Page (6900h) Registers

8.5.2.5.1 Register 0h (address = 0h), JESD Digital Page (6900h)

Figure 116. Register 0h

7

6

0

5

0

4

3

2

1

0

TESTMODE

EN

FLIP ADC

DATA

CTRL K

R/W-0h

LANE ALIGN

R/W-0h

FRAME ALIGN

R/W-0h

TX LINK DIS

R/W-0h

W-0h

R/W-0h

Table 52. Register 0h Field Descriptions

Bit

Field

Type

Reset

Description

7

CTRL K

R/W

0h

Enable bit for a number of frames per multi frame.

0 = Default is five frames per multi frame

1 = Frames per multi frame can be set in register 06h

6-5

4

0

W

0h

Must write 0

TESTMODE EN

R/W

This bit generates the long transport layer test pattern mode, as

per section 5.1.6.3 of the JESD204B specification.

0 = Test mode disabled

1 = Test mode enabled

3

2

FLIP ADC DATA

LANE ALIGN

R/W

0h

0 = Normal operation

1 = Output data order is reversed: MSB to LSB.

This bit inserts the lane alignment character (K28.3) for the

receiver to align to lane boundary, as per section 5.3.3.5 of the

JESD204B specification.

0 = Normal operation

1 = Inserts lane alignment characters

1

0

FRAME ALIGN

TX LINK DIS

R/W

0h

This bit inserts the lane alignment character (K28.7) for the

receiver to align to lane boundary, as per section 5.3.3.5 of the

JESD204B specification.

0 = Normal operation

1 = Inserts frame alignment characters

This bit disables sending the initial link alignment (ILA) sequence

when SYNC is de-asserted.

0 = Normal operation

1 = ILA disabled

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8.5.2.5.2 Register 1h (address = 1h), JESD Digital Page (6900h)

Figure 117. Register 1h

7

6

5

4

3

2

1

0

SYNC REG

R/W-0h

SYNC REG EN

R/W-0h

JESD FILTER

R/W-0h

JESD MODE

R/W-01h

Table 53. Register 1h Field Descriptions

Bit

Field

SYNC REG

Type

Reset

Description

7

R/W

0h

Register control for sync request.

0 = Normal operation

1 = ADC output data are replaced with K28.5 characters. Register

bit SYNC REG EN must also be set to 1.

6

SYNC REG EN

JESD FILTER

R/W

0h

Enables register control for sync request.

0 = Use the SYNC pin for sync requests

1 = Use the SYNC REG register bit for sync requests

5-3

These bits and the JESD MODE bits set the correct LMFS

configuration for the JESD interface. The JESD FILTER setting

must match the configuration in the decimation filter page.

000 = Filter bypass mode

See Table 54 for valid combinations for register bits JESD FILTER

along with JESD MODE.

2-0

JESD MODE

R/W

01h

These bits select the number of serial JESD output lanes per ADC.

The JESD PLL MODE register bit located in the JESD analog page

must also be set accordingly.

001 = Default after reset(Eight active lanes)

See Table 54 for valid combinations for register bits JESD FILTER

along with JESD MODE.

Table 54. Valid Combinations for JESD FILTER and JESD MODE Bits

NUMBER OF ACTIVE LANES

PER DEVICE

REGISTER BIT JESD FILTER

REGISTER BIT JESD MODE

DECIMATION FACTOR

000

100

010

No decimation

Four lanes are active

No decimation

(default after reset)

000

001

Eight lanes are active

111

110

100

111

100

001

010

001

010

4X (IQ)

2X

Four lanes are active

Two lanes are active

One lane is active

2X

4X

4X (IQ)

4X

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8.5.2.5.3 Register 2h (address = 2h), JESD Digital Page (6900h)

Figure 118. Register 2h

7

6

5

4

3

2

0

1

0

LINK LAYER TESTMODE

R/W-0h

LINK LAYER RPAT

R/W-0h

LMFC MASK RESET

R/W-0h

W-0h

Table 55. Register 2h Field Descriptions

Bit

Field

Type

Reset

Description

7-5

LINK LAYER TESTMODE

R/W

0h

These bits generate a pattern according to clause 5.3.3.8.2 of the

JESD204B document.

000 = Normal ADC data

001 = D21.5 (high-frequency jitter pattern)

010 = K28.5 (mixed-frequency jitter pattern)

011 = Repeat initial lane alignment (generates a K28.5 character

and continuously repeats lane alignment sequences)

100 = 12 octet RPAT jitter pattern

All others = Not used

4

LINK LAYER RPAT

R/W

0h

This bit changes the running disparity in the modified RPAT pattern

test mode (only when the link layer test mode = 100).

0 = Normal operation

1 = Changes disparity

3

LMFC MASK RESET

0

R/W

W

0h

Mask LMFC reset coming to digital block.

0 = LMFC reset is not masked

1 = Ignore LMFC reset request

2-0

Must write 0

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8.5.2.5.4 Register 3h (address = 3h), JESD Digital Page (6900h)

Figure 119. Register 3h

7

6

5

4

3

2

1

0

FORCE LMFC

COUNT

LMFC COUNT INIT

R/W-0h

RELEASE ILANE SEQ

R/W-0h

Table 56. Register 3h Field Descriptions

Bit

Field

Type

Reset

Description

7

FORCE LMFC COUNT

R/W

0h

This bit forces the LMFC count.

0 = Normal operation

1 = Enables using a different starting value for the LMFC

counter

6-2

1-0

LMFC COUNT INIT

R/W

0h

When SYSREF transmits to the digital block, the LMFC count

resets to 0 and K28.5 stops transmitting when the LMFC count

reaches 31. The initial value that the LMFC count resets to can

be set using LMFC COUNT INIT. In this manner, the receiver

can be synchronized early because it receives the LANE

ALIGNMENT SEQUENCE early. The FORCE LMFC COUNT

register bit must be enabled.

RELEASE ILANE SEQ

These bits delay the generation of the lane alignment sequence

by 0, 1, 2 or 3 multi frames after the code group synchronization.

00 = 0

01 = 1

10 = 2

11 = 3

8.5.2.5.5 Register 5h (address = 5h), JESD Digital Page (6900h)

Figure 120. Register 5h

7

6

0

5

4

3

2

0

1

0

SCRAMBLE EN

R/W-Undefined

0

W-0h

Table 57. Register 5h Field Descriptions

Bit

Field

Type

Reset

Description

7

SCRAMBLE EN

R/W

Undefined Scramble enable bit in the JESD204B interface.

0 = Scrambling disabled

1 = Scrambling enabled

6-0

0

W

0h

Must write 0

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8.5.2.5.6 Register 6h (address = 6h), JESD Digital Page (6900h)

Figure 121. Register 6h

7

0

6

0

5

0

4

3

2

1

0

FRAMES PER MULTI FRAME (K)

R/W-8h

W-0h

Table 58. Register 6h Field Descriptions

Bit

Field

Type

W

Reset

0h

Description

7-5

4-0

0

Must write 0

FRAMES PER MULTI FRAME (K)

R/W

8h

These bits set the number of multi frames.

Actual K is the value in hex + 1 (that is, 0Fh is K = 16).

8.5.2.5.7 Register 7h (address = 7h), JESD Digital Page (6900h)

Figure 122. Register 7h

7

0

6

0

5

0

4

3

2

0

1

0

SUBCLASS

R/W-1h

W-0h

Table 59. Register 7h Field Descriptions

Bit

Field

Type

W

Reset

0h

Description

7-4

3

0

Must write 0

SUBCLASS

R/W

1h

This bit sets the JESD204B subclass.

000 = Subclass 0 backward compatible with JESD204A

001 = Subclass 1 deterministic latency using the SYSREF signal

2-0

0

W

0h

Must write 0

8.5.2.5.8 Register 16h (address = 16h), JESD Digital Page (6900h)

Figure 123. Register 16h

7

1

6

0

5

0

4

3

0

2

0

1

0

LANE SHARE

W-0h

W-1h

W-0h

R/W-0h

W-0h

Table 60. Register 16h Field Descriptions

Bit

Field

Type

W

Reset

1h

Description

Must write 1

Must write 0

7

6-5

4

1

0

W

0h

LANE SHARE

R/W

0h

When using decimate-by-4, the data of both channels are output

over one lane (LMFS = 1241).

0 = Normal operation (each channel uses one lane)

1 = Lane sharing is enabled, both channels share one lane

(LMFS = 1241)

3-0

0

W

0h

Must write 0

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8.5.2.5.9 Register 31h (address = 31h), JESD Digital Page (6900h)

Figure 124. Register 31h

7

6

5

4

3

2

1

0

DA_BUS_REORDER[7:0]

R/W-0h

Table 61. Register 31h Field Descriptions

Bit

Field

DA_BUS_REORDER[7:0]

Type

Reset

Description

7-0

R/W

0h

Use these bits to program output connections between data

streams and output lanes in decimate-by-2 and decimate-by-4

mode. Table 14 lists the supported combinations of these bits.

8.5.2.5.10 Register 32h (address = 32h), JESD Digital Page (6900h)

Figure 125. Register 32h

7

6

5

4

3

2

1

0

DB_BUS_REORDER[7:0]

R/W-0h

Table 62. Register 32h Field Descriptions

Bit

Field

DB_BUS_REORDER[7:0]

Type

Reset

Description

7-0

R/W

0h

Use these bits to program output connections between data

streams and output lanes in decimate-by-2 and decimate-by-4

mode. Table 14 lists the supported combinations of these bits.

8.5.2.6 JESD Analog Page (6A00h) Registers

8.5.2.6.1 Register 12h (address = 12h), JESD Analog Page (6A00h)

Figure 126. Register 12h

7

6

5

4

3

2

1

0

SEL EMP LANE 1

ALWAYS

WRITE 1

R/W-0h

W-0h

Table 63. Register 12h-15h Field Descriptions

Bit

Field

Type

Reset

Description

7-2

SEL EMP LANE 1

R/W

0h

Selects the amount of de-emphasis for the JESD output

transmitter. The de-emphasis value in dB is measured as the

ratio between the peak value after the signal transition to the

settled value of the voltage in one bit period.

000000 = 0 dB

000001 = –1 dB

000011 = –2 dB

000111 = –4.1 dB

001111 = –6.2 dB

011111 = –8.2 dB

111111 = –11.5 dB

1

0

ALWAYS WRITE 1

0

W

0h

1 = Always write 1

0 = Must write 0

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8.5.2.6.2 Registers 13h-15h (address = 13h-15h), JESD Analog Page (6A00h)

Figure 127. Register 13h

7

6

5

4

3

2

1

0

SEL EMP LANE 0

R/W-0h

W-0h

Figure 128. Register 14h

5

4

3

1

0

SEL EMP LANE 2

R/W-0h

W-0h

Figure 129. Register 15h

5

4

3

1

0

SEL EMP LANE 3

R/W-0h

W-0h

Table 64. Register 13h-15h Field Descriptions

Bit

Field

Type

Reset

Description

7-2

SEL EMP LANE x (where x = 0, 2,

or 3)

R/W

0h

Selects the amount of de-emphasis for the JESD output

transmitter. The de-emphasis value in dB is measured as the

ratio between the peak value after the signal transition to the

settled value of the voltage in one bit period.

000000 = 0 dB

000001 = –1 dB

000011 = –2 dB

000111 = –4.1 dB

001111 = –6.2 dB

011111 = –8.2 dB

111111 = –11.5 dB

1-0

0

W

0h

0 = Must write 0

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8.5.2.6.3 Register 16h (address = 16h), JESD Analog Page (6A00h)

Figure 130. Register 16h

7

0

6

0

5

0

4

0

3

0

2

0

1

0

JESD PLL MODE

R/W-0h

W-0h

Table 65. Register 16h Field Descriptions

Bit

Field

Type

W

Reset

0h

Description

7-2

1-0

0

Must write 0

JESD PLL MODE

R/W

0h

These bits select the JESD PLL multiplication factor and must

match the JESD MODE setting.

00 = 20X mode, four lanes per ADC

01 = Not used

10 = 40X mode

11 = Not used

Table 14 lists a programming summary of the DDC modes and

JESD link configuration.

8.5.2.6.4 Register 17h (address = 17h), JESD Analog Page (6A00h)

Figure 131. Register 17h

7

0

6

5

4

0

3

2

0

1

0

PLL RESET

R/W-0h

LANE PDN 1

R/W-0h

LANE PDN 0

R/W-0h

W-0h

Table 66. Register 17h Field Descriptions

Bit

Field

Type

W

Reset

0h

Description

7

6

0

Must write 0

PLL RESET

R/W

0h

Pulse this bit after powering up the device; see Table 75.

0 = Default

0 → 1 → 0 = The PLL RESET bit is pulsed.

5

LANE PDN 1

R/W

0h

This bit powers down unused SERDES lanes DA0, DA3, DB0,

and DB3 in certain LMFS settings (applicable for LMFS = 4244,

2242, 2441, 4211, and 2221). Powering down unused lanes puts

the SERDES buffers in tri-state mode and saves approximately

15-mA current on the IOVDD supply.

00 : Default

11 : DA0, DB0, DA3, and DB3 are powered down

Others: Do not use

4

3

0

W

0h

Must write 0

LANE PDN 0

R/W

This bit powers down unused SERDES lanes DA0, DA3, DB0,

and DB3 in certain LMFS settings (applicable for LMFS = 4244,

2242, 2441, 4211, and 2221). Powering down unused lanes puts

the SERDES buffers in tri-state mode and saves approximately

15-mA current on the IOVDD supply.

00 : Default

11 : DA0, DB0, DA3, and DB3 are powered down

Others: Do not use

2-0

0

W

0h

Must write 0

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8.5.2.6.5 Register 1Ah (address = 1Ah), JESD Analog Page (6A00h)

Figure 132. Register 1Ah

7

0

6

0

5

0

4

0

3

0

2

0

1

0

FOVR CHA

R/W-0h

W-0h

Table 67. Register 1Ah Field Descriptions

Bit

Field

Type

W

Reset

0h

Description

7-2

1

0

Must write 0

FOVR CHA

R/W

0h

Outputs FOVR signal for channel A on the PDN pin. FOVR CHA

EN (register 1Bh, bit 3) must be enabled.

0 = Normal operation

1 = FOVR on the PDN pin

0

W

0h

Must write 0

8.5.2.6.6 Register 1Bh (address = 1Bh), JESD Analog Page (6A00h)

Figure 133. Register 1Bh

7

6

5

4

0

3

2

0

1

0

JESD SWING

R/W-0h

FOVR CHA EN

R/W-0h

W-0h

Table 68. Register 1Bh Field Descriptions

Bit

Field

Type

Reset

Description

7-5

JESD SWING

R/W

0h

Selects output amplitude VOD (mVpp) of the JESD transmitter

(for all lanes)

0 = 860 mVpp

1 = 810 mVpp

2 = 770 mVpp

3 = 745 mVpp

4 = 960 mVpp

5 = 930 mVpp

6 = 905 mVpp

7 = 880 mVpp

4

3

0

W

0h

Must write 0

FOVR CHA EN

R/W

Enables overwrite of PDN pin with the FOVR signal from ChA.

0 = Normal operation

1 = PDN is being overwritten

2-0

0

R/W

0h

Must write 0

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8.5.2.7 Offset Read Page (JESD BANK PAGE SEL = 6100h, JESD BANK PAGE SEL1 = 0000h) Registers

8.5.2.7.1 Register 068h (address = 068h), Offset Read Page

Figure 134. Register 068h

7

6

5

4

3

2

1

0

FREEZE

CORR

DC OFFSET CORR BW

BYPASS

CORR

ALWAYS

WRITE 1

R/W-0h

W-0h

Table 69. Register 068h Field Descriptions

Bit

Field

Type Reset

Description

Offset correction block is enabled by default. Set this bit to freeze the block.

0 = Default after reset

1 = Offset correction block is frozen

7

FREEZE CORR

R/W 0h

See the DC Offset Correction Block in the ADS54J60 section for details.

DC OFFSET CORR BW

These bits allow the user to program the 3-dB bandwidth of the notch filter centered

around k × f_S/ 4 (k = 0, 1, 2). The notch filter is a first-order digital filter with 3-dB

bandwidth:

3-dB bandwidth normalized to f_S

0 = 2.99479E-07

1 = 1.4974E-07

2 = 7.48698E-08

3 = 3.74349E-08

4 = 1.87174E-08

5 = 9.35872E-09

6-3

R/W 0h

6 = 4.67936E-09

7 = 2.33968E-09

8 = 1.16984E-09

9 = 5.8492E-10

10 = 2.9246E-10

11 = 1.4623E-10

For example, at f_S= 1 GSPS, if DC OFFSET CORR BW is set to 1, the notch filter has

a 3-dB bandwidth of 149.74 Hz.

0 = Default after reset

2

BYPASS CORR

R/W 0h

1 = Offset correction block is bypassed

See the DC Offset Correction Block in the ADS54J60 section for details.

1

0

ALWAYS WRITE 1

0

Always write 1

Must write 0

W

0h

8.5.2.7.2 Register 069h (address = 069h), Offset Read Page

Figure 135. Register 069h

7

0

6

0

5

0

4

0

3

0

2

0

1

0

EXT CORR EN

R/W-0h

W-0h

Table 70. Register 069h Field Descriptions

Bit

Field

Type

Reset

Description

7-1

0

W

0h

Must write 0

Enables loading of external estimate into offset correction block.

0 = Default after reset (device uses internal estimate for offset

correction)

0

EXT CORR EN

R/W

0h

1 = External estimate can be loaded by using the

ADCx_LOAD_EXT_EST register bits

See the DC Offset Correction Block in the ADS54J60 section for

details.

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8.5.2.7.3 Registers 074h, 076h, 078h, 7Ah (address = 074h, 076h, 078h, 7Ah), Offset Read Page

Figure 136. Registers 074h, 076h, 078h, 7Ah

7

6

5

4

3

2

1

0

ADCx_CORR_INT_EST[7:0]

R/W-0h

Table 71. Registers 074h, 076h, 078h, 7Ah Field Descriptions

Bit

Field

Type

Reset

Description

Internal estimate for all four interleaving ADC cores of the dc

offset corrector block can be read from these bits.

Keep the R/W bit set to 1 when reading from these registers.

See the DC Offset Correction Block in the ADS54J60 section for

details.

7-0

ADCx_CORR_INT_EST[7:0]

R/W

0h

8.5.2.7.4 Registers 075h, 077h, 079h, 7Bh (address = 075h, 077h, 079h, 7Bh), Offset Read Page

Figure 137. Registers 075h, 077h, 079h, 7Bh

7

0

6

0

5

0

4

0

3

0

2

1

0

ADCx_CORR_INT_EST[10:8]

R/W-0h

W-0h

Table 72. Registers 075h, 077h, 079h, 7Bh Field Descriptions

Bit

Field

Type

Reset

Description

7-3

0

W

0h

Must write 0

Internal estimate for all four interleaving ADC cores of the dc

offset corrector block can be read from these bits.

Keep the R/W bit set to 1 when reading from these registers.

See the DC Offset Correction Block in the ADS54J60 section for

details.

2-0

ADCx_CORR_INT_EST[10:8]

R/W

0h

8.5.2.8 Offset Load Page (JESD BANK PAGE SEL= 6100h, JESD BANK PAGE SEL1 = 0500h) Registers

8.5.2.8.1 Registers 00h, 04h, 08h, 0Ch (address = 00h, 04h, 08h, 0Ch), Offset Load Page

Figure 138. Registers 00h, 04h, 08h, 0Ch

7

6

5

4

3

2

1

0

ADCx_LOAD_EXT_EST[7:0]

R/W-0h

Table 73. Registers 00h, 04h, 08h, 0Ch Field Descriptions

Bit

Field

Type

Reset

Description

External estimate can be loaded into the dc offset corrector

blocks for all four interleaving ADC cores.

See the DC Offset Correction Block in the ADS54J60 section for

details.

7-0

ADCx_LOAD_EXT_EST[7:0]

R/W

0h

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8.5.2.8.2 Registers 01h, 05h, 09h, 0Dh (address = 01h, 05h, 09h, 0Dh), Offset Load Page

Figure 139. Registers 01h, 05h, 09h, 0Dh

7

0

6

0

5

0

4

0

3

0

2

1

0

ADCx_LOAD_EXT_EST[10:8]

R/W-0h

W-0h

Table 74. Registers 01h, 05h, 09h, 0Dh Field Descriptions

Bit

Field

Type

Reset

Description

7-3

0

W

0h

Must write 0

External estimate can be loaded into the dc offset corrector

blocks for all four interleaving ADC cores.

See the DC Offset Correction Block in the ADS54J60 section for

details.

2-0

ADCx_CORR_INT_EST[10:8]

R/W

0h

9 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

9.1 Application Information

9.1.1 Start-Up Sequence

The steps described in Table 75 are recommended as the power-up sequence with the ADS54J60 in 20X mode

(LMFS = 8224).

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9.1.2 Hardware Reset

Figure 140 and Table 76 show the timing for a hardware reset.

Power Supplies

t₁

RESET

t₂

t₃

SEN

Figure 140. Hardware Reset Timing Diagram

Table 76. Timing Requirements for Figure 140

MIN

TYP

MAX

UNIT

ms

ns

t₁

t₂

t₃

Power-on delay: delay from power up to active high RESET pulse

1

10

Reset pulse duration: active high RESET pulse duration

Register write delay: delay from RESET disable to SEN active

100

ns

9.1.3 SNR and Clock Jitter

The signal-to-noise ratio (SNR) of the ADC is limited by three different factors: quantization noise, thermal noise,

and jitter, as shown in Equation 4. The quantization noise is typically not noticeable in pipeline converters and is

98 dB for a 16-bit ADC. The thermal noise limits the SNR at low input frequencies and the clock jitter sets the

SNR for higher input frequencies.

(4)

The SNR limitation resulting from sample clock jitter can be calculated by Equation 5:

(5)

The total clock jitter (T_Jitter) has two components: the internal aperture jitter (130 fs) is set by the noise of the

clock input buffer and the external clock jitter. T_Jittercan be calculated by Equation 6:

(6)

External clock jitter can be minimized by using high-quality clock sources and jitter cleaners as well as band-pass

filters at the clock input. A faster clock slew rate also improves the ADC aperture jitter.

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The ADS54J60 has a thermal noise of approximately 71.1 dBFS and an internal aperture jitter of 120 fs. The

SNR, depending on the amount of external jitter for different input frequencies, is shown in Figure 141.

75

35 f_S

50 f_S

100 f_S

150 f_S

200 f_S

73

71

69

67

65

10

100

Input Frequency (MHz)

D052

Figure 141. SNR versus Input Frequency and External Clock Jitter

9.1.4 DC Offset Correction Block in the ADS54J60

The ADS54J60 employs eight dc offset correction blocks (four per channel, one per interleaving core).

Figure 142 shows a dc correction block diagram.

Input data, x(n)

(250 MSPS data from each interleaving core)

0

Output data, y(n)

at 250 MSPS

1

+

œ

DC Corrected data

ALWAYS WRITE 1

(Reg 68h, bit 1)

0

DC Correction

Engine

BYPASS CORR

1

FREEZE CORR

ADCx_LOAD_EXT_EST[10:0]

Internal Estimate

Read back path

EXT CORR EN

ADCx_CORR_INT_EST[10:0]

Figure 142. DC Offset Correction Block Diagram

The purpose of the dc offset correction block is to correct the dc offset of interleaving cores that mainly arise

from the amplifier in the first pipeline stage. Any mismatch in dc offset among interleaving cores results in spurs

at f_S/ 4 and f_S/ 2. The dc offset correction blocks estimate and correct the dc offset of an individual core, to the

ideal mid-code value, and thereby remove the effect of offset mismatch.

The dc offset correction block can correct the dc offset of an individual core up to ±1024 codes.

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In applications involving dc-coupling between the ADC and the driver, the dc offset correction block can either be

bypassed or frozen because the block cannot distinguish the external dc signal from the internal dc offset.

Figure 143 shows that when bypassed, the internal dc mismatch appears at dc, f_S/ 4, and f_S/ 2 frequency points

and can be as big as –40 dBFS.

0

-20

-40

-60

-80

-100

-120

0

100

200

300

400

500

Frequency (MHz)

D001

Figure 143. FFT After Bypassing the DC Offset Correction Block

9.1.4.1 Freezing the DC Offset Correction Block

After device is powered up, the dc offset correction block estimates the internal dc offset with the idle channel

input before the block is frozen. When frozen, the correction block holds the last estimated value that belongs to

the internal dc offset. After the correction block is frozen, an external signal can be applied.

9.1.4.2 Effect of Temperature

The internal dc offset of the individual cores changes with temperature, resulting in f_S/ 4 and f_S/ 2 spurs

appearing again in the spectrum at a different temperature.

Figure 144 shows a variation of the f_S/ 4 spur over temperature for a typical device.

-40

-50

-60

-70

-80

-90

-40

-15

10

35

60

85

Temperature (°C)

D068

NOTE: The offset correction block was frozen at room temperature, then the temperature was varied from –40°C to +85°C.

Figure 144. Variation of the f_S/ 4 Spur Over Temperature

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Although some systems can accept such a variation in the f_S/ 4 and f_S/ 2 spurs across temperature, other

systems may require the internal dc offset profile to be calibrated with temperature. To achieve this calibration,

the device provides an option to read the internal estimate values from the correction block for each of the

interleaving cores and also to load the values back to the correction block. For calibration, after power up, a

temperature sweep can be performed with the idle channel input and the internal dc offset can be read back

using the ADCx_CORR_INT_EST register bits for salient temperature points. Then during operation, when

temperature changes, the corresponding estimates can be externally loaded to the correction block using the

ADCx_LOAD_EXT_EST register bits.

The dc offset corrector block is enabled by default. For a given channel, the device can disable and freeze the

block, read the estimate of the block, and load the external estimate.

Table 77 lists an example of required SPI writes for reading an internal estimate of the dc offset correction block,

and then loading the estimate back to the corrector.

Table 77. Format (16-Bit Address, 8-Bit Data)

ADDRESS

STEP

DATA (Hex)

COMMENT

(Hex)⁽¹⁾

This setting disables broadcast mode (channel A and B can be individually

programmed)

4-005

01

4-004

4-003

4-002

4-001

61

00

Selects offset read page (61000000h)

Data from the offset read page can be read as below (keep the R/W bit = 1)

E-074

E-075

E-076

E-077

E-078

E-079

E-07A

E-07B

F-074

F-075

F-076

F-077

F-078

F-079

F-07A

F-07B

xx

Reading the internal estimate [7:0] for core 0, channel A on the SDOUT pin

Reading the internal estimate [10:8] for core 0, channel A on the SDOUT pin

Reading the internal estimate [7:0] for core 1, channel A on the SDOUT pin

Reading the internal estimate [10:8] for core 1, channel A on the SDOUT pin

Reading the internal estimate [7:0] for core 2, channel A on the SDOUT pin

Reading the internal estimate [10:8] for core 2, channel A on the SDOUT pin

Reading the internal estimate [7:0] for core 3, channel A on the SDOUT pin

Reading the internal estimate [10:8] for core 3, channel A on the SDOUT pin

Reading the internal estimate [7:0] for core 0, channel B on the SDOUT pin

Reading the internal estimate [10:8] for core 0, channel B on the SDOUT pin

Reading the internal estimate [7:0] for core 1, channel B on the SDOUT pin

Reading the internal estimate [10:8] for core 1, channel B on the SDOUT pin

Reading the internal estimate [7:0] for core 2, channel B on the SDOUT pin

Reading the internal estimate [10:8] for core 2, channel B on the SDOUT pin

Reading the internal estimate [7:0] for core 3, channel B on the SDOUT pin

Reading the internal estimate [10:8] for core 3, channel B on the SDOUT pin

Reading an

internal estimate

from both channels

(1) The address field is represented in four hex bits in a-bcd format, where a contains information about the R/W, M, P, and CH bits, and

bcd contain the actual address of the register.

80

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STEP

ZHCSE42D –APRIL 2015–REVISED APRIL 2019

Table 77. Format (16-Bit Address, 8-Bit Data) (continued)

ADDRESS

(Hex)⁽¹⁾

DATA (Hex)

COMMENT

6-069

7-069

4-004

4-003

4-002

4-001

6-000

6-001

6-004

6-005

6-008

6-009

6-00C

6-00D

7-000

7-001

7-004

7-005

7-008

7-009

7-00C

7-00D

01

61

00

05

00

xx

Enables the external correction bit located in the offset read page for channel A

Enables the external correction bit located in the offset read page for channel B

Change page to offset load page (61000500h)

Loading the external estimate [7:0] for core 0, channel A through SPI writes

Loading the external estimate [10:8] for core 0, channel A through SPI writes

Loading the external estimate [7:0] for core 1, channel A through SPI writes

Loading the external estimate [10:8] for core 1, channel A through SPI writes

Loading the external estimate [7:0] for core 2, channel A through SPI writes

Loading the external estimate [10:8] for core 2, channel A through SPI writes

Loading the external estimate [7:0] for core 3, channel A through SPI writes

Loading the external estimate [10:8] for core 3, channel A through SPI writes

Loading the external estimate [7:0] for core 0, channel B through SPI writes

Loading the external estimate [10:8] for core 0, channel B through SPI writes

Loading the external estimate [7:0] for core 1, channel B through SPI writes

Loading the external estimate [10:8] for core 1, channel B through SPI writes

Loading the external estimate [7:0] for core 2, channel B through SPI writes

Loading the external estimate [10:8] for core 2, channel B through SPI writes

Loading the external estimate [7:0] for core 3, channel B through SPI writes

Loading the external estimate [10:8] for core 3, channel B through SPI writes

Loading an

external estimate

to both channels

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9.1.5 Idle Channel Histogram

Figure 145 shows a histogram of output codes when no signal is applied at the analog inputs of the ADS54J60.

When the dc offset correction block of the device is bypassed, Figure 146 shows that the output code histogram

becomes multi-modal with as many as four peaks because the ADS54J60 is a 4-way interleaved ADC with each

ADC core having a different internal dc offset.

2500

2250

2000

1750

1500

1250

1000

750

700

600

500

400

300

200

100

0

500

250

0

32350 32450 32550 32650 32750 32850 32950 33050 33150

32740

32750

32760

32770

32780

32790

Output Code

D065

D064

Figure 146. Idle Channel Histogram

(No Signal at Analog Inputs, DC Offset Correction is Off)

Figure 145. Idle Channel Histogram

(No Signal at Analog Inputs, DC Offset Correction is On)

When the dc offset correction block is frozen (instead of being bypassed), as shown in Figure 147, the output

code histogram improves (compared to when bypassed). However, when temperature changes, the dc offset

difference among interleaving cores may increase, resulting in increased spacing between peaks in the

histogram.

3500

3000

2500

2000

1500

1000

500

0

32740

32750

32760

32770

32780

32790

Output Code

D066

Figure 147. Idle Channel Histogram

(No Signal at Analog Inputs, DC Offset Correction is Frozen)

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9.2 Typical Application

The ADS54J60 is designed for wideband receiver applications demanding excellent dynamic range over a large

input frequency range. A typical schematic for an ac-coupled receiver is shown in Figure 148.

DVDD

10 kꢀ

5 W

50 W

Driver

0.1 mF

2 pF

0.1 mF

SPI Master

GND

IOVDD GND

0.1 mF

10nF

GND

0.1 mF

AVDD3V

AVDD

AVDD3V

DVDD

100-W Differential

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

10 nF

DB2P

DB2M

IOVDD

DB1P

DB1M

DGND

DB0P

DB0M

IOVDD

SYNC

DA0M

DA0P

DGND

DA1M

DA1P

IOVDD

DA2M

DA2P

NC

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

IOVDD

10 nF

GND

NC

10 nF

VCM

0.1 mF

AGND

AVDD3V

AVDD

AGND

CLKINP

CLKINM

AGND

AVDD

AVDD3V

AGND

GND

0.1 mF

AVDD3V

GND

AVDD

0.1 mF

GND

10 nF

IOVDD

0.1 mF

GND

GND Pad

(Back Side)

GND

0.1 mF

FPGA

Low-Jitter Clock

Generator

AVDD3V

0.1 mF

GND

10 nF

GND

SYSREFP

SYSREFM

AVDD

100 W

IOVDD

10 nF

GND

AVDD

AGND

GND

10 nF

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

100-W Differential

AVDD3V

DVDD

AVDD

AVDD3V

0.1 mF

GND

0.1 mF

IOVDD GND

0.1 mF

GND

5 W

50 W

Driver

0.1 mF

2 pF

GND

NOTE: GND = AGND and DGND connected in the PCB layout.

Figure 148. AC-Coupled Receiver

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Typical Application (continued)

9.2.1 Design Requirements

9.2.1.1 Transformer-Coupled Circuits

Typical applications involving transformer-coupled circuits are discussed in this section. To achieve good phase

and amplitude balances at the ADC inputs, surface-mount transformers can be used (for example, for

frequencies up to 300 MHz, ADT1-1WT or WBC1-1 can be used and for higher input frequencies TC1-1-13M+

can be used). When designing dc driving circuits, the ADC input impedance must be considered. Figure 149 and

Figure 150 show the impedance (Z_IN= R_IN|| C_IN) across the ADC input pins.

5

4.75

4.5

1.4

1.2

1

4.25

4

0.8

0.6

0.4

0.2

0

3.75

3.5

3.25

3

2.75

2.5

2.25

0

100 200 300 400 500 600 700 800 900 1000

0

100 200 300 400 500 600 700 800 900 1000

Frequency (MHz)

D103

D102

Figure 149. R_INvs Input Frequency

Figure 150. C_INvs Input Frequency

By using the simple drive circuit of Figure 151, uniform performance can be obtained over a wide frequency

range. The buffers present at the analog inputs of the device help isolate the external drive source from the

switching currents of the sampling circuit.

0.1 ꢁF

T2

CHx_INP

T1

5 ꢀ

0.1 ꢁF

25 ꢀ

0.1 ꢁF

R_IN

C_IN

25 ꢀ

5 ꢀ

0.1 ꢁF

CHx_INM

1:1

Device

Figure 151. Input Drive Circuit

9.2.2 Detailed Design Procedure

For optimum performance, the analog inputs must be driven differentially. This architecture improves common-

mode noise immunity and even-order harmonic rejection. A small resistor (5 Ω to 10 Ω) in series with each input

pin is recommended to damp out ringing caused by package parasitics, as shown in Figure 151.

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Typical Application (continued)

9.2.3 Application Curves

Figure 152 and Figure 153 show the typical performance at 170 MHz and 230 MHz, respectively.

0

-20

0

-20

-40

-60

-80

-100

-120

-100

-120

0

100

200

300

400

500

0

100

200

300

400

500

Input Frequency (MHz)

D003

D004

SNR = 69.8 dBFS; SFDR = 88 dBc;

SNR = 68.9 dBFS; SFDR = 85 dBc;

IL spur = 86 dBc; non HD2, HD3 spur = 89 dBc

IL spur = 85 dBc; non HD2, HD3 spur = 86 dBc

Figure 152. FFT for 170-MHz Input Signal

Figure 153. FFT for 230-MHz Input Signal

10 Power Supply Recommendations

The device requires a 1.15-V nominal supply for IOVDD, a 1.9-V nominal supply for DVDD, a 1.9-V nominal

supply for AVDD, and a 3.0-V nominal supply for AVDD3V. For detailed information regarding the operating

voltage minimum and maximum specifications of different supplies, see the Recommended Operating Conditions

table.

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10.1 Power Sequencing and Initialization

Figure 154 shows the suggested power-up sequencing for the device. Note that the 1.15-V IOVDD supply must

rise before the 1.9-V DVDD supply. If the 1.9-V DVDD supply rises before the 1.15-V IOVDD supply, then the

internal default register settings may not load properly. The other supplies (the 3-V AVDD3V and the 1.9-V

AVDD), can come up in any order during the power sequence. The power supplies can ramp up at any rate and

there is no hard requirement for the time delay between IOVDD ramp up to DVDD ramp-up (can be in orders of

microseconds but is recommend to be a few milliseconds).

IOVDD = 1.15 V

DVDD = 1.9 V

AVDD = 1.9 V

AVDD = 3 V

Figure 154. Power Sequencing for the ADS54Jxx Family of Devices

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ZHCSE42D –APRIL 2015–REVISED APRIL 2019

11 Layout

11.1 Layout Guidelines

The device evaluation module (EVM) layout can be used as a reference layout to obtain the best performance. A

layout diagram of the EVM top layer is provided in Figure 155. A complete layout of the EVM is available at the

ADS54J60 EVM folder. Some important points to remember during board layout are:

•

Analog inputs are located on opposite sides of the device pinout to ensure minimum crosstalk on the package

level. To minimize crosstalk onboard, the analog inputs must exit the pinout in opposite directions, as

illustrated in the reference layout of Figure 155 as much as possible.

In the device pinout, the sampling clock is located on a side perpendicular to the analog inputs in order to

minimize coupling between them. This configuration is also maintained on the reference layout of Figure 155

as much as possible.

Keep digital outputs away from the analog inputs. When these digital outputs exit the pinout, the digital output

traces must not be kept parallel to the analog input traces because this configuration can result in coupling

from the digital outputs to the analog inputs and degrade performance. All digital output traces to the receiver

[such as a field-programmable gate array (FPGA) or an application-specific integrated circuit (ASIC)] must be

matched in length to avoid skew among outputs.

•

At each power-supply pin (AVDD, DVDD, or AVDDD3V), keep a 0.1-µF decoupling capacitor close to the

device. A separate decoupling capacitor group consisting of a parallel combination of 10-µF, 1-µF, and 0.1-µF

capacitors can be kept close to the supply source.

NOTE

The PDN and SDOUT traces must be routed away from the analog input traces. When the

PDN and SDOUT pins are programmed to carry OVR information, the proximity of these

pins to the analog input traces may result in degradation of ADC performance because of

coupling. For best performance, the PDN and SDOUT traces must not overlap or cross

the path of the analog input traces even if routed on different layers of the PCB.

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11.2 Layout Example

Figure 155. ADS54J60 EVM layout

88

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ZHCSE42D –APRIL 2015–REVISED APRIL 2019

12 器件和文档支持

12.1 文档支持

12.1.1 相关文档

请参阅如下相关文档：

•

德州仪器 (TI)，《ADS54J20 双通道 12 位 1.0GSPS 模数转换器》数据表

德州仪器 (TI)，《ADS54J40 双通道 14 位 1.0GSPS 模数转换器》数据表

德州仪器 (TI)，《ADS54J42 双通道 14 位 625MSPS 模数转换器》数据表

德州仪器 (TI)，《具有集成 DDC 的 ADS54J66 四通道 14 位 500MSPS ADC》数据表

德州仪器 (TI)，《ADS54J69 双通道 16 位 500MSPS 模数转换器》数据表

德州仪器 (TI)，《ADS54J60EVM 用户指南》

12.2 接收文档更新通知

要接收文档更新通知，请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我进行注册，即可每周接收产

品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

12.3 社区资源

下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，

并且不一定反映 TI 的观点；请参阅 TI 的《使用条款》。

TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration

among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help

solve problems with fellow engineers.

Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and

contact information for technical support.

12.4 商标

E2E is a trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

12.5 静电放电警告

ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可

能会损坏集成电路。

ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可

能会导致器件与其发布的规格不相符。

12.6 术语表

SLYZ022 — TI 术语表。

这份术语表列出并解释术语、缩写和定义。

13 机械、封装和可订购信息

以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且

不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。

89

PACKAGE MATERIALS INFORMATION

www.ti.com

5-Jan-2022

TRAY

Chamfer on Tray corner indicates Pin 1 orientation of packed units.

*All dimensions are nominal

Device

Package Package Pins SPQ Unit array

Max

matrix temperature

(°C)

L (mm)

W

K0

P1

CL

CW

Name

Type

(mm) (µm) (mm) (mm) (mm)

ADS54J60IRMP

RMP

VQFNP

72

168

8 X 21

150

315 135.9 7620 14.65

11

11.95

Pack Materials-Page 1

PACKAGE OUTLINE

RMP0072A

VQFN - 0.9 mm max height

SCALE 1.700

VQFN

10.1

9.9

A

B

PIN 1 ID

10.1

9.9

0.9 MAX

0.05

0.00

C

SEATING PLANE

0.08 C

(0.2)

4X (45 X0.42)

19

36

18

37

SYMM

4X

8.5

8.5 0.1

PIN 1 ID

(R0.2)

1

54

0.30

0.18

72X

72

55

68X 0.5

SYMM

0.5

0.3

0.1

C B

A

72X

0.05

C

4221047/B 02/2014

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

www.ti.com

EXAMPLE BOARD LAYOUT

RMP0072A

VQFN - 0.9 mm max height

VQFN

(

8.5)

SYMM

72X (0.6)

SEE DETAILS

55

72

1

54

72X (0.24)

(0.25) TYP

SYMM

(9.8)

(1.315) TYP

68X (0.5)

(

0.2) TYP

VIA

37

18

19

36

(1.315) TYP

(9.8)

LAND PATTERN EXAMPLE

SCALE:8X

0.07 MAX

ALL AROUND

0.07 MIN

ALL AROUND

SOLDER MASK

OPENING

METAL

SOLDER MASK

OPENING

METAL

NON SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4221047/B 02/2014

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see QFN/SON PCB application report

in literature No. SLUA271 (www.ti.com/lit/slua271).

www.ti.com

EXAMPLE STENCIL DESIGN

RMP0072A

VQFN - 0.9 mm max height

VQFN

(9.8)

72X (0.6)

(1.315) TYP

72

55

1

54

72X (0.24)

(1.315)

TYP

(0.25) TYP

SYMM

(9.8)

(1.315)

TYP

68X (0.5)

METAL

TYP

37

18

(

0.2) TYP

VIA

19

36

36X ( 1.115)

(1.315) TYP

SYMM

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD

62% PRINTED SOLDER COVERAGE BY AREA

SCALE:8X

4221047/B 02/2014

NOTES: (continued)

5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

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型号：	ADS54J60
厂家：	TEXAS INSTRUMENTS
描述：	双通道、16 位、1.0GSPS 模数转换器 (ADC) 转换器模数转换器
文件：	总96页 (文件大小：5036K)
中文：	中文翻译
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