ADS54J54 [TI]
四通道、14 位、500MSPS 模数转换器 (ADC);型号: | ADS54J54 |
厂家: | TEXAS INSTRUMENTS |
描述: | 四通道、14 位、500MSPS 模数转换器 (ADC) 转换器 模数转换器 |
文件: | 总67页 (文件大小:3535K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Support &
Community
Product
Folder
Order
Now
Tools &
Software
Technical
Documents
ADS54J54
ZHCSD79A –JANUARY 2015–REVISED AUGUST 2019
ADS54J54 四通道 14 位 500MSPS ADC
1 特性
3 说明
1
•
•
•
4 通道、14 位 500MSPS 模数转换器 (ADC)
ADS54J54 是一款低功耗、高带宽 14 位、500MSPS
四通道模数转换器 (ADC)。该器件支持 JESD204B 串
行接口,数据传输速率高达 5Gbps,每个 ADC 可支持
1 或 2 条通道。已缓冲模拟输入在大大减少采样保持
毛刺脉冲能量的同时,在宽频率范围内提供统一的输入
阻抗。采样时钟分频器可实现更灵活的系统时钟架构设
计。ADS54J54 以超低功耗在宽输入频率范围内提供
出色的无杂散动态范围 (SFDR)。该器件具有可选 2x
抽取滤波器,可提供高通或低通滤波器两种模式。
模拟输入缓冲器,具有高阻抗输入
灵活的输入时钟缓冲器,支持 1 分频、2 分频和 4
分频
•
•
1.25VPP 差分满量程输入
JESD204B 串行接口
–
–
–
符合子类 1,速率高达 5Gbps
每个 ADC 一条通道,速率高达 250Msps
每个 ADC 两条通道,速率高达 500Msps
•
•
64 引脚四方扁平无引线 (QFN) 封装 (9mm x 9mm)
器件信息(1)
主要规格:
器件型号
ADS54J54
封装
封装尺寸(标称值)
–
–
–
–
–
功率耗散:875mW/ch
输入带宽 (3dB):900MHz
孔径抖动:98fs rms
通道隔离:85dB
VQFN (64)
9.00mm x 9.00mm
(1) 如需了解所有可用封装,请参阅数据表末尾的可订购产品附
录。
简化原理图
ƒin = 170MHz、1.25 VPP
、
单通道、2x 抽取滤波器、–1dBFS 条件下的性
能
OVRA
Digital Block
14-bit
ADC
Optional 2x
Decimination
JESD204B
JESD204B
INAP/M
INBP/M
DA[0,1]P/M
–
–
信噪比 (SNR):67.2dBFS
Digital Block
Optional 2x
Decimination
14-bit
ADC
无杂散动态范围 (SFDR):85dBc
(HD2,HD3);95dBFS(非
HD2,HD3)
DB[0,1]P/M
OVRB
SYSREFABP/M
CLKINP/M
SYNCbAB
SYNCbCD
–
ƒin = 370MHz、1.25 VPP
、
Divide by
1, 2, 4
PLL
x10/x20
双通道、无抽取滤波器、–1dBFS 条件下的性能
SYSREFCDP/M
–
–
SNR:64.7dBFS
OVRC
SFDR:75dBc(HD2,HD3);83dBFS
(非 HD2,HD3)
Digital Block
Optional 2x
Decimination
14-bit
ADC
JESD204B
JESD204B
DC[0,1]P/M
INCP/M
Digital Block
Optional 2x
Decimination
2 应用
14-bit
ADC
INDP/M
VCM
DD[0,1]P/M
OVRD
•
多载波、多模式、多频带蜂窝接收器
Common
Mode
–
TDD-LTE、FDD-LTE、CDMA、WCMDA、
CMDA2k 和 GSM
•
•
•
•
•
•
•
•
•
•
微波回程连线
无线中继器
分布式天线系统 (DAS)
无线宽带
超宽带软件定义无线电
数据采集
测试和测量仪表
信号智能和干扰
雷达和卫星系统
电缆基础设施
1
本文档旨在为方便起见,提供有关 TI 产品中文版本的信息,以确认产品的概要。 有关适用的官方英文版本的最新信息,请访问 www.ti.com,其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前,请务必参考最新版本的英文版本。
English Data Sheet: SLASE67
ADS54J54
ZHCSD79A –JANUARY 2015–REVISED AUGUST 2019
www.ti.com.cn
目录
7.1 Overview ................................................................. 23
7.2 Functional Block Diagram ....................................... 23
7.3 Feature Description................................................. 24
7.4 Device Functional Modes........................................ 33
7.5 Programming........................................................... 35
7.6 Register Maps......................................................... 36
Application and Implementation ........................ 53
8.1 Application Information............................................ 53
8.2 Typical Application .................................................. 53
8.3 Design Requirements.............................................. 54
8.4 Detailed Design Procedure ..................................... 54
8.5 Application Curves .................................................. 55
Power Supply Recommendations...................... 56
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 5
6.1 Absolute Maximum Ratings ...................................... 5
6.2 ESD Ratings.............................................................. 5
6.3 Recommended Operating Conditions....................... 5
6.4 Thermal Information.................................................. 5
6.5 Electrical Characteristics........................................... 7
8
9
6.6 Electrical Characteristics: 250 MSPS Output, 2x
Decimation Filter ........................................................ 8
10 Layout................................................................... 56
10.1 Layout Guidelines ................................................. 56
10.2 Layout Example .................................................... 56
11 器件和文档支持 ..................................................... 58
11.1 商标....................................................................... 58
11.2 静电放电警告......................................................... 58
11.3 Glossary................................................................ 58
12 机械、封装和可订购信息....................................... 58
6.7 Electrical Characteristics: 500 MSPS Output............ 9
6.8 Electrical Characteristics: Sample Clock Timing
Characteristics ........................................................... 9
6.9 Electrical Characteristics: Digital Outputs............... 10
6.10 Timing Requirements............................................ 10
6.11 Reset Timing......................................................... 10
6.12 Typical Characteristics.......................................... 13
Detailed Description ............................................ 23
7
4 修订历史记录
Changes from Original (January 2015) to Revision A
Page
•
•
Added list item in Device and Register Initialization: "Write the data in 表 5 to.."................................................................ 33
Added 表 5 ........................................................................................................................................................................... 33
2
Copyright © 2015–2019, Texas Instruments Incorporated
ADS54J54
www.ti.com.cn
ZHCSD79A –JANUARY 2015–REVISED AUGUST 2019
5 Pin Configuration and Functions
ADS54J54
RGC 64 Pin Package
Top View
SDOUT
SDATA
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
SYNCbABM
SYNCbABP
DB0P
2
SCLK
3
SDENb
4
DB0M
SYSREFABM
SYSREFABP
AVDDC
5
IOVDD
6
DB1P
7
DB1M
CLKINM
8
PLLVDD
PLLVDD
DD1M
Thermal
Pad
CLKINP
9
AVDDC
10
11
12
13
14
15
16
SYSREFCDP
SYSREFCDM
SRESETb
ENABLE
VREF
DD1P
IOVDD
DD0
DD0P
SYNCbCDP
SYNCbCDM
VCM
Not to scale
Pin Functions
PIN
I/O
DESCRIPTION
NAME
NO.
INPUT OR REFERENCE
INAP, INAM
INBP, INBM
INCP, INCM
INDP, INDM
VCM
63, 62
I
I
Differential analog input for channel A
Differential analog input for channel B
Differential analog input for channel C
Differential analog input for channel D
58, 59
18, 19
23, 22
16
I
I
O
O
Common mode output voltage to bias analog inputs, Vcm = 2.0 V
VREF
15
Voltage reference output. A 0.1-µF bypass capacitor to ground close to the pin is recommended
CLOCK/SYNC
CLKINP,
CLKINM
9, 8
6, 5
I
I
I
Differential clock input for channel
SYSREFABP,
SYSREFABM
LVDS input with internal 100-Ω termination. External SYSREF input for channels A, B, C, and D
SYSREFCDP,
SYSREFCDM
LVDS input with internal 100-Ω termination. External SYSREF input for channels C and D if output
rate of channel A/B is different from channel C/D.
11, 12
Copyright © 2015–2019, Texas Instruments Incorporated
3
ADS54J54
ZHCSD79A –JANUARY 2015–REVISED AUGUST 2019
www.ti.com.cn
Pin Functions (continued)
PIN
I/O
DESCRIPTION
NAME
NO.
CONTROL OR SERIAL
Chip enable. Active high. Power down functionality can be configured through SPI register setting
and exercised using the ENABLE pin. Internal 51-kΩ pulldown resistor.
ENABLE
14
I
I
SCLK
3
2
4
1
Serial interface clock input
SDATA
SDENb
SDOUT
I/O Bidirectional serial data in 3-pin mode. In 4-pin interface, the SDATA pin is an input only.
I
Serial interface enable
O
Serial interface data output
Hardware reset. Active low. Initializes internal registers during high to low transition. This pin has
an internal 51-kΩ pullup resistor.
SRESETb
13
I
DATA OUTPUT INTERFACE
DA[0,1]P,
55, 54, 52, 51
DA[0,1]M
O
O
O
O
JESD204B output interface for channel A
JESD204B output interface for channel B
JESD204B output interface for channel C
JESD204B output interface for channel D
DB[0,1]P,
46, 45, 43, 42
DB[0,1]M
DC[0,1]P,
26, 27, 29, 30
DC[0,1]M
DD[0,1]P,
35, 36, 38, 39
DD[0,1]M
OVRA
OVRB
OVRC
OVRD
50
49
31
32
I/O Fast over-range indicator channel A.
Fast over-range indicator channel B.
I/O Fast over-range indicator channel C.
O
O
Fast over-range indicator channel D.
SYNCbABP,
SYNCbABM
47, 48
34, 33
I
SYNCb input for JESD204B interface for channel A/B, internal 100-Ω termination
SYNCbCDP,
SYNCbCDM
I
SYNCb input for JESD204B interface for channel C/D, internal 100-Ω termination
POWER SUPPLY
AVDDC
7, 10
I
I
I
I
I
I
I
Clock 1.8-V power supply
Analog 1.9-V power supply
Analog 3.3-V power supply
Digital 1.8-V power supply
Ground
AVDD18
AVDD33
DVDD
21, 24, 57, 60
17, 20, 61, 64
25, 56
GND
PowerPAD™
28, 37, 44, 53
40, 41
IOVDD
JESD204B output interface 1.8-V power supply
PLL 1.8-V power supply
PLLVDD
4
Copyright © 2015–2019, Texas Instruments Incorporated
ADS54J54
www.ti.com.cn
ZHCSD79A –JANUARY 2015–REVISED AUGUST 2019
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature (unless otherwise noted)(1)
MIN
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–40
MAX
UNIT
AVDD33
AVDD18
3.6
2.1
AVDDC
2.1
Supply voltage
DVDD
V
2.1
IOVDD
PLLVDD
2.1
2.1
Voltage between AGND and DGND
0.3
V
V
INAP, INBP, INCP, INDP, INAM, INBM, INCM, INDM
3
CLKINP, CLKINM
AVDD18 + 0.3 V
AVDD18 + 0.3 V
AVDD18 + 0.3 V
DVDD + 0.5 V
85
Voltage applied to input pins SYNCbABP, SYNCbABM, SYNCbCDP, SYNCbCDM
SYSREFABP, SYSREFABM, SYSREFCDP, SYSREFCDM
SCLK, SDENb, SDATA, SRESETb, ENABLE
Operating free-air temperature, TA
ºC
ºC
°C
(2)
Operating junction temperature, TJ
125
Storage temperature, Tstg
–65
150
(1) Stresses beyond those listed as absolute maximum ratings may cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions beyond those indicated as recommended operating conditions is
not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Prolonged use at this junction temperature may increase the device failure-in-time (FIT) rate.
6.2 ESD Ratings
VALUE
±1000
±500
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
V(ESD)
Electrostatic discharge
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
250
14
NOM
MAX
500
14
UNIT
MSPS
bits
ADC clock frequency
Resolution
AVDD33
3.15
1.8
1.7
1.7
1.7
1.7
–40
3.3
1.9
1.8
1.8
1.8
1.8
3.45
2
AVDD18
AVDDC
1.9
1.9
1.9
1.9
85
Supply
V
DVDD
IOVDD
PLLVDD
TA
TJ
Operating free-air temperature
Operating junction temperature
°C
°C
125
6.4 Thermal Information
Thermal Metric(1)
RGC (64 PINS)
UNIT
°C/W
RΘJA
Junction-to-ambient thermal resistance
23.5
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
Copyright © 2015–2019, Texas Instruments Incorporated
5
ADS54J54
ZHCSD79A –JANUARY 2015–REVISED AUGUST 2019
www.ti.com.cn
Thermal Information (continued)
Thermal Metric(1)
RGC (64 PINS)
UNIT
°C/W
°C/W
°C/W
°C/W
°C/W
RΘJC(top)
RΘJB
Junction-to-case, top
7.0
2.6
0.1
2.6
0.3
Junction-to-board thermal resistance
Junction-to-top of package
φJT
φJB
Junction-to-board characterization parameter
Junction-to-case, bottom
RΘJC(bot)
6
Copyright © 2015–2019, Texas Instruments Incorporated
ADS54J54
www.ti.com.cn
ZHCSD79A –JANUARY 2015–REVISED AUGUST 2019
6.5 Electrical Characteristics
Typical values at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 85°C, ADC sampling rate = 500 MSPS, 50%
clock duty cycle, AVDD33 = 3.3 V; AVDD18 = 1.9 V; AVDDC, DVDD, IOVDD, PLLVDD = 1.8 V, –1-dBFS differential input,
unless otherwise noted.
PARAMETER
POWER SUPPLY
TEST CONDITIONS
MIN
TYP
MAX UNIT
IAVDD33
IAVDD18
IAVDDC
3.3-V analog supply current
1.9-V analog supply current
1.8-V clock supply current
500
320
18
mA
mA
mA
4-channel decimation filter
323
324
4-channel bypass digital mode
IDVDD
1.8-V digital supply current
mA
2-channel decimation filter, 2-channel bypass digital
mode
324
2 lanes per ADC
1 lane per ADC
373
185
42
IIOVDD
I/O voltage supply current
PLL voltage supply current
mA
IPLLVDD
mA
3.7
4-channel bypass digital mode
4-channel decimation filter
3.46
3.34
3.27
Pdis
Total power dissipation
W
4-channel decimation filter, 1 lane per ADC
2-channel decimation filter, 2-channel bypass digital
mode
3.51
Deep sleep mode power
791
1.4
1.68
8
mW
ms
W
Wake-up time from deep sleep mode
Light sleep mode power
SNR > 60 dB
SNR > 60 dB
Wake-up time from light sleep mode
ANALOG INPUTS
µs
Differential input full-scale
1
1.25
1.5 Vpp
V
VCM
±
Input common mode voltage
50 mV
Input
Differential at DC
resistance
1
kΩ
Input
Each input to GND
capacitance
2.75
pF
VCM
Common mode voltage output
2.18
900
V
Analog input bandwidth (–3 dB)
MHz
LSB
LSB
INL
Integral nonlinearity
Dynamic nonlinearity
±3
DNL
–1
±0.9
Gain error
±2.24%
±1.91
Offset error
mV
dB
CHANNEL-TO-CHANNEL ISOLATION
Near channel
Far channel
ƒIN = 170 MHz
ƒIN = 170 MHz
85
95
Crosstalk(1)
CLOCK INPUT
Input clock frequency
Input clock amplitude
Input clock duty cycle
Internal clock biasing
250
0.4
2000(2) MHz
1.5
50%
0.9
Vpp
45%
55%
V
(1) Crosstalk is measured with a –1-dBFS input signal on aggressor channel and no input on victim channel.
(2) CLK / 4 mode
Copyright © 2015–2019, Texas Instruments Incorporated
7
ADS54J54
ZHCSD79A –JANUARY 2015–REVISED AUGUST 2019
www.ti.com.cn
6.6 Electrical Characteristics: 250 MSPS Output, 2x Decimation Filter
Typical values at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 85°C, ADC sampling rate = 500 MSPS, 50%
clock duty cycle, AVDD33 = 3.3 V; AVDD18 = 1.9 V; AVDDC, DVDD, IOVDD, PLLVDD = 1.8 V, –1-dBFS differential input,
unless otherwise noted.
PARAMETER
TEST CONDITIONS
ƒIN = 10 MHz
MIN
TYP
68.3
68.2
67.2
67.6
66.8
85
MAX
UNIT
ƒIN = 100 MHz
ƒIN = 170 MHz
ƒIN = 310 MHz
ƒIN = 450 MHz
ƒIN = 10 MHz
SNR
HD2
HD3
Signal-to-noise ratio
dBFS
ƒIN = 100 MHz
ƒIN = 170 MHz
ƒIN = 310 MHz
ƒIN = 450 MHz
ƒIN = 10 MHz
85
Second harmonic distortion
Third harmonic distortion
85
dBc
dBc
85
75
85
ƒIN = 100 MHz
ƒIN = 170 MHz
ƒIN = 310 MHz
ƒIN = 450 MHz
ƒIN = 10 MHz
85
85
85
85
95
ƒIN = 100 MHz
ƒIN = 170 MHz
ƒIN = 310 MHz
ƒIN = 450 MHz
FIN = 169 and 171 MHz
95
SFDR
(Non-HD2,
Non-HD3)
Spur free dynamic range
(excluding HD2 and HD3)
95
dBc
90
85
IMD3
2F1-F2, 2F2-F1, Ain = –7 dBFS
93
dBFS
8
Copyright © 2015–2019, Texas Instruments Incorporated
ADS54J54
www.ti.com.cn
ZHCSD79A –JANUARY 2015–REVISED AUGUST 2019
6.7 Electrical Characteristics: 500 MSPS Output
Typical values at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 85°C, ADC sampling rate = 500 MSPS, 50%
clock duty cycle, AVDD33 = 3.3 V; AVDD18 = 1.9 V; AVDDC, DVDD, IOVDD, PLLVDD = 1.8 V, –1-dBFS differential input,
unless otherwise noted.
PARAMETER
TEST CONDITIONS
ƒIN = 10 MHz
MIN
TYP
65.3
65.2
64.9
64.7
64.6
85
MAX
UNIT
ƒIN = 100 MHz
SNR
HD2
HD3
Signal-to-Noise Ratio Bypass Digital Mode (14 bit) ƒIN = 170 MHz
61
dBFS
ƒIN = 370 MHz
ƒIN = 450 MHz
ƒIN = 10 MHz
ƒIN = 100 MHz
85
Second Harmonic Distortion
Third Harmonic Distortion
ƒIN = 170 MHz
ƒIN = 370 MHz
ƒIN = 450 MHz
ƒIN = 10 MHz
70
70
70
85
dBc
dBc
75
75
85
ƒIN = 100 MHz
ƒIN = 170 MHz
ƒIN = 370 MHz
ƒIN = 450 MHz
ƒIN = 10 MHz
85
85
85
85
85
ƒIN = 100 MHz
ƒIN = 170 MHz
ƒIN = 370 MHz
ƒIN = 450 MHz
fIN = 169 and 171 MHz
85
SFDR
(Non-HD2,
Non-HD3)
Spur Free Dynamic Range
(excluding HD2 and HD3)
85
dBFS
dBFS
83
83
IMD3
2F1-F2, 2F2-F1, Ain = –7 dBFS
87
6.8 Electrical Characteristics: Sample Clock Timing Characteristics
Typical values at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 85°C, ADC sampling rate = 500 MSPS, 50%
clock duty cycle, AVDD33 = 3.3 V; AVDD18 = 1.9 V; AVDDC, DVDD, IOVDD, PLLVDD = 1.8 V, –1 dBFS differential input,
unless otherwise noted.
PARAMETER
MIN
TYP
98
38
6
MAX
UNIT
Aperture jitter, RMS
Data latency
fs rms
Sample clock cycles
ns
Fast over-range (OVR) latency
Clock aperture delay
tPDI
1.1
Copyright © 2015–2019, Texas Instruments Incorporated
9
ADS54J54
ZHCSD79A –JANUARY 2015–REVISED AUGUST 2019
www.ti.com.cn
6.9 Electrical Characteristics: Digital Outputs
The DC specifications refer to the condition where the digital outputs are not switching, but are permanently at a valid logic
level 0 or 1. AVDD33 = 3.3 V; AVDD18 = 1.9 V; AVDDC, DVDD, IOVDD, PLLVDD = 1.8 V.
PARAMETER
DIGITAL OUTPUTS: JESD204B INTERFACE (DA[0,1], DB[0,1], DC[0,1], DD[0,1])
Output differential voltage, |VOD|
MIN
TYP
MAX
UNIT
450
577
45
50
2
750
mV
mA
Ω
Transmitter terminals shorted to any voltage between
Transmitter short circuit current
–0.25 and 1.45 V
Single ended output impedance
Output capacitance inside the device, from either
Output capacitance
output to ground
pF
Unit interval, UI
Rise and fall times
Output jitter
5.0 Gbps
200
110
57
ps
ps
ps
Serial output data rate
5.0
Gbps
6.10 Timing Requirements
MIN
TYP
MAX
UNIT
DIGITAL INPUTS: SRESETb, SCLK, SDENb, SDATA, ENABLE, OVRA, OVRC, SYSREFCDP, SYSREFCDM
High-level input voltage
Low-level input voltage
High-level input current
Low-level input current
Input capacitance
1.2
V
All digital inputs support 1.8-V and 3.3-V logic
levels
0.4
V
50
–50
4
µA
µA
pF
DIGITAL OUTPUTS: SDOUT, OVRA, OVRB, OVRC, OVRD
High-level output voltage
Low-level output voltage
DIGITAL INPUTS:
ILoad = –100 µA
DVDD – 0.2
DVDD
V
V
0.2
SYNCbABP/M, SYNCbCDP/M, SYSREFABP/M, SYSREFCDP/M
Input voltage VID
250
0.4
350
0.9
450
1.4
mV
V
Input common mode voltage VCM
tS_SYSREFxx
tH_SYSREFxx
Referenced to rising edge of input clock
100
100
ps
ps
Referenced to rising edge of input clock
6.11 Reset Timing
PARAMETER
TEST CONDITIONS
Delay from power up to active-low RESET pulse
Active-low RESET pulse duration
MIN
3
TYP
MAX
UNIT
ms
ns
t1
t2
t3
Power-on delay
Reset pulse duration
Register write delay
20
Delay from RESET disable to SDENb active
100
ns
10
版权 © 2015–2019, Texas Instruments Incorporated
ADS54J54
www.ti.com.cn
ZHCSD79A –JANUARY 2015–REVISED AUGUST 2019
Power Supplies
t1
SRESETb
SDENb
t2
t3
图 1. Reset Timing Diagram
N + 1
N + 2
N
SAMPLE
tPD
Data Latency: 74 Clock Cycles
CLKINM
CLKINP
DA0P/M
DB0P/M
DC0P/M
DD0P/M
D
20
D
1
D
20
SAMPLE N œ 1
SAMPLE N
SAMPLE N + 1
A. tPD is the propagation delay from sample clock input edge to serial data output transition
图 2. Timing Diagram: 250 MSPS Output Data Rate
版权 © 2015–2019, Texas Instruments Incorporated
11
ADS54J54
ZHCSD79A –JANUARY 2015–REVISED AUGUST 2019
www.ti.com.cn
N +
2
N + 1
N
N + 3
SAMPLE
tPD
Data Latency: 38 Clock Cycles
CLKINM
CLKINP
DA0P/M
DB0P/M
DC0P/M
DD0P/M
D
20
D
D
D
D
11 20
11 20
SAMPLE N œ 1
SAMPLE N
SAMPLE N + 1
SAMPLE N + 2
DA1P/M
DB1P/M
DC1P/M
DD1P/M
D
10
D
1
D
10
D
1
D
10
SAMPLE N œ 1
SAMPLE N
SAMPLE N + 1
SAMPLE N + 2
B. tPD is the propagation delay from sample clock input edge to serial data output transition
图 3. Timing Diagram: 500 MSPS Output Data Rate
Sample N
ts_SYSREFxx
th_SYSREFxx
CLKIN
SYSREFxx
图 4. Timing Using SYSREF (Subclass 1)
12
版权 © 2015–2019, Texas Instruments Incorporated
ADS54J54
www.ti.com.cn
ZHCSD79A –JANUARY 2015–REVISED AUGUST 2019
6.12 Typical Characteristics
Typical values at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 85°C, Device clock frequency = 500 MHz,
Output sample data rate = 5Gbps, 50% Device clock duty cycle, AVDD33 = 3.3 V, AVDD18 = 1.9 V, AVDDC = 1.8 V, IOVDD
= 1.8 V, PLLVDD = 1.8 V, DVDD = 1.8 V, –1 dBFS differential input, unless otherwise noted, FFT sample size = 32768.
0
-20
0
-20
-40
-40
-60
-60
-80
-80
-100
-120
-100
-120
0
25
50
75
100
125
0
25
50
75
100
125
Frequency (MHz)
1-lane 2x decimation
SNR = 65.29 dBFS
Frequency (MHz)
1-lane 2x decimation
SNR = 65.40 dBFS
D001
D002
Fin = 10 MHz
Ain = –1 dBFS
SFDR = 84.72 dBc
Fin = 100 MHz
Ain = –1 dBFS
SFDR = 82.50 dBc
图 5. FFT 10 MHz
图 6. FFT 100 MHz
0
-20
0
-20
-40
-40
-60
-60
-80
-80
-100
-100
-120
0
-120
0
25
50
75
100
125
25
50
75
100
125
Frequency (MHz)
1-lane 2x decimation
SNR = 65.34 dBFS
Frequency (MHz)
1-lane 2x decimation
SNR = 65.16 dBFS
D003
D004
Fin = 170 MHz
Ain = –1 dBFS
SFDR = 91.62 dBc
Fin = 230 MHz
Ain = –1 dBFS
SFDR = 76.83 dBc
图 7. FFT 170 MHz
图 8. FFT 230 MHz
0
-20
96
93
90
87
84
81
78
75
72
69
66
63
-40
-60
-80
-100
-120
60
65
70
75
80
85
90
95
100
0
100 200 300 400 500 600 700 800 900 1000
Fin (MHz)
Frequency (MHz)
D005
D0086
Fin = 230 MHz
1-lane 2x decimation
SNR = 65.16 dBFS
Ain = –1 dBFS
SFDR = 76.83 dBc
1-lane 2x decimation
Ain = –1 dBFS
图 9. 2-Tone FFT
图 10. SFDR vs Frequency
版权 © 2015–2019, Texas Instruments Incorporated
13
ADS54J54
ZHCSD79A –JANUARY 2015–REVISED AUGUST 2019
www.ti.com.cn
Typical Characteristics (接下页)
Typical values at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 85°C, Device clock frequency = 500 MHz,
Output sample data rate = 5Gbps, 50% Device clock duty cycle, AVDD33 = 3.3 V, AVDD18 = 1.9 V, AVDDC = 1.8 V, IOVDD
= 1.8 V, PLLVDD = 1.8 V, DVDD = 1.8 V, –1 dBFS differential input, unless otherwise noted, FFT sample size = 32768.
110
105
100
95
70.0
68.0
66.0
64.0
62.0
-40èC
0èC
25èC
55èC
85èC
90
85
80
75
0
100 200 300 400 500 600 700 800 900 1000
Fin (MHz)
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
Input Amplitude (dBFS)
D007
D008
1-lane 2x decimation
Ain = –1 dBFS
1-lane 2x decimation
Fin = 170 MHz
图 11. SNR vs. Frequency
图 12. SFDR vs. Amplitude
71
70
69
68
67
66
95
90
85
80
75
70
65
60
55
50
45
40
-40èC
0èC
25èC
55èC
85èC
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
1.5
1.7
1.9
2.1
2.3
2.5
Input Amplitude (dBFS)
VCM (V)
D009
D010
1-lane 2x decimation
Fin = 170 MHz
1-lane 2x decimation
Fin = 170 MHz
图 13. SNR vs. Amplitude
图 14. SFDR vs. VCM
70
69
68
67
66
65
64
63
62
61
60
100
95
90
85
80
75
70
VREF=1.35V
VREF=1.5V
VREF=1.15V
VREF=1.0V
1.5
1.7
1.9
2.1
2.3
2.5
0
100 200 300 400 500 600 700 800 900 1000
Input Frequency (MHz)
VCM (V)
D011
D012
1-lane 2x decimation
Fin = 170 MHz
1-lane 2x decimation
Ain = –1 dBFS
图 15. SNR vs VCM
图 16. SFDR vs. VREF
14
版权 © 2015–2019, Texas Instruments Incorporated
ADS54J54
www.ti.com.cn
ZHCSD79A –JANUARY 2015–REVISED AUGUST 2019
Typical Characteristics (接下页)
Typical values at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 85°C, Device clock frequency = 500 MHz,
Output sample data rate = 5Gbps, 50% Device clock duty cycle, AVDD33 = 3.3 V, AVDD18 = 1.9 V, AVDDC = 1.8 V, IOVDD
= 1.8 V, PLLVDD = 1.8 V, DVDD = 1.8 V, –1 dBFS differential input, unless otherwise noted, FFT sample size = 32768.
94
92
90
88
86
84
82
80
78
72
70
68
66
64
62
-40èC
0èC
25èC
55èC
85èC
VREF=1.25V
VREF=1.35V
VREF=1.5V
VREF=1.15V
VREF=1.0V
0
100 200 300 400 500 600 700 800 900 1000
Input Frequency (MHz)
1.7
1.8
1.9
2.0
2.1
AVDD18 Supply Voltage (V)
D013
D0174
1-lane 2x decimation
Ain = –1 dBFS
1-lane 2x decimation
Ain = –1 dBFS
Fin = 170 MHz
图 17. SNR vs. VREF
图 18. SFDR vs. AVDD18
70
96
-40èC
0èC
25èC
55èC
85èC
-40èC
0èC
25èC
55èC
85èC
94
92
90
88
86
84
82
80
78
76
74
72
68
66
64
62
1.7
1.8
1.9
2.0
2.1
3.0
3.1
3.2
3.3
3.4
3.5
3.6
AVDD18 Supply Voltage (V)
AVDD33 Supply Voltage (V)
D015
D016
1-lane 2x decimation
Ain = –1 dBFS
Fin = 170 MHz
1-lane 2x decimation
Ain = –1 dBFS
Fin = 170 MHz
图 19. SNR vs. AVDD18
图 20. SFDR vs. AVDD33
70
94
-40èC
0èC
25èC
55èC
85èC
-40èC
92
0èC
25èC
55èC
85èC
68
66
64
62
90
88
86
84
82
80
78
3.0
3.1
3.2
3.3
3.4
3.5
3.6
1.6
1.7
1.8
1.9
2.0
AVDD33 Supply Voltage (V)
PLLVDD Supply Voltage (V)
D017
D018
1-lane 2x decimation
Ain = –1 dBFS
Fin = 170 MHz
1-lane 2x decimation
Ain = –1 dBFS
Fin = 170 MHz
图 21. SNR vs. AVDD33
图 22. SFDR vs. PLLVDD
版权 © 2015–2019, Texas Instruments Incorporated
15
ADS54J54
ZHCSD79A –JANUARY 2015–REVISED AUGUST 2019
www.ti.com.cn
Typical Characteristics (接下页)
Typical values at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 85°C, Device clock frequency = 500 MHz,
Output sample data rate = 5Gbps, 50% Device clock duty cycle, AVDD33 = 3.3 V, AVDD18 = 1.9 V, AVDDC = 1.8 V, IOVDD
= 1.8 V, PLLVDD = 1.8 V, DVDD = 1.8 V, –1 dBFS differential input, unless otherwise noted, FFT sample size = 32768.
100
90
80
70
60
50
40
30
20
70
68
66
64
-40èC
0èC
25èC
55èC
85èC
1.6
1.7
1.8
1.9
2.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
PLLVDD Supply Voltage (V)
Clock Amplitude (V peak to peak)
D019
D020
1-lane 2x decimation
Ain = –1 dBFS
Fin = 170 MHz
1-lane 2x decimation
Ain = –1 dBFS
Fin = 170 MHz
图 23. SNR vs PLLVDD
图 24. SFDR vs. Clock Amplitude
80
70
60
50
40
30
20
4.5
4.0
3.5
3.0
2.5
2x Decimation
Digital Bypass
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
250.0
300.0
350.0
400.0
450.0
500.0
550.0
Clock Amplitude (V peak to peak)
Sample Frequency (MHz)
AVDD33 = 3.3 V
Fin = 170 MHz
D021
D022
1-lane 2x decimation
Ain = –1 dBFS
Fin = 170 MHz
AVDD18 = 1.9 V
Ain = –1 dBFS
Other supplies = 1.8 V
图 25. SNR vs. Clock Amplitude
图 26. Power vs Sample Frequency
0
-10
0
-20
-20
-30
-40
-40
-50
-60
-60
-70
-80
-80
-90
-100
-110
-120
-130
-100
-120
B
A
C
D
C
D
0
25
50
75 100 125 150 175 200 225 250
Frequency (MHz)
hA
hB
o C
C t
Ch
hA
o C
D t
Ch
hB
o C
D t
Ch
hD
o C
C t
Ch
hC
o C
D t
Ch
Ch
Ch
Ch
Ch
Ch
Ch
o C
D023
D024
A to
Ch
B to
Ch
A to
A to
Ch
B to
Ch
B to
Ch
C t
Ch
Ch
2-lane no decimation
SNR = 65.27 dBFS
Ain = –1 dBFS
Fin = 10 MHz
Channel to Channel
SFDR = 86.63 dBc
1-lane 2x decimation
Ain = –1 dBFS
Fin = 170 MHz
图 28. FFT 10 MHz
图 27. Crosstalk by Channel
16
版权 © 2015–2019, Texas Instruments Incorporated
ADS54J54
www.ti.com.cn
ZHCSD79A –JANUARY 2015–REVISED AUGUST 2019
Typical Characteristics (接下页)
Typical values at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 85°C, Device clock frequency = 500 MHz,
Output sample data rate = 5Gbps, 50% Device clock duty cycle, AVDD33 = 3.3 V, AVDD18 = 1.9 V, AVDDC = 1.8 V, IOVDD
= 1.8 V, PLLVDD = 1.8 V, DVDD = 1.8 V, –1 dBFS differential input, unless otherwise noted, FFT sample size = 32768.
0
0
-20
-20
-40
-40
-60
-60
-80
-80
-100
-120
-100
-120
0
25
50
75 100 125 150 175 200 225 250
Frequency (MHz)
0
25
50
75 100 125 150 175 200 225 250
Frequency (MHz)
D025
D026
2-lane no decimation
SNR = 65.41 dBFS
Ain = –1 dBFS
Fin = 100 MHz
2-lane no decimation
SNR = 65.26 dBFS
Ain = –1 dBFS
Fin = 170 MHz
SFDR = 83.25 dBc
SFDR = 90.42 dBc
图 29. FFT 100 MHz
图 30. FFT 170 MHz
0
-20
0
-20
-40
-40
-60
-60
-80
-80
-100
-120
-100
-120
0
25
50
75 100 125 150 175 200 225 250
Frequency (MHz)
150
155
160
165
170
175
180
185
190
Frequency (MHz)
D027
D028
2-lane no decimation
SNR = 64.91 dBFS
Ain = –1 dBFS
Fin = 230 MHz
2-lane no decimation
Fin = 170 MHz
Ain = –1 dBFS
SFDR = 83.29 dBc
图 31. FFT 230 MHz
图 32. 2-Tone FFT
92
88
84
80
76
72
68
64
66.0
65.0
64.0
63.0
62.0
0
100 200 300 400 500 600 700 800 900 1000
Fin (MHz)
0
100 200 300 400 500 600 700 800 900 1000
Fin (MHz)
D02096
D030
2-lane no decimation
Ain = –1 dBFS
2-lane no decimation
Ain = –1 dBFS
图 33. SDFR vs Frequency
图 34. SNR vs Frequency
版权 © 2015–2019, Texas Instruments Incorporated
17
ADS54J54
ZHCSD79A –JANUARY 2015–REVISED AUGUST 2019
www.ti.com.cn
Typical Characteristics (接下页)
Typical values at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 85°C, Device clock frequency = 500 MHz,
Output sample data rate = 5Gbps, 50% Device clock duty cycle, AVDD33 = 3.3 V, AVDD18 = 1.9 V, AVDDC = 1.8 V, IOVDD
= 1.8 V, PLLVDD = 1.8 V, DVDD = 1.8 V, –1 dBFS differential input, unless otherwise noted, FFT sample size = 32768.
105
100
95
68
67
66
65
64
63
62
-40èC
0èC
25èC
55èC
85èC
-40èC
0èC
25èC
55èC
85èC
90
85
80
75
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
Input Amplitude (dBFS)
Input Amplitude (dBFS)
D031
D032
2-lane no decimation
Fin = 170 MHz
2-lane no decimation
Fin = 170 MHz
图 35. SFDR vs Amplitude
图 36. SNR vs Amplitude
68
67
66
65
64
63
62
61
60
95
90
85
80
75
70
65
60
55
50
45
40
1.5
1.7
1.9
2.1
2.3
2.5
1.5
1.7
1.9
2.1
2.3
2.5
VCM (V)
VCM (V)
D033
D034
2-lane no decimation
Fin = 170 MHz
2-lane no decimation
Fin = 170 MHz
图 37. SFDR vs VCM
图 38. SNR vs VCM
92
68
66
64
62
60
58
VREF=1.00V
VREF=1.15V
VREF=1.25V
VREF=1.35V
VREF=1.5V
VREF=1.00V
VREF=1.15V
VREF=1.25V
VREF=1.35V
VREF=1.50V
88
84
80
76
72
68
64
0
100 200 300 400 500 600 700 800 900 1000
Input Frequency (MHz)
0
100 200 300 400 500 600 700 800 900 1000
Input Frequency (MHz)
D035
D036
2-lane no decimation
Ain = –1 dBFS
2-lane no decimation
Ain = –1 dBFS
图 39. SFDR vs Input Frequency
图 40. SNR vs Input Frequency
18
版权 © 2015–2019, Texas Instruments Incorporated
ADS54J54
www.ti.com.cn
ZHCSD79A –JANUARY 2015–REVISED AUGUST 2019
Typical Characteristics (接下页)
Typical values at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 85°C, Device clock frequency = 500 MHz,
Output sample data rate = 5Gbps, 50% Device clock duty cycle, AVDD33 = 3.3 V, AVDD18 = 1.9 V, AVDDC = 1.8 V, IOVDD
= 1.8 V, PLLVDD = 1.8 V, DVDD = 1.8 V, –1 dBFS differential input, unless otherwise noted, FFT sample size = 32768.
94
92
90
88
86
84
82
80
78
76
74
68
66
64
62
60
-40èC
0èC
25èC
55èC
85èC
-40èC
0èC
25èC
55èC
85èC
1.7
1.8
1.9
2.0
2.1
1.7
1.8
1.9
2.0
2.1
AVDD18 Supply Voltage (V)
AVDD18 Supply Voltage (V)
D037
D038
2-lane no decimation
Ain = –1 dBFS
Fin = 170 MHz
2-lane no decimation
Ain = –1 dBFS
Fin = 170 MHz
图 41. SFDR vs AVDD18 Supply Voltage
图 42. SNR vs AVDD18 Supply Voltage
96
94
92
90
88
86
84
82
80
78
76
74
72
68
66
64
62
60
-40èC
0èC
25èC
55èC
85èC
-40èC
0èC
25èC
55èC
85èC
3.0
3.1
3.2
3.3
3.4
3.5
3.6
3.0
3.1
3.2
3.3
3.4
3.5
3.6
AVDD33 Supply Voltage (V)
AVDD33 Supply Voltage (V)
D039
D040
2-lane no decimation
Ain = –1 dBFS
Fin = 170 MHz
2-lane no decimation
Ain = –1 dBFS
Fin = 170 MHz
图 43. SFDR vs AVDD33 Supply Voltage
图 44. SNR vs AVDD33 Supply Voltage
90
88
86
84
82
80
78
68
67
66
65
64
63
62
-40èC
0èC
25èC
55èC
85èC
-40èC
0èC
25èC
55èC
85èC
1.6
1.7
1.8
1.9
2.0
1.6
1.7
1.8
1.9
2.0
PLLVDD Supply Voltage (V)
PLLVDD Supply Voltage (V)
D041
D042
2-lane no decimation
Ain = –1 dBFS
Fin = 170 MHz
2-lane no decimation
Ain = –1 dBFS
Fin = 170 MHz
图 45. SFDR vs PLLVDD Supply Voltage
图 46. SNR vs PLLVDD Supply Voltage
版权 © 2015–2019, Texas Instruments Incorporated
19
ADS54J54
ZHCSD79A –JANUARY 2015–REVISED AUGUST 2019
www.ti.com.cn
Typical Characteristics (接下页)
Typical values at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 85°C, Device clock frequency = 500 MHz,
Output sample data rate = 5Gbps, 50% Device clock duty cycle, AVDD33 = 3.3 V, AVDD18 = 1.9 V, AVDDC = 1.8 V, IOVDD
= 1.8 V, PLLVDD = 1.8 V, DVDD = 1.8 V, –1 dBFS differential input, unless otherwise noted, FFT sample size = 32768.
100
90
80
70
60
50
40
30
20
80
70
60
50
40
30
20
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
Clock Amplitude (V peak to peak)
Clock Amplitude (V peak to peak)
D043
D044
2-lane no decimation
Ain = –1 dBFS
Fin = 170 MHz
2-lane no decimation
Ain = –1 dBFS
Fin = 170 MHz
图 47. SFDR vs Clock Amplitude
图 48. SNR vs Clock Amplitude
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
B
A
C
D
C
D
hA
hB
o C
C t
Ch
hA
o C
D t
Ch
hB
o C
D t
Ch
hD
o C
C t
Ch
hC
o C
D t
Ch
Ch
Ch
Ch
Ch
Ch
Ch
o C
D04253
A to
Ch
B to
Ch
A to
A to
B to
B to
C t
Ch
Ch
Ch
Ch
Ch
Channel to Channel
2-lane no decimation
Ain = –1 dBFS
Fin = 170 MHz
图 49. Crosstalk by Channel
20
版权 © 2015–2019, Texas Instruments Incorporated
ADS54J54
www.ti.com.cn
ZHCSD79A –JANUARY 2015–REVISED AUGUST 2019
Typical Characteristics (接下页)
Typical values at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 85°C, Device clock frequency = 500 MHz,
Output sample data rate = 5Gbps, 50% Device clock duty cycle, AVDD33 = 3.3 V, AVDD18 = 1.9 V, AVDDC = 1.8 V, IOVDD
= 1.8 V, PLLVDD = 1.8 V, DVDD = 1.8 V, –1 dBFS differential input, unless otherwise noted, FFT sample size = 32768.
2lane no decimation
图 50. SNR Contour Plot
2lane no decimation
图 51. SFDR Contour Plot
版权 © 2015–2019, Texas Instruments Incorporated
21
ADS54J54
ZHCSD79A –JANUARY 2015–REVISED AUGUST 2019
www.ti.com.cn
Typical Characteristics (接下页)
Typical values at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 85°C, Device clock frequency = 500 MHz,
Output sample data rate = 5Gbps, 50% Device clock duty cycle, AVDD33 = 3.3 V, AVDD18 = 1.9 V, AVDDC = 1.8 V, IOVDD
= 1.8 V, PLLVDD = 1.8 V, DVDD = 1.8 V, –1 dBFS differential input, unless otherwise noted, FFT sample size = 32768.
d
d
d
n
n
n
a
a
a
B
B
B
n
o
n
n
i
d
n
t
i
o
i
o
i
t
s
a
t
i
i
n
B
s
a
s
r
n
n
n
T
a
o
a
i
r
r
r
t
e
i
T
T
t
l
s
n
a
r
i
r
e
t
F
e
t
l
i
r
T
l
i
F
F
r
e
t
l
i
F
1lane 2x decimation
图 52. SNR Contour Plot
d
n
a
d
d
n
n
B
a
a
d
n
n
B
B
o
i
n
a
B
n
t
i
o
o
i
i
t
t
i
s
i
n
o
n
s
s
i
t
n
a
n
r
i
a
a
r
T
s
n
a
r
T
r
T
r
e
t
e
r
r
T
t
l
l
e
t
i
i
r
l
i
F
F
e
t
F
l
i
F
1lane 2x decimation
图 53. SFDR Contour Plot
22
版权 © 2015–2019, Texas Instruments Incorporated
ADS54J54
www.ti.com.cn
ZHCSD79A –JANUARY 2015–REVISED AUGUST 2019
7 Detailed Description
7.1 Overview
The ADS54J54 is a low power, wide bandwidth 14-bit 500 MSPS quad channel ADC. It supports the JESD204B
serial interface with data rates up to 5.0 Gbps supporting 1 or 2 lanes per channel. The buffered analog input
provides uniform input impedance across a wide frequency range while minimizing sample-and-hold glitch
energy. A sampling clock divider allows more flexibility for system clock architecture design. The ADS54J54
provides excellent SFDR over a large input frequency range with low power consumption.
7.2 Functional Block Diagram
OVRA
Digital Block
Optional 2x
Decimination
14-bit
ADC
JESD204B
JESD204B
INAP/M
INBP/M
DA[0,1]P/M
Digital Block
Optional 2x
Decimination
14-bit
ADC
DB[0,1]P/M
OVRB
SYSREFABP/M
CLKINP/M
SYNCbAB
SYNCbCD
Divide
by 1,2,4
PLL
x10/x20
SYSREFCDP/M
OVRC
Digital Block
Optional 2x
Decimination
14-bit
ADC
JESD204B
JESD204B
DC[0,1]P/M
INCP/M
Digital Block
Optional 2x
Decimination
14-bit
ADC
INDP/M
VCM
DD[0,1]P/M
OVRD
Common
Mode
版权 © 2015–2019, Texas Instruments Incorporated
23
ADS54J54
ZHCSD79A –JANUARY 2015–REVISED AUGUST 2019
www.ti.com.cn
7.3 Feature Description
7.3.1 Decimation by 2 (250 MSPS Output)
Each channel has a digital filter in the data path as shown in 图 54. The filter can be programmed as a low-pass
or high-pass filter and the normalized frequency response of both filters is shown in 图 55.
Lowpass/
Highpass
500 MSPS
selection
Low Latency Filter
250 MSPS
ADC
2
0, Fs/2
图 54. 2x Decimation Filter
The decimation filter response has a 0.1-dB pass band ripple with approximately 41% pass-band bandwidth. The
stop-band attenuation is approximately 40 dB.
10
0
0.1
0.05
0
-10
-20
-30
-40
-50
-60
-0.05
-0.1
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
1
0
0.06 0.12 0.18 0.24
0.3
0.36 0.42 0.48
D00C
D00D
图 55. Decimation Filter Response
图 56. Decimation Filter Response Passband Ripple Detail
7.3.2 Over-Range Indication
The ADS54J54 provides a fast over-range indication on the OVRA, OVRB, OVRC, and OVRD pins. The fast
OVR is triggered if the input voltage exceeds the programmable over-range threshold and is output after just 6
clock cycles, enabling a quicker reaction to an over-range event. The OVR threshold can be configured using
SPI register writes.
The input voltage level at which the overload is detected is referred to as the threshold and is programmable
using the over-range threshold bits.
The threshold at which fast OVR is triggered is (full-scale × [the decimal value of the FAST OVR THRESH bits] /
8). After reset, the default value of the over-range threshold is set to 7 (decimal), which corresponds to a
threshold of 1.12 dB below full scale (20 × log(7/8)).
24
版权 © 2015–2019, Texas Instruments Incorporated
ADS54J54
www.ti.com.cn
ZHCSD79A –JANUARY 2015–REVISED AUGUST 2019
表 1. Fast Over Range
Threshold Settings
OVR Setting
(decimal)
OVR Threshold
(dBFS)
1
–18.1
–12.0
–8.5
–6.0
–4.1
–2.5
–1.1
2
3
4
5
6
7 (default)
Because the fast over-range indicator is single-ended LVCMOS logic, the ADS54J54 device can be configured
through the SPI register write to keep the over-range indicator asserted high for an extra one, two, or four clock
cycles. This longer assertion of the signal ensures the processor can capture the over-range event.
Sampling
Clock
Internal
Over-Range
Event
OVRA, OVRB,
OVRC, OVR D
Terminal Output
Normal
Hold 1 extra clock cycle
Hold 2 extra clock cycles
图 57. Fast Over Range Output Timing
The ADS54J54 device also provides the fast over-range indication bit in the JESD204B output data stream.
14-Bit Data Output
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
OVR
0
16-bit data going into 8b/10b encoder
图 58. Sample Data and Status Bit Format
7.3.3 JESD204B Interface
The ADS54J54 supports device subclass 1 with a maximum output data rate of 5 Gbps for each serial
transmitter. It allows independent JESD204B format configuration for channel A and B and channel C and D.
An external SYSREF signal is used to align all internal clock phases and the local multi-frame clock to a specific
sampling clock edge. This allows synchronization of multiple devices in a system and minimizes timing and
alignment uncertainty. SYNCbAB input is used to control all the JESD204B SerDes blocks for channel A and B
while SYNCbCD is used to control channel C and D. If the same LMFS configuration is used for all four
channels, the SYNCbAB and SYNCbCD signals can be tied together externally and driven from the same
source.
版权 © 2015–2019, Texas Instruments Incorporated
25
ADS54J54
ZHCSD79A –JANUARY 2015–REVISED AUGUST 2019
www.ti.com.cn
Depending on the channel output data rate, the JESD204B output interface can be operated with either 1 or 2
lanes per single channel. The JESD204B setup and configuration of the frame assembly parameters are
controlled via SPI interface.
The JESD204B transmitter block consists of the transport layer, the data scrambler and the link layer. The
transport layer maps the channel output data into the selected JESD204B frame data format and manages if the
channel output data or test patterns are being transmitted. The link layer performs the 8b/10b data encoding as
well as the synchronization and initial lane alignment using the SYNCb input signal. Optionally, data from the
transport layer can be scrambled.
SYNCb
AB
SYSREF
AB
JESD204B
D0/D1
JESD
204B
INA
INB
JESD204B
D0/D1
JESD
204B
Sample
Clock
JESD204B
D0/D1
JESD
204B
INC
IND
JESD204B
D0/D1
JESD
204B
SYNCb
CD
SYSREF
图 59. JESD204B Lane Assignment
Transport Layer
Link Layer
Frame Data
Mapping
8b/10b
encoding
D0
D1
Scrambler
1+x14+x15
Comma characters
Initial lane alignment
Test Patterns
SYNCb
图 60. JESD204B Block
26
版权 © 2015–2019, Texas Instruments Incorporated
ADS54J54
www.ti.com.cn
ZHCSD79A –JANUARY 2015–REVISED AUGUST 2019
7.3.3.1 JESD204B Initial Lane Alignment (ILA)
The ILA process is started by the receiving device by deasserting the SYNCb signal. Upon detecting a logic low
on the SYNCbAB input pins, the ADS54J54 device starts transmitting comma (K28.5) characters on channels A
and B to establish code group synchronization. Upon detecting a logic high on the SYNCbCD input pins, the
ADS54J54 device starts transmitting comma (K28.5) characters on channels C and D to establish code group
synchronization.
After synchronization is completed, the receiving device asserts the SYNCb signal and the ADS54J54 starts the
ILA sequence with the next local multi-frame clock boundary. The ADS54J54 device transmits 4 multi-frames
each containing K frames (K is SPI programmable). Each of the multi-frames contains the frame start and end
symbols and the second multi-frame also contains the JESD204 link configuration data.
SYSREF
LMFC Clock
LMFC Boundary
Multi
Frame
SYNCb
Transmit Data
xxx
K28.5
Code Group
Synchronization
图 61. Initial Lane Assignment Format
K28.5
Initial Lane
Alignment
ILA
ILA
DATA
Data Transmission
DATA
7.3.3.2 JESD204B Test Patterns
There are three different test patterns available in the transport layer of the JESD204B interface. The ADS54J54
supports a RAMP, 1555/2AAA and different PRBS patterns. They can be enabled through SPI register write and
are located in address 0x1D and 0x32/33.
7.3.3.3 JESD204B Frame Assembly
The JESD204B standard defines the following parameters:
•
•
•
•
•
L = number of lanes per link
M = number of converters for device
F = number of octets per frame clock period
S = number of samples per frame
HD = high density mode
The ADS54J54 supports independent configuration of the JESD204B format for channel A and B and channel C
and D. 表 2 lists the available JESD204B formats and valid ranges for the ADS54J54. The ranges are limited by
the SerDes line rate and the maximum channel sample frequency.
表 2. Permissible LMFS Settings
Max Channel
Max ƒSerDes
L
M
F
S
HD
Output Rate
(MSPS)
(Gsps)
8
4
4
4
1
2
1
1
1
0
500
250
5.0
5.0
版权 © 2015–2019, Texas Instruments Incorporated
27
ADS54J54
ZHCSD79A –JANUARY 2015–REVISED AUGUST 2019
www.ti.com.cn
The detailed frame assembly is shown in 表 3.
表 3. LMFS Data Formats
LMFS = 8411
A1[13:6] A2[13:6]
LMFS = 4421
A0[5:0], 00 A1[13:6]
Lane
DA0
A0[13:6]
A3[13:6]
A0[13:6]
B0[13:6]
C0[13:6]
D0[13:6]
A1[5:0], 00 A2[13:6]
B1[5:0], 00 B2[13:6]
C1[5:0], 00 C2[13:6]
D1[5:0], 00 D2[13:6]
A2[5:0], 00
B2[5:0], 00
C2[5:0], 00
D2[5:0], 00
Lane
DA1
A0[5:0], 00 A1[5:0], 00 A2[5:0], 00 A3[5:0], 00
B0[13:6] B1[13:6] B2[13:6] B3[13:6]
B0[5:0], 00 B1[5:0], 00 B2[5:0], 00 B3[5:0], 00
C0[13:6] C1[13:6] C2[13:6] C3[13:6]
C0[5:0], 00 C1[5:0], 00 C2[5:0], 00 C3[5:0], 00
D0[13:6] D1[13:6] D2[13:6] D3[13:6]
D0[5:0], 00 D1[5:0], 00 D2[5:0], 00 D3[5:0], 00
Lane
DB0
B0[5:0], 00 B1[13:6]
C0[5:0], 00 C1[13:6]
D0[5:0], 00 D1[13:6]
Lane
DB1
Lane
DC0
Lane
DC1
Lane
DD0
Lane
DD1
7.3.4 SYSREF Clocking Schemes
Periodic: The SYSREF signal is always on. This mode is supported, but not recommended as the continuous
SYSREF signal appears like an additional clock input, which can cause clock mixing spurs in the channel output
spectrum.
Gapped-Periodic (recommended): A periodic SYSREF signal is presented to the ADS54J54 SYSREF inputs
for a very short period of time. This configuration requires a DC-coupled SYSREF connection for proper
operation. Most of the time the SYSREF signal is in a logic-low state, and thus cannot cause any glitches and
spurs in the channel output spectrum.
Pulse/One Shot (recommended): A single SYSREF reset pulse is used to synchronize the ADS54J54. The
ADS54J54 device requires a minimum of 3 SYSREF pulses to complete the synchronization phase. The
SYSREF signal is in a logic-low state most of the time, and thus cannot cause any glitches and spurs in the
channel output spectrum. Special attention should be given to ensure the single pulse meets required the
SYSREF input setup and hold time.
7.3.5 Split-Mode Operation
The ADS54J54 provides several different options to interface it to the digital processor or processors. If the
ADS54J54 device is operated in split sampling rate (2 channels at 500-MSPS output rate and 2 channels at 250-
MSPS output rate), then it requires dual SYSREF (SYSREFAB and SYSREFCD) and dual SYNC (SYNCbAB
and SYNCbCD).
Subclass 1 – Deterministic Latency: The device clock and synchronous SYSREF signal are provided by the
timing unit to the ADS54J54 and the processor. The processor controls the SYNCb input signals for the
JESD204B state machine for all four channels. In case the ADS54J54 is connected to two different processors,
the differential SYNCb inputs of the ADS54J54 can be configured to two single-ended inputs where each pin
controls the JESD204B state machine of the two corresponding channels.
28
版权 © 2015–2019, Texas Instruments Incorporated
ADS54J54
www.ti.com.cn
ZHCSD79A –JANUARY 2015–REVISED AUGUST 2019
CLKIN
SYSREF
JESD204B
D0/D1
JESD204B
D0/D1
FPGA
ASIC
DSP
JESD
204B
JESD
204B
INA
INB
INA
JESD
204B
JESD
204B
INB
SYSREFAB
CLKIN
SYSREFAB
CLKIN
SYNCbAB
SYNCbCD
SYNCbAB
SYNCbCD
ADS54J54
ADS54J54
FPGA
ASIC
DSP
JESD
204B
JESD
204B
INC
IND
INC
IND
JESD
204B
JESD
204B
FPGA
ASIC
DSP
CLKIN
CLKIN
Timing Unit
For Example
LMK04828
Timing Unit
For Example
LMK04828
SYSREF
SYSREF
图 62. Four Channel and Dual Two Channel Usage
Split Mode Operation: If the ADS54J54 device is operated with 2-channel output at 500 MSPS and 2-channel
output at 250 MSPS, then dual SYSREF (SYSREFAB for channel A and B, SYSREFCD for channel C and D) as
well as dual SYNC (SYNCbAB for channel A and B, SYNCbCD for channel C and D) is required to ensure
normal operation because the JESD204B link configuration is different for the two channel pairs.
JESD204B
D0/D1
JESD
204B
INA
JESD
204B
INB
SYSREFAB
SYNCbAB
SYNCbCD
FPGA
ASIC
DSP
ADS54J54
JESD
INC
IND
204B
JESD
204B
SYSREF
CLKIN
Timing Unit
For Example
LMK04828
图 63. Dual SYSREF Usage
版权 © 2015–2019, Texas Instruments Incorporated
29
ADS54J54
ZHCSD79A –JANUARY 2015–REVISED AUGUST 2019
www.ti.com.cn
7.3.6 Eye Diagram Information
图 64 and 图 65 is the measured eye diagram at 2.5 and 5 Gbps output data rate, respectively. These are
overlaid with the JESD204B LV-OIF-6G-SR specification.
800 mV
800 mV
0 mV
0 mV
œ800 mV
œ800 mV
400 ps
666.67 ps
200 ps
333.33 ps
0 ps
133.33 ps
266.67 ps
533.33 ps
0 ps
66.67 ps
133.33 ps
266.67 ps
图 64. 2.5 Gbps Eye Diagram
图 65. 5.0 Gbps Eye Diagram
7.3.7 Analog Inputs
The ADS54J54 analog signal inputs are designed to be driven differentially. The analog input pins have internal
analog buffers that drive the sampling circuit. As a result of the analog buffer, the input pins present a high-
impedance input across a wide frequency range to the external driving source, which enables great flexibility in
the external analog filter design as well as excellent 50-Ω matching for RF applications. The buffer also helps
isolate the external driving circuit from the internal switching currents of the sampling circuit, which results in a
more constant SFDR performance across input frequencies.
The common-mode voltage of the signal inputs is internally biased to 2 V using 500-Ω resistors, which allows for
AC coupling of the input drive network. Each input pin (INP, INM) must swing symmetrically between (VCM +
0.3125 V) and (VCM – 0.3125 V), resulting in a 1.25-Vpp (default) differential input swing. The input sampling
circuit has a 3-dB bandwidth that extends up to 900 MHz.
2
1 nH
0.1 ꢀ
30 ꢀ
INxP
0
360 fF
3.4 pF
500 ꢀ
-2
Vcm
1 nH
0.1 ꢀ
30 ꢀ
500 ꢀ
-4
INxM
-6
360 fF
3.4 pF
-8
-10
-12
1E+7 2E+7
5E+7 1E+8 2E+8
5E+8 1E+9 2E+9
5E+9
Input Frequency (Hz)
D00E
图 66. Normalized Input Bandwidth
图 67. Equivalent Analog Input Circuit
30
版权 © 2015–2019, Texas Instruments Incorporated
ADS54J54
www.ti.com.cn
ZHCSD79A –JANUARY 2015–REVISED AUGUST 2019
7.3.8 Clock Inputs
The ADS54J54 clock input can be driven differentially with a sine wave or LVPECL source with little or no
difference in performance. The common mode voltage of the clock input is set to 0.9 V using internal 2-kΩ
resistors. This allows for AC coupling of the clock inputs. The termination resistors should be placed as close as
possible to the clock inputs in order to minimize signal reflections and jitter degradation.
CLKINP
2 kꢀ
0.9 V
2 kꢀ
CLKINN
图 68. Equivalent Clock Input Circuit
7.3.9 Input Clock Divider
The ADS54J54 is equipped with two internal dividers on the clock input – one on channel AB and one on
channel CD. The clock divider allows operation with a faster input clock simplifying the system clock distribution
design. The clock dividers can be bypassed (/1) for operation with a 500-MHz clock while /2 option supports a
maximum input clock of 1 GHz and the /4 option a maximum input clock frequency of 2 GHz. Different divider
options can be selected for channel AB and channel CD clock output. By default the divider output of channel AB
block is routed to all 4 channels but the configuration can be customized with different SPI register settings to
use either the channel AB or CD divider blocks for any two channels.
ChAB
ADC A
ADC B
Divide by
1, 2, 4
Phase Select
CLKIN
Divide by
1, 2, 4
Phase Select
ADC C
ADC D
ChCD
图 69. Input Clock Divider
7.3.10 Power-Down Control
The power down functions of the ADS54J54 can be controlled either through the parallel control pin (ENABLE) or
through a SPI register setting. Power-down modes for the different channels as well as for the JESD204B
interface are supported.
The ADS54J54 supports the following power-down modes. The analog sleep mode configurations are in register
0x05/06 and the JESD204b sleep mode configurations are in register 0x1E and 0x1F.
版权 © 2015–2019, Texas Instruments Incorporated
31
ADS54J54
ZHCSD79A –JANUARY 2015–REVISED AUGUST 2019
www.ti.com.cn
表 4. Low-Power Mode Power Consumption and Wake-Up Times
Configuration
Global power down
Standby
Power Consumption
24 mW
Wake-Up Time
Needs JESD resynch
Needs JESD resynch
1.4 ms
31 mW
Deep sleep
791 mW
Light sleep
1.68 W
8 µs
Control power-down function through ENABLE pin:
1. Configure power-down mode in register 0x05 and 0x1E
2. Normal operation: ENABLE pin high
3. Power-down mode: ENABLE pin low
Control power-down function through SPI (ENABLE pin always high):
1. Assign power-down mode in register 0x06 and 0x1F
2. Normal operation: 0x06 and 0x1F are 0xFFFF
3. Power-down mode: configure power down mode in register 0x06 and 0x1F
7.3.11 Device Configuration
The serial interface (SIF) included in the ADS54J54 is a simple 3- or 4-pin interface. In normal mode, 3 pins are
used to communicate with the device. There is an enable (SDENb), a clock (SCLK), and a bidirectional IO port
(SDATA). If the user would like to use the 4-pin interface, one write must be implemented in the 3-pin mode to
enable 4-pin communications. In this mode, the SDOUT pin becomes the dedicated output. The serial interface
has an 8-bit address word and a 16-bit data word. The first rising edge of SCLK after SDENb goes low will latch
the read or write bit. If a high is registered, then a read is requested, if it is low, then a write is requested. SDENb
must be brought high again before another transfer can be requested.
7.3.12 JESD204B Interface Initialization Sequence
After power-up, the internal JESD204B digital block must be initialized with the following sequence of steps:
1. Set JESD RESET AB/CD and JESD INIT AB/CD to 0 (address 0x0D, value 0x0000)
2. Set JESD INIT AB/CD to 1 (0x0D, 0x0202)
3. Set JESD RESET AB/CD to 1 (0x0D, 0x0303)
4. Configure all other JESD register and clock settings. If those settings change later on, this initialization
sequence must be repeated.
5. Set JESD RESET AB/CD to 0 (0x0D, 0x0202)
6. Set JESD RESET AB/CD to 1 (0x0D, 0x0303)
7. Wait for two SYSREF pulses
8. Set JESD INIT AB/CD to 0 (0x0D, 0x0101)
32
版权 © 2015–2019, Texas Instruments Incorporated
ADS54J54
www.ti.com.cn
ZHCSD79A –JANUARY 2015–REVISED AUGUST 2019
7.3.13 Device and Register Initialization
After power-up, the internal registers must be initialized to their default values through a hardware reset by
applying a low pulse on the SRESETb pin (of width greater than 10 ns), as shown in 图 1. If required later during
operation, the serial interface registers can be cleared by applying:
•
•
Another hardware reset using the SRESETb pin
A software reset (bit D0 in register 0x00). This setting resets the internal registers to the default values and
then self-resets the RESET bit (D0) back to 0. In this case, the RESET pin is kept high.
•
Write the data in 表 5 to the following registers after every device power-up or reset for optimum AC
performance:
表 5. AC Performance
ADDRESS
0x06
DATA
0xFFDF
0x0074
0x0074
0x4000
0x0800
0x0074
0x0074
0x4000
0x0800
REASON
turn off fuse logic for power savings - not required
trim value - required
0x44
0x47
trim value - required
0x4C
0x50
trim value - required
trim value - required
0x51
trim value - required
0x54
trim value - required
0x59
trim value - required
0x5D
trim value - required
7.4 Device Functional Modes
7.4.1 Operating Modes
表 6 details the five different operating modes. A pair of channels (channel A and B and channel C and D) can be
configured in the same operating mode.
表 6. Operating Modes Information
Channel
Sampling Rate
(MSPS)
Output Data
Rate (MSPS)
Output
Resolution
Output SerDes
Rate (GSPS)
Number of Lanes
per Channel
Digital Feature
500
500
Decimation by 2
Bypass digital logic mode
250
500
14 bit
14 bit
5.0
5.0
1
2
版权 © 2015–2019, Texas Instruments Incorporated
33
ADS54J54
ZHCSD79A –JANUARY 2015–REVISED AUGUST 2019
www.ti.com.cn
7.4.2 Output Format
表 7 provides detailed information on how the MSB or LSB get aligned for the different output data rates and resolution in the different operating modes.
表 7. Output Data Formats
Output
Rate
Mode
Resolution
14 bit
Bit 15
D13
Bit 14
D12
Bit 13
D11
Bit 12
D10
Bit 11
D9
Bit 10
D8
Bit 9
D7
Bit 8
D6
Bit 7
D5
Bit 6
D4
Bit 5
D3
Bit 4
D2
Bit 3
D1
Bit 2
D0
Bit 1
OVR
OVR
Bit 0
250 MSPS
Decimate by 2
0
0
Bypass digital
logic mode
500 MSPS
14 bit
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
34
版权 © 2015–2019, Texas Instruments Incorporated
ADS54J54
www.ti.com.cn
ZHCSD79A –JANUARY 2015–REVISED AUGUST 2019
7.5 Programming
7.5.1 Serial Register Write
The internal register of the ADS54J54 can be programmed following these steps:
1. Drive SDENb pin low.
2. Set the R/W bit to ‘0’ (bit A7 of the 8 bit address).
3. Initiate a serial interface cycle specifying the address of the register (A6 to A0) whose content has to be
written.
4. Write 16-bit data which is latched on the rising edge of SCLK.
表 8. Serial Register Read or Write Timing(1)
PARAMETER
SCLK frequency (equal to 1 / tSCLK
SDENb to SCLK setup time
SCLK to SDENb hold time
SDATA setup time
MIN
>DC
50
TYP
MAX
UNIT
MHz
ns
ƒSCLK
tSLOADS
tSLOADH
tDSU
)
10
50
ns
50
ns
tDH
SDATA hold time
50
ns
(1) Typical values at 25°C; minimum and maximum values across the full temperature range: TMIN = –40°C to TMAX = 85°C,
AVDD33 = 3.3 V; AVDD18 = 1.9 V; AVDDC, DVDD, IOVDD, PLLVDD = 1.8 V, unless otherwise noted.
SCLK
SDENb
RWB
A6
A5
A4
A3
A2
A1
A0 D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
SDATA
Read = 1
Write = 0
7-bit address space
16-bit data: D15 is MSB, D0 is LSB
图 70. Serial Register Write Timing Diagram
7.5.2 Serial Register Readout
The device includes a mode where the contents of the internal registers can be read back using the SDOUT and
SDATA pins. This read-back mode may be useful as a diagnostic check to verify the serial interface
communication between the external controller and the channel.
1. Drive SDENb pin low.
2. Set the RW bit (A7) to 1. This setting disables any further writes to the registers.
3. Initiate a serial interface cycle specifying the address of the register (A6 to A0) whose content has to be
read.
4. The device outputs the contents (D15 to D0) of the selected register on the SDOUT/SDATA pin.
5. The external controller can latch the contents at the SCLK rising edge.
6. To enable register writes, reset the RW register bit to 0.
SCLK
SDENb
RWB
A6
A5
A4
A3
A2
A1
A0 D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
SDATA
Read = 1
Write = 0
7-bit address space
16-bit data: D15 is MSB, D0 is LSB
图 71. Serial Register Read Timing Diagram
版权 © 2015–2019, Texas Instruments Incorporated
35
ADS54J54
ZHCSD79A –JANUARY 2015–REVISED AUGUST 2019
www.ti.com.cn
7.6 Register Maps
Register
Address
Register Data
A7 to A0 in
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
hex
0
3/4 WIRE
MODE 1
0
FORMAT
DEC EN AB
1
HP/LP AB
0
0
DEC EN CD
FOVR THRESH AB
0
HP/LP CD
0
0
0
0
0
0
0
0
1
0
RESET
1
0
1
FOVR LENGTH AB
FOVR THRESH CD
0
FOVR LENGTH CD
0
0
2
0
0
0
0
0
0
0
0
0
0
0
0
CLK SEL
CD
SYSREF
SEL CD
CLK SEL
AB
3
0
CLK DIV CD
CLK PHASE SELECT CD
SYSREF CD DELAY
CLK DIV AB
CLK PHASE SELECT AB
OVRA OUT OVRB OUT OVRC OUT OVRD OUT
SYNCb AB
EN
SYNCb CD
EN
4
5
6
SYSREF AB DELAY
0
0
0
1
1
EN
EN
EN
EN
ANALOG SLEEP MODES – ENABLE PIN
ANALOG SLEEP MODES – SPI
SYSREFCD
EN
7
8
0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
0
0
0
CLK SW AB
CLK SW CD
0
1
1
1
0
0
1
1
1
1
0
0
0
0
0
0
1
1
0
0
0
0
C
SYSREF JESD MODE CD
0
SYSREF JESD MODE AB
JESD INIT
CD
JESD
RESET CD
JESD INIT
AB
JESD
RESET AB
D
0
0
0
0
0
0
0
0
0
0
0
0
0
E
F
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
TX LANE EN CD
TX LANE EN AB
CTRL F AB
0
0
0
0
0
0
0
0
CTRL M AB
10
CTRL K AB
CTRL L AB
INV SYNCb
AB
13
0
0
0
0
0
0
0
0
HD AB
0
SCR EN AB
0
0
0
0
16
17
0
0
0
0
0
0
0
0
0
0
0
0
CTRL F CD
0
0
0
0
0
0
0
0
CTRL M CD
CTRL L CD
CTRL K CD
INV SYNCb
CD
1A
1D
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
HD CD
SCR EN CD
0
0
0
0
0
0
0
0
TEST
PATTERN
EN CD
TEST
PATTERN
EN AB
TEST
PATTERN
1E
1F
20
21
63
64
67
68
6B
0
1
0
1
0
1
0
1
0
1
0
1
JESD SLEEP MODES – ENABLE PIN
JESD SLEEP MODES – SPI
PRBS EN
JESD LANE POLARITY INVERT
0
0
PRBS SEL
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
VREF SEL
TEMP SENSOR
0
PRE EMP SEL AB
PRE EMP EN AB
DCC EN AB
DCC EN CD
0
0
0
0
0
0
OUTPUT CURRENT CONTROL AB
OUTPUT CURRENT CONTROL CD
PRE EMP SEL CD
PRE EMP EN CD
0
JESD PLL
CD
JESD PLL
AB
6C
0
0
0
0
0
0
0
0
0
0
0
0
0
0
36
版权 © 2015–2019, Texas Instruments Incorporated
ADS54J54
www.ti.com.cn
ZHCSD79A –JANUARY 2015–REVISED AUGUST 2019
7.6.1 Register Descriptions
7.6.1.1 Register Address 0
图 72. Register Address 0, Reset 0x0000, Hex = 0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
3/4
WIRE
FORM
AT
DEC EN
AB
DEC EN
CD
HP/LP AB
0
HP/LP CD
0
0
0
0
0
0
0
0
RESET
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表 9. Register Address 0 Field Descriptions
Bit
Field
Type
Reset
Description
Enables 4-bit serial interface when set
0 = 3-wire SPI (SDATA is bidirectional)
1 = 4-wire SPI (SDOUT is data output)
D15
3/4 WIRE
R/W
0
Selects digital output format
0 = Output is 2s complement
1 = Offset binary
D14
D13
FORMAT
R/W
R/W
0
0
Enables decimation filter for channel AB
0 = Normal operation
DEC EN AB
1 = Decimation filter enabled
Determines high-pass or low-pass configuration of decimation
filter for channel AB
0 = Low pass
1 = High pass
D12
D10
D9
HP/LP AB
DEC EN CD
HP/LP CD
RESET
R/W
R/W
R/W
R/W
0
0
0
0
Enables decimation filter for channel CD
0 = Normal operation
1 = Decimation filter enabled
Determines high-pass or low-pass configuration of decimation
filter for channel CD
0 = Low pass
1 = High pass
Software reset, self clears to 0
0 = Normal operation
D0
1 = Execute software reset
版权 © 2015–2019, Texas Instruments Incorporated
37
ADS54J54
ZHCSD79A –JANUARY 2015–REVISED AUGUST 2019
www.ti.com.cn
7.6.1.2 Register Address 1
图 73. Register Address 1, Reset 0xAF7A, Hex = 1
D15
D14 D13 D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
MODE
1
FOVR LENGTH
AB
FOVR LENGTH
CD
0
1
0
FOVR THRESH AB
FOVR THRESH CD
1
0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表 10. Register Address 1 Field Descriptions
Bit
Field
Type
R/W
R
Reset
Description
D15
D13
MODE 1
1
1
Set bit D15 to 0 for optimum performance
Reads back 1
Sets fast OVR thresholds for channel A and B
The fast over-range detection is triggered 6 output clock cycles
after the overload condition occurs. The threshold at which the
OVR is triggered is:
Input full scale × [decimal value of <over-range threshold>] / 8.
After power-up or reset, the default value is 7 (decimal), which
corresponds to an OVR threshold of 1.16-dB below full scale (20
× log(7/8)).
0
-2
-4
-6
D11:D9
FOVR THRESH AB
R/W
111
-8
-10
-12
-14
-16
-18
-20
0
1
2
3
4
5
6
7
8
Programmed Decimal Value
D00F
图 74. OVR Detection Threshold
Determines minimum pulse length for FOVR output
00 = 1 clock cycle
D8:D7
D6:D4
FOVR LENGTH AB
FOVR THRESH CD
FOVR LENGTH CD
R/W
R/W
10
01 = 2 clock cycles
10 = 4 clock cycles
11 = 8 clock cycles
Sets fast OVR thresholds for channel C and D See description
for channel A and B
111
Determines minimum pulse length for FOVR output
00 = 1 clock cycle
01 = 2 clock cycles
10 = 4 clock cycles
11 = 8 clock cycles
D3:D2
D1
R/W
R
10
1
Reads back 1
38
版权 © 2015–2019, Texas Instruments Incorporated
ADS54J54
www.ti.com.cn
ZHCSD79A –JANUARY 2015–REVISED AUGUST 2019
7.6.1.3 Register Address 3
图 75. Register Address 3, Reset: 0x4040, Hex = 3
D15
D14
D13
D12
D11 D10
D9
D8
D7
SYSREF CLK SEL
SEL CD AB
D6
D5
D4
D3
D2
D1
D0
CLK SEL
CD
CLK PHASE
SELECT CD
CLK PHASE
SELECT AB
0
CLK DIV CD
0
CLK DIV AB
0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表 11. Register Address 3 Field Descriptions
Bit
Field
Type
Reset
Description
Clock source selection for channel C and D
0 = Channel CD clock output divider
D14
CLK SEL CD
R/W
1
1 = Channel AB clock output divider (default)
Channel CD clock divider setting
00 = Clock input is up to 500 MHz. Input clock is not divided
(default)
01 = /2
10 = /4
11 = Not used
D13:D12 CLK DIV CD
R/W
R/W
00
Selects phase of channel divided clock, but depends on clock
divider setting. When clock CD divider is set to:
/1 = 2 phases are available (0º or 180º)
/2 = 4 phases are available (0º, 90º, 180º or 270º)
/4 = 8 phases are available (0º, 45º, 90º, 135º, 180º, 225º, 270º
or 315º)
D10:D8
CLK PHASE SELECT CD
000
When switching clock phases, register 0x08, D9 must be
enabled first and then disabled after the switch to ensure glitch-
free operation.
SYSREF Input selection for channel C and D
0 = Use SYSREFAB inputs (default)
1 = Use SYSREFCD inputs
D7
D6
SYSREF SEL CD
CLK SEL AB
R/W
R/W
0
1
Clock source selection for channel A and B
0 = Channel CD clock output divider
1 = Channel AB clock output divider (default)
Channel AB clock divider setting
00 = Clock input is up to 500 MHz. Input clock is not divided
(default)
01 = /2
10 = /4
11 = Not used
D5:D4
D2:D0
CLK DIV AB
R/W
R/W
00
Selects phase of channel AB divided clock, but depends on
clock divider setting. When clock divider is set to:
/1 = 2 phases are available (0º or 180º)
/2 = 4 phases are available (0º, 90º, 180º or 270º)
/4 = 8 phases are available (0º, 45º, 90º, 135º, 180º, 225º, 270º
or 315º)
CLK PHASE SELECT AB
000
When switching clock phases, register 0x07, D9 must be
enabled first and then disabled after the switch to ensure glitch-
free operation.
版权 © 2015–2019, Texas Instruments Incorporated
39
ADS54J54
ZHCSD79A –JANUARY 2015–REVISED AUGUST 2019
www.ti.com.cn
7.6.1.4 Register Address 4
图 76. Register Address 4, Reset: 0x000F, Hex = 4
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
OVRA
OVRB
OVRC
OVRD
SYSREF AB
DELAY
SYSREF CD
DELAY
SYNCb
AB EN
SYNCb
CD EN
0
0
0
0
1
1
OUT EN OUT EN OUT EN OUT EN
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表 12. Register Address 4 Field Descriptions
Bit
Field
Type
Reset
Description
OVRA pin output enable
0 = Not used (default)
1 = OVRA is an output
D15
OVRA OUT EN
R/W
0
OVRB pin output enable
0 = Not used (default)
1 = OVRB is an output
D14
D13
D12
OVRB OUT EN
OVRC OUT EN
OVRD OUT EN
R/W
R/W
R/W
0
0
0
OVRC pin output enable
0 = Not used (default)
1 = OVRC is an output
OVRD pin output enable
0 = Not used (default)
1 = OVRD is an output
Programmable input delay on SYSREFAB input
00 = 0-ps delay (default)
01 = 200-ps delay
10 = 100-ps delay
11 = 300-ps delay
D11:D10 SYSREF AB DELAY
R/W
R/W
00
00
Programmable input delay on SYSREFCD input
00 = 0-ps delay (default)
01 = 200-ps delay
D9:D8
SYSREF CD DELAY
10 = 100-ps delay
11 = 300-ps delay
SYNCbAB input buffer enable
0 = Input buffer disabled
1 = Input buffer enabled (default)
D3
D2
SYNCb AB EN
SYNCb CD EN
R/W
R/W
1
1
SYNCbCD input buffer enable
0 = Input buffer disabled
1 = Input buffer enabled (default)
D1
D0
R
R
1
1
Reads back 1
Reads back 1
40
版权 © 2015–2019, Texas Instruments Incorporated
ADS54J54
www.ti.com.cn
ZHCSD79A –JANUARY 2015–REVISED AUGUST 2019
7.6.1.5 Register Address 5
图 77. Register Address 5, Reset: 0x0000, Hex = 5
D15
D14
D13
D12
D11
D10
ANALOG SLEEP MODES – ENABLE pin
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
表 13. Register Address 5 Field Descriptions
Bit
Field
Type
Reset
Description
Power-down function assigned to ENABLE pin. When any bit is
set, the corresponding function is always enabled regardless of
status of the ENABLE pin. This assumes address 0x06 is in
default configuration.
ANALOG SLEEP MODES –
ENABLE pin
D15:D0
R/W
D13
D11
D9
D7
D6
D4
D3
D2
D1
D0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
0
0
Light sleep channel A
Light sleep channel B
Light sleep channel C
Light sleep channel D
Temperature sensor
Clock buffer
Clock divider channel AB
Clock divider channel CD
Buffer SYSREFAB
Buffer SYSREFCD
spacer
表 14. Configurations When ENABLE Pin is Low
Description
0000 0000 0000 0000
1000 0000 0000 0000
1000 0000 0001 1111
1010 1010 1001 1111
Global power down
Standby
Deep sleep
Light sleep (if unused, clock divider CD and SYSREFCD can be set to 0 also)
版权 © 2015–2019, Texas Instruments Incorporated
41
ADS54J54
ZHCSD79A –JANUARY 2015–REVISED AUGUST 2019
www.ti.com.cn
7.6.1.6 Register Address 6
图 78. Register Address 6, Reset: 0xFFFF, Hex = 6
D15
D14
D13
D12
D11
D10
ANALOG SLEEP MODES – SPI
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
1
表 15. Register Address 6 Field Descriptions
Bit
Field
Type
Reset
Description
Power-down function controlled via SPI. When a bit is set to 0,
the function is powered down when ENABLE pin is high.
However, register 0x05 has higher priority. For example, if D13
(deep sleep channel A) in 0x05 is enabled, it cannot be powered
down with the SPI.
D15:D1
ANALOG SLEEP MODES – SPI
D13
D11
D9
D7
D6
D4
D3
D2
D1
D0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1
1
1
1
1
1
1
1
1
1
Light sleep channel A
Light sleep channel B
Light sleep channel C
Light sleep channel D
Temperature sensor
Clock buffer
Clock divider channel AB
Clock divider channel CD
Buffer SYSREFAB
Should be left set to 1
spacer
表 16. Configurations When ENABLE Pin is High
Description
0000 0000 0000 000
1000 0000 0000 000
1000 0000 0001 111
1010 1010 1001 111
1111 1111 1111 111
Global power down
Standby
Deep sleep
Light sleep
Normal operation
Control power down function through ENABLE pin:
1. Configure power-down mode in register 0x05
2. Normal operation: ENABLE pin high
3. Power-down mode: ENABLE pin low
Control power down function through SPI (ENABLE pin always high):
1. Assign power-down mode in register 0x06
2. Normal operation 0x06 is 0xFFFF
3. Power-down mode: configure power down mode in register 0x06
42
版权 © 2015–2019, Texas Instruments Incorporated
ADS54J54
www.ti.com.cn
ZHCSD79A –JANUARY 2015–REVISED AUGUST 2019
7.6.1.7 Register Address 7
图 79. Register Address 7, Reset: 0x0144, Hex = 7
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
CLK SW AB
1
0
1
0
0
0
1
0
0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表 17. Register Address 7 Field Descriptions
Bit
Field
Type
Reset
Description
User should set this bit to 1 when changing the clock phase of
the clock divider AB. After the change is complete user needs to
write this bit back to 0.
D9
CLK SW AB
R/W
0
D8
D6
D2
R
R
R
1
1
1
Reads back 1
Reads back 1
Reads back 1
7.6.1.8 Register Address 8
图 80. Register Address 8, Reset: 0x0144, Hex = 8
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
CLK SW CD
1
0
1
0
0
0
1
0
0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表 18. Register Address 8 Field Descriptions
Bit
Field
Type
Reset
Description
User should set this bit to 1 when changing the clock phase of
the clock divider CD. After the change is complete user needs to
write this bit back to 0.
D9
CLK SW CD
R/W
0
D8
D6
D2
R
R
R
1
1
1
Reads back 1
Reads back 1
Reads back 1
7.6.1.9 Register Address 12
图 81. Register Address 12, Reset: 0x31E4, Hex = C
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
0
1
1
0
0
0
1
1
1
SYSREF JESD MODE CD SYSREF JESD MODE AB
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表 19. Register Address 12 Field Descriptions
Bit
D13
D12
D8
Field
Type
R
Reset
Description
1
1
1
1
1
Reads back 1
Reads back 1
Reads back 1
Reads back 1
Reads back 1
R
R
D7
R
D6
R
版权 © 2015–2019, Texas Instruments Incorporated
43
ADS54J54
ZHCSD79A –JANUARY 2015–REVISED AUGUST 2019
www.ti.com.cn
表 19. Register Address 12 Field Descriptions (接下页)
Bit
Field
Type
Reset
Description
Determines how SYSREF is used in the JESD block for channel
CD
000 = Ignore SYSREF input
001 = Use all SYSREF pulses
D5:D3
SYSREF JESD MODE CD
R/W
100
010 = Use only the next SYSREF pulse
011 = Skip one SYSREF pulse then use only the next one
100 = Skip one SYSREF pulse then use all pulses (default)
101 = Skip two SYSREF pulses and then use one
111 = Skip two SYSREF pulses and then use all
Determines how SYSREF is used in the JESD block for channel
AB. Same functionality as SYSREF JESD MODE CD
D2:D0
SYSREF JESD MODE AB
R/W
100
7.6.1.10 Register Address 13
图 82. Register Address 13, Reset: 0x0202, Hex = D
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
JESD
INIT CD RESET CD
JESD
JESD
INIT AB RESET AB
JESD
0
0
0
0
0
0
0
0
0
0
0
0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表 20. Register Address 13 Field Descriptions
Bit
D9
D8
D1
D0
Field
Type
R/W
R/W
R/W
R/W
Reset
Description
Puts the JESD block in INITIALIZATION state when set high. In
this state the JESD parameters can be programmed and the
outputs will stay at 0. See also JESD start-up sequence.
JESD INIT CD
JESD RESET CD
JESD INIT AB
JESD RESET AB
1
0
1
0
Resets the JESD block when low
Puts the JESD block in initialization state when set high. In this
state the JESD parameters can be programmed and the outputs
will stay at 0.
Resets the JESD block when low
7.6.1.11 Register Address 14
图 83. Register Address 14, Reset: 0x00FF, Hex = E
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
0
TX LANE EN CD
TX LANE EN AB
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表 21. Register Address 14 Field Descriptions
Bit
Field
Type
Reset
Description
Enables JESD204B transmitter for channel C and D. Set to 1 to
enable.
D7 = Lane DD1
D6 = Lane DD0
D5 = Lane DC1
D4 = Lane DC0
D7:D4
TX LANE EN CD
R/W
1111
Enables JESD204B transmitter for channel A and B. Set to 1 to
enable.
D3 = Lane DB1
D2 = Lane DB0
D1 = Lane DA1
D0 = Lane DA0
D3:D0
TX LANE EN AB
R/W
1111
44
版权 © 2015–2019, Texas Instruments Incorporated
ADS54J54
www.ti.com.cn
ZHCSD79A –JANUARY 2015–REVISED AUGUST 2019
7.6.1.12 Register Address 15
图 84. Register Address 15, Reset: 0x0001, Hex = F
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
CTRL F AB
0
0
0
0
0
0
CTRL M AB
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表 22. Register Address 15 Field Descriptions
Bit
Field
Type
Reset
Description
Controls number of octets per frame for channel AB.
D9:D8
CTRL F AB
R/W
00
00 = F = 1 (default)
01 = F = 2
Controls number of converters per link for channel AB.
01 = M = 2. This is the only valid option (default)
D1:D0
CTRL M AB
R/W
01
7.6.1.13 Register Address 16
图 85. Register Address 16, Reset: 0x03E3, Hex = 10
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
CTRL K AB
0
0
0
CTRL L AB
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表 23. Register Address 16 Field Descriptions
Bit
Field
Type
Reset
Description
Controls number of frames per multi-frame for channel AB.
0: K = 1 30 K = 31
1: K = 2 31 K = 32 (default)
And so forth
D9:D5
CTRL K AB
R/W
11111
Controls number of lanes for channel AB.
01: L = 2
D1:D0
CTRL L AB
R/W
11
11: L = 4 (default)
7.6.1.14 Register Address 19
图 86. Register Address 19, Reset: 0x0020, Hex = 13
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
INV SYNCb
AB
SCR EN
AB
0
0
0
0
0
0
0
0
0
HD AB
0
0
0
0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表 24. Register Address 19 Field Descriptions
Bit
Field
Type
Reset
Description
Inverts polarity of SYNCbAB input
0 = Normal operation
D6
INV SYNCb AB
R/W
0
1 = Polarity inverted
Enables high density mode for channel AB. This mode is
needed for LMFS = 4221.
0 = High-density mode disabled for mode LMFS = 2221
D5
D4
HD AB
R/W
R/W
1
0
1 = High-density mode enabled for mode LMFS = 4221 (default)
Enables scramble mode for channel AB
0 = Scramble mode disabled (default)
1 = Scramble mode enabled
SCR EN AB
版权 © 2015–2019, Texas Instruments Incorporated
45
ADS54J54
ZHCSD79A –JANUARY 2015–REVISED AUGUST 2019
www.ti.com.cn
7.6.1.15 Register Address 22
图 87. Register Address 22, Reset: 0x0001, Hex = 16
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
CTRL F CD
0
0
0
0
0
0
CTRL M CD
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表 25. Register Address 22 Field Descriptions
Bit
Field
Type
Reset
Description
Controls number of octets per frame for channel CD.
D9:D8
CTRL F CD
R/W
00
00: F = 1 (default)
01: F = 2
Controls number of converters per link for channel CD.
01: M = 2. This is the only valid option (default)
D1:D0
CTRL M CD
R/W
01
7.6.1.16 Register Address 23
图 88. Register Address 23, Reset: 0x03E3, Hex = 17
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
CTRL K CD
0
0
0
CTRL L CD
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表 26. Register Address 23 Field Descriptions
Bit
Field
Type
Reset
Description
Controls number of frames per multi-frame for channel CD
0: K = 1 30 K = 31
1: K = 2 31 K = 32 (default)
And so forth
D9:D5
CTRL K CD
R/W
11111
Controls number of lanes for channel CD
01: L = 2
D1:D0
CTRL L CD
R/W
11
11: L = 4 (default)
7.6.1.17 Register Address 26
图 89. Register Address 26, Reset: 0x0020, Hex = 1A
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
INV SYNCb
CD
SCR EN
CD
0
0
0
0
0
0
0
0
0
HD CD
0
0
0
0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表 27. Register Address 26 Field Descriptions
Bit
Field
Type
Reset
Description
Inverts polarity of SYNCbCD input
0 = Normal operation
D6
INV SYNCb CD
R/W
0
1 = Polarity inverted
Enables high density mode for channel CD. This mode is
needed for LMFS = 4221.
0 = High density mode disabled for mode LMFS = 2221
D5
D4
HD CD
R/W
R/W
1
0
1 = High density mode enabled for mode LMFS = 4221 (default)
Enables scramble mode for channel CD
0 = Scramble mode disabled (default)
1 = Scramble mode enabled
SCR EN CD
46
版权 © 2015–2019, Texas Instruments Incorporated
ADS54J54
www.ti.com.cn
ZHCSD79A –JANUARY 2015–REVISED AUGUST 2019
7.6.1.18 Register Address 29
图 90. Register Address 29, Reset: 0x0000, Hex = 1D
D15 D14 D13 D12 D11 D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
TEST
PATTERN
EN CD
TEST
PATTERN
EN AB
TEST
PATTERN
0
0
0
0
0
0
0
0
0
0
0
0
0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表 28. Register Address 29 Field Descriptions
Bit
Field
Type
Reset
Description
Enables test pattern output for channel C and D
0 = Normal operation
D6
TEST PATTERN EN CD
R/W
0
1 = Test pattern output enabled
Enables test pattern output for channel A and B
0 = Normal operation
1 = Test pattern output enabled
D5
D4
TEST PATTERN EN AB
TEST PATTERN
R/W
R/W
0
0
Selects test pattern
0 = RAMP pattern
1 = Output alternates between 0x1555 and 0x2AAA
7.6.1.19 Register Address 30
图 91. Register Address 30, Reset: 0x0000, Hex = 1E
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
JESD SLEEP MODES – ENABLE pin
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表 29. Register Address 30 Field Descriptions
Bit
Field
Type
Reset
Description
Power-down function assigned to ENABLE pin. When any bit is
set, the corresponding function is always enabled regardless of
status of the ENABLE pin.
D9 = JESD PLL channel CD
D8 = JESD PLL channel AB
D7 = Lane DD1
0
0000
0000
JESD SLEEP MODES – ENABLE
pin
D9:D0
R/W
D6 = Lane DD0
D5 = Lane DC1
D4 = Lane DC0
D3 = Lane DB1
D2 = Lane DB0
D1 = Lane DA1
D0 = Lane DA0
SPACE
表 30. Configurations
Description
00 0000 0000
00 0000 0000
11 0000 0000
11 0000 0000
Global power down (default)
Standby
Deep sleep
Light sleep
版权 © 2015–2019, Texas Instruments Incorporated
47
ADS54J54
ZHCSD79A –JANUARY 2015–REVISED AUGUST 2019
www.ti.com.cn
7.6.1.20 Register Address 31
图 92. Register Address 31, Reset: 0xFFFF, Hex = 1F
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
1
1
1
1
1
1
JESD SLEEP MODES – SPI
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表 31. Register Address 31 Field Descriptions
Bit
Field
Type
Reset
Description
Power-down function controlled via SPI. When a bit is set to 0,
the function is powered down when ENABLE pin is high.
However register 0x1E has higher priority. For example, if D9
(JESD PLL channel CD) in 0x1E is enabled, it cannot be
powered down with the ENABLE pin.
D9 = JESD PLL channel CD
D8 = JESD PLL channel AB
D7 = Lane DD1
11
1111
1111
D15:D0
JESD SLEEP MODES – SPI
R/W
D6 = Lane DD0
D5 = Lane DC1
D4 = Lane DC0
D3 = Lane DB1
D2 = Lane DB0
D1 = Lane DA1
D0 = Lane DA0
SPACE
表 32. Configurations
Description
00 0000 0000
00 0000 0000
11 0000 0000
11 0000 0000
11 1111 1111
Global power down
Standby
Deep sleep
Light sleep
Normal operation (default)
Control power down function through ENABLE pin:
1. Configure power down mode in register 0x1E
2. Normal operation: ENABLE pin high
3. Power down mode: ENABLE pin low
Control power down function through SPI (ENABLE pin always high):
1. Assign power down mode in register 0x1F
2. Normal operation 0x1F is 0xFFFF
3. Power-down mode: configure power down mode in register 0x1F
48
版权 © 2015–2019, Texas Instruments Incorporated
ADS54J54
www.ti.com.cn
ZHCSD79A –JANUARY 2015–REVISED AUGUST 2019
7.6.1.21 Register Address 32
图 93. Register Address 32, Reset: 0x0000, Hex = 20
D15
D14
D13
JESD LANE POLARITY INVERT
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
PRBS EN
表 33. Register Address 32 Field Descriptions
Bit
Field
Type
Reset
Description
Set to 1 for polarity inversion
D15 = Lane DD1
D14 = Lane DD0
D13 = Lane DC1
D12 = Lane DC0
D11 = Lane DB1
D10 = Lane DB0
D9 = Lane DA1
0000
0000
D15:D8
JESD LANE POLARITY INVERT
R/W
D8 = Lane DA0
Outputs PRBS pattern selected in address 0x21 on the selected
serial output lanes
D7 = Lane DD1
D6 = Lane DD0
D5 = Lane DC1
D4 = Lane DC0
D3 = Lane DB1
D2 = Lane DB0
D1 = Lane DA1
D0 = Lane DA0
0000
0000
D7:D0
PRBS EN
R/W
7.6.1.22 Register Address 33
图 94. Register Address 33, Reset: 0x0000, Hex = 21
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
PRBS SEL
0
0
0
0
0
0
0
0
0
0
VREF SEL
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表 34. Register Address 33 Field Descriptions
Bit
Field
Type
Reset
Description
Selects different PRBS output pattern (these are not 8b/10b
encoded)
000 = 231 – 1
001 = 27 – 1
010 = 215 – 1
011 = 223 – 1
D14:D13 PRBS SEL
R/W
00
Selects different input full-scale amplitude by adjusting voltage
reference setting
000 = Full scale is 1.25 Vpp (default)
001 = Full scale is 1.35 Vpp
010 = Full scale is 1.5 Vpp
D2:D0
VREF SEL
R/W
000
011 = External
100 = Full scale is 1.15 Vpp
101 = Full scale is 1.0 Vpp
版权 © 2015–2019, Texas Instruments Incorporated
49
ADS54J54
ZHCSD79A –JANUARY 2015–REVISED AUGUST 2019
www.ti.com.cn
7.6.1.23 Register Address 99
图 95. Register Address 99,Reset: 0x0000, Hex = 63
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
TEMP SENSOR
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表 35. Register Address 99 Field Descriptions
Bit
Field
Type
Reset
Description
Value of on chip temperature sensor (read only). Value is 2s
D8:D0
TEMP SENSOR
R
undefined complement of die temperature sensor in °C
For example: 0x0032 equals 50°C
7.6.1.24 Register Address 100
图 96. Register Address 100, Reset: 0x0000, Hex = 64
D15
D14
PRE EMP SEL AB
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
PRE EMP EN AB
DCC EN AB
0
0
0
0
表 36. Register Address 100 Field Descriptions
Bit
Field
Type
Reset
Description
Selects pre-emphasis of serializers for channel A and B
0 = Pre-emphasis
D15:D12 PRE EMP SEL AB
R/W
0000
1 = De-emphasis
Enables pre-emphasis, 0 = disabled, 1 = enabled
D11 = Lane DB1
D11:D8
D7:D4
PRE EMP EN AB
DCC EN AB
R/W
R/W
0000
0000
D10 = Lane DB0
D9 = Lane DA1
D8 = Lane DA0
Enables the duty cycle correction circuit for each of the
serializers
D7 = Lane DB1
D6 = Lane DB0
D5 = Lane DA1
D4 = Lane DA0
50
版权 © 2015–2019, Texas Instruments Incorporated
ADS54J54
www.ti.com.cn
ZHCSD79A –JANUARY 2015–REVISED AUGUST 2019
7.6.1.25 Register Address 103
图 97. Register Address 103, Reset: 0x0000, Hex = 67
D15
D14
D13
D12
D11
D10
D9
OUTPUT CURRENT CONTROL AB
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
D8
D7
D6
D5
D4
D3
D2
D1
D0
表 37. Register Address 103 Field Descriptions
Bit
Field
Type
Reset
Description
Selects pre-emphasis current for the serializers. There are 4 bit
per serializer of channel A and B.
D15:D12 = Lane DB1
D11:D8 = Lane DB0
D7:D4 = Lane DA1
spacer
0000
0000
0000
0000
D15:D0
OUTPUT CURRENT CONTROL AB R/W
D3:D0 = Lane DA0
表 38. Pre-Emphasis Level is: Decimal Value / 30
Description
0000
Normal operation
0001
1 / 30
2 / 30
0010
and so forth
7.6.1.26 Register Address 104
图 98. Register Address 104, Reset: 0x0000, Hex = 68
D15
D14
PRE EMP SEL CD
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
PRE EMP EN CD
DCC EN CD
0
0
0
0
表 39. Register Address 104 Field Descriptions
Bit
Field
Type
Reset
Description
Selects pre-emphasis of serializers for channel C and D
0 = Pre-emphasis
D15:D12 PRE EMP SEL CD
0000
1 = De-emphasis
Enables pre-emphasis, 0 = disabled, 1 = enabled
D11 = Lane DD1
D11:D8
D7:D4
PRE EMP EN CD
DCC EN CD
0000
0000
D10 = Lane DD0
D9 = Land DC1
D8 = Lane DC0
Enables the duty cycle correction circuit for each of the
serializers
D7 = Lane DD1
D6 = Lane DD0
D5 = Land DC1
D4 = Lane DC0
版权 © 2015–2019, Texas Instruments Incorporated
51
ADS54J54
ZHCSD79A –JANUARY 2015–REVISED AUGUST 2019
www.ti.com.cn
7.6.1.27 Register Address 107
图 99. Register Address 107, Reset: 0x0000, Hex = 6B
D15
D14
D13
D12
D11
D10
D9
OUTPUT CURRENT CONTROL CD
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
D8
D7
D6
D5
D4
D3
D2
D1
D0
表 40. Register Address 107 Field Descriptions
Bit
Field
Type
Reset
Description
Selects pre-emphasis current for the serializers. There are 4 bit
per serializer of channel C and D.
D15:D12 = Lane DD1
D11:D8 = Lane DD0
D7:D4 = Land DC1
spacer
0000
0000
0000
0000
D15:D0
OUTPUT CURRENT CONTROL CD R/W
D3:D0 = Lane DC0
表 41. Pre-Emphasis Level is: Decimal Value / 30
Description
0000
Normal operation
0001
1 / 30
2 / 30
0010
And so forth
7.6.1.28 Register Address 108
图 100. Register Address 108, Hex = 3C
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
JESD PLL JESD PLL
CD AB
D0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表 42. Register Address 108 Field Descriptions(1)
Bit
D1
D0
Field
Type
R
Reset
Description
JESD PLL CD
JESD PLL CD
1
1
JESD PLL for channel CD lost lock when flag is set high
JESD PLL for channel AB lost lock when flag is set high
R
(1) Register values in address 0x6C are read only alarms
52
版权 © 2015–2019, Texas Instruments Incorporated
ADS54J54
www.ti.com.cn
ZHCSD79A –JANUARY 2015–REVISED AUGUST 2019
8 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
In the design of any application involving a high-speed data converter, particular attention should be paid the
design of the analog input, the clocking solution, and careful layout of the clock and analog signals. In addition,
the JESD204B interface means there now are high-speed serial lines that should be handled to preserve
adequate signal integrity at the device that receives the sample data. The ADS54J54 evaluation module (EVM) is
one practical example of the design of the analog input circuit and clocking solution, as well as a practical
example of good circuit board layout practices around the ADC.
8.2 Typical Application
The analog inputs of the ADS54J54 must be fully differential and biased to a desired common mode voltage,
VCM. Therefore, there will be a signal conditioning circuit for each of the analog inputs. If the amplitude of the
input circuit is such that no gain is needed to make full use of the full-scale range of the ADC, then a transformer
coupled circuit as in 图 101 may be used with good results. The transformer coupling is inherently low-noise, and
inherently AC-coupled so that the signal may be biased to VCM after the transformer coupling. If signal gain is
required, or the input bandwidth is to include the spectrum all the way down to DC such that AC coupling is not
possible, then an amplifier-based signal conditioning circuit would be required.
By using the simple drive circuit of 图 101, uniform performance can be obtained over a wide frequency range.
The buffers present at the analog inputs of the device help isolate the external drive source from the switching
currents of the sampling circuit.
0.1 ꢁF
T2
CHx_INP
T1
5 ꢀ
0.1 ꢁF
25 ꢀ
0.1 ꢁF
RIN
CIN
25 ꢀ
5 ꢀ
0.1 ꢁF
CHx_INM
1:1
1:1
Device
图 101. Input Drive Circuit
版权 © 2015–2019, Texas Instruments Incorporated
53
ADS54J54
ZHCSD79A –JANUARY 2015–REVISED AUGUST 2019
www.ti.com.cn
Typical Application (接下页)
0.1 µF
CLKINP
CLKINN
RT
RT
0.1 µF
0.1 µF
图 102. Recommended Differential Clock Driving Circuit
8.3 Design Requirements
The ADS54J54 requires a fully differential analog input with a full-scale range not to exceed 1.25 V peak to peak,
biased to a common mode voltage of 2.0 V. In addition the input circuit must provide proper transmission line
termination (or proper load resistors in an amplifier-based solution) so the input of the impedance of the ADC
analog inputs should be considered as well.
The clocking solution will have a direct impact on performance in terms of SNR, as shown in 图 103. The
ADS54J54 is capable of a typical SNR of 66 dBFS for input frequencies of about 100 MHz (in 14-bit bypass
digital mode), so we will want to have a clocking solution that can preserve this level of performance.
8.4 Detailed Design Procedure
The ADS54J54 has an input bandwidth of approximately 900 MHz, but we will consider an application involving
the first or second Nyquist zones, so we will limit the frequency bandwidth here to be under 250 MHz. We will
also consider a 50-ohm signal source, so the proper termination would be 50-Ω differential. As seen in 图 104
and 图 105, the input impedance of the analog input at 250 MHz is large compared to 50 Ω, so the proper
termination can be 50-Ω differential as shown in 图 101. Splitting the termination into two 25-Ω resistors with an
AC capacitor to ground provides a path to filter out any ripple on the common mode that may result from any
amplitude or phase imbalance of the differential input, improving SFDR performance. The ADS54J54 provides a
VCM output that may be used to bias the input to the desired level, but as seen in 图 67 the signal is internally
biased inside the ADC so an external biasing to VCM is not required. If an external biasing to VCM were to be
employed, the VCM voltage may be applied to the mid-point of the two 25-Ω termination resistors in 图 101.
For the clock input, 图 103 shows the SNR of the device above 100 MHz begins to degrade with external clock
jitter of greater than 100 fs rms, so we will recommend the clock source be limited to approximately 100 fS of rms
jitter. For the ADS54J54 EVM, the LMK04828 clock device is capable of providing a low-jitter sample clock as
well as providing the SYSREF signal required as shown in 图 62 and 图 63, so that clocking device is one good
choice for the clocking solution for the ADS54J54.
8.4.1 SNR and Clock Jitter
The signal-to-noise ratio of the channel is limited by three different factors: the quantization noise is typically not
noticeable in pipeline converters and is 84 dB for a 14-bit channel. The thermal noise limits the SNR at low input
frequencies while the clock jitter sets the SNR for higher input frequencies.
2
2
2
SNRQuantizatoin Noise
SNRThermal Noise
SNRJitter
20
≈
’
÷
≈
’
÷
≈
’
÷
-
-
-
∆
∆
∆
20
20
SNRADC[dBc] = -20∂log 10
+ 10
+ 10
∆
∆
÷
÷
◊
∆
∆
÷
÷
◊
∆
∆
÷
÷
◊
«
«
«
(1)
Calculate the SNR limitation due to sample clock jitter using the following:
54
版权 © 2015–2019, Texas Instruments Incorporated
ADS54J54
www.ti.com.cn
ZHCSD79A –JANUARY 2015–REVISED AUGUST 2019
Detailed Design Procedure (接下页)
SNRJitter [dBc] = -20∂log(2p∂ fin ∂TJitter
)
(2)
The total clock jitter (tJitter) has two components – the internal aperture jitter (98 fs for ADS54J54), which is set by
the noise of the clock input buffer, the external clock jitter, and the jitter from the analog input signal. Calculate
total clock jitter using the following:
2
TJitter
= )
(TJitter,Ext.Clock _Input )2 + (TAperture _ ADC
(3)
External clock jitter can be minimized by using high quality clock sources and jitter cleaners, as well as bandpass
filters at the clock input while a faster clock slew rate improves the channel aperture jitter.
The ADS54J54 has a thermal noise of 66 dBFS and internal aperture jitter of 98 fs. The SNR depending on
amount of external jitter for different input frequencies is shown in 图 103.
67
35 fs
50 fs
100 fs
150 fs
200 fs
66
65
64
63
62
61
10
20
30
40
50 60 70 80 100
Fin (MHz)
200
300
400 500 600 700800 1000
D00A
图 103. SNR vs Input Frequency and External Clock Jitter
8.5 Application Curves
图 104 and 图 105 show the differential impedance between the channel INP and INM pins. The impedance is
modeled as a parallel combination of RIN and CIN (RIN || 1 / jwCIN).
550
500
450
400
350
300
250
200
150
100
50
3.4E-12
3.3E-12
3.2E-12
3.1E-12
3E-12
2.9E-12
2.8E-12
2.7E-12
2.6E-12
2.5E-12
0
0
500 1000 1500 2000 2500 3000 3500 4000
Frequency (MHz)
0
500 1000 1500 2000 2500 3000 3500 4000
Frequency (MHz)
D032
D033
图 104. Equivalent R
图 105. Equivalent C
版权 © 2015–2019, Texas Instruments Incorporated
55
ADS54J54
ZHCSD79A –JANUARY 2015–REVISED AUGUST 2019
www.ti.com.cn
9 Power Supply Recommendations
The device requires a 1.8-V nominal supply for AVDDC, IOVDD, PLLVDD, and DVDD. The device also requires
a 1.9-V supply for AVDD18 and a 3.3-V supply for AVDD33. There are no specific sequence power-supply
requirements during device power-up. AVDD, DVDD, IOVDD, PLLVDD, and AVDD33 can power up in any order.
10 Layout
10.1 Layout Guidelines
The Device EVM layout can be used as a reference layout to obtain the best performance. A layout diagram of
the EVM top layer is provided in 图 107. Some important points to remember during laying out the board are:
•
•
•
Analog inputs are located on opposite sides of the device pinout to ensure minimum crosstalk on the package
level. To minimize crosstalk on-board, the analog inputs should exit the pinout in opposite directions, as
shown in the reference layout of 图 107 as much as possible.
In the device pinout, the sampling clock is located on a side perpendicular to the analog inputs in order to
minimize coupling between them. This configuration is also maintained on the reference layout of 图 107 as
much as possible.
Digital outputs should be kept away from the analog inputs. When these digital outputs exit the pinout, the
digital output traces should not be kept parallel to the analog input traces because this configuration may
result in coupling from digital outputs to analog inputs and degrade performance. The digital sample data rate
can be as high as 5.0 Gsps, so care must be taken to maintain the signal integrity of these signals. A low-loss
dielectric circuit board is recommended or else these traces should be kept as short as possible. These
traces should be kept away from the analog inputs ad n clock input to the device as well.
•
At each power-supply pin, a 0.1-μF decoupling capacitor should be kept close to the device. A separate
decoupling
capacitor
group
consisting
of
a
parallel
combination
of
10-μF,
1-μF, and 0.1-μF capacitors can be kept close to the supply source.
10.1.1 CML SerDes Transmitter Interface
Each of the 5 Gbps SerDes CML transmitter outputs requires AC coupling between transmitter and receiver. The
differential pair should be terminated with a 100-Ω resistor as close to the receiving device as possible to avoid
unwanted reflections and signal degradation.
10.2 Layout Example
Board Trace
Board Trace
图 106. Layout Example Schematic
56
版权 © 2015–2019, Texas Instruments Incorporated
ADS54J54
www.ti.com.cn
ZHCSD79A –JANUARY 2015–REVISED AUGUST 2019
Layout Example (接下页)
图 107. Top and Bottom Layers
版权 © 2015–2019, Texas Instruments Incorporated
57
ADS54J54
ZHCSD79A –JANUARY 2015–REVISED AUGUST 2019
www.ti.com.cn
11 器件和文档支持
11.1 商标
PowerPAD is a trademark of Texas Instruments.
11.2 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时,应将导线一起截短或将装置放置于导电泡棉中,以防止 MOS 门极遭受静电损
伤。
11.3 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更,恕不另行通知,且
不会对此文档进行修订。如需获取此数据表的浏览器版本,请查阅左侧的导航栏。
58
版权 © 2015–2019, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
ADS54J54IRGCR
ADS54J54IRGCT
ACTIVE
ACTIVE
VQFN
VQFN
RGC
RGC
64
64
2000 RoHS & Green
250 RoHS & Green
NIPDAU
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 85
-40 to 85
AZ54J54
AZ54J54
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
1-Sep-2021
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
ADS54J54IRGCR
VQFN
RGC
64
2000
330.0
16.4
9.3
9.3
1.5
12.0
16.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
1-Sep-2021
*All dimensions are nominal
Device
Package Type Package Drawing Pins
VQFN RGC 64
SPQ
Length (mm) Width (mm) Height (mm)
350.0 350.0 43.0
ADS54J54IRGCR
2000
Pack Materials-Page 2
GENERIC PACKAGE VIEW
RGC 64
9 x 9, 0.5 mm pitch
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224597/A
www.ti.com
PACKAGE OUTLINE
RGC0064H
VQFN - 1 mm max height
S
C
A
L
E
1
.
5
0
0
PLASTIC QUAD FLATPACK - NO LEAD
9.15
8.85
A
B
PIN 1 INDEX AREA
9.15
8.85
1.0
0.8
C
SEATING PLANE
0.08 C
0.05
0.00
2X 7.5
SYMM
EXPOSED
THERMAL PAD
(0.2) TYP
17
32
16
33
65
SYMM
2X 7.5
7.4 0.1
60X
0.5
1
48
0.30
0.18
64X
49
64
PIN 1 ID
0.1
C A B
0.5
0.3
64X
0.05
4219011/A 05/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RGC0064H
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
7.4)
SEE SOLDER MASK
DETAIL
SYMM
64X (0.6)
49
64
64X (0.24)
1
48
60X (0.5)
(3.45) TYP
(R0.05) TYP
(1.16) TYP
65
SYMM
(8.8)
(
0.2) TYP
VIA
33
16
32
17
(1.16) TYP
(3.45) TYP
(8.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
METAL UNDER
SOLDER MASK
METAL EDGE
EXPOSED METAL
SOLDER MASK
OPENING
EXPOSED
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4219011/A 05/2018
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
RGC0064H
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
SYMM
64X (0.6)
64
49
64X (0.24)
1
48
60X (0.5)
(R0.05) TYP
(1.16) TYP
65
SYMM
(8.8)
(0.58)
36X ( 0.96)
33
16
17
32
(0.58)
(1.16)
TYP
(8.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 MM THICK STENCIL
SCALE: 10X
EXPOSED PAD 65
61% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
4219011/A 05/2018
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
重要声明和免责声明
TI 提供技术和可靠性数据(包括数据表)、设计资源(包括参考设计)、应用或其他设计建议、网络工具、安全信息和其他资源,不保证没
有瑕疵且不做出任何明示或暗示的担保,包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担保。
这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任:(1) 针对您的应用选择合适的 TI 产品,(2) 设计、验
证并测试您的应用,(3) 确保您的应用满足相应标准以及任何其他安全、安保或其他要求。这些资源如有变更,恕不另行通知。TI 授权您仅可
将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。您无权使用任何其他 TI 知识产权或任何第三方知
识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成本、损失和债务,TI 对此概不负责。
TI 提供的产品受 TI 的销售条款 (https:www.ti.com.cn/zh-cn/legal/termsofsale.html) 或 ti.com.cn 上其他适用条款/TI 产品随附的其他适用条款
的约束。TI 提供这些资源并不会扩展或以其他方式更改 TI 针对 TI 产品发布的适用的担保或担保免责声明。IMPORTANT NOTICE
邮寄地址:上海市浦东新区世纪大道 1568 号中建大厦 32 楼,邮政编码:200122
Copyright © 2021 德州仪器半导体技术(上海)有限公司
相关型号:
©2020 ICPDF网 联系我们和版权申明