BQ25606RGET [TI]
具有高输入电压和电源路径的独立型单节 3A 快速充电器 | RGE | 24 | -40 to 85;型号: | BQ25606RGET |
厂家: | TEXAS INSTRUMENTS |
描述: | 具有高输入电压和电源路径的独立型单节 3A 快速充电器 | RGE | 24 | -40 to 85 |
文件: | 总48页 (文件大小:3810K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
BQ25606
ZHCSGR3C –MAY 2017 –REVISED SEPTEMBER 2021
BQ25606 独立单节3.0A 降压电池充电器
– ±5% 0.5A、1.2A 和1.8A 输入电流调节
• 安全相关认证:
1 特性
• 高效1.5MHz 同步开关模式降压充电器
– 经IEC 62368-1 CB 认证
– 在2A 电流(5V 输入)下具有92% 的充电效率
– 针对USB 电压输入(5V) 进行了优化
• 支持USB On-The-Go (OTG)
2 应用
• EPOS、便携式扬声器
• 手机附件
• 医疗设备
– 具有高达1.2A 输出的升压转换器
– 在1A 输出下具有92% 的升压效率
– 精确的恒定电流(CC) 限制
– 高达500µF 容性负载的软启动
– 输出短路保护
3 说明
BQ25606 是高度集成的独立 3.0A 开关模式电池充电
管理和系统电源路径管理器件,适用于单节锂离子和锂
聚合物电池。该解决方案在系统和电池之间高度集成输
入反向阻断 FET(RBFET,Q1)、高侧开关 FET
(HSFET,Q2)、低侧开关 FET(LSFET,Q3)以
及电池 FET(BATFET,Q4)。其低阻抗电源路径对
开关模式运行效率进行了优化、缩短了电池充电时间并
延长了放电阶段的电池使用寿命。
• 单个输入,支持USB 输入和高电压适配器
– 支持3.9V 至13.5V 输入电压范围,绝对最大输
入电压额定值为22V
– 通过高达4.6V 的输入电压限制(VINDPM) 进行
最大功率跟踪
– VINDPM 阈值自动跟踪电池电压
– 自动检测USB SDP、DCP 以及非标准适配器
• 高电池放电效率,电池放电MOSFET 为19.5mΩ
• 窄VDC (NVDC) 电源路径管理
器件信息(1)
封装尺寸(标称值)
器件型号
BQ25606
封装
VQFN (24)
4.00mm × 4.00mm
– 无需电池或深度放电的电池即可瞬时启动
– 电池充电模式下实现理想的二极管运行
• 高集成度,包括所有MOSFET、电流感测和环路补
偿
(1) 如需了解所有可用封装,请参阅数据表末尾的可订购产品附
录。
• 在系统待机电压下具有58µA 的低电池泄漏电流
• 高精度
USB
VBUS
SW
– 充电电压调节范围为±0.5%
– ±6% 1.2A 和1.8A 充电电流调节
BTST
SYS
BAT
ILIM
ICHG
CE
ICHG
REGN
+
VSET
TS
简化版应用
本文档旨在为方便起见,提供有关TI 产品中文版本的信息,以确认产品的概要。有关适用的官方英文版本的最新信息,请访问
www.ti.com,其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前,请务必参考最新版本的英文版本。
English Data Sheet: SLUSCK6
BQ25606
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ZHCSGR3C –MAY 2017 –REVISED SEPTEMBER 2021
Table of Contents
9.3 Feature Description...................................................19
10 Application and Implementation................................26
10.1 Application Information........................................... 26
10.2 Typical Application.................................................. 27
11 Power Supply Recommendations..............................34
12 Layout...........................................................................35
12.1 Layout Guidelines................................................... 35
12.2 Layout Example...................................................... 35
13 Device and Documentation Support..........................37
13.1 Device Support....................................................... 37
13.2 接收文档更新通知................................................... 37
13.3 支持资源..................................................................37
13.4 Trademarks.............................................................37
13.5 Electrostatic Discharge Caution..............................37
13.6 术语表..................................................................... 37
14 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 说明(续).........................................................................4
6 Device Comparison Table...............................................5
7 Pin Configuration and Functions...................................6
8 Specifications.................................................................. 8
8.1 Absolute Maximum Ratings........................................ 8
8.2 ESD Ratings............................................................... 8
8.3 Recommended Operating Conditions.........................8
8.4 Thermal Information....................................................9
8.5 Electrical Characteristics.............................................9
8.6 Timing Requirements................................................13
8.7 Typical Characteristics..............................................15
9 Detailed Description......................................................17
9.1 Overview...................................................................17
9.2 Functional Block Diagram.........................................18
Information.................................................................... 38
4 Revision History
注:以前版本的页码可能与当前版本的页码不同
Changes from Revision B (November 2019) to Revision C (September 2021)
Page
• 添加了IEC 62368-1 CB 特性..............................................................................................................................1
• 删除了整个数据表中的WEBENCH.................................................................................................................... 1
• 从节5 中的第三段中删除了“为零”..................................................................................................................4
• Added 节6 .........................................................................................................................................................5
• Added 节9.3.4.1 ..............................................................................................................................................21
• Added 节9.3.4.2 ..............................................................................................................................................21
• Added 节9.3.4.3 ..............................................................................................................................................21
• Added sentence to third paragraph in 节9.3.5.4 .............................................................................................22
• Changed "fault" to "the timer" in last paragraph of 节9.3.5.6 ..........................................................................24
• Added 节9.3.6 .................................................................................................................................................24
• Added 节9.3.6.1 ..............................................................................................................................................24
• Added 节9.3.6.2 ..............................................................................................................................................24
• Added 表10-1 ..................................................................................................................................................27
• Changed > to ≤in last paragraph in 节10.2.2.3 ............................................................................................ 28
Changes from Revision A (August 2017) to Revision B (November 2019)
Page
• 更改了“应用”部分........................................................................................................................................... 1
Changes from Revision * (May 2017) to Revision A (August 2017)
Page
• 更改了数据表标题...............................................................................................................................................1
• 从节1 中删除了“200nS 快速关闭”................................................................................................................. 1
• 更改了简化应用原理图........................................................................................................................................1
• Changed ACDRV pin references to "NC" in 节7 section................................................................................... 6
• Deleted ACDRV pin references from Pin Functions table.................................................................................. 6
• Changed VAC pin description in Pin Functions table......................................................................................... 6
• Deleted ACDRV pin references from 节8.1 table...............................................................................................8
• Added 节8.2 table..............................................................................................................................................8
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• Deleted VAC debounce time fromTiming Requirements table..........................................................................13
• Changed 节9.2 ................................................................................................................................................18
• Changed Power Up from Input Source section................................................................................................ 19
• Deleted Power Up OVPFET section.................................................................................................................19
• Deleted OVPFET Startup Control timing illustration ........................................................................................19
• Added subsection explaining D+/D–detection ...............................................................................................19
• Changed Input Overvoltage (ACOV) section....................................................................................................25
• Changed BQ25606 Application Diagram schematic.........................................................................................27
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5 说明(续)
BQ25606 可为独立充电器和便携式设备提供快速充电功能和高输入电压支持。其输入电压和电流调节可以为电池
提供最大的充电功率。它还集成了自举二极管以进行高侧栅极驱动,从而简化系统设计。
该器件支持多种输入源,包括标准 USB 主机端口、USB 充电端口以及兼容USB 的高电压适配器。该器件根据内
置 USB 接口设置默认输入电流限值。该器件符合 USB 2.0 和 USB 3.0 电源规范,具有输入电流和电压调节功
能。当内置 USB 接口确定输入适配器未知时,该器件的输入电流限值由 ILIM 引脚设置电阻器值决定。该器件还
具有高达1.2A 的恒定电流限制能力,能够为VBUS 提供5.15V 的电压,符合USB On-the-Go (OTG) 运行功率额
定值规范。
电源路径管理将系统电压调节至稍高于电池电压的水平,但是不会下降至 3.5V 最小系统电压以下。借助于这个特
性,即使在电池电量完全耗尽或者电池被拆除时,系统也能保持运行。当达到输入电流限值或电压限值时,电源
路径管理自动将充电电流减少。随着系统负载持续增加,电源路径将使电池放电,直到满足系统电源需求。该补
充模式可防止输入源过载。
此器件在无需软件控制情况下启动并完成一个充电周期。它检测电池电压并通过三个阶段为电池充电:预充电、
恒定电流和恒定电压。在充电周期的末尾,当充电电流低于预设限值并且电池电压高于再充电阈值时,充电器自
动终止。如果已完全充电的电池降至再充电阈值以下,则充电器自动启动另一个充电周期。
此充电器提供针对电池充电和系统运行的多种安全特性,其中包括电池负温度系数热敏电阻监视、充电安全性计
时器和过压/过流保护。当结温超过 110°C 时,热调节会减小充电电流。STAT 输出报告充电状态和任何故障状
况。其他安全特性包括针对充电和升压模式的电池温度感应、热调节和热关断以及输入UVLO 和过压保护。
该器件采用24 引脚4mm x 4mm QFN 封装。
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6 Device Comparison Table
BQ25606
58 μA
BQ25616
9.5 μA
BQ25616J
9.5 μA
130 ns
Quiescent battery current (BAT,SYS,SW)
VBUS OVP reaction-time
Input voltage regulation accuracy
TS profile
200 ns
130 ns
±3%
±2%
±2%
JEITA
Hot/Cold
20 hr
JEITA
Charge safety timer accuracy
Charge voltage limit
10 hr
20 hr
4.2 V/4.35 V/4.4 V
±0.5%
4.1 V/4.2 V/4.35 V
±0.4%
4.1 V/4.2 V/4.35 V
±0.4%
Battery voltage regulation
ACDRV
No
Yes
Yes
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7 Pin Configuration and Functions
VAC
NC
1
2
3
4
5
6
18
17
16
15
14
13
GND
GND
SYS
SYS
BAT
BAT
D+
Thermal
Pad
Dœ
STAT
OTG
7
8
9
10 11 12
(Not to scale)
图7-1. BQ25606 RGE Package 24-Pin VQFN Top View
表7-1. Pin Functions
DESCRIPTION
PIN
NAME
I/O
NO.
2
NC
No connection. This pin must be floating.
13
14
Battery connection point to the positive terminal of the battery pack. The internal current sensing resistor
is connected between SYS and BAT. Connect a 10-µF capacitor closely to the BAT pin.
BAT
P
PWM high side driver positive supply. internally, the BTST is connected to the cathode of the boost-strap
diode. Connect a 0.047-μF bootstrap capacitor from SW to BTST.
BTST
CE
21
9
P
DI
Charge enable pin. When this pin is driven low, battery charging is enabled.
Positive line of the USB data line pair. D+/D–based USB host/charging port detection. The detection
includes data contact detection (DCD), primary and secondary detection in BC1.2 and nonstandard
adaptors.
D+
3
4
AIO
AIO
Negative line of the USB data line pair. D+/D–based USB host/charging port detection. The detection
includes data contact detection (DCD), primary and secondary detection in BC1.2 and nonstandard
adaptors.
D–
17
18
GND
P
Power ground and signal ground.
ICHG pin sets the charge current limit. A resistor is connected from ICHG pin to ground to set charge
current limit as ICHG = KICHG/RICHG. The acceptable range for charge current is 300 mA to 3000 mA.
ICHG
10
AI
ILIM sets the input current limit. A resistor is connected from ILIM pin to ground to set the input current
limit as IINDPM = KILIM/RILIM. The acceptable range for ILIM current is 500 mA to 3200 mA.
The resistor based input current limit is effective only when the input adapter is detected as unknown.
Otherwise, the input current limit is determined by D+/D–detection outcome.
ILIM
8
AI
OTG
PG
6
7
DI
Boost mode enable pin. When this pin is pulled HIGH, OTG is enabled. OTG cannot be floating.
Open drain active low power good indicator. Connect to the pull up rail through a 10-kΩresistor. LOW
indicates a good input if the input voltage is between UVLO and ACOV, above SLEEP mode threshold,
and input current limit is above 30 mA.
DO
Connected to the drain of the reverse blocking MOSFET (RBFET) and the drain of HSFET. Connect a
10-μF ceramic capacitor between PMID and GND.
PMID
23
P
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表7-1. Pin Functions (continued)
PIN
I/O
DESCRIPTION
NAME
NO.
PWM low side driver positive supply output. Internally, REGN is connected to the anode of the boost-
strap diode. Connect a 4.7-μF (10-V rating) ceramic capacitor from REGN to analog GND. The
capacitor should be placed close to the IC.
REGN
22
P
Open-drain interrupt output. Connect the STAT pin to a logic rail via 10-kΩ resistor. The STAT pin
indicates charger status.
STAT
5
DO
Charge in progress: LOW
Charge complete or charger in SLEEP mode: HIGH
Charge suspend (fault response): Blink at 1 Hz.
19
20
Switching node connecting to output inductor. Internally SW is connected to the source of the n-channel
HSFET and the drain of the n-channel LSFET. Connect a 0.047-μF bootstrap capacitor from SW to
BTST.
SW
P
P
15
16
Converter output connection point. The internal current sensing resistor is connected between SYS and
BAT. Connect a 20-µF capacitor close to the SYS pin.
SYS
Temperature qualification voltage input to support JEITA profile. Connect a negative temperature
coefficient thermistor. Program temperature window with a resistor divider from REGN to TS to GND.
Charge suspends when TS pin voltage is out of range. Recommend 103AT-2 thermistor.
TS
11
1
AI
AI
P
VAC
VBUS
Input voltage sensing. This pin must be shorted to the VBUS pin.
Charger input voltage. The internal n-channel reverse block MOSFET (RBFET) is connected between
VBUS and PMID with VBUS on source. Place a 1-uF ceramic capacitor from VBUS to GND and place it
as close as possible to the IC.
24
VSET pin sets default battery charge voltage in the BQ25606. Program battery regulation voltage with a
resistor pull-down from VSET to GND.
RPD > 50 kΩ(float pin) = 4.208 V
RPD < 500 Ω(short to GND) = 4.352 V
5 kΩ< RPD < 25 kΩ= 4.400 V
VSET
12
AI
P
Ground reference for the device that is also the thermal pad used to conduct heat from the device. This
connection serves two purposes. The first purpose is to provide an electrical ground connection for the
device. The second purpose is to provide a low thermal-impedance path from the device die to the PCB.
This pad should be tied externally to a ground plane.
Thermal Pad
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8 Specifications
8.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
UNIT
Voltage Range (with respect to
GND)
VAC
22
V
–2
Voltage Range (with respect to
VBUS (converter not switching)(2)
GND)
22
22
V
V
–2
Voltage Range (with respect to
BTST, PMID (converter not switching)(2)
GND)
–0.3
Voltage Range (with respect to
GND)
SW
16
7
V
V
–2
Voltage Range (with respect to
GND)
BTST to SW
–0.3
Voltage Range (with respect to
GND)
7
7
V
V
D+, D–
–0.3
–0.3
Voltage Range (with respect to
GND)
REGN, TS, CE, PG, BAT, SYS (converter not switching)
Output Sink Current
STAT
6
7
mA
V
Voltage Range (with respect to
GND)
VSET, ILIM, ICHG, OTG
–0.3
–0.3
Voltage Range (with respect to
GND)
PGND to GND (QFN package only)
0.3
V
Operating junction temperature, TJ
Storage temperature, Tstg
150
150
°C
°C
–40
–65
(1) Stresses beyond those listed under Absolute maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability. All voltage values are with respect to the network ground terminal unless otherwise noted.
(2) VBUS is specified up to 22 V for a maximum of one hour at room temperature
8.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per ANSI/
ESDA/JEDEC JS-001, all pins(1)
±2000
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per
JEDEC specification JESD22-C101, all
pins(2)
±250
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
8.3 Recommended Operating Conditions
MIN
NOM
MAX UNIT
VBUS
Iin
Input voltage
3.9
13.5 (1)
V
A
A
V
A
A
Input current (VBUS)
Output current (SW)
Battery voltage
3.25
3.0
4.4
3.0
6
ISYSOP
VBATOP
IBATOP
IBATOP
Fast charging current
Discharging current (continuous)
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8.3 Recommended Operating Conditions (continued)
MIN
NOM
MAX UNIT
85 °C
TA
Operating ambient temperature
–40
(1) The inherent switching noise voltage spikes should not exceed the absolute maximum voltage rating on either the BTST or SW pins. A
tight layout minimizes switching noise.
8.4 Thermal Information
BQ25606
THERMAL METRIC (1)
RGE (VQFN)
UNIT
24 PINS
31.9
27
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
9.2
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.4
ΨJT
9.2
ΨJB
RθJC(bot)
2.8
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics Application
Report.
8.5 Electrical Characteristics
VVAC_PRESENT < VVAC < VVAC_OV and VVAC > VBAT + VSLEEP, TJ = –40°C to 125°C and TJ = 25°C for typical values (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
QUIESCENT CURRENTS
VBAT = 4.5 V, VBUS < VAC-UVLOZ
leakage between BAT and VBUS,
TJ< 85°C
,
Battery discharge current (BAT, SW,
SYS) in buck mode
IBAT
5
µA
Battery discharge current (BAT, SW,
SYS)
IBAT
VBAT = 4.5 V, No VBUS, TJ < 85°C
58
85
3
µA
Input supply current (VBUS) in buck
mode
VVBUS = 12 V, VVBUS > VVBAT
converter not switching
,
IVBUS
1.5
mA
VVBUS > VUVLO, VVBUS > VVBAT
converter switching, VBAT = 3.8V,
ISYS = 0A
,
Input supply current (VBUS) in buck
mode
IVBUS
3
3
mA
mA
VBAT = 4.2 V, boost mode, IVBUS
0 A, converter switching
=
IBOOST
Battery discharge current in boost mode
VBUS, VAC AND BAT PIN POWER UP
VBUS_OP
VBUS operating range
REGN turn-on threshold
VVBUS rising
VVAC rising
3.9
13.5
3.97
V
V
VVAC_PRESENT
3.36
3.65
300
VVAC_PRESENT_H
mV
VVAC falling
YS
(VVAC–VVBAT ), VBUSMIN_FALL
BAT ≤VREG, VAC falling
≤
≤
VSLEEP
Sleep mode falling threshold
Sleep mode rising threshold
37
76
126
mV
mV
V
(VVAC–VVBAT ), VBUSMIN_FALL
BAT ≤VREG, VAC rising
VSLEEPZ
130
220
350
V
VVAC_OV_RISE
VVAC_OV_HYS
VAC Overvoltage rising threshold
VAC Overvoltage hysteresis
VAC rising
VAC falling
13.5
14.28
520
14.91
V
mV
Battery depletion falling threshold (Q4
turn-off threshold)
VBAT_DPL_FALL
VBAT_DPL_RISE
VBAT falling
VBAT rising
2.15
2.35
2.6
V
V
Battery Depletion rising threshold (Q4
turn-on threshold)
2.82
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8.5 Electrical Characteristics (continued)
VVAC_PRESENT < VVAC < VVAC_OV and VVAC > VBAT + VSLEEP, TJ = –40°C to 125°C and TJ = 25°C for typical values (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VBAT rising
MIN
TYP
180
3.8
MAX
UNIT
mV
V
VBAT_DPL_HYST
VBUSMIN_FALL
VBUSMIN_HYST
IBADSRC
Battery Depletion rising hysteresis
Bad adapter detection falling threshold
Bad adapter detection hysteresis
Bad adapter detection current source
VBUS falling
3.65
3.93
200
30
mV
mA
Sink current from VBUS to GND
POWER PATH
VVBAT < VSYS_MIN = 3.5V, charge
enabled or disabled
VSYS_MIN
VSYS
System regulation voltage
System regulation voltage
3.5
3.68
V
V
ISYS = 0 A, VVBAT > VSYSMIN
,
VBAT + 50
mV
charge disabled
Top reverse blocking MOSFET on-
resistance between VBUS and PMID -
Q1
RON(RBFET)
45
-40°C≤TA ≤125°C
mΩ
Top switching MOSFET on-resistance
between PMID and SW - Q2
VREGN = 5 V , -40°C≤TA ≤
125°C
RON(HSFET)
RON(LSFET)
VFWD
62
70
30
mΩ
mΩ
mV
Bottom switching MOSFET on-
resistance between SW and GND - Q3
VREGN = 5 V , -40°C≤TA ≤
125°C
BATFET forward voltage in supplement
mode
QFN package, Measured from
BAT to SYS, VBAT = 4.2V, TJ =
25°C
RON(BAT-SYS)
SYS-BAT MOSFET on-resistance
19.5
19.5
24
30
mΩ
mΩ
QFN package, Measured from
BAT to SYS, VBAT = 4.2V, TJ = –
40 - 125°C
RON(BAT-SYS)
BATTERY CHARGER
SYS-BAT MOSFET on-resistance
RVSET > 50 kΩ, –40 ≤TJ ≤
85°C
4.187
4.330
4.378
4.208
4.352
4.4
4.229
4.374
4.422
V
V
V
RVSET < 500 Ω, –40 ≤TJ ≤
85°C
VBATREG
Charge voltage
RVSET = 10 kΩ, –40 ≤TJ ≤
85°C
VBAT = 4.208 V or VBAT = 4.352 V,
–40 ≤TJ ≤85°C
VBATREG_ACC
Charge voltage setting accuracy
0.5%
3000
715
–0.5%
0
ICHG_REG_RANGE Charge current regulation range
mA
mA
RICHG = 1100 Ω, VVBAT = 3.1 V or
VVBAT = 3.8 V
ICHG_REG
Charge current regulation
516
615
RICHG = 1100 Ω, VVBAT = 3.1 V or
VVBAT = 3.8 V
ICHG_REG_ACC
ICHG_REG
Charge current regulation accuracy
Charge current regulation
-16%
1.14
16%
1.28
1.218
A
RICHG = 562 Ω, VVBAT = 3.1 V or
VVBAT = 3.8 V
RICHG = 562 Ω, VBAT = 3.1 V or
VBAT = 3.8 V
ICHG_REG
ICHG_REG
ICHG_REG_ACC
KICHG
Charge current regulation accuracy
Charge current regulation
-6%
1.715
-5%
6%
1.89
5%
RICHG = 372 Ω, VVBAT = 3.1 V or
VVBAT = 3.8 V
1.813
677
A
RICHG = 372 Ω, VVBAT = 3.1 V or
VVBAT = 3.8 V
Charge current regulation accuracy
Charge current regulation setting ratio
RICHG = 372 Ω, 562 ΩVVBAT
=
639
715
6%
A×Ω
3.1 V or VVBAT = 3.8 V
Charge current regulation setting ratio
accuracy
RICHG = 372Ω, 562 ΩVVBAT
=
KICHG_ACC
-6%
3.1 V or VVBAT = 3.8 V
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8.5 Electrical Characteristics (continued)
VVAC_PRESENT < VVAC < VVAC_OV and VVAC > VBAT + VSLEEP, TJ = –40°C to 125°C and TJ = 25°C for typical values (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
Fast charge to precharge
Pre-charge to fast charge
MIN
2.67
3.0
TYP
2.8
MAX
2.87
3.24
UNIT
V
VBATLOWV_FALL Battery LOWV falling threshold
VBATLOWV_RISE Battery LOWV rising threshold
3.1
V
RICHG = 1100 Ω, VVBAT = 2.6 V,
IPRECHG = 5% of ICHG = 615mA
IPRECHG
Precharge current regulation
21
3.4%
48
38
6.2%
67
mA
Percentage of ICHG,RICHG = 1100
Ω, VVBAT = 2.6 V, ICHG = 615mA
IPRECHG_ACC
IPRECHG
IPRECHG_ACC
IPRECHG
IPRECHG_ACC
ITERM
Precharge current regulation accuracy
Precharge current regulation
RICHG = 562 Ω, VVBAT = 2.6 V,
IPRECHG = 5% of ICHG = 1.218A
mA
Percentage of ICHG,RICHG = 562
Ω, V1330 = 2.6 V, ICHG = 1.218A
Precharge current regulation accuracy
Precharge current regulation
3.9%
76
5.5%
97
RICHG = 372 Ω, VVBAT = 2.6 V,
IPRECHG = 5% of ICHG = 1.813A
mA
mA
Percentage of ICHG,RICHG = 372
Ω, VVBAT = 2.6 V, ICHG = 1.813A
Precharge current regulation accuracy
Termination current regulation
4.1%
26
5.4%
100
RICHG = 562 Ω, VVBAT
=
4.35V,CHG = 1.218A
Percentage of ICHG, RICHG = 562
Ω, VVBAT = 4.35 V, ICHG = 1.218 A
ITERM_ACC
ITERM
Termination current regulation accuracy
Termination current regulation
2.1%
56
8.3%
126
RICHG = 372 Ω, VVBAT = 4.35 V,
ICHG = 1.813 A
100
mA
Percentage of ICHG, RICHG = 372
Ω, VVBAT = 4.35 V, ICHG = 1.813 A
ITERM_ACC
Termination current regulation accuracy
3.0%
7.0%
VSHORT
VSHORTZ
ISHORT
Battery short voltage
VVBAT falling
VVBAT rising
VVBAT < VSHORTZ
VBAT falling
1.85
2.05
70
2
2.25
90
2.15
2.35
110
V
Battery short voltage
V
Battery short current
mA
mV
mA
VRECHG
ISYSLOAD
Recharge Threshold below VBAT_REG
System discharge load current
87
121
30
156
VSYS = 4.2 V
INPUT VOLTAGE AND CURRENT REGULATION
VDPM_VBAT Input voltage regulation limit
VDPM_VBAT_ACC Input voltage regulation accuracy
VVBAT < 4.1 V (VVBAT= 3.6 V)
VVBAT < 4.1 V (VVBAT = 3.6 V)
4.171
4.3
4.429
3%
V
–3%
VVBUS = 5 V, USB500 charge port
detected by DPDM , –40 ≤TJ ≤
85°C
IINDPM
IINDPM
IINDPM
IINDPM
IINDPM_ACC
KILIM
USB input current regulation limit
Input current regulation limit
448
505
500
550
mA
mA
mA
A
RILIM = 910 Ω, unknown adaptor
detected by DPDM , –40 ≤TJ ≤
85°C
526
1276
1.8
RILIM = 374 Ω, unknown adaptor
detected by DPDM , –40 ≤TJ ≤
85°C
Input current regulation limit accuracy
Input current regulation limit
1220
1.73
–5%
459
1330
1.871
5%
RILIM = 265 Ω, unknown adaptor
detected by DPDM , –40 ≤TJ ≤
85°C
RILIM = 265 Ω, 374 Ω, 910 Ω,
unknown adaptor detected by
DPDM , –40 ≤TJ ≤85°C
Input current regulation limit accuracy
RILIM = 910 Ω, 374 Ω, 265 Ω,
unknown adaptor detected by
DPDM, –40 ≤TJ ≤85°C
Input current setting ratio, ILIM = KILIM
RILIM
/
478
500
A×Ω
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8.5 Electrical Characteristics (continued)
VVAC_PRESENT < VVAC < VVAC_OV and VVAC > VBAT + VSLEEP, TJ = –40°C to 125°C and TJ = 25°C for typical values (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
RILIM = 910 Ω, 374 Ω, 265 Ω,
unknown adaptor detected by
DPDM, –40 ≤TJ ≤85°C
Input current setting ratio, ILIM = KILIM
RILIM
/
KILIM_ACC
5%
–5%
Input current limit during system start-up
sequence
IIN_START
200
mA
BAT PIN OVERVOLTAGE PROTECTION
VBAT rising, as percentage of
VBAT_REG
VBATOVP_RISE
VBATOVP_FALL
Battery overvoltage threshold
Battery overvoltage threshold
103%
101%
104%
102%
105%
103%
VBAT falling, as percentage of
VBAT_REG
THERMAL REGULATION AND THERMAL SHUTDOWN
Junction Temperature Regulation
TJUNCTION_REG
Threshold
110
°C
TSHUT
Thermal Shutdown Rising Temperature Temperature Increasing
Thermal Shutdown Hysteresis
160
30
°C
°C
TSHUT_HYST
JEITA THERMISTOR COMPARATOR (BUCK MODE)
T1 (0°C) threshold, Charge suspended Charger suspends charge. As
VT1
VT1
VT2
VT2
72.4%
69%
73.3%
71.5%
68%
74.2%
74%
T1 below this temperature.
Percentage to VREGN
Falling
As Percentage to VREGN
T2 (10°C) threshold, Charge back to
ICHG/2 and 4.2 V below this temperature
As percentage of VREGN
As Percentage to VREGN
67.2%
66%
69%
Falling
66.8%
67.7%
T3 (45°C) threshold, charge back to
ICHG and 4.05V above this
temperature.
Charger suspends charge. As
Percentage to VREGN
VT3
43.8%
44.7%
45.8%
VT3
VT5
VT5
Falling
As Percentage to VREGN
As Percentage to VREGN
As Percentage to VREGN
45.1%
33.7%
34.5%
45.7%
34.2%
35.3%
46.2%
35.1%
36.2%
T5 (60°C) threshold, charge suspended
above this temperature.
Falling
COLD OR HOT THERMISTER COMPARATOR (BOOST MODE)
As Percentage to VREGN (Approx.
–20°C w/ 103AT), –20°C ≤
TJ≤125°C
Cold Temperature Threshold, TS pin
Voltage Rising Threshold
VBCOLD
VBCOLD
VBHOT
VBHOT
79.5%
78.5%
30.2%
33.8%
80%
79%
80.5%
79.5%
32.2%
34.9%
Falling
–20°C ≤TJ≤125°C
As Percentage to VREGN (Approx.
60°C w/ 103AT), –20°C ≤TJ≤
125°C
Hot Temperature Threshold, TS pin
Voltage falling Threshold
31.2%
34.4%
Rising
–20°C ≤TJ≤125°C
CHARGE OVERCURRENT COMPARATOR (CYCLE-BY-CYCLE)
HSFET cycle-by-cycle over-current
IHSFET_OCP
threshold
5.2
6.0
8.0
A
A
IBATFET_OCP
System over load threshold
PWM
Oscillator frequency, buck mode
Oscillator frequency, boost mode
1320
1170
1500
1412
97%
1680
1500
kHz
kHz
fSW
PWM switching frequency
DMAX
Maximum PWM duty cycle(1)
BOOST MODE OPERATION
VOTG_REG Boost mode regulation voltage
VVBAT = 3.8 V, I(PMID) = 0 A
4.972
5.126
5.280
V
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8.5 Electrical Characteristics (continued)
VVAC_PRESENT < VVAC < VVAC_OV and VVAC > VBAT + VSLEEP, TJ = –40°C to 125°C and TJ = 25°C for typical values (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
-3
TYP
MAX
3
UNIT
%
VOTG_REG_ACC
VBATLOWV_OTG
Boost mode regulation voltage accuracy VVBAT = 3.8 V, I(PMID) = 0 A
Battery voltage exiting boost mode
Battery voltage entering boost mode
OTG mode output current limit
OTG overvoltage threshold
VVBAT falling
VVBAT rising
2.6
2.9
1.2
5.55
2.8
3.0
1.4
5.8
2.9
V
3.15
1.6
V
IOTG
A
VOTG_OVP
REGN LDO
VREGN
Rising threshold
6.15
V
REGN LDO output voltage
REGN LDO output voltage
VVBUS = 9 V, IREGN = 40 mA
VVBUS = 5 V, IREGN = 20 mA
5.6
4.6
6
6.65
4.9
V
V
VREGN
4.7
LOGIC I/O PIN CHARACTERISTICS (CE, PSEL, SCL, SDA, INT)
VILO
VIH
Input low threshold CE
0.4
V
V
Input high threshold CE
1.3
1.3
IBIAS
VILO
VIH
High-level leakage current CE
Input low threshold OTG
Input high threshold OTG
High-level leakage current OTG
Pull up rail 1.8 V
Pull up rail 1.8 V
1
µA
V
0.4
V
IBIAS
1
µA
LOGIC I/O PIN CHARACTERISTICS (PG, STAT)
VOL Low-level output voltage
D+/D–DETECTION
D+ Threshold for Non-standard adapter
0.4
V
VD+_1P2
(combined V1P2_VTH_LO and
V1P2_VTH_HI)
1.05
1.35
V
ID+_LKG
Leakage current into D+
Voltage source (600 mV)
D–current sink (100 µA)
D–resistor to ground (19 kΩ)
HiZ
-1
500
1
700
150
24.8
µA
mV
µA
VD–_600MVSRC
ID–_100UAISNK
RD–_19K
600
100
VD– = 500 mV,
VD– = 500 mV,
50
14.25
kΩ
D–comparator threshold for primary
detection
VD–_0P325
250
400
mV
D–pin Rising
D–Threshold for non-standard adapter
(combined V2P8_VTH_LO and
V2P8_VTH_HI)
VD–_2P8
2.55
2.85
V
V
D–Comparator threshold for non-
standard adapter (For non-standard –
same as BQ2589x)
VD–_2P0
1.85
2.15
D–Threshold for non-standard adapter
(combined V1P2_VTH_LO and
V1P2_VTH_HI)
VD–_1P2
ID–_LKG
1.05
-1
1.35
1
V
HiZ
µA
Leakage current into D–
(1) Specified by design. Not production tested.
8.6 Timing Requirements
PARAMETER
MIN
NOM
MAX
UNIT
VBUS/BAT POWER UP
VAC rising above ACOV threshold to
turn off Q2
tACOV
VBUS OVP reaction time
200
ns
tBADSRC
Bad adapter detection duration
30
ms
ms
tTERM_DGL
Deglitch time for charge termination
250
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8.6 Timing Requirements (continued)
PARAMETER
MIN
NOM
MAX
UNIT
tRECHG_DGL
Deglitch time for recharge
250
ms
System over-current deglitch time to
turn off Q4
tSYSOVLD_DGL
100
µs
Battery overvoltage deglitch time to
disable charge
tBATOVP
tSAFETY
1
µs
hr
Typical Charge Safety Timer Range
8
10
12
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8.7 Typical Characteristics
100
95
90
85
80
75
70
65
60
100
95
90
85
80
75
70
65
60
55
50
VBUS Voltage
5 V
VBAT = 3.2 V
VBAT = 3.8 V
VBAT = 4.1 V
9 V
12 V
0
0.5
1
1.5
Charge Current (A)
2
2.5
3
0
0.2
0.4
0.6 0.8
OTG Current (A)
1
1.2
1.4
D001
D001
fSW = 1.5 MHz
VBAT = 3.8 V
VOTG = 5.15 V
图8-2. Efficiency vs. OTG Current
Inductor DCR = 18 mΩ
inductor DCR = 18 mΩ
图8-1. Charge Efficiency vs. Charge Current
6
5
4
3
2
1
0
3.85
3.8
3.75
3.7
3.65
3.6
3.55
3.5
-40 -25 -10
5
20 35 50 65 80 95 110 125
Junction Temperature (°C)
0
0.2
0.4
0.6
0.8
1
Output Current (A)
1.2
1.4
1.6
D001
D001
图8-4. SYSMIN Voltage vs. Junction Temperature
VOTG = 5.15 V
0 A ≤IOTG ≤1.37 A
VVBAT = 3.8 V
图8-3. OTG Output Voltage vs. Output Current
4.5
4.4
4.3
4.2
4.1
4
2.75
IINDPM = 1.8 A
IINDPM = 1.28 A
IINDPM = 0.52 A
2.5
2.25
2
1.75
1.5
1.25
1
0.75
0.5
0.25
0
VBATREG = 4.208 V
VBATREG = 4.352 V
VBATREG = 4.4 V
-40
-25
-10
5
20
35
50
Junction Temperature (°C)
65
80
95
-40 -25 -10
5
20 35 50 65 80 95 110 125
Junction Temperature (°C)
D001
D001
VVBUS = 5 V
图8-6. Input Current Limit vs. Junction Temperature
图8-5. BATREG Charge Voltage vs. Junction Temperature
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8.7 Typical Characteristics (continued)
2.6
2
1.8
1.6
1.4
1.2
1
ICHG = 1.8 A
ICHG = 1.2 A
ICHG = 0.68 A
2.4
2.2
2
1.8
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
0
0.8
0.6
0.4
0.2
0
-40 -25 -10
5
20
Junction Temperature (°C)
35
50
65
80
95 110
30
40
50
60
Junction Temperature (°C)
70
80
90 100 110 120 130
D001
D001
VVBUS = 5 V
VBAT = 3.8 V
VVBUS = 5V
VBAT = 3.8V
图8-7. Charge Current vs. Junction Temperature
图8-8. Charge Current vs. Junction Temperature Under Thermal
Regulation
486
705
RILIM = 265 W
RILIM = 374 W
RILIM = 910 W
RICHG = 372 W
700
RICHG = 562 W
484
482
480
478
476
474
472
RICHG = 1100 W
695
690
685
680
675
670
665
660
-40
-25
-10
5
Junction Temperature (°C)
20
35
50
65
80
95
-40 -25 -10
5
Junction Temperature (°C)
20
35
50
65
80
95 110
D001
D001
VVBUS = 5 V
VBAT = 3.8 V
VVBUS = 5 V
VBAT = 3.8 V
图8-9. Input Current Limit Setting Ratio vs. Junction
图8-10. Charge Current Setting Ratio vs. Junction Temperature
Temperature
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9 Detailed Description
9.1 Overview
The BQ25606 is a highly integrated 3.0-A switch-mode battery charger for single cell Li-ion and Li-polymer
batteries. It includes an input reverse-blocking FET (RBFET, Q1), high-side switching FET (HSFET, Q2), low-
side switching FET (LSFET, Q3), and battery FET (BATFET, Q4), and bootstrap diode for the high-side gate
drive.
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9.2 Functional Block Diagram
VBUS
PMID
VVVAC_PRESENT
RBFET (Q1)
+
UVLO
SLEEP
ACOV
VVAC
Q1 Gate
Control
œ
IIN
VBAT + VSLEEP
+
REGN
EN_REGN
EN_HIZ
VVAC
REGN
LDO
œ
VVAC
+
VVAC_OV
œ
BTST
FBO
VVBUS
VBUS_OVP_BOOST
+
VAC
VIN
VOTG_OVP
œ
IQ2
Q2_UCP_BOOST
Q3_OCP_BOOST
+
VOTG_HSZCP
VVBUS
œ
œ
HSFET (Q2)
LSFET (Q3)
IQ3
VINDPM
SW
+
+
VOTG_BAT
IIN
+
IINDPM
CONVERTER
Control
œ
REGN
BAT
+
œ
BATOVP
UCP
104% × V BAT_REG
IC TJ
PGND
œ
+
ILSFET_UCP
TREG
IQ2
BAT
Q2_OCP
œ
+
œ
+
œ
+
+
IHSFET_OCP
IQ3
SYS
VBAT_REG
œ
œ
œ
VSYSMIN
VBTST - VSW
ICHG
EN_HIZ
EN_CHARGE
EN_BOOST
+
+
REFRESH
VBTST_REFRESH
ICHG_REG
œ
SYS
ICHG
VBAT_REG
ICHG_REG
BATFET
(Q4)
Q4 Gate
Control
BAT
IBADSRC
IDC
BAD_SRC
+
REF
DAC
Converter
Control State
Machine
œ
ILIM
ICHG
VSET
IC TJ
TSHUT
+
TSHUT
œ
BAT
BAT_GD
+
VBATGD
Input
Source
Detection
D+
œ
USB
Adapter
DÅ
VREG -VRECHG
BAT
+
RECHRG
OTG
œ
ICHG
+
TERMINATION
BATLOWV
ITERM
œ
CHARGE
CONTROL
STATE
VBATLOWV
STAT
/PG
+
BAT
MACHINE
œ
BQ25606
VSHORT
+
BATSHORT
SUSPEND
BAT
œ
Battery
Sensing
Thermistor
TS
/CE
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9.3 Feature Description
9.3.1 Device Power Up from Battery without Input Source
If only battery is present and the voltage is above depletion threshold (VBAT _DPL_RISE), the BATFET turns on and
connects battery to system. The REGN stays off to minimize the quiescent current. The low RDSON of BATFET
and the low quiescent current on BAT minimize the conduction loss and maximize the battery run time.
The device always monitors the discharge current through BATFET (Supplement Mode). When the system is
overloaded or shorted (IBAT > IBATFET_OCP), the device turns off BATFET immediately until the input source plugs
in again.
9.3.2 Power Up from Input Source
When an input source is plugged in, the device checks the input source voltage to turn on REGN LDO and all
the bias circuits. It detects and sets the input current limit before the buck converter is started. The power-up
sequence from input source is as listed:
1. Power up REGN LDO
2. Poor source qualification
3. Input source type detection is based on D+/D–to set input current limit (IINDPM) .
4. Input voltage limit threshold setting (VINDPM threshold)
5. Converter power up
9.3.2.1 Power Up REGN Regulation
The REGN LDO supplies internal bias circuits as well as the HSFET and LSFET gate drive. The REGN also
provides bias rail to TS external resistors. The pull-up rail of STAT can be connected to REGN as well. The
REGN is enabled when all the below conditions are valid:
• VVAC above VVAC_PRESENT
• VVAC above VBAT + VSLEEPZ in buck mode or VBUS below VBAT + VSLEEP in boost mode
• After 220-ms delay is completed
If any one of the above conditions is not valid, the device is in high impedance mode (HIZ) with REGN LDO off.
The device draws less than IVBUS_HIZ from VBUS during HIZ state. The battery powers up the system when
the device is in HIZ.
9.3.2.2 Poor Source Qualification
After REGN LDO powers up, the device confirms the current capability of the input source. The input source
must meet both of the following requirements in order to start the buck converter.
• VAC voltage below VVAC_OV
• VBUS voltage above VVBUSMIN when pulling IBADSRC (typical 30 mA)
If the device fails the poor source detection, it repeats poor source qualification every 2 seconds.
9.3.2.3 Input Source Type Detection
After the REGN LDO is powered, the device runs input source detection through D+/D– lines. The BQ25606
follows the USB Battery Charging Specification 1.2 (BC1.2) to detect input source (SDP/ DCP) and nonstandard
adapter through USB D+/D–lines. The BQ25606 sets input current limit through D+/D- detection and ILIM pins.
9.3.2.3.1 D+/D–Detection Sets Input Current Limit in BQ25606
The BQ25606 contains a D+/D–based input source detection to set the input current limit at VBUS plug-in. The
D+/D– detection includes standard USB BC1.2 and nonstandard adapter. When input source is plugged in, the
device starts standard USB BC1.2 detections. The USB BC1.2 is capable to identify Standard Downstream Port
(SDP) and Dedicated Charging Port (DCP). When the Data Contact Detection (DCD) timer expires, the
nonstandard adapter detection is applied to set the input current limit. The nonstandard detection is used to
distinguish vendor specific adapters (Apple and Samsung) based on their unique dividers on the D+/D– pins. If
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an adapter is detected as DCP, the input current limit is set at 2.4 A. If an adapter is detected as unknown, the
input current limit is set at 500 mA by ILIM pin.
表9-1. Nonstandard Adapter Detection
NONSTANDARD
D+ THRESHOLD
INPUT CURRENT LIMIT (A)
D–THRESHOLD
ADAPTER
Divider 1
Divider 2
Divider 3
Divider 4
VD+ within VD+ _2p8
VD+ within VD+ _1p2
VD+ within VD+ _2p0
VD+ within VD+ _2p8
VD– within VD–_2p0
VD– within VD–_1p2
VD– within VD–_2p8
VD– within VD–_2p8
2.1
2
1
2.4
表9-2. Input Current Limit Setting from D+/D–Detection
INPUT CURRENT LIMIT (IINLIM)
D+/D–DETECTION
USB SDP (USB500)
USB DCP
500 mA
2.4 A
Divider 3
1 A
Divider 1
2.1 A
Divider 4
2.4 A
Divider 2
2 A
Unknown 5-V adapter
Set by ILIM pin
9.3.2.4 Input Voltage Limit Threshold Setting (VINDPM Threshold)
The device VINDPM is set at 4.3 V. The device supports dynamic VINDPM tracking which tracks the battery
voltage. The device VINDPM tracks battery voltage with 200 mV offset such that when VBAT + 200 mV is
greater than 4.3 V, the VINDPM value is automatically adjusted to VBAT + 200 mV.
9.3.2.5 Converter Power Up
After the input current limit is set, the converter is enabled and the HSFET and LSFET start switching. If battery
charging is disabled, BATFET turns off. Otherwise, BATFET stays on to charge the battery.
The device provides soft start when system rail is ramped up. When the system rail is below 2.2 V, the input
current is limited to is to 200 mA . After the system rises above 2.2 V, the device limits input current to the value
set by ILIM pin.
As a battery charger, the device deploys a highly efficient 1.5 MHz step-down switching regulator. The fixed
frequency oscillator keeps tight control of the switching frequency under all conditions of input voltage, battery
voltage, charge current and temperature, simplifying output filter design.
The device switches to PFM control at light load or when battery is below minimum system voltage setting or
charging is disabled.
9.3.3 Boost Mode Operation From Battery
The device supports boost converter operation to deliver power from the battery to other portable devices
through USB port. The maximum output current is up to 1.2 A. The boost operation can be enabled if the
conditions are valid:
1. BAT above VOTG_BAT
2. VBUS less than BAT+VSLEEP (in sleep mode)
3. Boost mode operation is enabled (OTG pin HIGH)
4. Voltage at TS (thermistor) pin as a percentage of VREGN is within acceptable range (VBHOT < VTS < VBCOLD
)
5. After 30-ms delay from boost mode enable
During boost mode, the VBUS output is 5.15 V and the output current can reach up to 1.2 A. The boost output is
maintained when BAT is above VOTG_BAT threshold.
When OTG is enabled, the device starts up with PFM and later transits to PWM to minimize the overshoot.
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9.3.4 Power Path Management
The device accommodates a wide range of input sources from USB, wall adapter, to car charger. The device
provides automatic power path selection to supply the system (SYS) from input source (VBUS), battery (BAT), or
both.
9.3.4.1 Narrow VDC Architecture
When the battery is below the minimum system voltage setting, the BATFET operates in linear mode (LDO
mode), and the system is typically 180 mV above the minimum system voltage setting. As the battery voltage
rises above the minimum system voltage, the BATFET is fully on and the voltage difference between the system
and battery is the VDS of the BATFET.
When battery charging is disabled and above the minimum system voltage setting or charging is terminated, the
system is always regulated at typically 50 mV above the battery voltage.
4.5
Minimum System Voltage
Charge Disabled
Charge Enabled
4.1
4.3
3.9
3.7
3.5
3.3
3.1
2.7
2.9
3.1
3.3
3.5
BAT (V)
3.7
3.9
4.1
4.3
D002
图9-1. System Voltage vs Battery Voltage
9.3.4.2 Dynamic Power Management
To meet maximum current limit in the USB specification and avoid over loading the adapter, the device features
Dynamic Power management (DPM), which continuously monitors the input current and input voltage. When
input source is overloaded, either the current exceeds the input current limit (IINDPM) or the voltage falls below
the input voltage limit (VINDPM). The device then reduces the charge current until the input current falls below
the input current limit or the input voltage rises above the input voltage limit.
When the charge current is reduced to zero, but the input source is still overloaded, the system voltage starts to
drop. Once the system voltage falls below the battery voltage, the device automatically enters the supplement
mode where the BATFET turns on and the battery starts discharging so that the system is supported from both
the input source and battery.
9.3.4.3 Supplement Mode
When the system voltage falls below the battery voltage, the BATFET turns on and the BATFET gate is
regulated the so that the minimum BATFET VDS stays at 30 mV when the current is low. This prevents oscillation
from entering and exiting the supplement mode.
As the discharge current increases, the BATFET gate is regulated with a higher voltage to reduce RDSON until
the BATFET is in full conduction. At this point onwards, the BATFET VDS linearly increases with discharge
current. shows the V-I curve of the BATFET gate regulation operation. The BATFET turns off to exit supplement
mode when the battery is below battery depletion threshold.
9.3.5 Battery Charging Management
The device charges 1-cell Li-Ion battery with up to 3.0-A charge current for high capacity tablet battery. The 19.5-
mΩBATFET improves charging efficiency and minimize the voltage drop during discharging.
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9.3.5.1 Autonomous Charging Cycle
With battery charging enabled (CE pin is LOW), the device autonomously completes a charging cycle. The
device default charging parameters are listed in 表9-3.
表9-3. Charging Parameter Default Setting
DEFAULT MODE
Charging voltage
Charging current
Precharge current
Termination current
Temperature profile
Safety timer
BQ25606
VSET controlled
ICHG controlled
5% of ICHG
5% of ICHG
JEITA
10 hours
A new charge cycle starts when the following conditions are valid:
• Converter starts
• Battery charging is enabled (CE is low)
• No thermistor fault on TS
• No safety timer fault
The charger device automatically terminates the charging cycle when the charging current is below termination
threshold, battery voltage is above recharge threshold, and device not is in DPM mode or thermal regulation.
When a fully charged battery is discharged below recharge threshold, the device automatically starts a new
charging cycle. After the charge is done, toggle CE pin can initiate a new charging cycle.
The STAT output indicates the charging status: charging (LOW), charging complete or charge disable (HIGH) or
charging fault (blinking).
9.3.5.2 Charging Termination
The device terminates a charge cycle when the battery voltage is above recharge threshold, and the current is
below termination current. After the charging cycle is completed, the BATFET turns off. The converter keeps
running to power the system, and BATFET can turn on again to engage Supplement Mode.
9.3.5.3 Thermistor Qualification
The charger device provides a single thermistor input for battery temperature monitor.
9.3.5.4 JEITA Guideline Compliance During Charging Mode
To improve the safety of charging Li-ion batteries, JEITA guideline was released on April 20, 2007. The guideline
emphasized the importance of avoiding a high charge current and high charge voltage at certain low and high
temperature ranges.
To initiate a charge cycle, the voltage on TS pin must be within the VT1 to VT5 thresholds. If TS voltage exceeds
the T1-T5 range, the controller suspends charging and waits until the battery temperature is within the T1 to T5
range.
At cool temperature (T1-T2), the charge current is reduced to 20% of programmed fast charge current. At warm
temperature (T3-T5), the charge voltage is reduced to 4.1 V. Charge termination is disabled for cool and warm
conditions.
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100
90
VBATREG
4.1
4
80
70
60
3
2
1
0
50
40
30
20
10
0
T1
0
T2
T3
T5
T1
T2
T3
T5
5
10 15 20
25
30 35
40
45 50
55
60 65
70
œ5
5
10 15 20
25
30 35
40
45 50
55
60 65
70
œ5
0
Battery Pack Temperature (°C)
Battery Pack Temperature (°C)
图9-3. JEITA Profile: Charging Voltage
图9-2. JEITA Profile: Charging Current
方程式1 through 方程式2 describe updates to the resistor bias network.
REGN
RT1
TS
NTC
103AT
RT2
图9-4. TS Pin Resistor Network
%
%
%
%
(1)
%
(2)
Select 0°C to 60°C range for Li-ion or Li-polymer battery:
• RTHCOLD = 27.28 kΩ
• RTHHOT = 3.02 kΩ
• RT1 = 5.23 kΩ
• RT2 = 30.9 kΩ
9.3.5.5 Boost Mode Thermistor Monitor during Battery Discharge Mode
For battery protection during boost mode, the device monitors the battery temperature to be within the VBCOLD to
VBHOT thresholds. When temperature is outside of the temperature thresholds, the boost mode is suspended.
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Temperature Range to Boost
Boost Disabled
100%
V
BCOLD
(œ10°C)
Boost Enabled
Boost Disabled
V
BHOT
(65°C)
0%
图9-5. TS Pin Thermistor Sense Threshold in Boost Mode
9.3.5.6 Charging Safety Timer
The device has built-in safety timer to prevent extended charging cycle due to abnormal battery conditions. The
safety timer is two hours when the battery is below VBATLOWV threshold and 10 hours when the battery is higher
than VBATLOWV threshold.
During input voltage, current, JEITA cool or thermal regulation, the safety timer counts at half clock rate as the
actual charge current is likely to be below the register setting. For example, if the charger is in input current
regulation throughout the whole charging cycle, the safety timer will expire in 20 hours.
During the fault, timer is suspended. Once the fault goes away, the timer resumes. If user stops the current
charging cycle, and start again, timer gets reset.
9.3.6 Status Outputs ( PG, STAT)
9.3.6.1 Power Good Indicator (PG Pin)
The PG pin goes LOW to indicate a good input source when:
• VBUS above VVBUS_UVLO
• VBUS above battery (not in sleep)
• VBUS below VACOV threshold
• VBUS above VPOOSRC (typical 3.8 V) when IBADSRC (typical 30 mA) current is applied (not a poor source)
• Completed 节9.3.2.3
9.3.6.2 Charging Status Indicator (STAT)
The device indicates charging state on the open drain STAT pin. The STAT pin can drive LED.
表9-4. STAT Pin State
CHARGING STATE
STAT INDICATOR
LOW
Charging in progress (including recharge)
Charging termination (top off timer may be running)
HIGH
Sleep mode, charge disable, boost mode
HIGH
Charge suspend (input overvoltage, TS fault, safety timer fault or system overvoltage)
Blinking at 1 Hz
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9.3.7 Protections
9.3.7.1 Input Current Limit
The device's ILIM pin is to program maximum input current when D+/D- detection identifies an unknown adaptor
plugged in. The maximum input current is set by a resistor from ILIM pin to ground as:
KILIM
=
I
INMAX
RILIM
(3)
9.3.7.2 Voltage and Current Monitoring in Converter Operation
The device closely monitors the input and system voltage, as well as internal FET currents for safe buck and
boost mode operation.
9.3.7.2.1 Voltage and Current Monitoring in Buck Mode
9.3.7.2.1.1 Input Overvoltage (ACOV)
If VAC exceeds VVAC_OV, HSFET stops switching immediately.
9.3.7.2.1.2 System Overvoltage Protection (SYSOVP)
The charger device clamps the system voltage during load transient so that the components connect to system
would not be damaged due to high voltage. SYSOVP threshold is 350 mV above minimum system regulation
voltage when the system is regulate at VSYS_MIN. Upon SYSOVP, converter stops switching immediately to
clamp the overshoot. The charger provides 30-mA discharge current (ISYSLOAD) to bring down the system
voltage.
9.3.7.3 Voltage and Current Monitoring in Boost Mode
The device closely monitors the VBUS voltage, as well as RBFET and LSFET current to ensure safe boost mode
operation.
9.3.7.3.1 VBUS Soft Start
When the boost function is enabled, the device soft-starts boost mode to avoid inrush current.
9.3.7.3.2 VBUS Output Protection
The device monitors boost output voltage and other conditions to provide output short circuit and overvoltage
protection. The boost build in accurate constant current regulation to allow OTG to adapt to various types of
load. If a short circuit is detected on VBUS, boost turns off and retries 7 times. If retries are not successful, OTG
is disabled.
9.3.7.3.3 Boost Mode Overvoltage Protection
When the VBUS voltage rises above regulation target and exceeds VOTG_OVP, the device stop switching.
9.3.7.4 Thermal Regulation and Thermal Shutdown
9.3.7.4.1 Thermal Protection in Buck Mode
The BQ25606 monitors the internal junction temperature TJ to avoid overheat of the chip and limits the IC
surface temperature in buck mode. When the internal junction temperature exceeds thermal regulation limit
(110°C), the device lowers down the charge current. During thermal regulation, the actual charging current is
usually below the programmed battery charging current. Therefore, termination is disabled, the safety timer runs
at half the clock rate.
9.3.7.4.2 Thermal Protection in Boost Mode
The device monitors the internal junction temperature to provide thermal shutdown during boost mode. When IC
junction temperature exceeds TSHUT (160°C), the boost mode is disabled and BATFET is turned off. When IC
junction temperature is below TSHUT(160°C) - TSHUT_HYS (30°C), the BATFET is enabled automatically to allow
system to restore.
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9.3.7.5 Battery Protection
9.3.7.5.1 Battery Overvoltage Protection (BATOVP)
The battery overvoltage limit is clamped at 4% above the battery regulation voltage. When battery over voltage
occurs, the charger device immediately disables charging.
9.3.7.5.2 Battery Overdischarge Protection
When battery is discharged below VBAT_DPL_FALL, the BATFET is turned off to protect battery from overdischarge.
To recover from overdischarge latch-off, an input source plug-in is required at VBUS. The battery is charged with
ISHORT (typically 100 mA) current when the VBAT < VSHORT, or precharge current as set by 5% of ICHG when the
battery voltage is between VSHORTZ and VBAT_LOWV
.
9.3.7.5.3 System Overcurrent Protection
When the system is shorted or significantly overloaded (IBAT > IBATOP) and the current exceeds BATFET
overcurrent limit, the BATFET latches off. The BATFET latch can be reset with VBUS plug-in.
10 Application and Implementation
Note
以下应用部分中的信息不属于TI 器件规格的范围,TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计,以确保系统功能。
10.1 Application Information
A typical application consists of the device configured as a stand-alone power path management device and a
single cell battery charger for Li-Ion and Li-polymer batteries used in a wide range of Smartphone and other
portable devices. It integrates an input reverse-block FET (RBFET, Q1), high-side switching FET (HSFET, Q2),
low-side switching FET (LSFET, Q3), and battery FET (BATFET Q4) between the system and battery. The
device also integrates a bootstrap diode for the high-side gate drive.
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10.2 Typical Application
System
3.5 V to 4.6 V
Input
3.9 V to 13.5 V
1 ꢀH
VBUS
PMID
SW
1 ꢀF
10 ꢀF
47 nF
BTST
REGN
GND
SYS
10 ꢀF
ACDRV
VAC
4.7 µF
SYS
SYS
2.2 kꢁ
2.2 kꢁ
/PG
BAT
BQ25606
STAT
OTG
10 ꢀF
Host
450 ꢁ
REGN
5.23 kꢁ
ICHG
/CE
TS
+
30.1 kꢁ 10 kꢁ
D+
D-
USB
ILIM
240 ꢁ
VSET
Float: VREG = 4.208 V
Short : VREG = 4.352 V
RPD=10 kΩ: VREG = 4.400 V
RPD
图10-1. BQ25606 Application Diagram
表10-1. Design Parameters
10.2.1 Design Requirements
PARAMETER
VALUE
4 V to 13.5 V
2.4 A
VBUS voltage range
Input current limit (D+/D–detection)
Fast charge current limit (ICHG pin)
Minimum system voltage
ICHG pin
3.5 V
Battery regulation voltage (VSET pin)
4.2 V
10.2.2 Detailed Design Procedure
10.2.2.1 Inductor Selection
The 1.5-MHz switching frequency allows the use of small inductor and capacitor values to maintain an inductor
saturation current higher than the charging current (ICHG) plus half the ripple current (IRIPPLE):
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I
SAT ≥ICHG + (1/2) IRIPPLE
(4)
The inductor ripple current depends on the input voltage (VVBUS), the duty cycle (D = VBAT/VVBUS), the switching
frequency (fS) and the inductance (L).
VIN ´D ´ (1- D)
=
IRIPPLE
fs ´ L
(5)
The maximum inductor ripple current occurs when the duty cycle (D) is 0.5 or approximately 0.5. Usually
inductor ripple is designed in the range between 20% and 40% maximum charging current as a trade-off
between inductor size and efficiency for a practical design.
10.2.2.2 Input Capacitor
Design input capacitance to provide enough ripple current rating to absorb input switching ripple current. The
worst case RMS ripple current is half of the charging current when duty cycle is 0.5. If the converter does not
operate at 50% duty cycle, then the worst case capacitor RMS current ICin occurs where the duty cycle is closest
to 50% and can be estimated using 方程式6.
ICIN = ICHG ´ D ´ (1- D)
(6)
Low ESR ceramic capacitor such as X7R or X5R is preferred for input decoupling capacitor and should be
placed to the drain of the high-side MOSFET and source of the low-side MOSFET as close as possible. Voltage
rating of the capacitor must be higher than normal input voltage level. A rating of 25 V or higher capacitor is
preferred for 15-V input voltage. Capacitance of 22 μF is suggested for typical of 3-A charging current.
10.2.2.3 Output Capacitor
Ensure that the output capacitance has enough ripple current rating to absorb the output switching ripple current.
方程式7 shows the output capacitor RMS current ICOUT calculation.
IRIPPLE
ICOUT
=
» 0.29 ´ IRIPPLE
2 ´
3
(7)
The output capacitor voltage ripple can be calculated as follows:
æ
ç
è
ö
VOUT
8LCfs2
VOUT
V
DVO =
1-
÷
IN ø
(8)
At certain input and output voltage and switching frequency, the voltage ripple can be reduced by increasing the
output filter LC.
The charger device has internal loop compensation optimized for ≤20-μF ceramic output capacitance. The
preferred ceramic capacitor is 10-V rating, X7R or X5R.
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10.2.3 Application Curves
VVBUS = 5 V
VVBAT = 3.2 V
VVBUS = 5 V
ICHG = 2 A
VVBAT = 3.2 V
图10-2. Power Up with Charge Disabled
图10-3. Power Up with Charge Enabled
VVBUS = 5 V
VVBUS = 9 V
ISYS = 50 mA
Charge Disabled
ISYS = 50 mA
Charge Disabled
图10-4. PFM Switching in Buck Mode
图10-5. PFM Switching in Buck Mode
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VVBUS = 5 V
ICHG = 2 A
VVBAT = 3.8 V
VVBUS = 12 V
ISYS = 50 mA
Charge Disabled
图10-7. PWM Switching in Buck Mode
图10-6. PFM Switching in Buck Mode
VVBUS = 12 V
ICHG = 2 A
VVBAT = 3.8 V
VVBUS = 5 V
ICHG = 2 A
VVBAT = 3.2 V
图10-8. PWM Switching in Buck mode
图10-9. Charge Enable
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VVBUS = 5 V
VVBAT = 3.2 V
VVBAT = 4 V
ILOAD= 50 mA
ICHG = 2 A
PFM Enabled
图10-10. Charge Disable
图10-11. OTG Switching
VVBUS = 5 V
IINDPM = 1 A
VVBAT = 4 V
ILOAD= 1 A
ISYS from 0 A to 2 A
VBAT = 3.7 V
ICHG = 1 A
PFM Enabled
图10-12. OTG Switching
图10-13. System Load Transient
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VVBUS = 5 V
IINDPM = 2 A
ICHG = 1 A
VVBUS = 5 V
IINDPM = 1 A
ICHG = 2 A
ISYS from 0 A to 4 A
VBAT = 3.7 V
ISYS from 0 A to 2 A
VBAT = 3.7 V
图10-14. System Load Transient
图10-15. System Load Transient
VVBUS = 5 V
IINDPM = 1 A
ICHG = 2 A
VVBUS = 5 V
IINDPM = 2 A
ICHG = 2 A
ISYS from 0 A to 4 A
VBAT = 3.7 V
ISYS from 0 A to 2 A
VBAT = 3.7 V
图10-16. System Load Transient
图10-17. System Load Transient
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VVBUS = 5 V
IINDPM = 2 A
ICHG = 2 A
VBAT = 3.8 V
CLOAD = 470 µF
ISYS from 0 A to 4 A
VBAT = 3.7 V
图10-19. OTG Start Up
图10-18. System Load Transient
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11 Power Supply Recommendations
In order to provide an output voltage on SYS, the BQ25606 device requires a power supply between 3.9-V and
13.5-V input with at least 100-mA current rating connected to VBUS and a single-cell Li-Ion battery with voltage
> VBATUVLO connected to BAT. The source current rating needs to be at least 3 A in order for the buck converter
of the charger to provide maximum output power to SYS.
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12 Layout
12.1 Layout Guidelines
The switching node rise and fall times should be minimized for minimum switching loss. Proper layout of the
components to minimize high frequency current path loop (see 图 12-1) is important to prevent electrical and
magnetic field radiation and high frequency resonant problems. Follow this specific order carefully to achieve the
proper layout.
1. Place input capacitor as close as possible to PMID pin and GND pin connections and use shortest copper
trace connection or GND plane.
2. Place inductor input pin to SW pin as close as possible. Minimize the copper area of this trace to lower
electrical and magnetic field radiation but make the trace wide enough to carry the charging current. Do not
use multiple layers in parallel for this connection. Minimize parasitic capacitance from this area to any other
trace or plane.
3. Put output capacitor near to the inductor and the device. Ground connections need to be tied to the IC
ground with a short copper trace connection or GND plane.
4. Route analog ground separately from power ground. Connect analog ground and connect power ground
separately. Connect analog ground and power ground together using thermal pad as the single ground
connection point. Or using a 0-Ωresistor to tie analog ground to power ground.
5. Use single ground connection to tie charger power ground to charger analog ground. Just beneath the
device. Use ground copper pour but avoid power pins to reduce inductive and capacitive noise coupling.
6. Place decoupling capacitors next to the IC pins and make trace connection as short as possible.
7. It is critical that the exposed thermal pad on the backside of the device package be soldered to the PCB
ground. Ensure that there are sufficient thermal vias directly under the IC, connecting to the ground plane on
the other layers.
8. Ensure that the number and sizes of vias allow enough copper for a given current path.
Refer to the BQ25601 and BQ25601D (PWR877) Evaluation Module User's Guide for the recommended
component placement with trace and via locations. For the VQFN information, refer to the Quad Flatpack No-
Lead Logic Packages Application Report and QFN and SON PCB Attachment Application Report.
12.2 Layout Example
+
+
œ
图12-1. High Frequency Current Path
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图12-2. Layout Example
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ZHCSGR3C –MAY 2017 –REVISED SEPTEMBER 2021
13 Device and Documentation Support
13.1 Device Support
13.1.1 第三方产品免责声明
TI 发布的与第三方产品或服务有关的信息,不能构成与此类产品或服务或保修的适用性有关的认可,不能构成此
类产品或服务单独或与任何TI 产品或服务一起的表示或认可。
13.2 接收文档更新通知
要接收文档更新通知,请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册,即可每周接收产品信息更
改摘要。有关更改的详细信息,请查看任何已修订文档中包含的修订历史记录。
13.3 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料,可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范,并且不一定反映 TI 的观点;请参阅
TI 的《使用条款》。
13.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
13.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
13.6 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
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ZHCSGR3C –MAY 2017 –REVISED SEPTEMBER 2021
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2021 Texas Instruments Incorporated
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重要声明和免责声明
TI 提供技术和可靠性数据(包括数据表)、设计资源(包括参考设计)、应用或其他设计建议、网络工具、安全信息和其他资源,不保证没
有瑕疵且不做出任何明示或暗示的担保,包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担保。
这些资源可供使用TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任:(1) 针对您的应用选择合适的TI 产品,(2) 设计、验
证并测试您的应用,(3) 确保您的应用满足相应标准以及任何其他安全、安保或其他要求。这些资源如有变更,恕不另行通知。TI 授权您仅可
将这些资源用于研发本资源所述的TI 产品的应用。严禁对这些资源进行其他复制或展示。您无权使用任何其他TI 知识产权或任何第三方知
识产权。您应全额赔偿因在这些资源的使用中对TI 及其代表造成的任何索赔、损害、成本、损失和债务,TI 对此概不负责。
TI 提供的产品受TI 的销售条款(https:www.ti.com/legal/termsofsale.html) 或ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI
提供这些资源并不会扩展或以其他方式更改TI 针对TI 产品发布的适用的担保或担保免责声明。重要声明
邮寄地址:Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2021,德州仪器(TI) 公司
PACKAGE OPTION ADDENDUM
www.ti.com
9-Oct-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
BQ25606RGER
BQ25606RGET
ACTIVE
ACTIVE
VQFN
VQFN
RGE
RGE
24
24
3000 RoHS & Green
250 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 85
-40 to 85
BQ25606
BQ25606
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
9-Oct-2021
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
BQ25606RGER
BQ25606RGET
VQFN
VQFN
RGE
RGE
24
24
3000
250
330.0
180.0
12.4
12.4
4.25
4.25
4.25
4.25
1.15
1.15
8.0
8.0
12.0
12.0
Q2
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
BQ25606RGER
BQ25606RGET
VQFN
VQFN
RGE
RGE
24
24
3000
250
367.0
210.0
367.0
185.0
35.0
35.0
Pack Materials-Page 2
GENERIC PACKAGE VIEW
RGE 24
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4204104/H
PACKAGE OUTLINE
VQFN - 1 mm max height
RGE0024H
PLASTIC QUAD FLATPACK- NO LEAD
A
4.1
3.9
B
4.1
3.9
PIN 1 INDEX AREA
1 MAX
C
SEATING PLANE
0.08 C
0.05
0.00
ꢀꢀꢀꢀꢁꢂꢃꢄꢂꢅ
(0.2) TYP
2X 2.5
12
7
20X 0.5
6
13
25
2X
SYMM
2.5
1
18
0.30
PIN 1 ID
(OPTIONAL)
24X
0.18
24
19
0.1
0.05
C A B
C
SYMM
0.48
0.28
24X
4219016 / A 08/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
VQFN - 1 mm max height
RGE0024H
PLASTIC QUAD FLATPACK- NO LEAD
(3.825)
2.7)
(
24
19
24X (0.58)
24X (0.24)
1
18
20X (0.5)
25
SYMM
(3.825)
2X
(1.1)
ꢆꢄꢂꢁꢇꢀ9,$
TYP
6
13
(R0.05)
7
12
2X(1.1)
SYMM
LAND PATTERN EXAMPLE
SCALE: 20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
METAL
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4219016 / A 08/2017
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments
literature number SLUA271 (www.ti.com/lit/slua271).
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
VQFN - 1 mm max height
RGE0024H
PLASTIC QUAD FLATPACK- NO LEAD
(3.825)
4X ( 1.188)
24
19
24X (0.58)
24X (0.24)
1
18
20X (0.5)
SYMM
(3.825)
(0.694)
TYP
6
13
25
(R0.05) TYP
METAL
TYP
7
12
(0.694)
TYP
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
78% PRINTED COVERAGE BY AREA
SCALE: 20X
4219016 / A 08/2017
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations..
www.ti.com
重要声明和免责声明
TI“按原样”提供技术和可靠性数据(包括数据表)、设计资源(包括参考设计)、应用或其他设计建议、网络工具、安全信息和其他资源,
不保证没有瑕疵且不做出任何明示或暗示的担保,包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担
保。
这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任:(1) 针对您的应用选择合适的 TI 产品,(2) 设计、验
证并测试您的应用,(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。
这些资源如有变更,恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。
您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成
本、损失和债务,TI 对此概不负责。
TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改
TI 针对 TI 产品发布的适用的担保或担保免责声明。
TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE
邮寄地址:Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2022,德州仪器 (TI) 公司
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