BQ25872YFFT [TI]
具有 ADC 和外部过压保护控制器的 I2C 单节 7A 电池开关模式充电器 | YFF | 42 | -40 to 85;型号: | BQ25872YFFT |
厂家: | TEXAS INSTRUMENTS |
描述: | 具有 ADC 和外部过压保护控制器的 I2C 单节 7A 电池开关模式充电器 | YFF | 42 | -40 to 85 电池 开关 控制器 |
文件: | 总72页 (文件大小:1119K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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bq25872
ZHCSFK5 –OCTOBER 2016
bq25872 集成 10 位 ADC 的 14V、7A、电池开关充电器
1 特性
3 说明
1
•
适配器输入电压范围:3V 至 14V
该器件是一款集成有 10 位 ADC 的 7A 电池开关充电
器。该大电流电池开关充电器是一个具有反向电流阻断
功能的 13mΩ MOSFET,设计用于提高效率并最大限
度减小压降。高充电电流能力使得该器件成为智能手
机、平板电脑和其他具有大电池容量的便携式设备的理
想选择。
–
最高支持 14V 适配器电压
•
•
高度集成的 7A 电池开关
–
集成金属氧化物半导体场效应晶体管
(MOSFET) 和电流感应功能
–
低 RDS(on) (13mΩ) MOSFET,适用于在高电流
条件下运行
集成的 10 位 ADC 可以测量输入电压和电流、电池电
压和电流,以及电池温度和输入连接器温度。这使得用
户应用能够连续监视电力输入和电池充电参数,以确保
电池充电的安全性。当电池进入恒定电流 (CC) 和恒定
电压 (CV) 模式时,可以通过 I2C 寄存器灵活修改
VBUS、VOUT 和电池的 OVP 和 OCP 阈值。
集成有用于系统监视的高精度模数转换器 (ADC)
–
–
–
VBUS、VBAT、VOUT、VDROP 电压
输入和电池电流
电池和 VBUS 连接器温度
•
•
线性稳压 (LDO) 模式操作
–
四个线性调节环路:IBUS、IBAT、VBAT 和
该器件的 I2C 串行接口能以高达 1MHz 的速度工作,
允许访问 ADC 对不同充电参数的测量结果,并且还允
许对器件进行灵活的软件控制。INT 引脚可在发生故障
时即刻向主机提供反馈。I2C 状态寄存器允许主机读取
所有故障和事件的当前状态。
VOUT
–
可编程线性稳压阈值
可编程安全保护
–
–
–
–
–
–
VBUS、VOUT 和 VBAT 过压保护 (OVP)
IBUS 和 IBAT 过流保护 (OCP)
IBUS 反向电流保护 (RCP)
VDROP (VBUS-VOUT) OVP
VBUS 连接器和电池热保护
热关断
该器件采用 DSBGA 封装。
器件信息(1)
器件型号
bq25872
封装
YFF (42)
封装尺寸(标称值)
2.5mm x 3.1mm
•
•
•
•
•
集成输入 OVP FET 控制,OVP 响应迅速 (2µs)
用于主机处理器警报的中断状态输出
高达 1Mhz 的 I2C 读写速度
(1) 要了解所有可用封装,请见数据表末尾的可订购产品附录。
简化电路原理图
仅电池模式下的电池泄漏电流较低
小型 WCSP 封装
Switch-Mode
Charger
VBUS
SW
SYS
BAT
System
SDA/
SCL
2 应用
•
•
智能手机
平板电脑
Power Supply
Host
bq25872
VOUT
SDA/
SCL
BATP
VBUS
OVP
GATE
BATN
SRP
Battery
Pack
VUSB
SRN
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SLUSCQ6
bq25872
ZHCSFK5 –OCTOBER 2016
www.ti.com.cn
目录
8.4 Device Functional Modes........................................ 28
8.5 I2C Register Maps .................................................. 29
Application and Implementation ........................ 58
9.1 Application Information............................................ 58
9.2 Typical Application ................................................. 58
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 5
6.1 Absolute Maximum Ratings ...................................... 5
6.2 ESD Ratings ............................................................ 5
6.3 Recommended Operating Conditions....................... 6
6.4 Thermal Information.................................................. 6
6.5 Electrical Characteristics........................................... 7
6.6 Timing Requirements ............................................. 12
Typical Characteristics........................................ 13
Detailed Description ............................................ 15
8.1 Overview ................................................................. 15
8.2 Functional Block Diagram ....................................... 16
8.3 Feature Description................................................. 16
9
10 Power Supply Recommendations ..................... 62
11 Layout................................................................... 62
11.1 Layout Guidelines ................................................. 62
11.2 Layout Example .................................................... 62
12 器件和文档支持 ..................................................... 64
12.1 接收文档更新通知 ................................................. 64
12.2 社区资源................................................................ 64
12.3 商标....................................................................... 64
12.4 静电放电警告......................................................... 64
12.5 Glossary................................................................ 64
13 机械、封装和可订购信息....................................... 65
7
8
4 修订历史记录
日期
修订版本
注释
2016 年 10 月
*
最初发布。
2
Copyright © 2016, Texas Instruments Incorporated
bq25872
www.ti.com.cn
ZHCSFK5 –OCTOBER 2016
5 Pin Configuration and Functions
DSBGA Package
42 Pin YYF
Top View
Top View
Bottom View
1
2
3
4
5
6
6
5
4
3
2
1
OVPGATE
OVPGATE
VUSB
VOUT
VOUT
PMID
VBUS
VBUS
VBUS
VBUS
VBUS
VBUS
VBUS
VUSB
PMID
VOUT
VOUT
VBUS
A
B
C
A
B
TS_BUS
SCL
SDA
TS_BUS
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
PMID
PMID
PMID
PMID
PMID
PMID
SCL
SDA
PMID
PMID
PMID
PMID
PMID
PMID
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VBUS
VBUS
VBUS
VBUS
VBUS
VBUS
/INT
EN
/INT
EN
C
D
TS_BAT
SRN
TS_BAT
SRN
D
E
F
CHGSTAT
CHGSTAT
E
F
SRP
GND
SRP
GND
BATN
BATP
BATP
BATN
G
G
Copyright © 2016, Texas Instruments Incorporated
3
bq25872
ZHCSFK5 –OCTOBER 2016
www.ti.com.cn
Pin Functions
PIN
I/O
DESCRIPTION
NAME
NO.
A3-G3, A4-
G4
VOUT
P
P
Device power output. Connected to the drain of Q2.
Tie pins to each other and leave floating. Do not connect to any other pins. Connected to the
drain of Q1 and source of Q2.
PMID
A5-G5
VBUS connector temperature qualification voltage input. Requires external resistor divider
and voltage reference.
TS_BUS
GND
B2
F2
D1
AI
P
Device ground.
Battery temperature qualification voltage input. Requires external resistor divider and voltage
reference.
TS_BAT
AI
Negative input for battery voltage sensing. Connect to negative terminal of battery pack.
Place 100-Ω/1-kΩ series resistance between pin and negative terminal.
BATN
BATP
SRN
G1
G2
E1
F1
AI
AI
AI
AI
Positive input for battery voltage sensing. Connect to positive terminal of battery pack. Place
100-Ω/1-kΩ series resistance between pin and positive terminal.
Negative input for battery current sensing. Place RSENSE between SRN and SRP for battery
current sensing.
Positive input for battery current sensing. Place RSENSE between SRN and SRP for battery
current sensing.
SRP
A6, B6, C6,
D6, E6, F6,
G6
VBUS
EN
P
Device power input.
Active high device enable. Pull low to disable device. ADC not available when device is
disabled.
D2
DI
DI
Open drain, active low battery switch indicator. Connect to pull-up voltage via 10-kΩ pull-up
resistor. This pin will assert low if battery switch is enabled and will go high when battery
switch is disabled (due to fault or charge disabled or POR event).
CHGSTAT
E2
Open drain, active low interrupt output. Connect to pull-up voltage via 10-kΩ pull-up resistor.
Normally low, the INT pin asserts low to report status and faults. Keep constant low until the
host reads this register 0x03, 0x04.
INT
C2
DO
SDA
C1
B1
A2
A1
DIO
DI
I2C interface data. Connect to pull-up voltage via 1-kΩ pull-up resistor.
I2C interface clock. Connect to pull-up voltage via 1-kΩ pull-up resistor.
External OVP FET N-channel gate drive pin.
SCL
OVPGATE
VUSB
AO
AI
Device power input. Place a 500-Ω series resistor between this pin and USB supply voltage.
4
Copyright © 2016, Texas Instruments Incorporated
bq25872
www.ti.com.cn
ZHCSFK5 –OCTOBER 2016
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
UNIT
V
VUSB (EN = Low, or CHG_EN = '0')
VBUS (EN = Low, or CHG_EN = '0')
–2
–2
40
22
7
V
VOUT (EN = Low, or CHG_EN = '0')
Voltage range (with respect to GND)
–0.3
–0.3
–0.3
–0.3
–0.5
–22
V
SRP, SRN, BATP, BATN
7
V
INT, SDA, SCL, EN, CHGSTAT
TS_BUS, TS_BAT
7
V
5
V
SRP – SRN
Maximum voltage difference
0.5
7
V
VOUT– VBUS
V
Output sink current
INT
6
mA
°C
°C
°C
Operating free-air temperature range
Junction temperature, TJ
Storage temperature, Tstg
–40
–40
–65
85
150
150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±2000
V
V(ESD)
Electrostatic discharge
Charged-device model (CDM), per JEDEC specification JESD22-
C101(2)
±500
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
Copyright © 2016, Texas Instruments Incorporated
5
bq25872
ZHCSFK5 –OCTOBER 2016
www.ti.com.cn
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
2.8
2.8
2.8
0
NOM
MAX
14
6
UNIT
VUSB
EN = low, or CHG_EN = '0'
EN = high, or CHG_EN = '1'
EN = high, or CHG_EN = '1'
V
V
V
V
V
VBUS
VOUT
6
BATP, BATN
SRP – SRN
6
Differential voltage between SRP and SRN
TS pin voltage range
–0.2
0.2
TS_BUS,
TS_BAT
0
3
V
SDA, SCL,
ADDR, INT,
EN
TS pin voltage range
0
5
V
IOUT
TJ
Maximum current from VBUS to VOUT
Operating junction temperature range
–3
7
A
–40
85
°C
6.4 Thermal Information
bq25872
THERMAL METRIC(1)
YFF (DSBGA)
UNIT
42 PINS
50.0
0.2
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
8.9
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.1
ψJB
8.9
RθJC(bot)
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6
Copyright © 2016, Texas Instruments Incorporated
bq25872
www.ti.com.cn
ZHCSFK5 –OCTOBER 2016
6.5 Electrical Characteristics
Unless otherwise noted, the specification in the following table applies over operating ambient temperature range –40 °C ≤ TA
≤ 85 °C. Typical values are for TA = 25 °C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
QUIESCENT CURRENTS
ADC disabled (ADC_EN = 0), charge
disabled (CHG_EN = 0), EN = low, VVUSB
3.6 V, VOUT floating, current into VBUS
and VUSB
115
145
µA
=
Adaptor operation
quiescent current
IQ_OP
ADC enabled (ADC_EN = 1), charge
disabled (CHG_EN = 0), EN = high,
VVUSB= 3.6 V, VOUT floating, current into
VBUS and VUSB
1.75
2.0
mA
ADC disabled (ADC_EN = 0), charge
disabled (CHG_EN = 0), EN = low, VVOUT
= 3.6 V, current into VOUT
20
80
30
120
µA
µA
ADC disabled (ADC_EN = 0), charge
IQ_BAT
Battery quiescent current disabled (CHG_EN = 0), EN = high, VVOUT
= 3.6 V, current into VOUT
ADC enable (ADC_EN = 1), charge
disabled (CHG_EN = 0), EN = high, VVOUT
= 3.6 V, current into VOUT
1.35
1.75
mA
RESISTANCE AND LEAKAGE
VVBUS = 3.6 V, TA = 25 °C
13
13
16
22
mΩ
mΩ
kΩ
VBUS to VOUT
resistance
RON
VVBUS = 3.6 V, –40 °C ≤ TA ≤ 85 °C
VBUS pull-down
0.5
1.0
1.35
VVBUS_PD
resistance
VBUS_PD_EN = '1'
INTERNAL THRESHOLDS
Rising
3.2
2.8
2.8
V
mV
V
VUSB_PRESENT
Falling hysteresis
375
120
Rising
VBUS_PRESENT
Falling hysteresis
mV
V
Rising
VBAT_INSERT
Falling hysteresis
120
150
mV
°C
Internal thermal
TSHUT
shutdown- rising
TSHUT_HYS
IRCP
TSHUT falling hysteresis
30
0.25
3.00
10
°C
A
RCP_SET = '0'
RCP_SET = '1'
0.10
2.75
0.40
3.25
Current from VOUT to
VBUS
A
Short circuit current from
VBUS to VOUT
A
ISCP
VUSBOVP_setting = 6.5
V
100
kΩ
kΩ
kΩ
leave pin floating, resistance to ground
VUSBOVP_setting =
10.5 V
Tie to GND with a 22-kΩ series resistor,
resistance to ground
17.6
26.4
2.0
VOVPSET
VUSBOVP_setting =
14.0 V
Short to ground, resistance to ground
Copyright © 2016, Texas Instruments Incorporated
7
bq25872
ZHCSFK5 –OCTOBER 2016
www.ti.com.cn
Electrical Characteristics (continued)
Unless otherwise noted, the specification in the following table applies over operating ambient temperature range –40 °C ≤ TA
≤ 85 °C. Typical values are for TA = 25 °C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VUSBOVP_I2C = '00'
MIN
TYP
MAX
UNIT
V
Rising
5.6
6.0
Falling hystersis
VUSBOVP_I2C = '00'
100
mV
V
VUSBOVP_I2C = '01' or OVPSET pin =
6.5
7.0
Rising
floating (VUSBOVP_12C = '01', '10' or '11'
)
VUSBOVP_I2C = '01' or OVPSET pin =
floating (VUSBOVP_12C = '01', '10' or '11'
)
120
mV
V
Falling hystersis
Rising
VUSBOVP_I2C = '10' (OVPSET pin = mid
or ground) or OVPSET pin = low
(VUSBOVP_12C = ('10' or '11' )
10.8
11.3
VUSB_OVP
VUSBOVP_I2C = '10' (OVPSET pin = mid
or low ) or OVPSET pin = low
(VUSBOVP_12C = ('10' or '11' )
200
300
mV
Falling hystersis
VUSBOVP_I2C = '11' and OVPSET pin =
low
14.5
15.0
V
Rising
VUSBOVP_I2C = '11' and OVPSET pin =
low
mV
Falling hystersis
PROTECTION THRESHOLD and ACCURACY
VDROP OVP range
VBUS – VOUT. Programmable range
0
1000
mV
mV
mV
0 mV ≤ VDROP_OVP ≤ 640 mV
700 mV < VDROP_OVP ≤ 1000 mV
VDROP_OVP = 80 mV
10
VDROP OVP step size
VDROP_OVP
100
–8.0%
–5.0%
0
8.0%
5.0%
1000
VDROP OVP
comparator accuracy
VDROP_OVP = 160 mV
VDROP ALM range
VBUS – VOUT. Programmable range
0 mV ≤ VDROP_OVP ≤ 640 mV
700 mV < VDROOP_OVP ≤ 1000 mV
VDROP_ALM = 80 mV
mV
mV
mV
10
VDROP ALM step size
100
VDROP_ALM
–8.0%
–5.0%
8.0%
5.0%
VDROP ALM
comparator accuracy
VDROP_ALM = 160 mV
VDROP ALM falling
hysteresis
10
30
mV
VBUS OVP range
Programmable range
4.20
6.51
V
VBUS OVP step size
mV
VBUS_OVP = 4.20 V
VBUS_OVP = 4.50 V
VBUS_OVP = 5.49 V
–1.25%
–1.25%
–1.25%
1.25%
1.25%
1.25%
VBUS OVP comparator
accuracy
VBUS_OVP
VBUS OVP falling
hysteresis
50
mV
VBUS_OVP = 4.20 V
Programmable range
IBUS REG range
0
6.3
A
IBUS REG step size
100
mA
IBUS_REG
IBUS_REG = 1.5 A, –40 °C ≤ TA ≤ 85 °C
IBUS_REG = 1.5 A, TA = 25 °C
Programmable range
–20%
–10%
0
20%
10%
7.5
IBUS REG accuracy
IBUS OCP range
A
IBUS OCP step size
500
mA
IBUS_OCP
IBUS OCP comparator
accuracy
–20%
20%
IBUS_OCP = 1.5 A
8
Copyright © 2016, Texas Instruments Incorporated
bq25872
www.ti.com.cn
ZHCSFK5 –OCTOBER 2016
Electrical Characteristics (continued)
Unless otherwise noted, the specification in the following table applies over operating ambient temperature range –40 °C ≤ TA
≤ 85 °C. Typical values are for TA = 25 °C (unless otherwise noted)
PARAMETER
IBAT REG range
TEST CONDITIONS
Programmable range
MIN
TYP
MAX
UNIT
A
0
6.35
IBAT REG step
Rsense = 10 mΩ
50
mA
IBAT_REG
IBAT_REG = 2 A, Rsense = 10 mΩ
IBAT_REG = 5 A, Rsense = 10 mΩ
–6.5%
–4%
6.5%
2%
IBAT REG accuracy
IBAT OCP rising
threshold
Percentage of IBAT_REG threshold,
IBAT_REG = 6 A
105%
IBAT_OCP
IBAT OCP falling
threshold
Percentage of IBAT_REG threshold,
IBAT_REG = 6 A
102.5%
VBAT REG range
Programmable range
4.2
4.975
V
VBAT REG step size
12.5
mV
VBAT_REG = 4.35 V
VBAT_REG = 4.40 V
–1.5%
–1.5%
1.0%
1.0%
VBAT REG accuracy
VBAT_REG
VBAT OVP rising
threshold
Percentage of VBAT_REG threshold,
VBAT_REG = 4.40 V
104%
102%
VBAT_OVP
VBAT OVP falling
threshold
Percentage of VBAT_REG threshold,
VBAT_REG = 4.40 V
VOUT REG range
Programmable range
4.2
4.975
V
VOUT REG step size
25
mV
VOUT_REG
VOUT_REG = 4.35 V
VOUT_REG = 4.40 V
–0.5%
–0.5%
0.5%
0.5%
VOUT REG accuracy
VOUT OVP rising
threshold
Percentage of VOUT_REG threshold,
VOUT_REG = 4.40 V
104%
102%
VOUT_OVP
VOUT OVP falling
threshold
Percentage of VOUT_REG threshold,
VOUT_REG = 4.40 V
TS_BUS pin voltage
range
0.2
1.4
V
Programmable range
TS_BUS step size
25
mV
TSBUS_FLT
TS_BUS = 0.4 V
TS_BUS = 0.7 V
–4.0%
–4.0%
4.0%
4.0%
TS_BUS comparator
accuracy
TS_BUS hysteresis
1%
25
TS_BAT pin voltage
range
0.2
1.4
V
Programmable range
TS_BAT step size
mV
TSBAT_FLT
TS_BAT = 0.4 V
TS_BAT = 0.6 V
–2.5%
–2.5%
2.5%
2.5%
TS_BAT comparator
accuracy
TS_BAT hysteresis
1%
Copyright © 2016, Texas Instruments Incorporated
9
bq25872
ZHCSFK5 –OCTOBER 2016
www.ti.com.cn
Electrical Characteristics (continued)
Unless otherwise noted, the specification in the following table applies over operating ambient temperature range –40 °C ≤ TA
≤ 85 °C. Typical values are for TA = 25 °C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
INTEGRATED ADC: temperature range: 0°C ≤ TA ≤ 85°C
ADCRES
Resolution
10
bits
µs
ADC individual
measurement and
conversion time
30
tADC_CONV
ADC samples interval in
averaging mode
300
µs
A
tADC_INT
IBAT current
measurement range
0
7.504
RANGEIBAT
RESIBAT
ACCIBAT
IBAT current LSB
IBAT accuracy
8
8
mA
IBAT = 6 A
–2%
0
2%
IBUS current
measurement range
7.504
A
RANGEIBUS
RESIBUS
ACCIBUS
ACCIBUS
IBUS current LSB
IBUS accuracy
IBUS accuracy
mA
IBUS = 1.6 A
IBUS = 5 A
–5%
–4.5%
2.048
5%
4.5%
6.140
VBUS voltage
measurement range
V
RANGEVBUS
RESVBUS
ACCVBUS
VBUS voltage LSB
VBUS accuracy
4
4
4
4
1
4
4
mV
mV
V
VBUS = 4.5 V
–20
20
VUSB voltage
measurement range
2.048
6.140
RANGEVUSB
RESVUSB
ACCVUSB
VUSB voltage LSB
VUSB accuracy
mV
mV
V
VUSB = 4.5 V
–20
20
VBAT voltage
measurement range
2.048
6.140
RANGEVBAT
RESVBAT
ACCVBAT
VBAT voltage LSB
VBAT accuracy
mV
mV
V
VBAT = 4.4 V
-12
12
VOUT voltage
measurement range
2.048
6.140
RANGEVOUT
RESVOUT
ACCVOUT
VOUT voltage LSB
VOUT accuracy
mV
mV
mV
VOUT = 4.4 V
-12
0
12
VDROP voltage
measurement range
1000
RANGEVDROP
RESVDROP
ACCVDROP
VDROP voltage LSB
VDROP accuracy
mV
mV
V
VDROP = 200 mV
TS_BUS = 400 mV
TS_BAT = 400 mV
-10
0
10
TS_BUS voltage
measurement range
2.420
RANGETS_BUS
RESTS_BUS
ACCTS_BUS
TS_BUS voltage LSB
TS_BUS accuracy
mV
mV
V
-13.4
0
13.4
TS_BAT voltage
measurement range
2.420
RANGETS_BAT
RESTS_BAT
ACCTS_BAT
TS_BAT voltage LSB
TS_BAT accuracy
mV
mV
-13.4
13.4
10
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ZHCSFK5 –OCTOBER 2016
Electrical Characteristics (continued)
Unless otherwise noted, the specification in the following table applies over operating ambient temperature range –40 °C ≤ TA
≤ 85 °C. Typical values are for TA = 25 °C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
LOGIC I/O THRESHOLD (EN, INT, ADDR)
VIL
VIH
Input low threshold level ISINK = 5 mA
0.4
V
V
Input high threshold level ISINK = 5 mA
High level leakage
1.3
5
5
µA
ILEAK (INT)
VPULL-UP = 3.3 V
VPULL-UP = 3.3 V
VPULL-UP = 3.3 V
current
ILEAK
(CHGSTAT)
High level leakage
current
µA
µA
High level leakage
current
10
ILEAK (EN)
I2C TIMINGS
VIL
VIH
Input low threshold level VPULL-UP = 1.8 V, SDA and SCL
Input high threshold level VPULL-UP = 1.8 V, SDA and SCL
0.4
V
V
V
1.3
Output low threshold
IOL = 20 mA
level
0.4
5
VOL
High-level leakage
VPULL-UP = 1.8 V, SDA and SCL
current
µA
IBIAS
fSCL
SCL clock frequency
1
MHz
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6.6 Timing Requirements
MIN
NOM
MAX
UNIT
PROTECTION
OSC
Oscillator frequency
1.8
2
8
2.4
MHz
µs
tVBUS_OVP
tVBUS_OVP
VBUS OVP deglitch time, VBUS_OVP_DLY = 0
VBUS OVP deglitch time, VBUS_OVP_DLY = 1
128
8
µs
tIBUS_OCP_BLANK IBUS OCP deglitch time, OCP_RES = 0
µs
tIBUS_OCP
tIBUS_OCP_HP
tIBUS_OCP_RST
tIBAT_OCP
tVDROP_OVP
tVBAT_OVP
tVOUT_OVP
tLDO_RES
tLDO_ACTIVE
TTS_OTP
IBUS OCP deglitch time in hiccup mode, OCP_RES = 1
8
µs
Retry wait time for IBUS OCP in hiccup mode, OCP_RES = 1
Hiccup count reset timer
100
400
512
64
64
64
1
ms
ms
µs
IBAT OCP deglitch time
VDROP deglitch time
µs
VBAT OVP deglitch time
µs
VOUT OVP deglitch time
µs
LDO response time for IBUS, IBAT, VBAT, VOUT
LDO active signal deglitch time
TS_BAT and TS_BUS deglitch time
Reverse current protection (RCP) deglitch time
Short circuit protection (RCP) deglitch time
VOUT soft-start rise time
ms
µs
128
100
8
ms
µs
tIREV
tSCP
2
µs
tON_VOUT
tOFF_FET
0.5
1
ms
µs
Battery switch turn off time
Battery switch turn-off time, RVBUS = 100 Ω, CVBUS = 0 µF, when VVUSB
VUSBOVP to VOVPGATE falling (95 % threshold)
>
tOFF_FLT
100
ns
WATCHDOG[3:2] = 01
0.5
1
s
s
s
Watchdog
timer
tWTDG
WATCHDOG[3:2] = 10
WATCHDOG[3:2] = 11
2
12
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ZHCSFK5 –OCTOBER 2016
7 Typical Characteristics
4.44
4.43
4.42
4.41
4.4
2.1
2.08
2.06
2.04
2.02
2
VBAT = 4.40 V
IBAT = 2.0 A
1.98
1.96
1.94
1.92
1.9
4.39
4.38
4.37
4.36
-10
15
40
65
90
-10
15
40
65
90
Temperature (èC)
Temperature (èC)
D001
D002
D004
D006
图 1. VBAT ADC vs Temperature at 4.4 V
图 2. IBAT ADC vs Temperature at 2 A
6.1
4.44
4.43
4.42
4.41
4.4
IBAT = 6.0 A
VOUT = 4.40 V
6.08
6.06
6.04
6.02
6
5.98
5.96
5.94
5.92
5.9
4.39
4.38
4.37
4.36
-10
15
40
65
90
-10
15
40
65
90
Temperature (èC)
Temperature (èC)
D003
图 3. IBAT ADC vs Temperature at 6 A
图 4. VOUT ADC vs Temperature at 4.4 V
40
35
30
25
20
15
10
5
17
16
15
14
13
12
11
10
9
EN = low, ADC disabled, CHG_EN = 0
VBUS = 3.0 V
VBUS = 3.6 V
0
-50
8
-50
-25
0
25
50
75
100
-25
0
25
50
75
100
Temperature (èC)
Temperature (èC)
D005
图 5. Quiescent Current with Battery Only vs Temperature
图 6. Rdson vs Temperature
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Typical Characteristics (接下页)
4.46
4.44
4.42
4.4
4.46
VOUT = 4.35 V
VBAT = 4.35 V
VBAT = 4.40 V
VOUT = 4.40 V
4.44
4.42
4.4
4.38
4.36
4.34
4.32
4.3
4.38
4.36
4.34
4.32
4.3
4.28
4.26
-50
-25
0
25
50
75
100
-50
-25
0
25
50
75
100
Temperature (èC)
Temperature (èC)
D007
D008
图 7. VOUT Regulation vs Temperature
图 8. VBAT Regulation vs Temperature
2.1
6.1
6.08
6.06
6.04
6.02
6
IBAT = 2.0 A
IBAT = 6.0 A
2.08
2.06
2.04
2.02
2
1.98
1.96
1.94
1.92
1.9
5.98
5.96
5.94
5.92
5.9
-50
-25
0
25
50
75
100
-50
-25
0
25
50
75
100
Temperature (èC)
Temperature (èC)
D009
D010
图 9. IBAT Regulation vs Temperature at 2 A
图 10. IBAT Regulation vs Temperature at 6 A
14
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ZHCSFK5 –OCTOBER 2016
8 Detailed Description
8.1 Overview
The bq25872 is an I2C controlled device and a single cell Li-Ion battery charger. The device allows 7-A charging
current with 13-mΩ MOSFETs for minimum power loss. A 10 -bit ADC, four linear regulation loops and multiple
OVP and OCP are integrated for host monitoring and safe operation of the device.
8.1.1 Device Protection Overview
The following table summarizes the protection features implemented in the device.
表 1. Protection Features Overview
PROTECTION
DESCRIPTION
RESPOND
NAME
Monitors VUSB voltage and compares to the voltage
defined by OVPSET and VUSBOVP_I2C
(REG29[3:2])
VUSB OVP
Turn off external OVPFET via OVPGATE
Turn off load switch after a deglitch time of tVBUS_OVP
Monitors VBUS voltage and compares to the
threshold programmed in REG 0A
VBUS_OVP
VOUT_REG
VOUT_OVP
Monitors VOUT voltage and compares to the
threshold programmed in REG 0B
Enable linear regulation of battery switch within a response time
of tLDO_RES
Monitors VOUT voltage and compares to 1.04 times
of the threshold programmed in REG 0B
Turn off load switch after a deglitch time of tVOUT_OVP
Monitors voltage difference between VBUS and
VDROP_OVP VOUT (VBUS – VOUT) and compares to the
threshold programmed in REG 0C
Turn off load switch after a deglitch time of tVDROP_OVP
Monitors voltage difference between VBUS and
VDROP_ALM VOUT (VBUS – VOUT) and compares to the
threshold programmed in REG 0D
INT is asserted low to alert host
Monitors VBAT voltage and compares to the
VBAT_REG
Enable linear regulation of battery switch within a response time
of tLDO_RES
threshold programmed in REG 0E
Monitors VBAT voltage and compares to 1.04 times
VBAT_OVP
Turn off load switch after a deglitch time of tVBAT_OVP
of the threshold programmed in REG 0E
Monitors battery current measured by sensing
resistor and compares to the threshold programmed
in REG 0F
Enable linear regulation of battery switch within a response time
of tLDO_RES
IBAT_REG
Monitors VBAT voltage and compares to 1.05 times
of the threshold programmed in REG 0E
IBAT_OCP
IBUS_OCP
IBUS_REG
IBUS_RCP
Turn off load switch after a deglitch time of tVBAT_OVP
Turn off load switch after a deglitch time of tIBUS_OCP
Monitors input current and compares to the threshold
programmed in REG 09
Monitors input current and compares to the threshold Enable linear regulation of battery switch within a response time
programmed in REG 10
of tLDO_RES
Monitors current flowing from battery to adaptor and
compares to the threshold selected in REG 06
Turn off load switch after a deglitch time of tIBUS_RCP
Monitors temperature based on voltage measured by
a negative temperature coefficient (NTC) resistor at
VBUS and compares to the threshold programmed in
REG 11
TS_BUS_OTP
TS_BAT_OTP
Turn off load switch after a deglitch time of tTS_OTP
Turn off load switch after a deglitch time of tTS_OTP
Monitors temperature based on voltage measured by
a negative temperature coefficient (NTC) resistor at
battery and compares to the threshold programmed
in REG 12
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8.2 Functional Block Diagram
Q1
Q2
VOUT
VBUS
Internal Charge Pump
VBUS_PD_EN
Internal Power
VUSB
GND
Supply
+
VUSB_OVP
External FET
charge pump
OVPGATE
OVPSET
VBAT_ADC
IBAT_ADC
SCL
SDA
EN
TBUS_ADC
TBAT_ADC
VDROP_ADC
10-Bit ADC
Digital Core
INT
BATP
BATN
+
+
CHGSTAT
VBAT_REG
TS_BUS
TS_BAT
+
+
+
+
VBUS
TS_BUS_FLT
TS_BAT_FLT
VBUS_OVP
VBUS-VOUT
VDROP_OVP
Protection
RCP
RCP
+
+
+
+
VBUS-VOUT
VDROP_ALM
IBUS
VOUT
VOUT_REG
IBUS_OCP
SRP
SRN
+
VOUT-VBUS
RCP
+
+
IBAT_REG
Copyright © 2016, Texas Instruments Incorporated
8.3 Feature Description
8.3.1 Device Power Up
The internal bias circuits of the device are powered from higher of the two voltages among VUSB, VBUS and
VOUT as long as one of the pins is above its respective PRESENT threshold (VUSBPRESENT, VBUSPRESENT, or
VOUTPRESENT). Once either VVUSB > VUSBPRESENT, VVBUS > VBUSPRESENT, or VVOUT > VOUTPRESENT is qualified,
the device is considered to have a valid power supply. However, the device will begin to draw current from VBUS
or VOUT (depending upon which supply is present) once either supply is above its respective UVLO threshold.
16
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Feature Description (接下页)
8.3.2 Battery Switch (Q1 + Q2)
The device contains an integrated 13mΩ battery switch that is capable of handling up to 7 A of current. This
battery switch can be controlled by the host via CHG_EN I2C bit. The device can be disabled, including the
battery switch and the I2C core, by pulling the EN pin low. To turn on the battery switch charger for conduction,
the EN pin must be pulled high, CHG_EN bit must be set to ‘1’, and no fault conditions must be present (unless
they have been disabled in EVENT_1_EN register). See EVENT_1 and EVENT_2 registers for a list of
faults/events. In the event of a fault/event, the battery switch will be automatically disabled, and the host will be
notified via the INT for error reporting if the corresponding event bit is unmasked in the EVENT_x_MASK
registers.
In order to ensure that the IBUS OCP threshold is not falsely tripped during turn-on of the battery switch, the
device employs a soft-start scheme where the battery switch is slowly turned to minimize the inrush current. The
rise time of VOUT is tON_VOUT
.
8.3.3 Integrated 10-bit ADC for Monitoring
With the integrated 10-bit ADC of the device, the user application can monitor the voltage of VUSB, the voltage
and current of VBUS, voltage of VOUT and VUSB, and the voltage and current of the battery. The ADC is also
used for temperature reporting of the internal junction temperature, battery temperature (via external resistor
divider and NTC thermistor), and VBUS connector temperature (via external resistor divider and NTC thermistor).
The integrated ADC has a conversion time of tADC_CONV for each parameter (except IBAT_ADC which has
conversion time of 2 x tADC_CONV ). The total conversion time of all parameters (in 1-shot mode) is between 80 µs
and 140 µs. The rate at which the ADC output registers are updated depends on the settings of ADC_AVG_EN,
ADC_SAMPLES, and the parameter conversions that have been enabled in the ADC_MASK register.
To enable the ADC, the ADC_EN bit must be set to ‘1’. The ADC is allowed to operate if either VVUSB
>
VUSBPRESENT, VVBUS > VBUSPRESENT or VVOUT > VOUTPRESENT is valid. If ADC_EN is set to ‘1’ before VUSB or
VBUS or VOUT reach their respective PRESENT threshold, then ADC conversion will be postponed until one of
the power supplies reaches their respective PRESENT threshold. If EN pin is asserted low, then ADC conversion
is not allowed.
The integrated ADC has two conversion rate options – 1-shot conversion (only one conversion) and continuous
conversion (back-to-back conversions). To select the appropriate conversion rate, the ADC_RATE bit must be
set accordingly (‘0’ for 1-shot, ‘1’ for continuous). If ADC_AVG_EN is set to ‘0’, the ADC will convert
instantaneous measurements. If ADC_AVG_EN is set to ‘1’, the average measurement of a parameter (in both
continuous and 1-shot mode) will be determined by the setting of ADC_SAMPLES. If the user reads the output
registers before the ADC averaging is complete, then the read-back value would be unchanged from the
previous converted measurement. However, the value in the register will not change during the read-back of the
register(s). If the measured signal is outside of the range of the ADC output register in question, the reported
value in the ADC will be clamped to the min/max of the range specified. When ADC_EN is changed from 1 to 0,
the ADC registers will maintain their values from the previous converted measurement.
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Feature Description (接下页)
The user application has the option of selecting which parameters (voltage, current, temperature) the ADC needs
to convert when the ADC is set to continuous conversion mode (ADC_RATE is set to ‘1’) or in 1-shot mode
(ADC_RATE is set to ‘0’). By default, all parameters (VUSB_ADC, IBUS_ADC, VBUS_ADC, IBAT_ADC,
VBAT_ADC, VOUT_ADC, VDROP_ADC, TBUS_ADC, TBAT_ADC, TDIE_ADC) will be converted in 1-shot and
continuous conversion mode unless disabled in the ADC_MASK register. If an ADC parameter is masked (by
setting the corresponding bit in the ADC_MASK_x register), then the value in that register will be from the last
valid ADC conversion or the default POR value (which is all zeros if no conversions have taken place). If an ADC
parameter is masked in the middle of an ADC measurement cycle, the device will finish the conversion of that
parameter in the current conversion cycle and will not convert that parameter starting the next conversion cycle.
Even though no conversion takes place when all ADC measurement parameters are masked off, the ADC
circuitry is active and ready to begin conversion as soon as one of the bits in the ADC_MASK register is set to
‘0’.
The ADC_DONE bit signals when a 1-shot mode conversion is completed. During continuous conversion mode,
this bit is always set to ‘0’.
The ADC_EN bit controls when the ADC is enabled for a conversion. Upon enabling the ADC, the ADC
conversion will follow the settings in ADC_AVG_EN, ADC_SAMPLE, and ADC_RATE.
ADC conversion operates independently of the faults present in the device. ADC conversion will continue even
after a fault has occurred (that causes the battery switch to be disabled), and the host must set ADC_EN = ‘0’ to
disable ADC.
ADC readings are only valid for DC states of the signals, not for transients.
8.3.4 Linear Regulation Mode (LDO)
The device employs LDO mode that helps regulate VOUT voltage, battery voltage, input current and battery
current. In an event that the VOUT_REG, VBAT_REG, IBUS_REG or IBAT_REG threshold is exceeded, the
battery switch will act as an LDO and will regulate VOUT, VBAT, IBUS and IBAT (depending upon which
threshold is exceeded). The purpose of LDO mode is to provide temporary protection until the host is able to
read the EVENT_x registers (upon INT trigger), ADC output registers, and then update the adapter voltage
accordingly.
When VOUT_REG, VBAT_REG, or IBAT_REG threshold is exceeded, the response time of the LDO will be
1ms. Depending upon which LDO mode event occurs, the corresponding bit (VBAT_REG_LDO,
IBAT_REG_LDO, VOUT_REG_LDO) will be set in EVENT_1 register and INT will be asserted low to alert the
host (if the corresponding bit is not masked in EVENT_1_MASK register).
18
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Feature Description (接下页)
8.3.5 Protection Features
The device contains various protection features that are active depending upon the states of various inputs:
•
If VVUSB > VUSBPRESENT, VVBUS > VBUSPRESENT, VVOUT > VOUTPRESENT, EN asserted high, and CHG_EN = ‘1’
–
Active protection: VBUS_OVP, IBUS_OCP, VOUT_OVP, VBAT_OVP, IBAT_OCP, SCP, RCP,
VDROP_OVP
•
If VVUSB > VUSBPRESENT, VVBUS > VBUSPRESENT, VVOUT > VOUTPRESENT, EN asserted high, and CHG_EN = ‘0’
–
–
Active protection: VBUS_OVP, IBUS_OCP, VOUT_OVP, IBAT_OCP, SCP, RCP, VDROP_OVP
VBAT_OVP active until VBAT OVP condition is over (protection becomes inactive on falling threshold of
VBAT_OVP, which is 102% of VBAT_REG setting)
•
•
If VVUSB > VUSBPRESENT, EN asserted low, and CHG_EN = ‘0’
Active protection: VUSB_OVP
If VVUSB < VUSBPRESENT, VVBUS > VBUSPRESENT, VVOUT > VOUTPRESENT, and CHG_EN = ‘0’
–
–
–
Active protection: VUSB_OVP
VOUTPRESENT, VBUSPRESENT, and VUSBPRESENT comparators active
Tripping any of these protection faults will cause the battery switch to be disabled (unless the protection is
disabled in EVENT_1_EN and EVENT_2_EN registers) and an interrupt to be issued on the INT pin (see INT
Pin, EVENT_x Registers, EVENT_x_MASK Registers section for details of when INT is toggled).
8.3.5.1 Reverse Current Protection (RCP)
The device monitors the current flow from VBUS to VOUT to ensure there is no reverse current (current flow
from VOUT to VBUS). In an event that a reverse current flow is detected, the battery switch is disabled within
tOFF_FET after a deglitch time of tIREV and CHG_EN is set to ‘0’. Host intervention is required to set CHG_EN to ‘1’
to enable the power switch again. The RCP threshold is set by the RCP_SET bit.
Reverse current protection is always active when the device has valid power. The RCP threshold is based on the
RCP_SET bit setting in the CONTROL register. It has a response delay of tIREV. When RCP is tripped,
IBUS_IREV_FLT bit in the EVENT_1 register is set to ‘1’, and INT is asserted low to alert the host (unless
masked by IBUS_IREV_MASK).
8.3.5.2 Internal Thermal Shutdown
The device monitors the die junction temperature and the battery switch is disabled when device junction
temperature reaches TSHUT within tOFF_FET and CHG_EN is set to ‘0’ . When the internal thermal shutdown is
triggered, INT is asserted low to alert the host, and the device temperature must drop by TSHUT_HYS before the
battery switch can be enabled again (host must enable battery switch). While the TSHUT condition persists (and
before the junction temperature dropped by TSHUT_HYS), all other functions are unaffected.
If the DIE_TEMP_FLT threshold has been crossed, TSHUT_FLT bit in EVENT_2 register is set to ‘1’, and INT
will assert low to alert the host (no mask bit for TSHUT_FLT). After the TSHUT_FLT is cleared by the host with a
register read, it is possible the TSHUT_FLT bit is set again if the die junction temperature has not reduced by
TSHUT_HYS.
DIE_TEMP_FLT allows the user to select TSHUT thresholds between different junction temperatures as the
thermal shutdown point. DIE_TEMP_ADC is the die (junction) temperature of the device that is measured via the
10-bit ADC.
The ADC measurement (DIE_TEMP_ADC) is independent of the TSHUT fault that triggers TSHUT_FLT in the
EVENT_x register. Therefore, it is possible to have the ADC output value be a higher value that the
DIE_TEMP_FLT threshold, while the TSHUT fault has not yet been triggered.
8.3.5.3 Input Overvoltage Protection
The device integrates the functionality of an overvoltage protector. The device can be paired with an external N-
channel FET to block input voltages higher than the setting programmed by OVPSET pin. The device senses the
input (via VUSB) and turns the external N-channel FET on or off (via OVPGATE pin) to protect the downstream
system. This eliminates the need for a separate OVP chip to protect the overall system. The integrated OVP
feature has a reaction time of tOFF_FLT (the actual time to turn off OVP FET will be longer and depends upon the
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Feature Description (接下页)
FET gate capacitance) and does not depend on the EN pin status (i.e., feature is always active as long as VVUSB
> VUSBPRESENT). If the EN pin is pulled high, then I2C communication to the device is available, and the OVP
threshold can then be changed via the VUSBOVP_I2C bits. The final VUSB OVP threshold is set by the lower
setting of the OVPSET pin and the VUSBOVP_I2C bits. VUSBOVP_I2C bits are not reset when EN is asserted
low and are only reset by REG_RST or a POR event.
8.3.5.3.1 OVPSET pin
The data on the SDA line must be stable during the HIGH period of the clock. The HIGH or LOW state of the
data line can only change when the clock signal on the SCL line is LOW. One clock pulse is generated for each
data bit transferred.
The default power up OVP threshold can be set via the OVPSET pin with a single external resistor to one of
three preset thresholds – 6.5 V, 10.5 V, and 14 V. The OVPSET pin will source a current to determine the
resistance on the pin, and then set the OVP threshold accordingly. The OVPSET pin will follow these threshold
assignments:
•
•
•
Highest pin threshold (floating) = 6.5-V OVP threshold
Lowest pin threshold (tied to GND) = 14.5-V OVP threshold
Mid-point pin threshold (22 kΩ to GND) = 10.5 V
20
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Feature Description (接下页)
8.3.5.4 IBUS and VBUS Protection
Over-current protection on VBUS (IBUS_OCP) monitors the current flow from VBUS to VOUT pins. IBUS_OCP
protection is always active when the battery switch is enabled, and the protection has a deglitch time that
depends on the OCP_RES setting as described below.
If OCP_RES = ‘0’ (blanking mode), the device will wait tIBUS_OCP_BLANK before disabling the battery switch within
tOFF_FET and setting CHG_EN to ‘0’. When the battery switch is disabled, IBUS_OCP_FLT is set to ‘1’. If during
the tIBUS_OCP_BLANK duration a short circuit protection scenario occurs, then the device will follow the behavior as
listed in short circuit protection (SCP). Once the battery switch is disabled, CHG_EN is set to ‘0’ and host
intervention is required to set CHG_EN to ‘1’ to enable the battery switch again.
IBUS_OCP
tSCP
IBUS_OCP
ISCP
ISCP
IBUS
IBUS
tOFF_FET
VOUT
VOUT
tIBUS_OCP_BLANK
tOFF_FET
tIBUS_OCP_BLANK
time starts here
图 11. IBUS OCP and SCP
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Feature Description (接下页)
If OCP_RES = ‘1’ (hiccup mode), the device will turn off the battery switch within tIBUS_OCP and will attempt to turn
on the battery switch every tIBUS_OCP_HP, up to seven times before latching off the battery switch. Upon latching
off after the seventh try, IBUS_OCP_FLT is set to ‘1’. Once the battery switch is latched off, CHG_EN is set to ‘0’
and host intervention is required to set CHG_EN to ‘1’ to enable the battery switch again.
Hiccup count = 1 Hiccup count = 2
Hiccup count = 1
Hiccup count resets
ISCP
IBUS_OCP
IBUS
tIBUS_OCP
tIBUS_OCP
tIBUS_OCP
tIBUS_HP_RST
tIBUS_OCP_HP
VOUT
tOFF_FET
tOFF_FET
tOFF_FET
图 12. IBUS OCP in Hiccup Mode
VBUS over-voltage protection (VBUS_OVP) monitors the voltage on VBUS. VBUS_OVP protection is always
active when the device voltage is above at least one PRESENT level (VBUS or VOUT), and the protection has a
selectable deglitch time set by VBUS_OVP_DLY. When VBUS_OVP threshold is reached, the battery switch is
turned off in tVBUS_OVP and latched off. If the VBUS_OVP or IBUS_OCP value written to the register is greater
than the max defined value for the register, then the corresponding register will be set to the highest defined
value.
If a threshold has been crossed (IBUS_OCP or VBUS_OVP), the appropriate bit in the EVENT_1 register is
updated (set to ‘1’ if threshold is crossed, ‘0’ if threshold is not crossed). If the EVENT_1_MASK bit is not set to
‘1’ for the corresponding bit in the EVENT_1 register, then INT will assert low to alert the host of a fault.
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Feature Description (接下页)
8.3.5.5 IBAT and VBAT Protection
The device monitors current through the battery by monitoring the voltage across the external, series battery
sense resistor. The differential voltage of this sense resistor is measured on SRP and SRN. A 10-mΩ series
resistor is recommended for battery current monitoring. A lower resistor value can be used, but it will result in
lower measurement accuracy. A higher resistor value can be used, but it will result in decreased charging
efficiency.
When the IBAT_REG threshold is reached, the device will go into LDO mode to regulate the battery current at
the IBAT_REG threshold. See LDO mode section for more details about the device operation during LDO mode.
If the IBAT_OCP threshold is reached and IBAT_OCP protection has been enabled, the battery switch will be
disabled within tOFF_FET after a deglitch time of tIBAT_OCP and CHG_EN is set to ‘0’. Host intervention is required to
set CHG_EN to ‘1’ to enable the battery switch again.
The device monitors battery voltage by measuring the differential voltage on BATP and BATN pins. When the
VBAT_REG threshold is reached, the device will go into LDO mode to regulate the battery voltage at the
VBAT_REG threshold. See LDO mode section for more details about the device operation during LDO mode. If
the VBAT_OVP threshold is reached and VBAT_OVP protection is enabled, the battery switch will be disabled
within tOFF_FET after a deglitch time of tVBAT_OVP and CHG_EN is set to ‘0’. Host intervention is required to set
CHG_EN to ‘1’ to enable the battery switch again. If the VBAT_REG or IBAT_REG value written to the register is
greater than the max defined value for the register, then the corresponding register will be set to the highest
defined value.
If a threshold has been reached (IBAT_REG, VBAT_REG, IBAT_OCP or VBAT_OVP), the appropriate bit in the
EVENT_x register is updated (set to ‘1’ if threshold is crossed, ‘0’ if threshold is not crossed). If the
EVENT_x_MASK bit is not set to ‘1’ for the corresponding bit in the EVENT_x register, then INT will assert low to
alert the host of a fault.
8.3.5.6 VOUT Protection
The device monitors voltage on VOUT when the device has a valid power supply. When the VOUT_REG
threshold is reached, the device will go into LDO mode to regulate the VOUT voltage at the VOUT_REG
threshold. See LDO mode section for more details about the device operation during LDO mode. If the
VOUT_OVP threshold is reached and VOUT_OVP protection is enabled, the battery switch will be disabled
within tOFF_FET after a deglitch time of tVOUT_OVP and CHG_EN is set to ‘0’. Host intervention is required to set
CHG_EN to ‘1’ to enable the battery switch again. If the VOUT_REG value written to the register is greater than
the max defined value for the register, then VOUT_REG will be set to the highest defined value for the register.
If a threshold has been reached (VOUT_REG or VOUT_OVP), the appropriate bit in the EVENT_1 register is
updated (set to ‘1’ if threshold is crossed, ‘0’ if threshold is not crossed). If the EVENT_x_MASK bit is not set to
‘1’ for the corresponding bit in the EVENT_x register, then INT will assert low to alert the host of a fault.
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Feature Description (接下页)
8.3.5.7 VDROP Protection
VDROP is the voltage difference from VBUS to VOUT and can be used to monitor the health of MOSFET and
power loss of the device. There are two VDROP thresholds, VDROP alarm (VDROP_ALM) and VDROP fault
(VDROP_FLT). VDROP_ALM is an indicator (via I2C register bit and INT) to alert the host that the voltage
differential between VBUS and VOUT is higher than normal, and that the host to should take action to reduce
this drop. VDROP_OVP is a fault threshold that results in the battery switch being disabled within tOFF_FET after a
deglitch time of tVDROP_OVP and CHG_EN set to ‘0’ when VDROP_OVP protection is enabled. Host intervention is
required to set CHG_EN to ‘1’ to enable the battery switch again. If the VDROP_OVP or VDROP_ALM value
written to the register is greater than the max defined value for the register, then the corresponding register will
be set to the highest defined value.
If a threshold has been reached (VDROP_ALM or VDROP_OVP), the appropriate bit in the EVENT_1 register is
updated (set to ‘1’ if threshold is crossed, ‘0’ if threshold is not crossed). If the EVENT_x_MASK bit is not set to
‘1’ for the corresponding bit in the EVENT_x register, then INT will assert low to alert the host of a fault.
VDROP_ALM does not affect the state of the battery switch and only causes INT to assert low when the
threshold is crossed. VDROP_OVP does turn off the battery switch and causes INT to assert low if this threshold
is crossed. Therefore, if VDROP_ALM threshold is set higher than the VDROP_OVP threshold accidentally (user
error), then VDROP_ALM functionality is never triggered since VDROP_OVP threshold will turn off the battery
switch and assert INT low.
注
The threshold of VDROP_OVP and VDROP_ALM is around 13 mV lower than the actual
setting when VDROP ADC is enabled.
8.3.5.8 VBUS Temperature (TS_BUS_FLT) and Battery Temperature (TS_BAT_FLT)
TBUS_OTP and TBAT_OTP protection is active whenever the device has a valid power supply. The purpose of
VBUS temperature is to have connector temperature monitor to improve user experience. TS_BUS and TS_BAT
both rely on a resistor divider that has an external pull-up voltage. Internally, the TS_BUS and TS_BAT pins are
clamped to 2.42 V. Place a negative coefficient thermistor in parallel to the low-side resistor. A fault on the
TS_BUS and TS_BAT pin is triggered on the falling edge of the voltage threshold (signifying a “hot”
temperature).
If the TBUS_OTP or TBAT_OTP threshold is reached, the battery switch will be disabled within tOFF_FET after a
deglitch time of tTS_OTP and CHG_EN is set to ‘0’. Host intervention is required to set CHG_EN to ‘1’ to enable
the battery switch again. If the TS_BUS_FLT or TS_BAT_FLT value written to the register is greater than the
max defined value for the register, then the corresponding register will be set to the highest defined value.
For TS_BUS_FLT and TS_BAT_FLT, if a threshold has been crossed, the appropriate bit in the EVENT_x
register is updated (set to ‘1’ if threshold is crossed, ‘0’ if threshold is not crossed). If the EVENT_x_MASK bit is
not set to ‘1’ for the corresponding bit in the EVENT_1 register, then INT will toggle to alert the host of a fault.
注
TS_BUS_FLT will not trip when TS_BUS ADC is enabled.
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Feature Description (接下页)
8.3.6 I2C Serial Interface
The device uses I2C compatible interface for flexible charging parameter programming and instantaneous device
status reporting. I2C communication to the device is available as long as VVUSB > VUSBUVLO or VVBUS
>
VBUSUVLOor VVOUT > VOUTUVLO. I2C™ is a bi-directional 2-wire serial interface developed by Philips
Semiconductor (now NXP Semiconductors). Only two bus lines are required, a serial data line (SDA) and a serial
clock line (SCL). Devices can be considered as masters or slaves when performing data transfers. A master is
the device which initiates a data transfer on the bus and generates the clock signals to permit that transfer. At
that time, any device addressed is considered a slave.
The device operates as a slave device with address set by the ADDR pin. The device receives control inputs
from the master device like micro controller or a digital signal processor through REG00-REG29 and REG40.
Register read between REG29 and REG39 beyond REG40 returns 0xFF. The I2C interface supports standard
mode (up to 100 kbit/s), fast mode (up to 400 kbit/s), and fast mode plus (up to 1 Mbit/s). Connect the SDA and
SCL pins to the positive supply voltage via a current source or pull-up resistor. When the bus is free, both lines
are high. The SDA and SCL pins are open drain.
The device supports 7-bit addressing. The 8th bit will change depending upon the command (read or write) that
is issued. The device’s 7-bit address is defined as shown in the image below.
Slave Address
1
1
0
0
1
0
1
R/W
图 13. Slave Address
8.3.6.1 Data Validity
The data on the SDA line must be stable during the HIGH period of the clock. The HIGH or LOW state of the
data line can only change when the clock signal on the SCL line is LOW. One clock pulse is generated for each
data bit transferred.
SDA
SCL
Data line stable;
Data valid
Change of data
allowed
图 14. Bit Transfer on the I2C Bus
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Feature Description (接下页)
8.3.6.2 START and STOP Conditions
All transactions begin with a START (S) and can be terminated by a STOP (P). A HIGH to LOW transition on the
SDA line while SCL is HIGH defines a START condition. A LOW to HIGH transition on the SDA line when the
SCL is HIGH defines a STOP condition.
START and STOP conditions are always generated by the master. The bus is considered busy after the START
condition, and free after the STOP condition.
SDA
SDA
SCL
SCL
START
(S)
STOP
(P)
图 15. START and STOP Conditions
8.3.6.3 Byte Format
Every byte on the SDA line must be 8 bits long. The number of bytes to be transmitted per transfer is
unrestricted. Each byte has to be followed by an Acknowledge bit. Data is transferred with the Most Significant
Bit (MSB) first. If a slave cannot receive or transmit another complete byte of data until it has performed some
other function, it can hold the clock line SCL low to force the master into a wait state (clock stretching). Data
transfer then continues when the slave is ready for another byte of data and release the clock line SCL.
Acknowledgement signal from slave
Acknowledgement signal from receiver
MSB
SDA
SCL
S or Sr
1
2
7
8
9
1
2
8
9
P or Sr
ACK
ACK
START or Repeated START
STOP or Repeated START
图 16. Data Transfer on the I2C Bus
8.3.6.4 Acknowledge (ACK) and Not Acknowledge (NACK)
The acknowledge takes place after every byte. The acknowledge bit allows the receiver to signal the transmitter
that the byte was successfully received and another byte may be sent. All clock pulses, including the
acknowledge 9th clock pulse, are generated by the master.
The transmitter releases the SDA line during the acknowledge clock pulse so the receiver can pull the SDA line
LOW and it remains stable LOW during the HIGH period of this clock pulse.
When SDA remains HIGH during the ninth clock pulse, this is the Not Acknowledge signal. The master can then
generate either a STOP to abort the transfer or a repeated START to start a new transfer.
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Feature Description (接下页)
8.3.6.5 Slave Address and Data Direction bit
After the START, a slave address is sent. This address is 7 bits long followed by the eighth bit as a data direction
bit (bit R/W). A zero indicates a transmission (WRITE) and a one indicates a request for data (READ).
SDA
S
8
9
8
9
8
9
P
SCL
1-7
1-7
1-7
START
ADDRESS
R/W
ACK
DATA
ACK
DATA
ACK
STOP
图 17. Complete Data Transfer
1
7
1
0
1
8
1
1
7
1
1
1
S
Slave Address
ACK
Reg Address
ACK
S
Slave Address
ACK
8
1
1
Data
NCK
P
图 18. Single Read
If the register address is not defined, the charger device send back NACK and go back to the idle state.
8.3.6.6 Multi-Read and Multi-Write
The charger device supports multi-read and multi-write on REG00 through REG08.
1
7
1
0
1
8
1
1
7
1
1
1
S
Slave Address
ACK
Reg Address
ACK
S
Slave Address
ACK
8
1
8
1
8
1
1
Data at Address
ACK
Data at Address +1
ACK
Data at Addr+N
NCK
P
图 19. Multi-Read
EVENT_1, EVENT_2, and EVENT_3 keep all the information from last read until the host issues a new read. For
example, if VBUS_OVP fault occurs but recovers later, the fault register EVENT_1 reports the fault when it is
read the first time, but returns to normal when it is read the second time. In order to get the fault information at
present, the host has to read EVENT_1, EVENT_2, and EVENT_3 for the second time.
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8.4 Device Functional Modes
The device is a host controlled device. After power-on-reset, all the registers are in the default settings. All the
device parameters can be programmed by the host. Writing 1 to REG 06 [0] will reset all registers to default
setting. When watchdog timer expires, charge enable bit (REG06 [4]) and ADC enable bit (REG07 [3]) will be
reset to default settings. To prevent watchdog timer expiring, the host has to read or write any register before the
watchdog timer expires, or disable watchdog timer by setting REG06 [3:2] = 00.
thw
íatchdog timer expired
weset registers
L2/ interface enabled
ò
{tart íatchdog timer
Iost programs registers
L2/ írite?
weset íatchdog Çimer
weset w9D 06 bit [4]
w9D 07 bit [3]
weset w9D 06
bit[0]
ò
ò
ꢀ
íatchdog Çimer 9xpired?
图 20. Operation Mode
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8.5 I2C Register Maps
8.5.1 I2C Register Summary Table
表 2. I2C Register Summary Table
I2C ADDRESS
0x00
R/W
R
REGISTER NAME
DESCRIPTION
Device rev and device ID
POR STATE
0x03
DEVICE_INFO
EVENT_1_MASK
EVENT_2_MASK
EVENT_1
0x01
R/W
R/W
R
Masks INT toggle of events in EVENT_1
Masks INT toggle of events in EVENT_2
First event register
0x00
0x02
0x00
0x03
0x00
0x04
R
EVENT_2
Second event register
0x00
0x05
R/W
EVENT_1_EN
Enables/disables protection in EVENT_1 register
0xFE
Settings for battery switch, watchdog, reset, and RCP
threshold
0x06
0x07
R/W
R/W
CONTROL
ADC_CTRL
0x2C
Contains ADC control bits such as enable/disable, rate, and
number of samples to take
0x87
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
0x20
0x21
0x22
0x23
0x24
0x25
0x26
0x27
0x28
0x29
0x40
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
ADC_MASK
PROTECTION
VBUS_OVP
VOUT_REG
VDROP_OVP
VDROP_ALM
VBAT_REG
IBAT_REG
Controls which parameters the ADC converts – first set
Deglitch setting and VBUS OCP threshold
Sets VBUS OVP threshold
0xFF
0xA0
5.49 V
4.4 V
300 mV
100 mV
4.3 V
2 A
Sets VOUT voltage regulation threshold
Sets the VDROP OVP threshold
Sets the VDROP alarm threshold
Battery (BATP – BATN) regulation threshold
Sets battery current regulation threshold
Sets VBUS REG threshold
IBUS_REG
5 A
TS_BUS_FLT
TS_BAT_FLT
Sets VBUS temperature threshold
Sets battery temperature threshold
0.6 V
0.7 V
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x04
0x00
0x00
0x00
0x00
0x6E
0x03
VBUS_ADC
IBUS_ADC
VOUT_ADC
VDROP_ADC
VBAT_ADC
IBAT_ADC
TBUS_ADC
TBAT_ADC
ADC output of VBUS voltage measurement
ADC output of VBUS current measurement
ADC output of VOUT voltage measurement
ADC output of (VBUS – VOUT) voltage measurement
ADC output of battery voltage measurement
ADC output of battery current measurement
ADC output of TS_BUS voltage
R
R
R
R
R
R
R
R
R
R
R
R
R
R
ADC output of TS_BAT voltage
R
R
DIE_TEMP_ADC
EVENT_3_EN
EVENT_3_MASK
EVNET_3
ADC output of the die temperature
Enables/disables protection in EVENT_3 register
Masks INT toggle of events in EVENT_3
Third event register
R/W
R/W
R/W
R
VUSB_ADC
ADC output of VUSB voltage
R
R/W
R/W
CONTROL_2
VUSB settings
TDIE_TEMP_FLT
Setting die over temperature fault threshold
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8.5.2 REG00 (DEVICE_INFO)
图 21. REG00 (DEVICE_INFO)
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
1
R
R
R
R
R
R
R
R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表 3. REG00 (DEVICE_INFO)
Reset
Bit
Field
Type
Description
REG_RST Watchdog
EN
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
7
6
5
4
3
2
1
0
Reserved
R
R
R
R
R
R
R
R
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Reserved bit. Always reads 0.
Reserved bit. Always reads 0.
Device revision.
Reserved
DEVICE_REV[2]
DEVICE_REV[1]
DEVICE_REV[0]
DEVICE_ID[2]
DEVICE_ID[1]
DEVICE_ID[0]
Device revision.
Device revision.
Device ID 011
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8.5.3 REG01 (EVENT_1_MASK)
图 22. REG01 (EVENT_1_MASK)
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表 4. REG01 (EVENT_1_MASK)
Reset
Bit
Field
Type
Description
REG_RST Watchdog
EN
VBUS over voltage fault mask
0 – no mask. INT will assert low when VBUS_OVP_FLT bit
is set (default)
1 – VBUS_OVP_FLT is mask. INT will not assert low when
VBUS_OVP_FLT is set.
7
VBUS_OVP_MASK
R/W
Y
Y
Y
Y
Y
Y
Y
Y
N
N
N
N
N
N
N
N
Y
LDO active bit mask
0 – no mask. INT will assert low when LDO_ACTIVE bit is
set (default)
1 – LDO_ACTIVE is mask. INT will not assert low when
LDO_ACTIVE bit is set.
6
5
4
3
2
1
0
LDO_ACTIVE_MASK
LDO_ACTIVE_MASK
LDO_ACTIVE_MASK
LDO_ACTIVE_MASK
TS_BUS_FLT_MASK
TS_BAT_FLT_MASK
IBUS_REV_MASK
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Y
Y
Y
Y
Y
Y
Y
LDO active bit mask
0 – no mask. INT will assert low when LDO_ACTIVE bit is
set (default)
1 – LDO_ACTIVE is mask. INT will not assert low when
LDO_ACTIVE is set.
LDO active bit mask
0 – no mask. INT will assert low when LDO_ACTIVE bit is
set (default)
1 – LDO_ACTIVE is mask. INT will not assert low when
LDO_ACTIVE is set.
LDO active bit mask
0 – no mask. INT will assert low when LDO_ACTIVE bit is
set (default)
1 – LDO_ACTIVE is mask. INT will not assert low when
LDO_ACTIVE is set.
VBUS over temperature fault mask
0 – no mask. INT will assert low when TS_BUS_FLT bit is
set (default)
1 – TS_BUS_FLT is mask. INT will not assert low when
TS_BUS_FLT is set.
VBUS over temperature fault mask
0 – no mask. INT will assert low when TS_BAT_FLT bit is
set (default)
1 – TS_BAT_FLT is mask. INT will not assert low when
TS_BAT_FLT is set.
IBUS reverse current fault mask
0 – no mask. INT will assert low when IBUS_REV bit is set
(default)
1 – IBUS_REV is mask. INT will not assert low when
IBUS_REV is set.
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8.5.4 REG02 (EVENT_2_MASK)
图 23. REG02 (EVENT_2_MASK)
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
R
R/W
R/W
R/W
R/W
R/W
R
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表 5. REG02 (EVENT_2_MASK)
Reset
Bit
Field
Type
Description
REG_RST Watchdog
EN
7
Reserved
R
N/A
N/A
N/A
Reserved bit. Always reads 0.
ADC_DONE bit mask
0 – no mask. INT will assert low when ADC_DONE bit is set
(default)
1 – ADC_DONE is mask. INT will not assert low when
ADC_DONE bit is set.
6
5
4
3
ADC_DONE_MASK
VDROP_ALM_MASK
VDROP_OVP_MASK
R/W
R/W
R/W
R/W
Y
N
Y
Y
Y
Y
VDROP_ALM event mask
0 – no mask. INT will assert low when VDROP_ALM bit is
set (default)
1 – VDROP_ALM is mask. INT will not assert low when
VDROP_ALM bit is set.
Y
Y
Y
N
N
N
VDROP_OVP event mask
0 – no mask. INT will assert low when VDROP_OVP bit is
set (default)
1 – VDROP_OVP is mask. INT will not assert low when
VDROP_OVP is set.
VBUS_INSERT mask
0 – no mask. INT will assert low when VBUS_INSERT bit is
set (default)
1 – VBUS_INSERT is mask. INT will not assert low when
VBUS_INSERT is set.
VBUS_INSERT_MAS
K
BAT_INSERT mask
0 – no mask. INT will assert low when BAT_INSERT bit is
set (default)
1 – BAT_INSERT is mask. INT will not assert low when
BAT_INSERT is set.
2
1
0
BAT_INSERT_MASK
Reserved
R/W
R
Y
N/A
Y
N
N/A
N
Y
N/A
Y
Reserved bit. Always reads 0.
IBUS over current fault mask
0 – no mask. INT will assert low when IBUS_OCP bit is set
(default)
IBUS_OCP_MASK
R/W
1 – IBUS_OCP is mask. INT will not assert low when
IBUS_OCP is set.
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8.5.5 REG03 (EVENT_1)
图 24. REG03 (EVENT_1)
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
R
R
R
R
R
R
R
R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表 6. 6.4.5 REG03 (EVENT_1)
Reset
Bit
Field
Type
Description
REG_RST Watchdog
EN
VBUS over voltage fault. This bit is set when VBUS voltage
exceeds the limit set in VBUS_OVP register
0 – no fault (default)
7
VBUS_OVP_FLT
R
Y
N
Y
1 – VBUS OVP fault
Indicates if the device is in LDO mode
0 – not in LDO mode (default)
1 – in LDO mode
6
5
4
3
LDO_ACTIVE
LDO_ACTIVE
LDO_ACTIVE
LDO_ACTIVE
R
R
R
R
Y
Y
Y
Y
N
N
N
N
Y
Y
Y
Y
Indicates if the device is in LDO mode
0 – not in LDO mode (default)
1 – in LDO mode
Indicates if the device is in LDO mode
0 – not in LDO mode (default)
1 – in LDO mode
Indicates if the device is in LDO mode
0 – not in LDO mode (default)
1 – in LDO mode
VBUS over temperature fault. This bit is set when TS_BUS
voltage falls below the limit set in TS_BUS_register. Battery
switch is disabled.
2
TS_BUS_FLT
R
Y
N
Y
0 – no fault (default)
1 – VBUS over temperature fault
Battery over temperature fault. This bit is set when TS_BAT
voltage falls below the limit set in TS_BAT_register. Battery
switch is disabled.
0 – no fault (default)
1 – VBAT over temperature fault
1
0
TS_BAT_FLT
R
R
Y
Y
N
N
Y
Y
IBUS reverse current fault. This bit is set when current from
VOUT to VBUS is detected. Battery switch is disabled.
0 – no fault (default)
IBUS_IREV_FLT
1 – IBUS reverse current fault
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8.5.6 REG04 (EVENT_2)
图 25. REG04 (EVENT_2)
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
R
R
R
R
R
R
R
R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表 7. REG04 (EVENT_2)
Reset
Bit
Field
Type
Description
REG_RST Watchdog
EN
7
Reserved
R
N/A
N/A
N/A
Reserved bit. Always reads 0.
Indicates if ADC conversion is complete for the required
parameters in 1-shot mode only. This bit will change to '0'
when an ADC conversion is is requested in 1-shot mode,
and it will change back to '1' when the conversion is
complete. During continuous conversion mode, this bit will
be '0'.
6
ADC_DONE.
R
Y
N
Y
0 – conversion not complete (default)
1 – conversion complete
Indicates if VDROP_ALM threshold is reached
0 – no fault (default)
1 – VDROP_ALM fault
5
4
VDROP_ALM
R
R
Y
Y
N
N
Y
Y
Indicates if VDROP_OVP threshold is reached. Battery
switch is disabled.
0 – no fault (default)
VDROP_OVP_FLT
1 – VDROP_OVP fault
Indicates if VBUS is detected. \INT toggles when VBUS is
inserted but does not toggle when VBUS is removed.
0 – VBUS not inserted (default)
3
VBUS_INSERT
R
Y
N
Y
1 – VBUS inserted
Indicates if battery is detected. \INT toggles when battery is
inserted but does not toggle when battery is removed.
0 – Battery not inserted (default)
2
1
0
BAT_INSERT
TSHUT_FLT
R
Y
Y
Y
N
N
N
Y
Y
Y
1 – Battery inserted
IC thermal shutdown indictator. Battery switch is disabled.
0 – no fault (default)
1 – IC thermal shutdown fault
R/W
R/W
IBUS over current fault. This bit is set when IBUS exceeds
IBUS_OCP register. Battery switch is disabled.
0 – no fault (default)
IBUS_OCP_FLT
1 – IBUS over current fault
34
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ZHCSFK5 –OCTOBER 2016
8.5.7 REG05 (EVENT_1_EN)
图 26. REG05 (EVENT_1_EN)
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表 8. REG05 (EVENT_1_EN)
Reset
Bit
Field
Type
Description
REG_RST Watchdog
EN
Enables VBUS_OVP protection
7
VBUS_OVP_EN
R/W
Y
Y
Y
Y
Y
Y
Y
Y
N
N
N
N
N
N
N
N
Y
0 – disable VBUS_OVP protection
1 – enable VBUS_OVP protection (default)
Enable IBUS regulation
0 – disable IBUS regulation
1 – enable IBUS regulation (default)
6
5
4
3
2
1
0
IBUS_REG_EN
VBAT_REG_EN
IBAT_REG_EN
VOUT_REG_EN
TS_BUS_FLT_EN
TS_BAT_FLT_EN
VBUS_PD_EN
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Y
Y
Y
Y
Y
Y
Y
Enable VBAT regulation
0 – disable VBAT regulation
1 – enable VBAT regulation (default)
Enable IBAT regulation
0 – disable IBAT regulation
1 – enable IBAT regulation (default)
Enable VOUT regulation
0 – disable VOUT regulation
1 – enable VOUT regulation (default)
Enable TS_BUS protection
0 – disable TS_BUS protection
1 – enable TS_BUS protection (default)
Enable TS_BAT protection
0 – disable TS_BAT protection
1 – enable TS_BAT protection (default)
Enable the VBUS pull-down resistor (RVBUS_PD)
0 – disable RVBUS_PD (default)
1 – enable RVBUS_PD
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8.5.8 REG06 (CONTROL)
图 27. REG06 (CONTROL)
7
0
6
0
5
1
4
0
3
0
2
1
1
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表 9. REG06 (CONTROL)
Reset
Bit
Field
Type
Description
REG_RST Watchdog
EN
Enables VDROP_OVP protection
7
VDROP_OVP_EN
R/W
Y
Y
Y
N
N
N
Y
0 – disable VDROP_OVP protection (default)
1 – enable VDROP_OVP protection
Enables VDROP_ALM protection
0 – disable VDROP_ALM protection (default)
1 – enable VDROP_ALM protection
6
5
VDROP_ALM_EN
SENSE_R
R/W
R/W
Y
Y
Select the sense resistor value between SRP and SRN
0 – 5 mΩ
1 – 10 mΩ (default)
Software bit for charge enable. This enables the battery
switch. This bit will set to '0' if any fault causes the battery
switch to be disabled.
4
CHG_EN
R/W
Y
Y
Y
0 – charge disabled (default)
1 – charge enabled
3
2
WATCHDOG[1]
WATCHDOG[0]
R/W
R/W
Y
Y
N
N
Y
Y
Watchdog timer setting
00 – disable watchdog timer
01 – 0.5 s
10 – 1.0 s (default)
11 – 2 s
Reverse current protection (RCP) threshold setting
0 – RCP set to 0 A (default)
1 – RCP set to -3 A
1
0
RCP_SET
REG_RST
R/W
R/W
Y
Y
N
N
Y
Y
Register reset
0 – no reset (default)
1 – reset all registers to default values
36
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ZHCSFK5 –OCTOBER 2016
8.5.9 REG07 (ADC_CONTROL)
图 28. REG07 (ADC_CONTROL)
7
1
6
0
5
0
4
0
3
0
2
1
1
1
0
1
R/W
R
R
R
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表 10. REG07 (ADC_CONTROL)
Reset
Bit
Field
Type
Description
REG_RST Watchdog
EN
Enable/ disable conversion of die junction temperature
0 – disable conversion
7
TDIE_ADC_EN
R/W
Y
N
Y
1 – enabled conversion (default)
6
5
4
Reserved
Reserved
Reserved
R
R
R
Y
Y
Y
N
N
N
Y
Y
Y
Reserved bit. Always read 0.
Reserved bit. Always read 0.
Reserved bit. Always read 0.
Enable/ disable ADC
0 – disable ADC (default)
1 – enable ADC
3
2
1
ADC_EN
R/W
R/W
R/W
Y
Y
Y
Y
N
N
Y
Y
Y
Set ADC conversion rate
0 – 1-shot conversion
1 – continuous conversion (default)
ADC_RATE
ADC_AVG_EN
Enable/disable ADC measurement averaging
0 – disable averaging, instantaneous measurement
1 – enable averaging (default)
Set the number of samples to be taken for an ADC
conversion
0 – 8 samples taken for averaging
1 – 16 samples taken for averaging (default)
0
ADC_SAMPLES
R/W
Y
N
Y
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8.5.10 REG08 (ADC_EN)
图 29. REG08 (ADC_EN)
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表 11. REG08 (ADC_EN)
Reset
Bit
Field
Type
Description
REG_RST Watchdog
EN
Enable/ disable conversion of VBUS voltage
0 – disable conversion
1 – enabled conversion (default)
7
VBUS_ADC_EN
R/W
Y
Y
Y
Y
Y
Y
Y
Y
N
N
N
N
N
N
N
N
Y
Enable/ disable conversion of IBUS current
0 – disable conversion
1 – enabled conversion (default)
6
5
4
3
2
1
0
IBUS_ADC_EN
VOUT_ADC_EN
VDROP_ADC_EN
VBAT_ADC_EN
IBAT_ADC_EN
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Y
Y
Y
Y
Y
Y
Y
Enable/ disable conversion of VOUT voltage
0 – disable conversion
1 – enabled conversion (default)
Enable/ disable conversion of VDROP voltage
0 – disable conversion
1 – enabled conversion (default)
Enable/ disable conversion of VBAT voltage
0 – disable conversion
1 – enabled conversion (default)
Enable/ disable conversion of IBAT current
0 – disable conversion
1 – enabled conversion (default)
Enable/ disable conversion of TS_BUS voltage
0 – disable conversion
1 – enabled conversion (default)
TS_BUS_ADC_EN
TS_BAT_ADC_EN
Enable/ disable conversion of TS_BAT voltage
0 – disable conversion
1 – enabled conversion (default)
38
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8.5.11 REG09 (PROTECTION)
图 30. REG09 (PROTECTION)
7
1
6
0
5
1
4
0
3
0
2
0
1
0
0
0
R/W
R/W
R/W
R/W
R
R
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表 12. REG09
Reset
Bit
Field
Type
Description
REG_RST Watchdog
EN
7
6
5
4
3
2
IBUS_OCP[3]
IBUS_OCP[2]
IBUS_OCP[1]
IBUS_OCP[0]
Reserved
R/W
R/W
R/W
R/W
R
Y
Y
Y
Y
Y
Y
N
N
N
N
N
N
Y
Y
Y
Y
Y
Y
4 A
VBUS input overcurrent threshold
Offset: none
Range: 0 A to 7.5 A
Default: 5 A (1010)
2 A
1 A
0.5 A
Reserved bit. Always read 0.
Reserved bit. Always read 0.
Reserved
R
Controls the response of the OCP event or IBUS
0 – BLANKING mode; the device will wait 128 µs
before the battery switch is disabled and latched off
(default)
1 – HICCUP mode; battery switch is disabled
instantaneously, and the device will attampt to turn on
the battery switch every 100 ms, up to 7 times before
latching off.
1
0
OCP_RES
R/W
R/W
Y
Y
N
N
Y
Y
Set VBUS fault deglitch time
0 – 8 µs deglitch time (default)
1 – 128 µs deglitch time
VBUS_OVP_DLY
8.5.12 REG0A (VBUS_OVP)
图 31. REG0A (VBUS_OVP)
7
0
6
0
5
1
4
0
3
1
2
0
1
1
0
1
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表 13. REG0A (VBUS_OVP)
Reset
Bit
Field
Type
Description
REG_RST Watchdog
EN
Y
7
6
5
4
3
2
1
0
Reserved
R
Y
Y
Y
Y
Y
Y
Y
Y
N
N
N
N
N
N
N
N
Reserved bit. Always read 0.
VBUS_OVP[6]
VBUS_OVP[5]
VBUS_OVP[4]
VBUS_OVP[3]
VBUS_OVP[2]
VBUS_OVP[1]
VBUS_OVP[0]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Y
1920 mV
960 mV
480 mV
240 mV
120 mV
60 mV
VBUS over voltage threshold
Offset: 4.2 V
Range: 4.2 V to 6.51 V
Default: 5.49 V (00101011)
Y
Y
Y
Y
Y
Y
30 mV
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8.5.13 REG0B (VOUT_REG)
图 32. REG0B (VOUT_REG)
7
0
6
0
5
0
4
1
3
0
2
0
1
0
0
0
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表 14. REG0B (VOUT_REG)
Reset
Bit
Field
Type
Description
REG_RST Watchdog
EN
Y
7
6
5
4
3
2
1
0
Reserved
R
Y
Y
Y
Y
Y
Y
Y
Y
N
N
N
N
N
N
N
N
Reserved bit. Always read 0.
VOUT_OVP[5]
VOUT_OVP[4]
VBUS_OVP[3]
VBUS_OVP[2]
VBUS_OVP[1]
VBUS_OVP[0]
Reserved
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Y
800 mV
400 mV
200 mV
100 mV
50 mV
VOUT regulation threshold
Offset: 4.2 V
Range: 4.2 V to 4.975 V
Default: 4.4 V (00010000)
Y
Y
Y
Y
Y
25 mV
Y
Reserved bit. Always read 0.
40
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8.5.14 REG0C (VDROP_OVP)
图 33. REG0C (VDROP_OVP)
7
0
6
0
5
1
4
1
3
1
2
1
1
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表 15. REG0C (VDROP_OVP)
Reset
Bit
Field
Type
Description
REG_RST Watchdog
EN
Y
7
6
5
4
3
2
1
0
VDROP_OVP[6]
VDROP_OVP[5]
VDROP_OVP[4]
VDROP_OVP[3]
VDROP_OVP[2]
VDROP_OVP[1]
VDROP_OVP[1]
Reserved
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
Y
Y
Y
Y
Y
Y
Y
Y
N
N
N
N
N
N
N
N
640 mV
320 mV
160 mV
80 mV
40 mV
20 mV
10 mV
VDROP OVP threshold
Offset: none
Range: 0 mV to 1000 mV
Default: 300 mV (00111100)
Y
Y
Y
Y
Y
Y
Y
Reserved bit. Always read 0.
8.5.15 REG0D (VDROP_ALM)
图 34. REG0D (VDROP_ALM)
7
0
6
0
5
0
4
1
3
0
2
1
1
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表 16. REG0D (VDROP_ALM)
Reset
Bit
Field
Type
Description
REG_RST Watchdog
EN
Y
7
6
5
4
3
2
1
0
VDROP_ALM[6]
VDROP_ALM[5]
VDROP_ALM[4]
VDROP_ALM[3]
VDROP_ALM[2]
VDROP_ALM[1]
VDROP_ALM[1]
Reserved
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
Y
Y
Y
Y
Y
Y
Y
Y
N
N
N
N
N
N
N
N
640 mV
320 mV
160 mV
80 mV
40 mV
20 mV
10 mV
VDROP ALM threshold
Offset: none
Range: 0 mV to 1000 mV
Default: 100 mV (00010100)
Y
Y
Y
Y
Y
Y
Y
Reserved bit. Always read 0.
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8.5.16 REG0E (VBAT_REG)
图 35. REG0E (VBAT_REG)
7
0
6
0
5
0
4
0
3
1
2
0
1
0
0
0
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表 17. REG0E (VBAT_REG)
Reset
Bit
Field
Type
Description
REG_RST Watchdog
EN
Y
7
6
5
4
3
2
1
0
Reserved
R
Y
Y
Y
Y
Y
Y
Y
Y
N
N
N
N
N
N
N
N
Reserved bit. Always read 0.
VBAT_REG[6]
VBAT_REG[5]
VBAT_REG[4]
VBAT_REG[3]
VBAT_REG[2]
VBAT_REG[1]
VBAT_REG[0]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Y
800 mV
400 mV
200 mV
100 mV
50 mV
Battery voltage regulation threshold
Offset: 4.2 V
Range: 4.2 V to 4.975 V
Default: 4.3 V (00001000)
Y
Y
Y
Y
Y
25 mV
Y
12.5 mV
8.5.17 REG0F (IBAT_REG)
图 36. REG0F (IBAT_REG)
7
0
6
0
5
1
4
0
3
1
2
0
1
0
0
0
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表 18. REG0F (IBAT_REG)
Reset
Bit
Field
Type
Description
REG_R Watchd
EN
ST
og
N
N
N
N
N
N
N
N
7
6
5
4
3
2
1
0
Reserved
R
Y
Y
Y
Y
Y
Y
Y
Y
Y
Reserved bit. Always read 0.
IBAT_REG[6]
IBAT_REG[5]
IBAT_REG[4]
IBAT_REG[3]
IBAT_REG[2]
IBAT_REG[1]
IBAT_REG[0]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Y
3200 mA
1600 mA
800 mA
400 mA
200 mA
100 mA
50 mA
Battery current regulation threshold
Offset: 0 A
Range: 0 A to 6.35 A
Default: 2 A (00101000)
Y
Y
Y
Y
Y
Y
42
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8.5.18 REG10 (IBUS_REG)
图 37. REG10 (IBUS_REG)
7
1
6
1
5
1
4
0
3
0
2
1
1
0
0
0
R
R/W
R/W
R/W
R/W
R/W
R/W
R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表 19. REG10 (IBUS_REG)
Reset
Bit
Field
Type
Description
REG_RST Watchdog
EN
Y
7
6
5
4
3
2
1
0
Reserved
R
Y
Y
Y
Y
Y
Y
Y
Y
N
N
N
N
N
N
N
N
Reserved bit. Always read 0.
IBUS_REG[5]
IBUS_REG[4]
IBUS_REG[3]
IBUS_REG[2]
IBUS_REG[1]
IBUS_REG[0]
Reserved
R/W
R/W
R/W
R/W
R/W
R/W
R
Y
3200 mA
1600 mA
800 mA
400 mA
200 mA
100 mA
Battery current regulation threshold
Offset: 0 A
Range: 0 A to 6.3 A
Y
Y
Default: 5 A (01100100)
Y
Y
Y
Y
Reserved bit. Always read 0.
8.5.19 REG11 (TS_BUS_FLT)
图 38. REG11 (TS_BUS_FLT)
7
0
6
0
5
0
4
1
3
1
2
0
1
0
0
0
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表 20. REG11 (TS_BUS_FLT)
Reset
Bit
Field
Type
Description
REG_RST Watchdog
EN
Y
7
6
5
4
3
2
1
0
Reserved
R
Y
Y
Y
Y
Y
Y
Y
Y
N
N
N
N
N
N
N
N
Reserved bit. Always read 0.
TS_BUS_FLT[6]
TS_BUS_FLT[5]
TS_BUS_FLT[4]
TS_BUS_FLT[3]
TS_BUS_FLT[2]
TS_BUS_FLT[1]
TS_BUS_FLT[0]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Y
1600 mA
800 mA
400 mA
200 mA
100 mA
50 mA
TS_BUS voltage threshold
Offset: 0 V
Range: 0 V to 1.4 V
Default: 0.6 V (00011000)
Y
Y
Y
Y
Y
Y
25 mA
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8.5.20 REG12 (TS_BAT_FLT)
图 39. REG12 (TS_BAT_FLT)
7
0
6
0
5
0
4
1
3
1
2
1
1
0
0
0
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表 21. REG12 (TS_BAT_FLT)
Reset
Bit
Field
Type
Description
REG_RST Watchdog
EN
Y
7
6
5
4
3
2
1
0
Reserved
R
Y
Y
Y
Y
Y
Y
Y
Y
N
N
N
N
N
N
N
N
Reserved bit. Always read 0.
TS_BAT_FLT[6]
TS_BAT_FLT[5]
TS_BAT_FLT[4]
TS_BAT_FLT[3]
TS_BAT_FLT[2]
TS_BAT_FLT[1]
TS_BAT_FLT[0]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Y
1600 mA
800 mA
400 mA
200 mA
100 mA
50 mA
TS_BAT voltage threshold
Offset: 0 V
Range: 0 V to 1.4 V
Default: 0.7 V (00011100)
Y
Y
Y
Y
Y
Y
25 mA
8.5.21 REG 13 and REG 14 (VBUS_ADC)
图 40. REG 13 and REG 14 (VBUS_ADC)
REG13
REG14
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表 22. REG 13 and REG 14 (VBUS_ADC)
Reset
Register
Bit
Field
Type
Description
REG_RST Watchdog
EN
Indicates polarity of VBUS voltage. Always
positive.
0 - positive voltage
7
VBUS_POL
R
Y
N
Y
1 - negative voltage
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
VBUS_ADC[14]
VBUS_ADC[13]
VBUS_ADC[12]
VBUS_ADC[11]
VBUS_ADC[10]
VBUS_ADC[9]
VBUS_ADC[8]
VBUS_ADC[7]
VBUS_ADC[6]
VBUS_ADC[5]
VBUS_ADC[4]
VBUS_ADC[3]
VBUS_ADC[2]
VBUS_ADC[1]
VBUS_ADC[0]
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
16384 mV Voltage representation of ADC
conversion of VBUS voltage.
Range: 0 V, and 2.048 V to 6.140
8192 mV
REG13
4096 mV
2048 mV
1024 mV
512 mV
256 mV
128 mV
64 mV
32 mV
16 mV
8 mV
V
Default: 0 V (0000000000000000)
If VBUS < 0.3 V, VBUS_ADC =
0.3 V
REG14
4 mV
2 mV
1 mV
44
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8.5.22 REG15 and REG16 (IBUS_ADC)
图 41. REG15 and REG16 (IBUS_ADC)
REG15
REG16
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表 23. REG15 and REG16 (IBUS_ADC)
Reset
Register
Bit
Field
Type
Description
REG_RST Watchdog
EN
Indicates polarity of IBUS current. Always
positive.
0 - positive current
7
IBUS_POL
R
Y
N
Y
1 - negative current
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
IBUS_ADC[14]
IBUS_ADC[13]
IBUS_ADC[12]
IBUS_ADC[11]
IBUS_ADC[10]
IBUS_ADC[9]
IBUS_ADC[8]
IBUS_ADC[7]
IBUS_ADC[6]
IBUS_ADC[5]
IBUS_ADC[4]
IBUS_ADC[3]
IBUS_ADC[2]
IBUS_ADC[1]
IBUS_ADC[0]
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
16384 mA Current representation of ADC
conversion of VBUS current.
Range: 0 A to 7.5 A
8192 mA
REG15
4096 mA
2048 mA
1024 mA
512 mA
256 mA
128 mA
64 mA
32 mA
16 mA
8 mA
Default: 0 A (0000000000000000)
REG16
4 mA
2 mA
1 mA
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8.5.23 REG17 and REG18 (VOUT_ADC)
图 42. REG17 and REG18 (VOUT_ADC)
REG17
REG18
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表 24. REG17 and REG18 (VOUT_ADC)
Reset
Register
Bit
Field
Type
Description
REG_RST Watchdog
EN
Indicates polarity of VDROP voltage. Always
positive.
0 - positive voltage
7
VOUT_POL
R
Y
N
Y
1 - negative voltage
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
VOUT_ADC[14]
VOUT_ADC[13]
VOUT_ADC[12]
VOUT_ADC[11]
VOUT_ADC[10]
VOUT_ADC[9]
VOUT_ADC[8]
VOUT_ADC[7]
VOUT_ADC[6]
VOUT_ADC[5]
VOUT_ADC[4]
VOUT_ADC[3]
VOUT_ADC[2]
VOUT_ADC[1]
VOUT_ADC[0]
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
16384 mV Voltage representation of ADC
conversion of VDROP voltage.
Range: 2.048 V to 6.140 V
8192 mV
REG17
4096 mV
2048 mV
1024 mV
512 mV
256 mV
128 mV
64 mV
32 mV
16 mV
8 mV
Default: 0 V (0000000000000000)
REG18
4 mV
2 mV
1 mV
46
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ZHCSFK5 –OCTOBER 2016
8.5.24 REG19 and REG1A (VDROP_ADC)
图 43. REG19 and REG1A (VDROP_ADC)
REG19
REG1A
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表 25. REG19 and REG1A (VDROP_ADC)
Reset
Register
Bit
Field
Type
Description
REG_RST Watchdog
EN
Indicates polarity of VDROP voltage. Always
positive.
0 - positive voltage
7
VDROP_POL
R
Y
N
Y
1 - negative voltage
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
VDROP_ADC[14]
VDROP_ADC[13]
VDROP_ADC[12]
VDROP_ADC[11]
VDROP_ADC[10]
VDROP_ADC[9]
VDROP_ADC[8]
VDROP_ADC[7]
VDROP_ADC[6]
VDROP_ADC[5]
VDROP_ADC[4]
VDROP_ADC[3]
VDROP_ADC[2]
VDROP_ADC[1]
VDROP_ADC[0]
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
16384 mV Voltage representation of ADC
conversion of VBUS voltage.
Range: 0 mV to 1000 mV
8192 mV
REG19
4096 mV
2048 mV
1024 mV
512 mV
256 mV
128 mV
64 mV
32 mV
16 mV
8 mV
Default: 0 mV
(0000000000000000)
REG1A
4 mV
2 mV
1 mV
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8.5.25 REG1B and REG1C (VBAT_ADC)
图 44. REG1B and REG1C (VBAT_ADC)
REG1B
REG1C
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
7
0
6
0
5
0
4
3
0
2
0
1
0
0
0
0
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表 26. REG1B and REG1C (VBAT_ADC)
Reset
Register
Bit
Field
Type
Description
REG_RST Watchdog
EN
Indicates polarity of VBUS voltage. Always
positive.
0 - positive voltage
7
VBAT_POL
R
Y
N
Y
1 - negative voltage
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
VBAT_ADC[14]
VBAT_ADC[13]
VBAT_ADC[12]
VBAT_ADC[11]
VBAT_ADC[10]
VBAT_ADC[9]
VBAT_ADC[8]
VBAT_ADC[7]
VBAT_ADC[6]
VBAT_ADC[5]
VBAT_ADC[4]
VBAT_ADC[3]
VBAT_ADC[2]
VBAT_ADC[1]
VBAT_ADC[0]
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
16384 mV Voltage representation of ADC
conversion of VBAT voltage.
Range: 2.048 V to 6.140 V
8192 mV
REG1B
4096 mV
2048 mV
1024 mV
512 mV
256 mV
128 mV
64 mV
32 mV
16 mV
8 mV
Default: 0 V (0000000000000000)
REG1C
4 mV
2 mV
1 mV
48
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ZHCSFK5 –OCTOBER 2016
8.5.26 REG1D and REG1E (IBAT_ADC)
图 45. REG1D and REG1E (IBAT_ADC)
REG1D
REG1E
7
0
6
0
5
0
4
3
0
2
0
1
0
0
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
0
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表 27. REG1D and REG1E (IBAT_ADC)
Reset
Register
Bit
Field
Type
Description
REG_RST Watchdog
EN
Indicates polarity of battery current.
0 - positive voltage (default)
1 - negative voltage
7
IBAT_POL
R
Y
N
Y
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
IBAT_ADC[14]
IBAT_ADC[13]
IBAT_ADC[12]
IBAT_ADC[11]
IBAT_ADC[10]
IBAT_ADC[9]
IBAT_ADC[8]
IBAT_ADC[7]
IBAT_ADC[6]
IBAT_ADC[5]
IBAT_ADC[4]
IBAT_ADC[3]
IBAT_ADC[2]
IBAT_ADC[1]
IBAT_ADC[0]
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
16384 mV Voltage representation of ADC
conversion of VBUS voltage.
Range: 0 A to 7.104 A
8192 mV
REG1D
4096 mV
2048 mV
1024 mV
512 mV
256 mV
128 mV
64 mV
32 mV
16 mV
8 mV
Default: 0 A(0000000000000000)
REG1E
4 mV
2 mV
1 mV
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8.5.27 REG1F and REG20 (TS_BUS_ADC)
图 46. REG1F and REG20 (TS_BUS_ADC)
REG1F
REG20
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表 28. REG1F and REG20 (TS__BUS_ADC)
Reset
Register
Bit
Field
Type
Description
REG_RST Watchdog
EN
Indicates polarity of TS_BUS voltage. Always
positive.
0 - positive voltage
7
TS_BUS_POL
R
Y
N
Y
1 - negative voltage
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
TS_BUS_ADC [14]
TS_BUS_ADC [13]
TS_BUS_ADC [12]
TS_BUS_ADC [11]
TS_BUS_ADC [10]
TS_BUS_ADC [9]
TS_BUS_ADC [8]
TS_BUS_ADC [7]
TS_BUS_ADC [6]
TS_BUS_ADC [5]
TS_BUS_ADC [4]
TS_BUS_ADC [3]
TS_BUS_ADC [2]
TS_BUS_ADC [1]
TS_BUS_ADC [0]
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
16384 mV Voltage representation of ADC
conversion of TS_BUS voltage.
Range: 0 V to 2.420 V
8192 mV
REG1F
4096 mV
2048 mV
1024 mV
512 mV
256 mV
128 mV
64 mV
32 mV
16 mV
8 mV
Default: 0 V (0000000000000000)
REG20
4 mV
2 mV
1 mV
50
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ZHCSFK5 –OCTOBER 2016
8.5.28 REG21 and REG22 (TS_BAT_ADC)
图 47. REG21 and REG22 (TS_BAT_ADC)
REG21
REG22
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表 29. REG21 and REG22 (TS_BAT_ADC)
Reset
Register
Bit
Field
Type
Description
REG_RST Watchdog
EN
Indicates polarity of TS_BAT voltage. Always
positive.
0 - positive voltage
7
TS_BAT_POL
R
Y
N
Y
1 - negative voltage
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
TS_BAT_ADC [14]
TS_BAT_ADC [13]
TS_BAT_ADC [12]
TS_BAT_ADC [11]
TS_BAT_ADC [10]
TS_BAT_ADC [9]
TS_BAT_ADC [8]
TS_BAT_ADC [7]
TS_BAT_ADC [6]
TS_BAT_ADC [5]
TS_BAT_ADC [4]
TS_BAT_ADC [3]
TS_BAT_ADC [2]
TS_BAT_ADC [1]
TS_BAT_ADC [0]
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
16384 mV Voltage representation of ADC
conversion of TS_BAT voltage.
Range: 0 V to 2.420 V
8192 mV
REG21
4096 mV
2048 mV
1024 mV
512 mV
256 mV
128 mV
64 mV
32 mV
16 mV
8 mV
Default: 0 V (0000000000000000)
REG22
4 mV
2 mV
1 mV
8.5.29 REG 23 (TDIE_ADC)
图 48. REG23 (TDIE_ADC)
7
0
6
0
5
4
0
3
0
2
0
1
0
0
0
0
R
R
R
R
R
R
R
R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表 30. REG23 (TDIE_ADC)
Reset
Bit
Field
Type
Description
REG_RST Watchdog
EN
Y
7
6
5
4
3
2
1
0
DIE_TEMP_ADC [7]
DIE_TEMP_ADC [6]
DIE_TEMP_ADC [5]
DIE_TEMP_ADC [4]
DIE_TEMP_ADC [3]
DIE_TEMP_ADC [2]
DIE_TEMP_ADC [1]
DIE_TEMP_ADC [0]
R
R
R
R
R
R
R
R
Y
Y
Y
Y
Y
Y
Y
Y
N
N
N
N
N
N
N
N
128°C
64°C
32°C
16°C
8°C
Temperature representation of ADC
conversion of die junction temperature.
Range: 25°C to 150°C
Y
Y
Default: 0°C (0000000000000000)
Y
Y
Y
4°C
Y
2°C
Y
1°C
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8.5.30 REG 24 (EVENT_2_EN)
图 49. REG24 (EVENT_2_EN)
7
0
6
0
5
0
4
0
3
1
2
0
1
0
0
0
R/W
R
R
R
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表 31. REG24 (EVENT_2_EN) (0x24 Register)
Reset
Bit
Field
Type
Description
REG_RST Watchdog
EN
Turn on/ off VDROP AMP
7
VDROP_AMP_DIS
R/W
Y
N
Y
0 – Turn on VDROP AMP (default)
1 – Turn off VDROP AMP
6
5
4
Reserved
Reserved
Reserved
R
R
R
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Reserved bit. Always reads 0.
Reserved bit. Always reads 0.
Reserved bit. Always reads 0.
Enable/ disable IBUS over current protection
0 – disable IBUS OCP
1 – enabled IBUS OCP (default)
3
2
1
0
IBUS_OCP_EN
VBAT_OVP_EN
IBAT_OCP_EN
VOUT_OVP_EN
R/W
R/W
R/W
R/W
Y
Y
Y
Y
N
N
N
N
Y
Y
Y
Y
Enable/ disable VBAT over voltage protection
0 – disable VBAT OVP (default)
1 – enabled VBAT OVP
Enable/ disable IBAT over current protection
0 – disable IBAT OCP (default)
1 – enabled IBAT OCP
Enable/ disable VOUT over voltage protection
0 – disable VOUT OVP protection (default)
1 – enabled VOUT_OVP
52
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8.5.31 REG 25 (EVENT_3_MASK)
图 50. REG25 (EVENT_3_MASK)
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
R
R
R
R
R
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表 32. REG26 (EVENT_3_MASK) (0x026 Register)
Reset
Bit
Field
Type
Description
REG_RST Watchdog
EN
N/A
N/A
N/A
N/A
N/A
7
6
5
4
3
Reserved
Reserved
Reserved
Reserved
Reserved
R
R
R
R
R
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Reserved bit. Always reads 0.
Reserved bit. Always reads 0.
Reserved bit. Always reads 0.
Reserved bit. Always reads 0.
Reserved bit. Always reads 0.
VBAT over voltage fault mask.
0 – no mask. INT will assert low when VBAT_OVP bit is
set (default)
1 – VBAT_OVP is masked. INT will not assert low when
VBAT_OVP bit is set.
2
1
0
VBAT_OVP_MASK
IBAT_OCP_MASK
VOUT_OVP_MASK
R/W
R/W
R/W
Y
Y
Y
N
N
N
Y
Y
Y
IBAT over current fault mask.
0 – no mask. INT will assert low when IBAT_OCP bit is
set (default)
1 – IBAT_OCP is masked. INT will not assert low when
IBAT_OCP bit is set.
VOUT over voltage fault mask.
0 – no mask. INT will assert low when VOUT_OVP bit is
set (default)
1 – VOUT_OVP is masked. INT will not assert low when
VOUT_OVP bit is set.
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8.5.32 REG 26 (EVENT_3)
图 51. REG26 (EVENT_3)
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
R
R
R
R
R
R
R
R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表 33. REG26 (EVENT_3) (0x26 Register)
Reset
Bit
Field
Type
Description
REG_RST Watchdog
EN
Indicates if high current from VBUS to VOUT has hit
ISCP threshold. Battery switch is disabled
0 – no fault (default)
7
SCP_FLT
R
Y
N
Y
1 – short circuit fault
6
5
4
Reserved
Reserved
Reserved
R
R
R
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Reserved bit. Always reads 0.
Reserved bit. Always reads 0.
Reserved bit. Always reads 0.
Indicates if VUSB_OVP threshold is reached. Battery
switch is disabled
0 – no fault (default)
3
2
1
0
VUSB_OVP_FLT
VBAT_OVP_FLT
IBAT_OCP_FLT
VOUT_OVP_FLT
R
R
R
R
Y
Y
Y
Y
N
N
N
N
Y
Y
Y
Y
1 – VUSB_OVP fault
Indicates if VBAT_OVP threshold is reached. Battery
switch is disabled
0 – no fault (default)
1 – VBAT_OVP fault
Indicates if IBAT_OCP threshold is reached. Battery
switch is disabled
0 – no fault (default)
1 – IBAT_OCP fault
Indicates if VOUT_OVP threshold is reached. Battery
switch is disabled
0 – no fault (default)
1 – VOUT_OVP fault
8.5.33 REG27 and REG28 (VUSB_ADC)
图 52. REG27 and REG28 (VUSB_ADC)
REG27
REG28
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
54
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ZHCSFK5 –OCTOBER 2016
表 34. REG27 and REG28 (VUSB_ADC)
Reset
Regi
Bit
Field
Type
Description
REG_ Watch
ster
EN
RST
dog
Indicates polarity of TS_BAT voltage. Always positive.
0 - positive voltage
1 - negative voltage
7
6
VUSB_POL
R
Y
N
Y
VUSB_ADC [14]
VUSB_ADC [13]
VUSB_ADC [12]
VUSB_ADC [11]
VUSB_ADC [10]
VUSB_ADC [9]
VUSB_ADC [8]
VUSB_ADC [7]
VUSB_ADC [6]
VUSB_ADC [5]
VUSB_ADC [4]
VUSB_ADC [3]
VUSB_ADC [2]
VUSB_ADC [1]
VUSB_ADC [0]
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
16384 mV Voltage representation of ADC conversion of VUSB
voltage.
Range: 2.048 V to 6.140 V
Default: 0 V (0000000000000000)
5
8192 mV
REG
21
4
4096 mV
2048 mV
1024 mV
512 mV
256 mV
128 mV
64 mV
32 mV
16 mV
8 mV
3
2
1
0
7
6
5
4
3
2
1
0
REG
22
4 mV
2 mV
1 mV
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8.5.34 REG 29 (CONTROL_2)
图 53. REG29 (CONTROL_2)
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
R
R
R
R
R
R
R
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表 35. REG29 (RSENSE) (0x29 Register)
Reset
Bit
Field
Type
Description
REG_RST
N/A
Watchdog
N/A
EN
N/A
N/A
N/A
N/A
N/A
7
4
3
2
1
Reserved
Reserved
Reserved
Reserved
Reserved
R
R
R
R
R
Reserved bit. Always reads 0.
Reserved bit. Always reads 0.
Reserved bit. Always reads 0.
Reserved bit. Always reads 0.
Reserved bit. Always reads 0.
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
VUSBOVP_TH[
1]
Indicates the VUSB OVP threshold.
00 – 5.5 V (default)
01 – 6.5 V
10 – 10.5 V
11 – 14.0 V
6
5
R
R
Y
Y
N
N
Y
Y
VUSBOVP_TH[
0]
Disables the OVPSET pin setting. When
disabled, VUSBOVP threshold is only determined
by the settings in VUSBOVP_I2C[2:1].
0 – Enable OVPSET pin (default)
4
3
OVPSET_DIS
R/W
R/W
Y
Y
N
N
N
Y
1 – Disable OVPSET pin
VUSBOVP_I2C[
1]
Indicates the VUSB OVP threshold.
00 – 5.5 V
01 – 6.5 V
10 – 10.5 V
11 – 14.0 V (default)
VUSBOVP_I2C[
0]
2
1
R/W
R
Y
N
Y
Reserved
R_PLACE
N/A
N/A
N/A
Reserved bit. Always reads 0.
Select location of SRP/SRN sense resistor
0 – low-side placement (default)
1 – high-side placement
0
R/W
Y
N
Y
56
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ZHCSFK5 –OCTOBER 2016
8.5.35 REG 40 (DIE_TEMP_FLT)
图 54. REG 40 (DIE_TEMP_FLT)
7
0
6
0
5
0
4
0
3
0
2
0
1
1
0
1
R
R
R
R
R
R
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表 36. REG 40 (DIE_TEMP_FLT) (0x40 Register)
Reset
Bit
Field
Type
Description
REG_RST
N/A
Watchdog
N/A
EN
N/A
N/A
N/A
N/A
N/A
N/A
7
6
5
4
3
2
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
R
R
R
R
R
R
Reserved bit. Always reads 0.
N/A
N/A
Reserved bit. Always reads 0.
Reserved bit. Always reads 0.
Reserved bit. Always reads 0.
Reserved bit. Always reads 0.
Reserved bit. Always reads 0.
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
DIE_TEMP_FLT
[1]
TSHUT temperature threshold
Offset: 105°C
Range: 105°C to 150°C
Default: 150°C (0b11)
1
0
R/W
R/W
Y
Y
N
N
Y
Y
30 C
15 C
DIE_TEMP_FLT
[0]
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9 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
A typical application consists of the device configured as an I2C controlled device and another switch mode
charger for Li-Ion and Li-polymer batteries used in a wide range of smart phones and other portable devices. A
host controls which charger is enabled during the charging process.
9.2 Typical Application
Switch-Mode
Charger
VBUS
SW
SYS
BAT
System
SDA/
SCL
GND
Power Supply
Connector
Host
VSYS
10 mF
(1)
EN
VOUT
SDA
SCL
100 W
100 W
BATP
Battery
Pack
CHGSTAT
BATN
INT
SRP
SRN
VBUS
1 mF
OVPGATE
VREF
5.23 kΩ
VUSB
VREF
5.23 kΩ
TS_BAT
TS_VUSB
GND
103 AT
30.1 kΩ
103 AT
30.1 kΩ
Copyright © 2016, Texas Instruments Incorporated
图 55. bq25872 Typical Application
58
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bq25872
www.ti.com.cn
ZHCSFK5 –OCTOBER 2016
Typical Application (接下页)
9.2.1 Design Requirements
表 37. Design Requirement
PARAMETER
Input voltage range
Input current limit
Output voltage range
VALUE
3 V to 6 V
0.1 A to 7.5 A
3 V to 4.975 V
9.2.2 Detailed Design Procedure
The bq25872 continuously monitors battery and adaptor connector temperature by measuring the voltage
between TS_BAT pin and TS_BUS pins and ground, typically determined by a negative temperature coefficient
thermistor and an external voltage divider. The device compares this voltage against its internal thresholds to
determine if charging is allowed. To initiate a charging cycle, both battery and connector temperatures must be
lower than the temperature threshold, else the device suspends charging and waits until both temperatures are
blow the threshold.
Assuming a 103 AT NTC thermistor is used on the battery pack, the values RT1 (connected between TS_X pin
to VREF) and RT2 (connected between TS_X and ground) can be determined by using the following equations.
1
1
62%& × 24(#/,$ × 24((/4 × @
F
A
6,4& 64#/
62%&
24ꢀ =
62%&
24((/4 × @
F 1A F 24(#/,$ × @
F 1A
64#/
6,4&
62%&
F 1
6,4&
241 =
1
1
+
24ꢀ 24(#/,$
where
•
RTHcold and VLTF are the resistance of NTC under the cold temperature and the corresponding TS_X pin
voltage when charge is allowed, RTHhot and VTCOare the resistance of NTC under the hot temperature and the
corresponding TS_X pin voltage when charge is allowed.
(1)
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9.2.3 Application Curves
图 56. Power Up with IBUS_REG = 1 A
图 57. IBAT Regulation During Load Step Down
图 59. IBUS OCP During Load Transient
图 58. VBAT Regulation During Load Step Down
图 60. TS BUS OTP
图 61. VBUS OVP with IBUS Regulation
60
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ZHCSFK5 –OCTOBER 2016
图 62. Power Up of bq25872
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10 Power Supply Recommendations
In order to provide an output voltage on SYS, the device requires a power supply between 3.9-V and 14-V input
with at least 100-mA current rating connected to VBUS or a single-cell Li-Ion battery with voltage > VBATUVLO
connected to BAT. The source current rating needs to be at least 7.5 A to meet the current capability of the
device.
11 Layout
11.1 Layout Guidelines
bq25872 supports up to 7-A charge current. It is very critical to maximize Cu trace of VBUS and VOUT.
Following PCB layout guideline is recommended:
•
Use Cu trace of at least 110 mil (2.794 mm) wide for VBUS and VOUT respectively. This allows current flow
evenly through all 7 WCSP solder balls.
•
Cu trace of VBUS and VOUT should run at least 150 mil (3.81 mm) straight (perpendicular to WCSP ball
array) before making turns.
•
•
•
Use as large as possible Cu pour for VBUS and VOUT trace elsewhere.
Use as large as possible Cu pour for PGND.
Place decoupling capacitors of VBUS and VOUT as close as possible to the device.
11.2 Layout Example
图 63. bq25872 Layout Diagram (Top Layer)
图 64. bq25872 Layout Diagram (Mid Layer 2)
62
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bq25872
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ZHCSFK5 –OCTOBER 2016
Layout Example (接下页)
图 65. bq25872 Layout Diagram (Mid Layer 1)
图 66. bq25872 Layout Diagram (Bottom 1)
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ZHCSFK5 –OCTOBER 2016
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12 器件和文档支持
12.1 接收文档更新通知
如需接收文档更新通知,请访问 www.ti.com.cn 网站上的器件产品文件夹。点击右上角的提醒我 (Alert me) 注册
后,即可每周定期收到已更改的产品信息。有关更改的详细信息,请查阅已修订文档中包含的修订历史记录。
12.2 社区资源
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.3 商标
E2E is a trademark of Texas Instruments.
I2C is a trademark of Philips Semiconductor.
All other trademarks are the property of their respective owners.
12.4 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
64
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13 机械、封装和可订购信息
以下页中包括机械、封装和可订购信息。这些信息是针对指定器件可提供的最新数据。这些数据会在无通知且不对
本文档进行修订的情况下发生改变。欲获得该数据表的浏览器版本,请查阅左侧的导航栏。
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65
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Copyright © 2016, 德州仪器半导体技术(上海)有限公司
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
BQ25872YFFR
BQ25872YFFT
ACTIVE
ACTIVE
DSBGA
DSBGA
YFF
YFF
42
42
3000 RoHS & Green
250 RoHS & Green
SNAGCU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 85
-40 to 85
BQ25872
BQ25872
SNAGCU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
PACKAGE OUTLINE
YFF0042
DSBGA - 0.625 mm max height
S
C
A
L
E
4
.
5
0
0
DIE SIZE BALL GRID ARRAY
B
E
A
BUMP A1
CORNER
D
C
0.625 MAX
SEATING PLANE
0.05 C
BALL TYP
0.30
0.12
2 TYP
SYMM
G
F
E
D
C
D: Max = 3.168 mm, Min =3.108 mm
E: Max = 2.488 mm, Min =2.428 mm
SYMM
2.4
TYP
0.3
0.2
42X
B
A
0.015
C A
B
0.4 TYP
1
2
3
4
5
6
0.4 TYP
4222067/A 05/2015
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
YFF0042
DSBGA - 0.625 mm max height
DIE SIZE BALL GRID ARRAY
(0.4) TYP
3
42X ( 0.23)
(0.4) TYP
1
2
4
5
6
A
B
C
SYMM
D
E
F
G
SYMM
LAND PATTERN EXAMPLE
SCALE:25X
0.05 MAX
0.05 MIN
(
0.23)
(
0.23)
METAL
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
NOT TO SCALE
4222067/A 05/2015
NOTES: (continued)
3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
For more information, see Texas Instruments literature number SNVA009 (www.ti.com/lit/snva009).
www.ti.com
EXAMPLE STENCIL DESIGN
YFF0042
DSBGA - 0.625 mm max height
DIE SIZE BALL GRID ARRAY
(0.4) TYP
42X ( 0.25)
(R0.05) TYP
1
2
3
4
5
6
A
(0.4)
TYP
B
METAL
TYP
C
D
E
F
SYMM
G
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
SCALE:30X
4222067/A 05/2015
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
www.ti.com
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