CSD18536KTTT_技术文档

Sample &

Buy

Support &

Community

Product

Folder

Tools &

Software

Technical

Documents

TPS25810-Q1

ZHCSF05 –NOVEMBER 2016

TPS25810-Q1 具有负载检测功能的 USB Type-C DFP 控制器和电源开关

1 特性

3 说明

1

•

兼容 USB Type-C 版本 1.2 的下行数据端口 (DFP)

控制器

TPS25810-Q1 是一款 USB Type-C 下行数据端口

(DFP) 控制器，集成了一个额定电流为 3A 的 USB 电

源开关。TPS25810-Q1 器件监测 Type-C 配置通道

(CC) 线路，确定 USB 设备何时与其相连。如果连接

与上行数据端口 (UFP) 器件相连，TPS25810-Q1 可

将电源应用于 V_BUS并将可选 V_BUS拉电流能力通过

CC 线路传输至 UFP。如果使用以电气方式标记的电

缆连接 UFP，TPS25810‑Q1 器件也可以将 V_CONN电

源应用于电缆的 CC 引脚。TPS25810-Q1 器件还会识

别何时连接了 Type-C 音频或调试附件。

•

连接器连接或断开检测

配置通道 (CC) STD、1.5A、3A 电流能力通告

超高速极性确定

V_BUS应用和放电

V_CONN应用于电子标记电缆

音频和调试附件识别

端口未连接时，I_DDQ的典型值为 0.7µA

三个输入电源选项

–

IN1：USB 充电电源

IN2：V_CONN电源

AUX：器件电源

TPS25810-Q1 器件在未连接器件时的电流消耗低于

0.7µA（典型值）。在未连接 UFP 时，S4 和 S5 系统

电源使用 UFP 输出禁用 5V 高功率电源，从而进一步

实现系统节能。在此模式下，器件能够由电压较低

(3.3V) 的辅助电源 (AUX) 供电运行，该电源通常在低

功耗状态（S4 和 S5）下为系统微控制器供电。

•

电源唤醒可保证系统冬眠 (S4) 和关闭 (S5) 功耗状

态下的低功耗

34mΩ（典型值）高侧金属氧化物半导体场效应晶

体管 (MOSFET)

•

1.7A 或 3.4A 可编程 I_LIM(±7.1%)

TPS25810-Q1 34mΩ 电源开关具备两种固定电流限值

可供选择，对应于 Type-C 电流水平。FAULT 输出在

开关处于过流和过热条件时发出信号。在所有端口无法

同时提供高电流 (3A) 的环境下，LD_DET 输出可针对

多个高电流 Type-C 端口的功率管理进行控制。

端口功率管理可实现多端口功率资源优化

封装：20 引脚晶圆级四方扁平无引线 (WQFN) 封

(1)

装 (3mm x 4mm)

2 应用

器件信息⁽¹⁾

•

汽车信息娱乐系统

汽车后座 USB 充电

器件型号

封装

封装尺寸（标称值）

超薄四方扁平无引线

(WQFN) (20)

TPS25810-Q1

3.00mm x 4.00mm

(1) 要了解所有可用封装，请参见数据表末尾的可订购产品附录。

(1) CC 引脚符合 IEC-61000-4-2 标准

简化电路原理图

6 ´ 100 kΩ

(Optional)

TPS25810-Q1

V_BUS

Bus Power

CC Power

4.5 V–6.5 V

4.5 V–5.5 V

2.9 V–5.5 V

120 µF

OUT

IN1

FAULT

LD_DET

CC1

IN2

Power Switch

Status Signals

Auxiliary Power

AUX

EN

CC2

Control Signals

CHG

CHG_HI

REF

UFP

POL

10 µF

Type-C DFP

Status Signals

AUDIO

DEBUG

Thermal Pad

100 kΩ (1%)

REF_RTN

GND

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

English Data Sheet: SLVSD95

TPS25810-Q1

ZHCSF05 –NOVEMBER 2016

www.ti.com.cn

7.4 Device Functional Modes........................................ 23

Application and Implementation ........................ 25

8.1 Application Information............................................ 25

8.2 Typical Applications ................................................ 25

Power Supply Recommendations...................... 30

1

2

3

4

5

6

特性.......................................................................... 1

8

9

应用.......................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 2

Pin Configuration and Functions......................... 3

Specifications......................................................... 5

6.1 Absolute Maximum Ratings ...................................... 5

6.2 ESD Ratings ............................................................ 5

6.3 Recommended Operating Conditions....................... 5

6.4 Thermal Information.................................................. 6

6.5 Electrical Characteristics........................................... 6

6.6 Switching Characteristics.......................................... 8

6.7 Typical Characteristics............................................ 10

Detailed Description ............................................ 12

7.1 Overview ................................................................. 12

7.2 Functional Block Diagram ....................................... 14

7.3 Feature Description................................................. 14

10 Layout................................................................... 31

10.1 Layout Guidelines ................................................. 31

10.2 Layout Example .................................................... 32

11 器件和文档支持 ..................................................... 33

11.1 器件支持 ............................................................... 33

11.2 文档支持 ............................................................... 33

11.3 接收文档更新通知 ................................................. 33

11.4 社区资源................................................................ 33

11.5 商标....................................................................... 33

11.6 静电放电警告......................................................... 33

11.7 Glossary................................................................ 33

12 机械、封装和可订购信息....................................... 33

7

4 修订历史记录

日期

修订版本

注

2016 年 11 月

*

最初发布版本

2

TPS25810-Q1

www.ti.com.cn

ZHCSF05 –NOVEMBER 2016

5 Pin Configuration and Functions

RVC Package

20-Pin WQFN With Exposed Thermal Pad

Top View

FAULT

IN1

1

2

3

4

5

6

16

15

14

13

12

11

DEBUG

OUT

Thermal

Pad

IN1

OUT

IN2

CC2

AUX

EN

GND

CC1

Not to scale

Pin Functions

I/O

DESCRIPTION

NO.

NAME

Fault event indicator. Open-drain logic output that asserts low to indicate a current-limit or thermal-

shutdown event due to overtemperature.

1

FAULT

O

2

3

IN1

I

V_BUSinput supply. Internal power switch connects IN1 to OUT.

V_CONNinput supply. Internal power switch connects IN2 to CC1 or CC2. Short to IN1 if only one

supply is used.

4

IN2

I

Auxiliary input supply. Connect to an always-alive system rail to use the power-wake feature. Short

to IN1 and IN2 if only one supply is used.

5

6

AUX

EN

I

Enable logic input. Turns the device on and off

Charge-logic input to select between standard USB (500 mA for a Type-C receptacle supporting

only USB 2.0, and 900 mA for Type-C receptacle supporting USB 3.1) or a Type-C current-sourcing

ability.

7

CHG

I

High-charge logic input to select between 1.5-A and 3-A Type-C current sourcing capability. Valid

when CHG is set to Type-C current.

8

9

CHG_HI

REF_RTN

REF

I

Precision signal-reference return. Connect to the REF pin via a 100-kΩ, 1% resistor.

Analog input used to generate the internal current reference. Connect a 1% or better, 100-ppm,

100-kΩ resistor between this pin and REF_RTN.

10

11

12

13

14

15

16

17

CC1

GND

I/O

—

I/O

O

Analog input/output that connects to the Type-C receptacle CC1 pin

Power ground

CC2

Analog input/output that connects to the Type-C receptacle CC2 pin.

Power switch output

OUT

O

Power switch output

DEBUG

AUDIO

O

Open-drain logic output that asserts when a Type-C debug accessory is identified on the CC lines.

Open-drain logic output that asserts when a Type-C audio accessory is identified on the CC lines.

O

3

TPS25810-Q1

ZHCSF05 –NOVEMBER 2016

www.ti.com.cn

Pin Functions (continued)

I/O

DESCRIPTION

NO.

NAME

Polarity open-drain logic output that signals which Type-C CC pin is connected to the CC line. This

gives the information needed to multiplex the super-speed lines. Asserted when the CC2 pin is

connected to the CC line in the cable.

18

POL

O

19

20

UFP

O

Open-drain logic output that asserts when a Type-C UFP is identified on the CC lines.

Load-detect open-drain logic output that signals when a device set to source Type-C 3-A current is

sourcing over 1.95 A, nominal.

LD_DET

Thermal pad on the bottom of the package. The thermal pad is internally connected to GND and is

used to heat-sink the device to the circuit board. Connect the thermal pad to the GND plane.

—

Thermal pad

—

4

TPS25810-Q1

www.ti.com.cn

ZHCSF05 –NOVEMBER 2016

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range, voltages are respect to GND (unless otherwise noted)

(1)

MIN

MAX

UNIT

IN1, IN2, AUX, EN, CHG, CHG_HI, REF, OUT, LD_DET,

FAULT, CC1, CC2, UFP, POL, AUDIO, DEBUG

–0.3

7

V

Pin voltage, V

Internally

connected

to GND

REF_RTN

V

Internally

limited

Pin positive source current, I_SRC

Pin positive sink current, I_SNK

OUT, REF, CC1, CC2

A

OUT (while applying V_BUS

)

5

1

A

CC1, CC2 (while applying V_CONN

)

Internally

limited

LD_DET, FAULT, UFP, POL, AUDIO, DEBUG

mA

Operating junction temperature, T_J

Storage temperature range, T_stg

–40

–65

180

150

°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

VALUE

±2 000

±500

UNIT

Human-body model (HBM), per per AEC Q100-002⁽²⁾

Charged-device model (CDM), per per AEC Q100-011

61000-4-2 contact discharge, CC1 and CC2⁽³⁾IEC

IEC 61000-4-2 air discharge, CC1 and CC2⁽³⁾

Electrostatic

discharge

(1)

V_(ESD)

V

±8 000

±15 000

(1) Electrostatic discharge (ESD) to measure device sensitivity and immunity to damage caused by assembly line electrostatic discharges

into the device.

(2) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

(3) Surges per IEC61000-402, 1999 applied between CC1/CC2 and output ground of the TPS25810EVM-745.

6.3 Recommended Operating Conditions

Voltages are with respect to GND (unless otherwise noted)

MIN NOM

MAX UNIT

IN1

4.5

2.9

0

6.5

V_IN

Supply voltage

IN2

5.5

V

AUX

V_I

Input voltage

EN, CHG, CHG_HI

V

V_IH

V_IL

High-level input voltage

Low-level voltage

1.17

0.63

5.5

Used on LD_DET, FAULT, UFP, POL, AUDIO,

DEBUG

V_PU

I_SRC

I_SNK

Pullup voltage

0

V

OUT

3

A

Positive source current

CC1 or CC2 when supplying VCONN

250

mA

Positive sink current (10 ms moving

average)

LD_DET, FAULT, UFP, POL, AUDIO, DEBUG

10

mA

Internally

limited

I_{SNK_PULSE}Positive repetitive pulse sink current LD_DET, FAULT, UFP, POL, AUDIO, DEBUG

R_REF

T_J

Reference resistor

98

100

102

125

kΩ

Operating junction temperature

–40

°C

5

TPS25810-Q1

ZHCSF05 –NOVEMBER 2016

www.ti.com.cn

6.4 Thermal Information

TPS25810-Q1

THERMAL METRIC⁽¹⁾

RVC (WQFN)

UNIT

20 PINS

39.3

43.4

13

R_θJA

Junction-to-ambient thermal resistance

°C/W

R_θJC(top)

R_θJB

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

0.7

ψ_JB

13

R_θJC(bot)

4.2

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report, SPRA953.

6.5 Electrical Characteristics

–40°C ≤ T_J≤ 125°C, 4.5 V ≤ V_IN1≤ 6.5 V, 4.5 V ≤ V_IN2≤ 5.5 V, 2.9 V ≤ V_AUX≤ 5.5 V; V_EN= V_CHG= V_{CHG_HI}= V_AUX, R_REF

=

100 kΩ. Typical values are at 25°C. All voltages are with respect to GND. I_OUTand I_OSdefined positive out of the indicated pin

(unless otherwise noted)

PARAMETER

OUT – POWER SWITCH

TEST CONDITIONS

MIN

TYP

MAX

UNIT

T_J= 25°C, I_OUT= 3 A

34

37

46

55

r_DS(on)

On-resistance⁽¹⁾

–40°C ≤ T_J≤ 85°C, I_OUT= 3 A

–40°C ≤ T_J≤ 125°C, I_OUT= 3 A

V_OUT= 6.5 V, V_IN1= V_EN= 0 V,

mΩ

I_REV

OUT to IN reverse leakage current –40°C ≤ T_J≤ 85°C,

0

3

µA

I_REVis current out of IN1 pin

OUT – CURRENT LIMIT

V_CHG= 0 V or V_CHG= V_AUXand V_{CHG_HI}

0 V

=

1.58

3.16

1.7

3.4

1.82

(1)

I_OS

Short circuit current limit

A

3.64

7

R_REF= 10 Ω

OUT – DISCHARGE

V_OUT= 4 V, UFP signature removed from

CC lines, time < t_{w_DCHG}

Discharge resistance

400

100

500

150

600

250

Ω

V_OUT= 4 V, No UFP signature on CC lines,

time > t_{w_DCHG}

Bleed discharge resistance

kΩ

REF

V_O

Output voltage

0.78

9.5

0.8

0.82

15.3

V

I_OS

Short circuit current

R_REF= 10 Ω

µA

FAULT

V_OL

Output low voltage

Off-state leakage

I_FAULT= 1 mA

V_FAULT= 5.5 V

350

1

mV

µA

I_OFF

LD_DET

V_OL

Output low voltage

Off-state leakage

I_{LD_DET}= 1 mA

V_{LD_DET}= 5.5 V

350

1

mV

µA

I_OFF

OUT sourcing, rising threshold

current for load detect

Hysteresis⁽²⁾

I_TH

1.8

1.95

125

2.1

A

mA

(1) Pulse-testing techniques maintain junction temperature close to ambient temperature; thermal effects must be taken into account

separately.

(2) These parameters are provided for reference only and do not constitute part of TI’s published specifications for purposes of TI’s product

warranty.

6

TPS25810-Q1

www.ti.com.cn

ZHCSF05 –NOVEMBER 2016

Electrical Characteristics (continued)

–40°C ≤ T_J≤ 125°C, 4.5 V ≤ V_IN1≤ 6.5 V, 4.5 V ≤ V_IN2≤ 5.5 V, 2.9 V ≤ V_AUX≤ 5.5 V; V_EN= V_CHG= V_{CHG_HI}= V_AUX, R_REF

=

100 kΩ. Typical values are at 25°C. All voltages are with respect to GND. I_OUTand I_OSdefined positive out of the indicated pin

(unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

CC1, CC2 – V_CONNPOWER SWITCH

T_J= 25°C, I_OUT= 250 mA

365

420

530

600

r_DS(on)

On-resistance

–40°C ≤ T_J≤ 85°C, I_OUT= 250 mA

–40°C ≤ T_J≤ 125°C, I_OUT= 250 mA

mΩ

CC1, CC2 – V_CONNPOWER SWITCH – CURRENT LIMIT

300

355

410

800

I_OS

Short-circuit current limit⁽¹⁾

mA

µA

R_REF= 10 Ω

CC1, CC2 – CONNECT MANAGEMENT – DANGLING ELECTRONICALLY MARKED CABLE MODE

Sourcing current on the pass-

0 V ≤ V_CCx≤ 1.5 V

64

80

96

through CC Line

I_SRC

Sourcing current on the Ra CC

0 V ≤ V_CCx≤ 1.5 V

line

CC1, CC2 – CONNECT MANAGEMENT – ACCESSORY MODE

CCx sourcing current

0 V ≤ V_CCx≤ 1.5 V

64

80

0

96

(CC2 – audio, CC1-debug)

I_SRC

µA

CCx sourcing current

0 V ≤ V_CCx≤ 1.5 V

(2)

(CC1 – audio, CC2-debug)

CC1, CC2 – CONNECT MANAGEMENT – UFP MODE

0 V ≤ V_CCx≤ 1.5 V

V_IN1< V_{TH_UVLO_IN1}or V_IN2< V_{TH_UVLO_IN2}

Sourcing current with either IN1 or

IN2 in UVLO

I_SRC

64

75

80

96

85

V_CHG= 0 V and V_{CHG_HI}= 0 V

0 V ≤ V_CCx≤ 1.5 V

V_CHG= V_AUXand V_{CHG_HI}= 0 V

0 V ≤ V_CCx≤ 1.5 V

I_SRC

Sourcing current

170

312

180

330

190

348

V_CHG= V_AUXand V_{CHG_HI}= V_AUX

0 V ≤ V_CCx≤ 2.45 V

UFP, POL, AUDIO, DEBUG

V_OL

I_OFF

Output low voltage

Off-state leakage

I_{SNK_PIN}= 1 mA

V_PIN= 5.5 V

250

1

mV

µA

EN, CHG, CHG_HI – LOGIC INPUTS

V_TH

Rising threshold voltage

Falling threshold voltage

Hysteresis⁽²⁾

0.925

0.875

50

1.15

0.5

V

0.65

–0.5

mV

µA

I_IN

Input current

V_EN= 0 V or 6.5 V

OVERTEMPERATURE SHUTDOWN

Rising threshold temperature for

device shutdown

Hysteresis⁽²⁾

T_{TH_OTSD2}

155

135

°C

20

Rising threshold temperature for

OUT/ V_CONNswitch shutdown in

current limit

Hysteresis⁽²⁾

T_{TH_OTSD1}

°C

IN1

V_{TH_UVLO_IN1}Rising threshold voltage for UVLO

Hysteresis⁽²⁾

3.9

4.1

4.3

V

100

mV

µA

I_IN1(DIS)

Disabled supply current

V_EN= 0 V, –40°C ≤ T_J≤ 85°C

–40°C ≤ T_J≤ 85°C

1

Enabled supply current with CC

lines open

I_{IN1(CC_OPEN)}

µA

7

TPS25810-Q1

ZHCSF05 –NOVEMBER 2016

www.ti.com.cn

Electrical Characteristics (continued)

–40°C ≤ T_J≤ 125°C, 4.5 V ≤ V_IN1≤ 6.5 V, 4.5 V ≤ V_IN2≤ 5.5 V, 2.9 V ≤ V_AUX≤ 5.5 V; V_EN= V_CHG= V_{CHG_HI}= V_AUX, R_REF

=

100 kΩ. Typical values are at 25°C. All voltages are with respect to GND. I_OUTand I_OSdefined positive out of the indicated pin

(unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Enabled supply current with

accessory or dangling

electronically marked cable

signature on CC lines

I_IN1(Ra)

2

µA

V_CHG= 0 V, or V_CHG= V_AUXand V_{CHG_HI}

0 V

=

75

85

100

110

Enabled supply current with UFP

attached

I_IN1(Rd)

µA

IN2

V_{TH_UVLO_IN2}Rising threshold voltage for UVLO

Hysteresis⁽²⁾

3.9

4.1

4.3

V

100

mV

µA

I_IN2(DIS)

Disabled supply current

V_EN= 0 V, –40°C ≤ T_J≤ 85°C

–40°C ≤ T_J≤ 85°C

1

I_{IN2(CC_OPEN)}Enabled supply current with CC

lines open

µA

Enabled supply current with

accessory or dangling

electronically marked cable

I_IN2(Ra)

2

µA

signature on CC lines

Enabled supply current with UFP

signature on CC lines

(Includes IN current that provides

the CC output current to the UFP

Rd resistor)

V_CHG= 0 V, 0 V ≤ V_CCx≤ 1.5 V

98

198

348

110

215

373

V_CHG= V_INand V_{CHG_HI}= 0 V, 0 V ≤ V_CCx

1.5 V

≤

I_IN2(Rd)

µA

0 V ≤ V_CCx≤ 2.45 V

AUX

V_{TH_UVLO_AUX}Rising threshold voltage for UVLO

Hysteresis⁽²⁾

2.65

2.75

100

2.85

V

mV

µA

I_AUX(DIS)

Disabled supply current

V_EN= 0 V, –40°C ≤ T_J≤ 85°C

–40°C ≤ T_J≤ 85°C

1

3

Enabled internal supply current

with CC lines open

I_{AUX(CC_OPEN)}

0.7

µA

Enabled supply current with

accessory or dangling active cable

signature on CC lines

I_AUX(Ra)

140

185

µA

Enabled supply current with UFP

termination on CC lines and with

either IN1 or IN2 in UVLO

I_{AUX(Rd_noIN)}

V_IN1< V_{TH_UVLO_IN1}or V_IN2< V_{TH_UVLO_IN2}

145

55

190

82

µA

Enabled supply current with UFP

termination on CC lines

I_AUX(Rd)

6.6 Switching Characteristics

–40°C ≤ T_J≤ 125°C, 4.5 V ≤ V_IN1≤ 6.5 V, 4.5 V ≤ V_IN2≤ 5.5 V, 2.9 V ≤ V_AUX≤ 5.5 V; V_EN= V_CHG= V_{CHG_HI}= V_AUX, R_REF

=

100 kΩ. Typical values are at 25°C. All voltages are with respect to GND. I_OUTand I_OSdefined positive out of the indicated pin

(unless otherwise noted)

PARAMETER

OUT – POWER SWITCH

TEST CONDITIONS

MIN

TYP

MAX

UNIT

t_r

t_f

Output-voltage rise time

Output-voltage fall time

V_IN1= 5 V, C_L= 1 µF, R_L= 100 Ω

(measured from 10% to 90% of final

value)

1.2

1.8

2.5

ms

0.35

0.55

0.75

t_on

t_off

Output-voltage turnon time

Output-voltage turnoff time

2.5

2

3.5

3

5

ms

V_IN1= 5 V, C_L= 1 µF, R_L= 100 Ω

4.5

OUT – CURRENT LIMIT

Current-limit response time to short V_IN1– V_OUT= 1 V, R_L= 10 mΩ, see

circuit Figure 1

t_ios

1.5

4

µs

8

TPS25810-Q1

www.ti.com.cn

ZHCSF05 –NOVEMBER 2016

Switching Characteristics (continued)

–40°C ≤ T_J≤ 125°C, 4.5 V ≤ V_IN1≤ 6.5 V, 4.5 V ≤ V_IN2≤ 5.5 V, 2.9 V ≤ V_AUX≤ 5.5 V; V_EN= V_CHG= V_{CHG_HI}= V_AUX, R_REF

=

100 kΩ. Typical values are at 25°C. All voltages are with respect to GND. I_OUTand I_OSdefined positive out of the indicated pin

(unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

FAULT

t_DEGA

Asserting deglitch due to overcurrent

5.5

8.2

0

10.7

ms

Asserting deglitch due to

t_DEGA(OC)

overtemperature in current limit⁽¹⁾

t_DEGA(OT)

LD_DET

t_DEGA

Deasserting deglitch

5.5

8.2

10.7

Asserting deglitch

45

65

85

ms

s

t_DEGD

Deasserting deglitch

1.45

2.15

2.9

OUT – DISCHARGE

R_DCHGdischarge time

CC1, CC2 - V_CONNPOWER SWITCH

V_OUT= 1 V, time I_{SNK_OUT}> 1 mA

after UFP signature removed from

CC lines

39

65

96

ms

t_r

t_f

Output voltage rise time

Output voltage fall time

V_IN2= 5 V, C_L= 1 µF, R_L= 100 Ω

(measured from 10% to 90% of final

value)

0.15

0.18

0.25

0.22

0.35

0.26

ms

t_on

t_off

Output voltage turnon time

Output voltage turnoff time

1

1.5

0.4

2

ms

V_IN2= 5 V, C_L= 1 µF, R_L= 100 Ω

0.3

0.55

CC1, CC2 – V_CONNPOWER SWITCH – CURRENT LIMIT

Current limit response time to short

circuit

V_IN2– V_CONN= 1 V, R = 10 mΩ, see

Figure 1

t_res

1

3

µs

UFP, POL, AUDIO, DEBUG

t_DEGR

t_DEGF

Asserting deglitch

100

7.9

150

200

ms

Deasserting deglitch

12.5

17.7

(1) These parameters are provided for reference only and do not constitute part of TI’s published specifications for purposes of TI’s product

warranty.

I_OS

I_OUT

t_ios

Figure 1. Output Short-Circuit Timing Diagram

9

TPS25810-Q1

ZHCSF05 –NOVEMBER 2016

www.ti.com.cn

6.7 Typical Characteristics

50

500

450

400

350

300

250

40

30

20

10

0

-40 -25 -10

5

20 35 50 65 80 95 110 125

-40 -25 -10

5

20 35 50 65 80 95 110 125

T_J- Junction Temperature (^oC)

D001

Figure 2. V_BUSCurrent-Limiting Switch On-Resistance vs

Temperature

Figure 3. V_CONNCurrent-Limiting Switch On-Resistance vs

Temperature

0.25

0.2

0.15

0.1

0.05

0

4000

3500

3000

VBUS ILIM 3 A

VBUS ILIM 1.5 A

VCONN_ILIM

2500

2000

1500

1000

500

0

-40 -25 -10

5

20 35 50 65 80 95 110 125

-40 -25 -10

5

20 35 50 65 80 95 110 125

T_J- Junction Temperature (^oC)

D001

Device = Disabled; (V_OUT– V_IN) = 6. 5V

Figure 4. OUT Reverse Leakage Current vs Temperature

Figure 5. I_LIMfor V_BUSand V_CONNvs Temperature

2010

350

300

250

200

150

100

50

LD_DET Threshold Rising

LD_DET Threshold Falling

1990

1970

1950

1930

1910

1890

1870

1850

1830

1810

1790

1770

1750

UFP 3 A

UFP 1.5 A

UFP 0.5 A/0.9 A

-40 -25 -10

5

20 35 50 65 80 95 110 125

-40 -25 -10

5

20 35 50 65 80 95 110 125

T_J- Junction Temperature (^oC)

D001

Figure 6. LD_DET Threshold vs Temperature

Figure 7. CC Sourcing Current to UFP vs Temperature

10

TPS25810-Q1

www.ti.com.cn

ZHCSF05 –NOVEMBER 2016

Typical Characteristics (continued)

100

400

350

300

250

200

150

100

50

IN1 UFP 3 A

IN1 UFP 0.5 A/1.5 A

95

IN2 UFP 3 A

IN2 UFP 1.5 A

IN2 UFP 0.5 A

90

85

80

75

70

-40 -25 -10

5

20 35 50 65 80 95 110 125

-40 -25 -10

5

20 35 50 65 80 95 110 125

T_J- Junction Temperature (^oC)

D001

Figure 8. IN1 Current With UFP vs Temperature

Figure 9. IN2 Current With UFP vs Temperature

70

65

60

55

50

45

40

-40 -25 -10

5

20 35 50 65 80 95 110 125

T_J- Junction Temperature (^oC)

D001

V_AUX= 5 V

Figure 10. AUX Current With UFP vs Temperature

11

TPS25810-Q1

ZHCSF05 –NOVEMBER 2016

www.ti.com.cn

7 Detailed Description

7.1 Overview

The TPS25810-Q1 device is a highly integrated USB Type-C™ downstream-facing port (DFP) controller with

built-in power switch developed for the new USB Type-C connector and cable. The device provides all of the

functionality needed to support a USB Type-C DFP in a system where USB power delivery (PD) source

capabilities (for example, V_BUS> 5 V) are not implemented. The device is designed to be compliant with the

Type‑C specification, revision 1.1.

7.1.1 USB Type-C Basic

For a detailed description of the Type-C specification, see the USB-IF Web site to download the latest released

version. Some of the basic concepts of the Type-C specification that pertain to understanding the operation of

the TPS25810-Q1 device (a DFP device) are described as follows.

USB Type-C removes the need for different plug and receptacle types for host and device functionality. The

Type-C receptacle replaces both Type-A and Type-B receptacles because the Type-C cable is pluggable in

either direction between host and device. A host-to-device logical relationship is maintained via the configuration

channel (CC). Optionally, hosts and devices can be either providers or consumers of power when USB PD

communication is used to swap roles.

All USB Type-C ports operate in one of the following three data modes:

•

Host mode: the port can only be host (provider of power).

Device mode: the port can only be device (consumer of power).

Dual-role mode: the port can be either host or device.

Port types:

•

DFP (downstream facing port): Host

UFP (upstream facing port): Device

DRP (dual-role port): Host or device

Valid DFP-to-UFP connections:

•

Table 1 describes valid DFP-to-UFP connections.

Host-to-host and device-to-device have no functions.

Table 1. DFP-to-UFP Connections

DEVICE-MODE

PORT

HOST-MODE PORT

DUAL-ROLE PORT

Host-mode port

Device-mode port

Dual-role port

No function

Works

No function

Works

Works⁽¹⁾

Works

(1) This may be automatic or manually driven.

7.1.2 Configuration Channel

The function of the configuration channel (CC) is to detect connections and configure the interface across the

USB Type-C cables and connectors.

Functionally, the configuration channel serves the following purposes:

•

Detect connection to the USB ports

Resolve cable orientation and twist connections to establish USB data bus routing

Establish DFP and UFP roles between two connected ports

Discover and configure power: USB Type-C current modes or USB power delivery

Discover and configure optional alternate and accessory modes

Enhance flexibility and ease of use

Typical flow of DFP to UFP configuration is shown in Figure 11:

12

TPS25810-Q1

www.ti.com.cn

ZHCSF05 –NOVEMBER 2016

Detect Valid

Connection

Establish USB

Power Method

USB Device

Enumeration

Figure 11. Flow of DFP to UFP Configuration

7.1.3 Detecting a Connection

DFPs and DRPs fulfill the role of detecting a valid connection over USB Type-C. Figure 12 shows a DFP-to-UFP

connection made with Type-C cable. As shown in Figure 12, the detection concept is based on being able to

detect terminations in the product that has been attached. A pullup and pulldown termination model is used. A

pullup termination can be replaced by a current source.

•

In the DFP-UFP connection, the DFP monitors both CC pins for a voltage lower than the unterminated

voltage.

•

A UFP advertises Rd on both its CC pins (CC1 and CC2).

A powered cable advertises Ra on only one of the CC pins of the plug. Ra is used to inform the source to

apply V_CONN

.

•

An analog audio device advertises Ra on both CC pins of the plug, which identifies it as an analog audio

device. V_CONNis not applied on either CC pin in this case.

UFP monitors for

connection

DFP monitors for

connection

Cable

CC

Rp

Rds

Ra

DFP monitors for

connection

UFP monitors for

connection

Figure 12. DFP-UFP Connection

13

TPS25810-Q1

ZHCSF05 –NOVEMBER 2016

www.ti.com.cn

7.2 Functional Block Diagram

7.3 Feature Description

The TPS25810-Q1 device is a DFP Type-C port controller with integrated power switches for V_CONNand V_BUS

.

The TPS25810-Q1 device does not support BC1.2 charging modes, because it does not interact with USB D+

and D– data lines. The TPS25810-Q1 device can be used in conjunction with a BC 1.2 device like the

TPS2514A-Q1 to support BC1.2 and Type-C charging modes in a single Type-C DFP port. See the TPS25810

EVM user's guide (SLVUAI0) and Application and Implementation section of this data sheet for more details. The

TPS25810-Q1 device can be used in a USB 2.0 only or in a USB 3.1 port implementation. When used in a USB

3.1 port, the TPS25810-Q1 device can control an external super-speed MUX to handle the Type-C flippable

feature.

14

TPS25810-Q1

www.ti.com.cn

ZHCSF05 –NOVEMBER 2016

Feature Description (continued)

7.3.1 Configuration Channel Pins CC1 and CC2

The TPS25810-Q1 device has two pins, CC1 and CC2, that serve to detect an attachment to the port and to

resolve cable orientation. These pins are also used to establish the current broadcast to a valid UFP, configure

V_CONN, and detect attachment of a debug or audio-adapter accessory.

Table 2 lists the TPS25810-Q1 response to various attachments to its port.

Table 2. TPS25810-Q1 Response

TPS25810-Q1 RESPONSE⁽¹⁾

V_CONN

on CC1 or

CC2

TPS25810-Q1 TYPE-C PORT

CC1

CC2

OUT

POL

UFP

AUDIO

DEBUG

Nothing attached

UFP connected

OPEN

Rd

OPEN

Rd

OPEN

IN1

NO

Hi-Z

LOW

Hi-Z

OPEN

IN1

LOW

Powered cable, no UFP

connected

OPEN

Ra

OPEN

Ra

OPEN

IN1

NO

Hi-Z

Powered cable, no UFP

connected

Powered cable, UFP

connected

Rd

CC2

LOW

Powered cable, UFP

connected

Ra

Rd

Ra

Rd

Ra

IN1

CC1

NO

LOW

Hi-Z

LOW

Hi-Z

LOW

Hi-Z

Debug accessory connected

OPEN

Audio-adapter accessory

connected

NO

LOW

(1) POL, UFP, AUDIO, and DEBUG are open-drain outputs; pull high with 100 kΩ to AUX when used. Tie to GND or leave open when not

used.

7.3.2 Current Capability Advertisement and Overload Protection

The TPS25810-Q1 device supports all three Type-C current advertisements as defined by the USB Type-C

standard. Current broadcast to a connected UFP is controlled by the CHG and CHG_HI pins. For each broadcast

level, the device protects itself from a UFP that draws current in excess of the USB Type-C current

advertisement of that port by setting the current limit as shown in Table 3.

Table 3. USB Type-C Current Advertisement

CC CAPABILITY

BROADCAST

LOAD DETECT

THRESHOLD (TYP)

CHG

CHG_HI

CURRENT LIMIT (TYP)

0

1

0

1

0

1

STD

1.5 A

3 A

1.7 A

3.4 A

NA

1.95 A

Under OUT overload conditions, an internal OUT current-limit regulator limits the output current to the selected

I_LIMbased on CHG and CHG_HI selection. In applications where V_CONNis supplied via CC1 or CC2, separate

fixed current-limit regulators protect these pins from overload at the level indicated in the Electrical

Characteristics table. When an overload condition is present, the device maintains a constant output current, with

the output voltage determined by (I_OS× R_LOAD). Two possible overload conditions can occur. The first overload

condition occurs when either: 1) input voltage is first applied, enable is true, and a short circuit is present (load

which draws I_OUT> I_OS), or 2) input voltage is present and the TPS25810-Q1 device is enabled into a short

circuit. The output voltage is held near zero potential with respect to ground and the TPS25810-Q1 device ramps

the output current to I_OS. The TPS25810-Q1 device limits the current to I_OSuntil the overload condition is

removed or the device begins to thermal cycle. This is demonstrated in Figure 24 where the device was enabled

into a short, and subsequently cycles current off and on as the thermal protection engages.

15

TPS25810-Q1

ZHCSF05 –NOVEMBER 2016

www.ti.com.cn

The second condition is when an overload occurs while the device is enabled and fully turned on. The device

responds to the overload condition within time t_ios(see Figure 1) when the specified overload (per Electrical

Characteristics) is applied. The response speed and shape vary with the overload level, input circuit, and rate of

application. The current-limit response varies between simply settling to I_OSor turnoff and controlled return to I_OS

.

Similar to the previous case, the TPS25810-Q1 device limits the current to I_OSuntil the overload condition is

removed or the device begins to thermal cycle.

The TPS25810-Q1 device thermal cycles if an overload condition is present long enough to activate thermal

limiting in any of the above cases. This is due to the relatively large power dissipation [(V_IN– V_OUT) × I_OS] driving

the junction temperature up. The device turns off when the junction temperature exceeds 135°C (min) while in

current limit. The device remains off until the junction temperature cools 20°C and then restarts. The

TPS25810‑Q1 current-limit profile is shown in Figure 13.

V_OUT

Slope = -r _DS(on)

0 V

I_OUT

0 A

I_OS

Figure 13. Current Limit Profile

7.3.3 Undervoltage Lockout (UVLO)

The undervoltage lockout (UVLO) circuit disables the power switch until the input voltage reaches the UVLO

turnon threshold. Built-in hysteresis prevents unwanted on-off cycling due to input voltage droop during turnon.

7.3.3.1 Device Power Pins (IN1, IN2, AUX, OUT, and GND)

The device has multiple input power pins: IN1, IN2 and AUX. IN1 is connected to OUT by the internal power FET

and serves the supply for the Type-C charging current. IN2 is the supply for V_CONNand ties directly between the

V_CONNpower switch on its input and CC1 or CC2 on its output. AUX, the auxiliary input supply, provides power to

the device. See the Functional Block Diagram.

In the simplest implementation where multiple supplies are not available; IN1, IN2, and AUX can be tied together.

However, in mobile systems (battery powered) where system power savings is paramount, IN1 and IN2 can be

powered by the high-power dc-dc supply (>3-A capability), and AUX can be connected to the low-power supply

that typically powers the system microcontroller when the system is in the hibernate or sleep power state. Unlike

IN1 and IN2, AUX can operate directly from a 3.3-V supply commonly used to power the microcontroller when

the system is put in low-power mode. Ceramic bypass capacitors close to the device from the INx and AUX pins

to GND are recommended to alleviate bus transients.

The recommended operating voltage range for IN1 and IN2 is 4.5 V to 5.5 V, whereas AUX can be operated

from 2.9 V to 5.5 V. However IN1, the high-power supply, can operate up to 6.5 V. This higher input voltage

affords a larger IR loss budget in systems where a long cable harness is used, and results in high IR losses with

3-A charging current. Increasing IN1 beyond 5.5 V enables longer cable and board trace lengths between the

device and the Type-C receptacle while meeting the USB specification for V_BUS≥ 4.75 V at the connector.

Figure 14 illustrates the point. In this example IN1 is at 5 V, which restricts the IR loss budget from the dc-dc

converter to the connector to 250 mV.

16

TPS25810-Q1

www.ti.com.cn

ZHCSF05 –NOVEMBER 2016

Total IR Drop Budget = 250 mV

Trace IR Drop Budget at 3 A

= 250 – 165 = 85 mV

V_Trace1

V_Trace2

V_TPS25810-Q1

V_DC-DC = 5 V

V_Connector

= 4.75 V (MIN)

IN1

OUT

5-V DC-DC

MaxRds_On = 55 mΩ

165-mV Drop at 3 A

82.5-mV Drop at 1.5 A

Figure 14. Total IR Loss Budget

7.3.3.2 FAULT Response

The FAULT pin is an open-drain output asserted low when the device OUT current exceeds its programmed

value and the overtemperature threshold (T_{TH_OTSD1}) is crossed. See the Electrical Characteristics for overcurrent

and overtemperature values. The FAULT signal remains asserted until the fault condition is removed and the

device resumes normal operation. The TPS25810-Q1 device is designed to eliminate false overcurrent fault

reporting by using an internal deglitch circuit.

Connect FAULT with a pullup resistor to AUX. FAULT can be left open or tied to GND when not used.

7.3.3.3 Thermal Shutdown

The device has two internal overtemperature shutdown thresholds, T_{TH_OTSD1}and T_{TH_OTSD2}, to protect the

internal FET from damage and assist with overall safety of the system. T_{TH_OTSD2}is greater than T_{TH_OTSD1}

.

FAULT is asserted low to signal a fault condition when the device temperature exceeds T_{TH_OTSD1}and the

current-limit switch is disabled. However when T_{TH_OTSD2}is exceeded, all open-drain outputs are left open and

the device is disabled such that minimum power and heat are dissipated. The device attempts to power up when

the die temperature decreases by 20°C.

7.3.3.4 REF

A 100-kΩ (1% or better recommended) resistor is connected from this pin to REF_RTN. The REF pin sets the

reference current required to bias the internal circuitry of the device. The overload current-limit tolerance and CC

currents depend upon the accuracy of this resistor. Using a ±1% or better low-temperature-coefficient resistor

yields the best current-limit accuracy and overall device performance.

7.3.3.5 Audio Accessory Detection

The USB Type-C specification defines an audio-adapter decode state which allows implementation of an analog

USB Type-C to 3.5-mm headset adapter. The TPS25810-Q1 device detects an audio accessory device when

both CC1 and CC2 pins detect V_Ravoltage (when pulled to ground by an Ra resistor). The device asserts the

open-drain AUDIO pin low to indicate the detection of such a device.

17

TPS25810-Q1

ZHCSF05 –NOVEMBER 2016

www.ti.com.cn

Table 4. Audio Accessory Detection

CC1

CC2

AUDIO

STATE

Audio-adapter accessory connected

Ra

Asserted (pulled low)

Platforms supporting the audio accessory function can be triggered by the AUDIO pin to enable accessory mode

circuits to support the audio function. When the Ra pulldown is removed from the CC2 pin, AUDIO is deasserted

or pulled high. The TPS25810-Q1 device monitors the CC2 pin for audio device detach. When this function is not

needed (for example in a data-less port), AUDIO can be tied to GND or left open.

7.3.3.6 Debug Accessory Detection

The Type-C spec supports an optional debug-accessory mode, used for debug only and not to be used for

communicating with commercial products. When the TPS25810-Q1 device detects V_Rdvoltage on both CC1 and

CC2 pins (when pulled to ground by an Rd resistor), it asserts DEBUG low. With DEBUG asserted, the system

can enter debug mode for factory testing or a similar functional mode. DEBUG deasserts or pulls high when Rd

is removed from CC1. The TPS25810-Q1 device monitors the CC1 pin for debug-accessory detach.

If the debug-accessory mode is not used, tie DEBUG to GND or leave it open.

Table 5. Debug Accessory Detection

CC1

CC2

POL

STATE

Rd

Asserted (pulled low)

Debug accessory connected

7.3.3.7 Plug Polarity Detection

Reversible Type-C plug orientation is reported by the POL pin when a UFP is connected. However, when no

UFP is attached POL remains deasserted, irrespective of cable plug orientation. Table 6 describes the POL state

based on which of the device CC pins detects V_Rdfrom an attached UFP pulldown.

Table 6. Plug Polarity Detection

CC1

Rd

CC2

Open

Rd

POL

Hi-Z

STATE

UFP connected

Open

Asserted (pulled low)

UFP connected with reverse plug orientation

18

TPS25810-Q1

www.ti.com.cn

ZHCSF05 –NOVEMBER 2016

Figure 15 shows an example implementation which uses the POL terminal to control the SEL terminal on the

HD3SS3212 device. The HD3SS3212 device provides switching on the differential channels between Port B and

Port C to Port A, depending on cable orientation. For details on the HD3SS3212 device, see the HD3SS3212

data sheet (SLASE74).

3.3 V

HD3SS3212

USB C

SSTXp2

0.1 µF

B0+

Dp1

Dp2

USB Host

SSTXp

V_CC

Dp

B0–

C0+

C0–

B1+

B1–

C1+

C1–

SSTXn2

SSTXp1

SSTXn1

SSRXp2

SSRXn2

SSRXp1

SSRXn1

A0+

A0–

Dm

Dm1

Dm2

SSTXn

SSRXp

A1+

A1–

SSRXn

Dp

GND

Dp

Dm

OEn

SEL

3.3 V

GND

TPS25810-Q1

OUT

5 V

POL

OUT

UFP

CC1

CC2

IN1

5 V

IN2

CHG

AUX

EN

CHG H_I

FAULT

LD_DET

AUDIO

REF

REF_RTN

GND

DEBUG

Thermal Pad

Figure 15. Example Implementation

7.3.3.8 Device Enable Control

The logic enable pin (EN) controls the power switch and device supply current. The supply current is reduced to

less than 1 μA when a logic low is present on EN. The EN pin provides a convenient way to turn on or turn off

the device while it is powered. The enable input threshold has built-in hysteresis. When this pin is pulled high, the

device is turned on or enabled. When the device is disabled (EN pulled low) the internal FETs tied to IN1 and

IN2 are disconnected, all open-drain outputs are left open (Hi-Z), and the monitor block for CC1 and CC2 is

turned off. The EN terminal should not be left floating.

7.3.3.9 Load Detect

The load-detect function in the device is enabled when the device is set to broadcast high-current V_BUScharging

(CHG = CHG_HI = High) on the CC pin. In this mode, the device monitors the OUT current to a UFP; if the

current exceeds 1.95 A (typ), the LD_DET pin asserts. Because LD_DET is an open-drain output, pull it high with

100 kΩ to AUX when used; tie it to GND or leave it open when not used.

19

TPS25810-Q1

ZHCSF05 –NOVEMBER 2016

www.ti.com.cn

7.3.3.10 Power Wake

The power-wake feature supported in the TPS25810-Q1 device offers the mobile-systems designer a way to

save on system power when no UFP is attached to the Type-C port. See Figure 16. To enable power wake, the

UFP pins from device No. 1 and No. 2 are tied together (each with its own 100-kΩ pullup) to the enable pin of a

5-V, 6-A dc-dc buck converter. When no UFP is detected on both Type-C ports, the EN pin of the dc-dc

converter is pulled high, thereby disabling it. Because both TPS25810-Q1 devices are powered by an always-on

3.3-V LDO, turning off the supply to IN1 and IN2 does not affect its operation in detach state. Anytime a UFP is

detected on either port, the corresponding TPS25810-Q1 UFP pin is pulled low, enabling the dc-dc converter to

provide charging current to the attached UFP. Turning off the high-power dc-dc converter when ports are

unattached saves on system power. This method can save a significant amount of power, because the

TPS25810-Q1 device only requires < 5 µA when no UFP device is connected.

20

TPS25810-Q1

www.ti.com.cn

ZHCSF05 –NOVEMBER 2016

Both UFP High

Converters

Disabled

OUT

CC1

CC2

IN1

TPS54620

Buck

Converter

No UFP

Attached

I

IN2

AUX

TPS25810-Q1

No. 1

EN

CHG

UFP_1

CHG_HI

12 V

UFP_1

(High)

UFP_2

(High)

OUT

CC1

CC2

IN1

No UFP

Attached

IN2

LP2950-33

LDO

AUX

TPS25810-Q1

No. 2

CHG

UFP_2

CHG_HI

One UFP Low

Converter

Enabled

OUT

CC1

CC2

IN1

TPS54620

Buck

Converter

UFP

IN2

Attached

AUX

TPS25810-Q1

No. 1

EN

CHG

UFP_1

-

CHG_HI

12 V

UFP_1

(High)

UFP_2

(High)

IN1

OUT

CC1

CC2

No UFP

Attached

IN2

LP2950-33

LDO

AUX

TPS25810-Q1

No. 2

CHG

UFP_2

CHG_HI

Figure 16. Power-Wake Implementation

7.3.3.11 Port Power Management (PPM)

PPM is the intelligent and dynamic allocation of power made possible with the use of the LD_DET pin. PPM is for

systems that have multiple charging ports but cannot power them all at their maximum charging current

simultaneously.

Goals of PPM are:

•

Enhanced user experience, because the user needs not to search for a high-current charging port.

Lowered cost and size of the power supply needed for implementing high-current charging in a multiport

system.

21

TPS25810-Q1

ZHCSF05 –NOVEMBER 2016

www.ti.com.cn

7.3.3.12 Implementing PPM in a System With Two Type-C Ports

Figure 17 shows PPM and power wake implemented in a system with two Type-C ports, both initially set to

broadcast high-current charging (3 A, CHG and CHG_HI pulled high via 100-kΩ resistors to AUX). To enable

PPM, tie the LD_DET pin from TPS25810-Q1 device No. 1 to CHG_HI of TPS25810-Q1 device No. 2 and vice

versa, as shown in Figure 17. Each device independently monitors the charging current drawn by its attached

UFP.

IN1 and IN2 are connected to a TPS54620, a 6-A synchronous step-down converter. AUX is powered by an

LP2950-33, a low-quiescent-current 3.3-V LDO. With no UFP attached to either Type-C port, the TPS25810-Q1

device is powered by the LP2950-33. This method saves a significant amount of power, because the

TPS25810‑Q1 device requires less than 2 µA when no USB device is connected.

TPS54620

Buck

Converter

OUT

CC1

CC2

IN1

IN2

3-A Broadcast

EN

AUX TPS25810-Q1

No. 1

LD_DET_1

UFP_1

CHG

CHG_HI

12 V

UFP_1 UFP_2

OUT

CC1

CC2

IN1

IN2

3-A Broadcast

LP2950-33

LDO

AUX TPS25810-Q1

No. 2

CHG

LD_DET_2

CHG_HI

UFP_2

Figure 17. PPM and Power Wake Implemented

7.3.3.13 PPM Operation

When no UFP is attached, or either of the two attached UFPs is drawing current less than the LD_DET threshold

(1.95 A typical), the LD_DET output for both devices is high (shown in blue in Figure 18). Now when a UFP is

attached to device No. 1 that draws a charging current higher than the LD_DET threshold (1.95 A), this causes

LD_DET to assert or pull low (shown in red in Figure 18). Because the LD-DET pins of the No. 1 and No. 2

devices are connected to the CHG_HI pins of each other, a high-current detection on device No. 1 forces device

No. 2 to broadcast 1.5 A or medium charging-current capability on its CC pin. The Type-C specification requires

a UFP to monitor the CC pins continuously and adjust its current consumption (within 60 ms) to remain within the

value advertised by the DFP.

Figure 19 shows the case when a UFP attached to device No. 1 reduces its charging current below the LD_DET

threshold, which causes LD-DET to de-assert, thereby toggling the device No. 2 CH_HI pin from low to high.

This scheme:

•

Delivers a better user experience, as the user has no worry about the maximum charging current rating of the

host ports. Both ports initially advertise high-current charging.

•

Enables a smaller and lower-cost power supply, as the loading is controlled and never allowed to exceed 5 A.

22

TPS25810-Q1

www.ti.com.cn

ZHCSF05 –NOVEMBER 2016

TPS54620

Buck

Converter

OUT

CC1

CC2

IN1

IN2

3-A USB Device Connected

EN

AUX TPS25810-Q1

No. 1

LD_DET_1

UFP_1

CHG

CHG_HI

12 V

UFP_1 UFP_2

OUT

CC1

CC2

IN1

IN2

1.5-A Broadcast

LP2950-33

LDO

AUX TPS25810-Q1

No. 2

CHG

LD_DET_2

UFP_2

CHG_HI

Figure 18. 3-A USB Device Connected

TPS54620

Buck

Converter

OUT

CC1

CC2

IN1

IN2

1.5-A USB Device Connected

EN

AUX TPS25810-Q1

No. 1

LD_DET_1

UFP_1

CHG

CHG_HI

12 V

UFP_1 UFP_2

OUT

CC1

CC2

IN1

IN2

3-A Broadcast

LP2950-33

LDO

AUX TPS25810-Q1

No. 2

CHG

LD_DET_2

UFP_2

CHG_HI

Figure 19. 1.5-A USB Device Connected

7.4 Device Functional Modes

The TPS25810-Q1 device is a Type-C controller with integrated power switch that supports all Type-C functions

in a downstream facing port. The device is also used to manage current advertisement and protection for a

connected UFP and active cable. The device starts its operation by monitoring the AUX bus. When V_AUXexceeds

the undervoltage-lockout threshold, the device samples the EN pin. A high level on this pin enables the device,

and normal operation begins. Having successfully completed its start-up sequence, the device now actively

23

TPS25810-Q1

ZHCSF05 –NOVEMBER 2016

www.ti.com.cn

Device Functional Modes (continued)

monitors its CC1 and CC2 pins for attachment to a UFP. When a UFP is detected on either the CC1 or CC2 pin,

the internal MOSFET starts to turn on after the required debounce time is met. The internal MOSFET starts

conducting and allows current to flow from IN1 to OUT. If Ra is detected on the other CC pin (not connected to

the UFP), V_CONNis applied to allow current to flow from IN2 to the CC pin connected to Ra. For a complete listing

of various device operational modes, see Table 2.

24

TPS25810-Q1

www.ti.com.cn

ZHCSF05 –NOVEMBER 2016

8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

8.1 Application Information

The TPS25810-Q1 device is a Type-C DFP controller that supports all Type-C DFP required functions. The

TPS25810-Q1 device only applies power to V_BUSwhen it detects that a UFP is attached and removes power

when it detects the UFP is detached. The device exposes its identity via its CC pin, advertising its current

capability based on CHG and CHG_HI pin settings. The TPS25810-Q1 device also limits its advertised current

internally and provides robust protection to a fault on the system V_BUSpower rail.

After a connection is established by the TPS25810-Q1 device, the device is capable of providing V_CONNto power

circuits in the cable plug on the CC pin that is not connected to the CC wire in the cable. V_CONNis internally

current limited and has its own supply pin IN2. Apart from providing charging current to a UFP, the

TPS25810‑Q1 device also supports audio and debug accessory modes.

The following design procedure can be used to implement a full-featured Type-C DFP.

NOTE

BC 1.2 is not supported in the TPS25810-Q1 device. To support BC1.2 with Type-C

charging modes in a single Type-C connector, a device like a TPS2514A-Q1 must be

used.

8.2 Typical Applications

8.2.1 Type-C DFP Port Implementation Without BC 1.2 Support

Figure 20 shows a minimal Type-C DFP implementation capable of supporting 5-V and 3-A charging.

USB Type-C

Receptacle

TPS25810-Q1

5 V

2

3

4

5

6

7

8

V_BUS

IN1

14

15

13

11

1

OUT

IN1

OUT

CC2

CC1

IN2

AUX

EN

FAULT

20

19

18

17

16

10 µF

CHG

CHG_HI

LD_DET

UFP

POL

AUDIO

DEBUG

10

9

REF

100 kW

(1%)

12

GND

REF_RTN

Figure 20. Type-C DFP Port Implementation Without BC 1.2 Support

25

TPS25810-Q1

ZHCSF05 –NOVEMBER 2016

www.ti.com.cn

Typical Applications (continued)

8.2.1.1 Design Requirements

8.2.1.1.1 Input and Output Capacitance

Input and output capacitance improves the performance of the device. The actual capacitance should be

optimized for the particular application. For all applications, a 0.1-μF or greater ceramic bypass capacitor

between INx and GND is recommended as close to the device as possible for local noise decoupling.

All protection circuits, such as the TPS25810-Q1 device, have the potential for input voltage overshoots and

output voltage undershoots. Input voltage overshoots can be caused by either of two effects. The first cause is

an abrupt application of input voltage in conjunction with input power-bus inductance and input capacitance when

the INx pin is high-impedance (before turnon). Theoretically, the peak voltage is 2 times the applied voltage. The

second cause is due to the abrupt reduction of output short-circuit current when the TPS25810-Q1 device turns

off and energy stored in the input inductance drives the input voltage high. Input voltage droops may also occur

with large load steps and as the TPS25810-Q1 output is shorted. Applications with large input inductance (for

instance, connecting the evaluation board to the bench power supply through long cables) may require large

input capacitance to prevent the voltage overshoot from exceeding the absolute maximum voltage of the device.

The fast current-limit speed of the TPS25810-Q1 device to hard output short circuits isolates the input bus from

faults. However, ceramic input capacitance in the range of 1 μF to 22 μF adjacent to the TPS25810-Q1 input aids

in both response time and limiting the transient seen on the input power bus. Momentary input transients to 6.5 V

are permitted. Output voltage undershoot is caused by the inductance of the output power bus just after a short

has occurred and the TPS25810-Q1 device has abruptly reduced the OUT current. Energy stored in the

inductance drives the OUT voltage down, and potentially negative, as it discharges. An application with large

output inductance (such as from a cable) benefits from the use of a high-value output capacitor to control voltage

undershoot.

When implementing a USB-standard application, 120-μF minimum output capacitance is required. Typically, a

150-μF electrolytic capacitor is used, which is sufficient to control voltage undershoots. Because in Type-C

applications, DFP is a cold socket when no UFP is attached, the output capacitance should be placed at the INx

pin versus the OUT pin, as is done in USB Type-A ports. It is also recommended to put a 10-μF ceramic

capacitor on the OUT pin for better voltage bypass.

8.2.1.2 Detailed Design Procedure

The TPS25810-Q1 device supports up to three different input voltages, based on the application. In the simplest

implementation, all input pins are tied to a single voltage source set to 5 V, as shown in Figure 20. However, it is

recommended to set a slightly higher (100 mV to 200 mV) input voltage, when possible, to compensate for IR

loss from the source to the Type-C connector.

Other design considerations are listed as follows:

•

Place at least 120 µF of bypass capacitance close to the INx pins versus the OUT pin, as Type-C is a cold-

socket connector.

A 10-µF bypass capacitor is recommended to be placed near a Type-C receptacle V_BUSpin to handle load

transients.

Depending on the maximum current-level advertisement supported by the Type-C port in the system, set the

CHG and CHG_HI levels accordingly. Advertisement of 3 A is shown in Figure 20.

EN, CHG, and CHG_HI pins can be tied directly to GND or V_AUXwithout a pullup resistor.

–

CHG and CHG_HI can also be dynamically controlled by a microcontroller to change the current

advertisement level to the UFP.

•

When an open-drain output of the TPS25810-Q1 device is not used, it can be left open or tied to GND.

Use a 1% 100-kΩ resistor to connect between the REF and REF_RTN pins, placing it close to the device pin

and isolated from switching noise on the board.

26

TPS25810-Q1

www.ti.com.cn

ZHCSF05 –NOVEMBER 2016

Typical Applications (continued)

8.2.1.3 Application Curves

VIN

CC1

VIN

VBUS

CC2

CC1

IN

Time 20 ms/div

Basic start-up: IN1 = IN2 = AUX = EN = CHG = CHG_HI = 5 V,

CC1 = Rd, CC2 = open

Time 50 ms/div

IN1 = IN2 = AUX = EN = CHG = CHG_HI = 5 V, CC1 = open,

CC2 = open → Rd

Figure 21. Basic Start-Up

Figure 22. Start-Up

VBUS VIN

VIN

VBUS

IN

CC1

IN

CC1

Time 50 ms/div

IN1 = IN2 = AUX = EN = CHG = CHG_HI = 5 V, CC1 = Rd,

CC2 = open, OUT = shorted

Time 200 ms/div

IN1 = IN2 = AUX = EN = 5 V; CHG = CHG_HI = 0 V,

CC1 = open, CC2 = Rd, OUT = open → 5 Ω

Figure 24. Hot-Plug to Short

Figure 23. Load Step

VIN

VBUS

VOUT

CC1

IN

CC1

CC2

Time 20 ms/div

IN1 = IN2 = AUX = EN = CHG = CHG_HI = 5 V, CC1 = short,

CC2 = Rd

Time 20 ms/div

IN1 = IN2 = AUX = EN = CHG = CHG_HI = 5 V, CC1 = Rd →

open, CC2 = open

Figure 25. Short On CC1

Figure 26. Remove Rd

27

TPS25810-Q1

ZHCSF05 –NOVEMBER 2016

www.ti.com.cn

Typical Applications (continued)

VIN

VBUS

CC2

CC1

Time 50 ms/div

V_IN5 V → 3.5 V (100 ms) → 5 V (1 V/ms),

IN1 = IN2 = AUX = EN = CHG = CHG_HI = 5 V,

CC1 = Rd, CC2 = Ra

Figure 27. Brown-Out Test

28

TPS25810-Q1

www.ti.com.cn

ZHCSF05 –NOVEMBER 2016

Typical Applications (continued)

8.2.2 Type-C DFP Port Implementation With BC 1.2 (DCP Mode) Support

Figure 28 shows a Type-C DFP implementation capable of supporting 5-V, 3-A charging in a Type-C port that is

also able to support charging of legacy devices when used with a Type-C µB cable assembly for charging

phones and handheld devices equipped with a µB connector.

This implementation requires the use of a TPS2514A-Q1, a USB dedicated charging-port (DCP) controller with

auto-detect feature to charge not only BC1.2 compliant handheld devices but also popular phones and tablets

that incorporate their own propriety charging algorithm. See the TPS2514A-Q1 datasheet for more details.

TPS2514A-Q1

IN

DM1

DP1

NC

0.1 µF

NC

GND

USB Type-C

Receptacle

TPS25810-Q1

5 V

2

3

4

5

6

7

8

V_BUS

IN1

14

15

13

11

1

OUT

CC2

CC1

IN1

D–

D+

IN2

AUX

EN

FAULT

20

19

18

17

16

12

10 µF

CHG

CHG_HI

LD_DET

UFP

POL

10

REF

AUDIO

DEBUG

GND

100 kW

(1%)

9

REF_RTN

Figure 28. Type-C DFP Port Implementation With BC 1.2 (DCP Mode) Support

8.2.2.1 Design Requirements

See Design Requirements for the design requirements.

8.2.2.2 Detailed Design Procedure

See Detailed Design Procedure for the detailed design procedure.

8.2.2.3 Application Curves

See Application Curves for the application curves.

29

TPS25810-Q1

ZHCSF05 –NOVEMBER 2016

www.ti.com.cn

9 Power Supply Recommendations

The device has three power supply inputs. IN1, which is directly connected to OUT via the power MOSFET, is

tied to the V_BUSpin in the Type-C receptacle. IN2 also has a current-limiting switch and is multiplexed either to

the CC1 or CC2 pin in the Type-C receptacle, depending on cable plug polarity. AUX is the device supply. In

most applications, all three supplies are tied together. In a special implementation like power wake, IN1 and IN2

are tied to a single supply, whereas AUX is powered by a supply that is always ON and can be as low as 2.9 V.

USB Specification Revisions 2.0 and 3.1 require V_BUSvoltage at the connector to be between 4.75 V and 5.5 V.

Depending on layout and routing from the supply to the connector, the voltage drop on V_BUSmust be tightly

controlled. Locate the input supply close to the device. For all applications, a 10-μF or greater ceramic bypass

capacitor between OUT and GND is recommended, located as close to the Type-C connector of the device as

possible for local noise decoupling. The power supply should be rated higher than the current limit setting to

avoid voltage droops during overcurrent and short-circuit conditions.

30

TPS25810-Q1

www.ti.com.cn

ZHCSF05 –NOVEMBER 2016

10 Layout

10.1 Layout Guidelines

Layout best practices as they apply to the TPS25810-Q1 device are listed as follows.

•

For all applications, a 10-µF ceramic capacitor is recommended near the Type-C receptacle and another

120‑µF ceramic capacitor close to the IN1 pin.

–

The optimum placement of the 120-µF capacitor is closest to the IN1 and GND pins of the device.

Care must be taken to minimize the loop area formed by the bypass capacitor connection, the IN1 pin,

and the GND pin of the IC. See Figure 29 for a PCB layout example.

•

High-current-carrying power-path connections to the device should be as short as possible and should be

sized to carry at least twice the full-load current.

–

Have the input and output traces as short as possible. The most common cause of voltage loss failure in

USB power delivery is the resistance associated with the V_BUStrace. Trace length, maximum current being

supplied for normal operation, and total resistance associated with the V_BUStrace must be taken into

account while budgeting for voltage loss.

–

For example, a power-carrying trace that supplies 3 A, at a distance of 20 inches, 0.1-in. wide, with 2‑oz.

copper on the outer layer has a total resistance of approximately 0.046 Ω and voltage loss of 0.14 V. The

same trace at 0.05 in. wide has a total resistance of approximately 0.09 Ω and voltage loss of 0.28 V.

Make power traces as wide as possible.

•

The resistor attached to the REF pin of the device has several requirements:

–

It is recommended to use a 1% 100-kΩ low-temperature-cocoefficient resistor.

It should be connected to the REF and REF_RTN pins (pins 9 and pin 10, respectively).

The REF_RTN pin should be isolated from the GND plane. See Figure 29.

The trace routing between the REF and REF_RTN pins of the device should be as short as possible to

reduce parasitic effects on current-limit and current-advertisement accuracy. These traces should not have

any coupling to switching signals on the board.

Locate all TPS25810-Q1 pullup resistors for open-drain outputs close to their connection pin. Pullup resistors

should be 100 kΩ.

–

When a particular open-drain output is not used or needed in the system, leave the associated pin open or

tied to GND.

•

Keep the CC lines close to the same length.

Thermal considerations:

–

When properly mounted, the thermal-pad package provides significantly greater cooling ability than an

ordinary package. To operate at rated power, the thermal pad must be soldered to the board GND plane

directly under the device. The thermal pad is at GND potential and can be connected using multiple vias

to inner-layer GND. Other planes, such as the bottom side of the circuit board, can be used to increase

heat sinking in higher-current applications. See the PowerPad™ Thermally Enhanced Package technical

report (SLMA002) and PowerPAD™ Made Easy application brief (SLMA004) for more information on

using this thermal pad package.

–

The thermal via land pattern specific to the TPS25810-Q1 device can be downloaded from the device

Web page at www.ti.com.

Obtaining acceptable performance with alternate layout schemes is possible; however, the layout example

in the following section has been shown to produce good results and is intended as a guideline.

•

ESD considerations:

–

The TPS25810-Q1 device has built-in ESD protection for CC1 and CC2. Keep trace length to a minimum

from the Type-C receptacle to the TPS25810-Q1 device on CC1 and CC2.

–

A 10-µF output capacitor should be placed near the Type-C receptacle.

See the TPS25810EVM-745 evaluation module for an example of a double-layer board that passes

IEC61000-4-2 testing.

–

Do not create stubs or test points on the CC lines. Keep the traces short if possible, and use minimal vias

along the traces (1–2 inches or less).

–

See the ESD Protection Layout Guide application report (SLVA680) for additional information.

Have a dedicated ground plane layer, if possible, to avoid differential voltage buildup.

31

TPS25810-Q1

ZHCSF05 –NOVEMBER 2016

www.ti.com.cn

10.2 Layout Example

Top Layer Signal Trace

Top Layer Signal Ground Plane

Bottom Layer Signal Trace

Bottom Layer Signal Ground Plane

Via to Bottom Layer Signal Ground Plane

Via to Bottom Layer Signal

AUX

1

16

15

2

Thermal

Pad

IN1

OUT

3

14

13

12

11

4

5

6

IN2

CC2

GND

CC1

AUX

EN

Signal Ground

Bottom Layer

Signal Ground

Top Layer

Figure 29. Layout Example

32

TPS25810-Q1

www.ti.com.cn

ZHCSF05 –NOVEMBER 2016

11 器件和文档支持

11.1 器件支持

11.1.1 Third-Party Products Disclaimer

TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT

CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES

OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER

ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.

11.2 文档支持

11.2.1 相关文档ꢀ

《PowerPAD™ 耐热增强型封装》（文献编号：SLMA002）

《PowerPAD™ 速成》（文献编号：SLMA004）

《TPS25810EVM-745 用户指南》（文献编号：SLVUA0）

《TPS25810 高压 DFP 保护》（文献编号：SLVA751）

11.3 接收文档更新通知

如需接收文档更新通知，请访问 www.ti.com.cn 网站上的器件产品文件夹。点击右上角的提醒我 (Alert me) 注册

后，即可每周定期收到已更改的产品信息。有关更改的详细信息，请查阅已修订文档中包含的修订历史记录。

11.4 社区资源

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective

contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of

Use.

TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration

among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help

solve problems with fellow engineers.

Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and

contact information for technical support.

11.5 商标

E2E is a trademark of Texas Instruments.

USB Type-C is a trademark of USB Implementers Forum, Inc..

All other trademarks are the property of their respective owners.

11.6 静电放电警告

这些装置包含有限的内置 ESD 保护。存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损

伤。

11.7 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

12 机械、封装和可订购信息

以下页中包括机械、封装和可订购信息。这些信息是针对指定器件提供的最新数据。本数据随时可能发生变更并且

不对本文档进行修订，恕不另行通知。要获得这份数据表的浏览器版本，请查阅左侧的导航窗格。

33

重要声明

德州仪器(TI) 及其下属子公司有权根据 JESD46 最新标准, 对所提供的产品和服务进行更正、修改、增强、改进或其它更改，并有权根据

JESD48 最新标准中止提供任何产品和服务。客户在下订单前应获取最新的相关信息, 并验证这些信息是否完整且是最新的。所有产品的销售

都遵循在订单确认时所提供的TI 销售条款与条件。

TI 保证其所销售的组件的性能符合产品销售时 TI 半导体产品销售条件与条款的适用规范。仅在 TI 保证的范围内，且 TI 认为有必要时才会使

用测试或其它质量控制技术。除非适用法律做出了硬性规定，否则没有必要对每种组件的所有参数进行测试。

TI 对应用帮助或客户产品设计不承担任何义务。客户应对其使用 TI 组件的产品和应用自行负责。为尽量减小与客户产品和应用相关的风险，

客户应提供充分的设计与操作安全措施。

TI 不对任何 TI 专利权、版权、屏蔽作品权或其它与使用了 TI 组件或服务的组合设备、机器或流程相关的 TI 知识产权中授予的直接或隐含权

限作出任何保证或解释。TI 所发布的与第三方产品或服务有关的信息，不能构成从 TI 获得使用这些产品或服务的许可、授权、或认可。使用

此类信息可能需要获得第三方的专利权或其它知识产权方面的许可，或是 TI 的专利权或其它知识产权方面的许可。

对于 TI 的产品手册或数据表中 TI 信息的重要部分，仅在没有对内容进行任何篡改且带有相关授权、条件、限制和声明的情况下才允许进行

复制。TI 对此类篡改过的文件不承担任何责任或义务。复制第三方的信息可能需要服从额外的限制条件。

在转售 TI 组件或服务时，如果对该组件或服务参数的陈述与 TI 标明的参数相比存在差异或虚假成分，则会失去相关 TI 组件或服务的所有明

示或暗示授权，且这是不正当的、欺诈性商业行为。TI 对任何此类虚假陈述均不承担任何责任或义务。

客户认可并同意，尽管任何应用相关信息或支持仍可能由 TI 提供，但他们将独力负责满足与其产品及在其应用中使用 TI 产品相关的所有法

律、法规和安全相关要求。客户声明并同意，他们具备制定与实施安全措施所需的全部专业技术和知识，可预见故障的危险后果、监测故障

及其后果、降低有可能造成人身伤害的故障的发生机率并采取适当的补救措施。客户将全额赔偿因在此类安全关键应用中使用任何 TI 组件而

对 TI 及其代理造成的任何损失。

在某些场合中，为了推进安全相关应用有可能对 TI 组件进行特别的促销。TI 的目标是利用此类组件帮助客户设计和创立其特有的可满足适用

的功能安全性标准和要求的终端产品解决方案。尽管如此，此类组件仍然服从这些条款。

TI 组件未获得用于 FDA Class III（或类似的生命攸关医疗设备）的授权许可，除非各方授权官员已经达成了专门管控此类使用的特别协议。

只有那些 TI 特别注明属于军用等级或“增强型塑料”的 TI 组件才是设计或专门用于军事/航空应用或环境的。购买者认可并同意，对并非指定面

向军事或航空航天用途的 TI 组件进行军事或航空航天方面的应用，其风险由客户单独承担，并且由客户独力负责满足与此类使用相关的所有

法律和法规要求。

TI 已明确指定符合 ISO/TS16949 要求的产品，这些产品主要用于汽车。在任何情况下，因使用非指定产品而无法达到 ISO/TS16949 要

求，TI不承担任何责任。

产品

应用

www.ti.com.cn/telecom

数字音频

www.ti.com.cn/audio

www.ti.com.cn/amplifiers

www.ti.com.cn/dataconverters

www.dlp.com

通信与电信

计算机及周边

消费电子

能源

放大器和线性器件

数据转换器

DLP® 产品

DSP - 数字信号处理器

时钟和计时器

接口

www.ti.com.cn/computer

www.ti.com/consumer-apps

www.ti.com/energy

www.ti.com.cn/dsp

工业应用

医疗电子

安防应用

汽车电子

视频和影像

www.ti.com.cn/industrial

www.ti.com.cn/medical

www.ti.com.cn/security

www.ti.com.cn/automotive

www.ti.com.cn/video

www.ti.com.cn/clockandtimers

www.ti.com.cn/interface

www.ti.com.cn/logic

逻辑

电源管理

www.ti.com.cn/power

www.ti.com.cn/microcontrollers

www.ti.com.cn/rfidsys

www.ti.com/omap

微控制器 (MCU)

RFID 系统

OMAP应用处理器

无线连通性

www.ti.com.cn/wirelessconnectivity

德州仪器在线技术支持社区

www.deyisupport.com

IMPORTANT NOTICE

邮寄地址：上海市浦东新区世纪大道1568 号，中建大厦32 楼邮政编码： 200122

重要声明和免责声明

TI 均以“原样”提供技术性及可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资

源，不保证其中不含任何瑕疵，且不做任何明示或暗示的担保，包括但不限于对适销性、适合某特定用途或不侵犯任何第三方知识产权的暗示

担保。

所述资源可供专业开发人员应用TI 产品进行设计使用。您将对以下行为独自承担全部责任：(1) 针对您的应用选择合适的TI 产品；(2) 设计、

验证并测试您的应用；(3) 确保您的应用满足相应标准以及任何其他安全、安保或其他要求。所述资源如有变更，恕不另行通知。TI 对您使用

所述资源的授权仅限于开发资源所涉及TI 产品的相关应用。除此之外不得复制或展示所述资源，也不提供其它TI或任何第三方的知识产权授权

许可。如因使用所述资源而产生任何索赔、赔偿、成本、损失及债务等，TI对此概不负责，并且您须赔偿由此对TI 及其代表造成的损害。

TI 所提供产品均受TI 的销售条款 (http://www.ti.com.cn/zh-cn/legal/termsofsale.html) 以及ti.com.cn上或随附TI产品提供的其他可适用条款的约

束。TI提供所述资源并不扩展或以其他方式更改TI 针对TI 产品所发布的可适用的担保范围或担保免责声明。IMPORTANT NOTICE

邮寄地址：上海市浦东新区世纪大道 1568 号中建大厦 32 楼，邮政编码：200122


型号：	CSD18536KTTT
厂家：	TEXAS INSTRUMENTS
描述：	采用 D2PAK 封装的单路、1.6mΩ、60V、N 沟道 NexFET™ 功率 MOSFET \| KTT \| 3 \| -55 to 175
文件：	总38页 (文件大小：909K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

CSD18536KTTT [TI]

相关型号：

CSD18537NKCS

CSD18537NQ5A

CSD18537NQ5AT

CSD18537NQ5A_14

CSD18541F5

CSD18541F5T

CSD18542KCS

CSD18542KTT

CSD18542KTTT

CSD18543Q3A

CSD18543Q3AT

CSD18563Q5A