CSD19537Q3 [TI]
采用 3mm x 3mm SON 封装的单路、14.5mΩ、100V、N 沟道 NexFET™ 功率 MOSFET;
| 型号： | CSD19537Q3 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 采用 3mm x 3mm SON 封装的单路、14.5mΩ、100V、N 沟道 NexFET™ 功率 MOSFET |
| 文件： | 总13页 (文件大小：1225K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CSD19537Q3
ZHCSE28B –AUGUST 2015 –REVISED NOVEMBER 2022
CSD19537Q3 100V N 通道NexFET™ 功率MOSFET
产品概要
1 特性
TA = 25°C
VDS
典型值
100
单位
V
漏源电压
• 超低Qg 和Qgd
• 低热阻
Qg
16
nC
栅极电荷总量(10V)
Qgd
2.9
nC
• 雪崩级
• 无铅端子镀层
• 符合RoHS
• 无卤素
栅极电荷（栅极到漏极）
漏源导通电阻
VGS = 6V
VGS = 10V
13.8
12.1
mΩ
mΩ
V
RDS(on)
VGS(th)
3
阈值电压
• 小外形尺寸无引线(SON) 3.3mm × 3.3mm 塑料封
装
.
订购信息(1)
数量
2 应用
器件
介质
封装
配送
SON 3.3mm x
3.3mm
塑料封装
CSD19537Q3
2500
250
13 英寸卷带
• 一次侧隔离式转换器
• 电机控制
卷带包装
CSD19537Q3T
13 英寸卷带
3 说明
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
这款 100V 12.1mΩ SON 3.3mm × 3.3mm NexFET™
功率 MOSFET 旨在用于更大限度地降低功率转换应用
中的损耗。
绝对最大额定值
TA = 25°C
值
单位
V
VDS
VGS
100
±20
漏源电压
S
S
S
G
1
2
3
4
8
7
6
5
D
D
D
V
栅源电压
50
53
A
A
持续漏极电流（受封装限制）
持续漏极电流（受芯片限制），TC = 25°C 时
测得
ID
持续漏极电流(1)
脉冲漏极电流(2)
功耗(1)
9.7
219
2.8
83
A
A
IDM
PD
D
D
W
W
P0095-01
功率耗散，TC = 25°C
TJ、 工作结温，
–55 至
150
图3-1.
顶视图
°C
Tstg
贮存温度
雪崩能量，单脉冲
ID = 33A，L = 0.1mH，RG = 25Ω
EAS
55
mJ
(1)
R
θJA = 45°C/W，这是在0.06 英寸厚FR4 PCB 上的1 平方英
寸、2oz 铜焊盘上测得的典型值。
(2) 最大RθJC = 1.5°C/W，脉冲持续时间≤100μs，占空比≤
1%.
40
35
30
25
20
15
10
5
10
TC = 25° C, ID = 10 A
TC = 125° C, ID = 10 A
ID = 10 A
VDS = 50 V
9
8
7
6
5
4
3
2
1
0
0
0
2
4
6
8
10
12
14
VGS - Gate-To-Source Voltage (V)
16
18
20
0
2
4
6
8
10
Qg - Gate Charge (nC)
12
14
16
D007
D004
R
DS(on) 与VGS 之间的关系
栅极电荷
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLPS549
CSD19537Q3
ZHCSE28B –AUGUST 2015 –REVISED NOVEMBER 2022
www.ti.com.cn
Table of Contents
6.1 Community Resources................................................7
6.2 Trademarks.................................................................7
6.3 Electrostatic Discharge Caution..................................7
6.4 术语表......................................................................... 7
7 Mechanical, Packaging, and Orderable Information....8
7.1 Q3 Package Dimensions............................................ 8
7.2 Recommended PCB Pattern.......................................9
7.3 Recommended Stencil Opening................................. 9
7.4 Q3 Tape and Reel Information..................................10
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Specifications.................................................................. 3
5.1 Electrical Characteristics.............................................3
5.2 Thermal Information....................................................3
5.3 Typical MOSFET Characteristics................................4
6 Device and Documentation Support..............................7
4 Revision History
Changes from Revision A (May 2016) to Revision B (November 2022)
Page
• Corrected legend on 图5-11 ..............................................................................................................................4
Changes from Revision * (August 2015) to Revision A (May 2016)
Page
• Corrected typo in X axis legend on 图5-11 ....................................................................................................... 4
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5 Specifications
5.1 Electrical Characteristics
TA = 25°C (unless otherwise stated)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
STATIC CHARACTERISTICS
BVDSS
IDSS
V
Drain-to-source voltage
100
VGS = 0 V, ID = 250 μA
VGS = 0 V, VDS = 80 V
VDS = 0 V, VGS = 20 V
VDS = VGS, ID = 250 μA
VGS = 6 V, ID = 10 A
VGS = 10 V, ID = 10 A
VDS = 10 V, ID = 10 A
Drain-to-source leakage current
Gate-to-source leakage current
Gate-to-source threshold voltage
1
100
3.6
μA
nA
V
IGSS
VGS(th)
2.6
3
13.8
12.1
45
16.6
14.5
mΩ
mΩ
S
RDS(on)
gfs
Drain-to-source on-resistance
Transconductance
DYNAMIC CHARACTERISTICS
Ciss
Coss
Crss
RG
Input capacitance
1290
251
13.3
1.2
16
1680
326
17.3
2.4
pF
pF
pF
Output capacitance
Reverse transfer capacitance
Series gate resistance
Gate charge total (10 V)
Gate charge gate-to-drain
Gate charge gate-to-source
Gate charge at Vth
Output charge
VGS = 0 V, VDS = 50 V, ƒ= 1 MHz
Ω
Qg
21
nC
nC
nC
nC
nC
ns
Qgd
Qgs
Qg(th)
Qoss
td(on)
tr
2.9
5.5
3.8
44
VDS = 50 V, ID = 10 A
VDS = 50 V, VGS = 0 V
Turn on delay time
Rise time
5
3
ns
VDS = 50 V, VGS = 10 V,
IDS = 10 A, RG = 0 Ω
td(off)
tf
Turn off delay time
Fall time
10
ns
3
ns
DIODE CHARACTERISTICS
VSD
Qrr
trr
Diode forward voltage
Reverse recovery charge
Reverse recovery time
ISD = 10 A, VGS = 0 V
0.8
134
36
1
V
nC
ns
VDS= 50 V, IF = 10 A,
di/dt = 300 A/μs
5.2 Thermal Information
TA = 25°C (unless otherwise stated)
THERMAL METRIC
Junction-to-case thermal resistance (1)
Junction-to-ambient thermal resistance, Note 1 and Note 2(1) (2)
MIN
TYP
MAX UNIT
1.5 °C/W
55 °C/W
RθJC
RθJA
(1)
R
θJC is determined with the device mounted on a 1-in2 (6.45-cm2), 2-oz (0.071-mm) thick Cu pad on a 1.5-in × 1.5-in (3.81-cm × 3.81-
cm), 0.06-in (1.52-mm) thick FR4 PCB. RθJC is specified by design, whereas RθJA is determined by the user’s board design.
(2) Device mounted on FR4 material with 1-in2 (6.45-cm2), 2-oz (0.071-mm) thick Cu.
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GATE
Source
GATE
Source
Max RθJA = 55°C/W when
mounted on 1 in2 (6.45 cm2) of 2-
oz (0.071-mm) thick Cu.
Max RθJA = 160°C/W when
mounted on a minimum pad area
of 2-oz (0.071-mm) thick Cu.
DRAIN
DRAIN
M0161-01
M0161-02
5.3 Typical MOSFET Characteristics
TA = 25°C (unless otherwise stated)
图5-1. Transient Thermal Impedance
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100
90
80
70
60
50
40
30
20
10
80
70
60
50
40
30
20
10
0
TC = 125° C
TC = 25° C
TC = -55° C
VGS = 6 V
VGS = 8 V
VGS = 10 V
0
0
0.2 0.4 0.6 0.8
1
VDS - Drain-to-Source Voltage (V)
1.2 1.4 1.6 1.8
2
2
3
4
5
VGS - Gate-to-Source Voltage (V)
6
7
D002
D003
VDS = 5 V
图5-2. Saturation Characteristics
图5-3. Transfer Characteristics
10000
1000
100
10
10
9
8
7
6
5
4
3
2
1
0
Ciss = Cgd + Cgs
Coss = Cds + Cgd
Crss = Cgd
1
0
10
20
30
40
50
60
VDS - Drain-to-Source Voltage (V)
70
80
90 100
0
2
4
6
8
10
Qg - Gate Charge (nC)
12
14
16
D005
D004
图5-5. Capacitance
ID = 10 A
VDS = 50 V
图5-4. Gate Charge
3.6
3.4
3.2
3
40
35
30
25
20
15
10
5
TC = 25° C, ID = 10 A
TC = 125° C, ID = 10 A
2.8
2.6
2.4
2.2
2
1.8
0
0
-75 -50 -25
0
25
TC - Case Temperature (° C)
50
75 100 125 150 175
2
4
6
8
10
12
VGS - Gate-To-Source Voltage (V)
14
16
18
20
D007
D006
ID = 250 µA
图5-7. On-State Resistance vs Gate-to-Source
Voltage
图5-6. Threshold Voltage vs Temperature
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100
10
2.2
TC = 25° C
TC = 125° C
VGS = 6 V
VGS = 10 V
2
1.8
1.6
1.4
1.2
1
1
0.1
0.01
0.001
0.0001
0.8
0.6
0.4
0
0.2
0.4
0.6
VSD - Source-to-Drain Voltage (V)
0.8
1
-75 -50 -25
0
25
50
TC - Case Temperature (° C)
75 100 125 150 175
D009
D008
图5-9. Typical Diode Forward Voltage
ID = 10 A
图5-8. Normalized On-State Resistance vs
Temperature
1000
100
10
100
10
1
T
T
C = 25° C
C = 125° C
1
DC
10 ms
1 ms
100 µs
10 µs
0.1
0.1
1
10
100
VDS - Drain-to-Source Voltage (V)
1000
0.01
0.1
1
D010
TAV - Time in Avalanche (ms)
D011
Single Pulse, Max RθJC = 1.5°C/W
图5-11. Single Pulse Unclamped Inductive
图5-10. Maximum Safe Operating Area
Switching
60
50
40
30
20
10
0
-50
-25
0
25
50
TC - Case Temperature (° C)
75
100 125 150 175
D012
图5-12. Maximum Drain Current vs Temperature
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6 Device and Documentation Support
6.1 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among
engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with
fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact
information for technical support.
6.2 Trademarks
NexFET™ is a trademark of Texas Instruments.
E2E™ are trademarks of Texas Instruments.
所有商标均为其各自所有者的财产。
6.3 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
6.4 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
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7 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
7.1 Q3 Package Dimensions
MILLIMETERS
NOM
INCHES
NOM
DIM
MIN
0.950
0.000
0.280
MAX
1.100
0.050
0.400
MIN
0.037
0.000
0.011
MAX
0.043
0.002
0.016
A
A1
b
1.000
0.039
0.000
0.000
0.340
0.013
b1
c
0.310 NOM
0.200
0.012 NOM
0.008
0.150
3.200
1.650
0.150
0.300
3.200
2.350
0.250
3.400
1.800
0.250
0.400
3.400
2.550
0.006
0.126
0.065
0.006
0.012
0.126
0.093
0.010
0.134
0.071
0.010
0.016
0.134
0.100
D
3.300
0.130
D2
d
1.750
0.069
0.200
0.008
d1
E
0.350
0.014
3.300
0.130
E2
e
2.450
0.096
0.650 TYP
0.450
0.026 TYP
0.018
H
0.35
0.550
0.014
0.022
K
0.650 TYP
0.450
0.026 TYP
0.018
L
0.35
0
0.550
0.014
0.022
L1
θ
0
0
0
0
0
0
—
—
0
—
—
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7.2 Recommended PCB Pattern
For recommended circuit layout for PCB designs, see application note SLPA005 – Reducing Ringing Through
PCB Layout Techniques.
7.3 Recommended Stencil Opening
All dimensions are in mm, unless otherwise specified.
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7.4 Q3 Tape and Reel Information
4.00 0.ꢀ0 ꢁ(SS ꢂNoS ꢀ1
8.00 0.ꢀ0
2.00 0.0ꢃ
Ø ꢀ.ꢃ0
+0.ꢀ0
–0.00
3.60
M0ꢀ44-0ꢀ
Notes:
1. 10 sprocket hole pitch cumulative tolerance ±0.2
2. Camber not to exceed 1 mm in 100 mm, noncumulative over 250 mm
3. Material: black static dissipative polystyrene
4. All dimensions are in mm (unless otherwise specified).
5. Thickness: 0.30 ±0.05 mm
6. MSL1 260°C (IR and Convection) PbF-Reflow Compatible
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PACKAGE OPTION ADDENDUM
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16-Nov-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
2500
250
(1)
(2)
(3)
(4/5)
(6)
CSD19537Q3
CSD19537Q3T
ACTIVE
VSON-CLIP
VSON-CLIP
DQG
8
8
RoHS-Exempt
& Green
SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-55 to 150
-55 to 150
CSD19537
CSD19537
Samples
Samples
ACTIVE
DQG
RoHS-Exempt
& Green
SN
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
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16-Nov-2022
Addendum-Page 2
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