CSD22205L [TI]
采用 1.2mm x 1.2mm LGA 封装、具有栅极 ESD 保护的单路、9.9mΩ、-8V、P 沟道 NexFET™ 功率 MOSFET;
| 型号： | CSD22205L |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 采用 1.2mm x 1.2mm LGA 封装、具有栅极 ESD 保护的单路、9.9mΩ、-8V、P 沟道 NexFET™ 功率 MOSFET 栅 开关 脉冲 晶体管 栅极 |
| 文件： | 总14页 (文件大小：1909K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CSD22205L
ZHCSGI4B –AUGUST 2017 –REVISED FEBRUARY 2022
CSD22205L –8V P 沟道NexFET™ 功率MOSFET
产品概要
1 特性
TA = 25°C
值
–8
6.5
1.0
单位
VDS
V
漏源电压
栅极电荷总量(–4.5V)
• 低电阻
• 1.2mm × 1.2mm 小尺寸封装
• 0.36mm 厚，超薄型
• 无铅
• 栅源电压钳位
• 栅极ESD 保护
• 符合RoHS
Qg
nC
nC
Qgd
栅极电荷（栅极到漏极）
30
20
VGS = –1.5V
VGS = –1.8V
VGS = –2.5V
VGS = –4.5V
–0.7
RDS(on)
mΩ
漏源导通电阻
11.5
8.2
• 无卤素
VGS(th)
V
阈值电压
2 应用
器件信息(1)
介质
• 电池管理
• 负载开关
• 电池保护
器件
数量
封装
配送
CSD22205L
CSD22205LT
3000
1.20mm × 1.20mm
基板栅格阵列
封装
7 英寸卷带
卷带包装
250
3 说明
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
这款 -8V、8.2mΩ、1.2mm × 1.2mm 基板栅格阵列
(LGA) NexFET™ 器件设计用于在超薄且具有出色散热
特性的超小外形尺寸封装内提供更低的导通电阻和栅极
电荷。基板栅格阵列 (LGA) 封装是一种带有金属接触
板（而非焊球）的器件芯片级封装。
绝对最大额定值
TA = 25°C
VDS
值
–8
单位
V
漏源电压
VGS
ID
V
A
–6
栅源电压
40
持续漏极电流(1)
脉冲漏极电流(2)
功率耗散(1)
–7.4
–71
0.6
TC = 25°C, ID = -1 A
TC = 125°C, ID = -1 A
35
30
25
20
15
10
5
IDM
A
PD
W
TJ、
Tstg
工作结温，
贮存温度
–55 至
150
°C
(1)
RθJA = 225°C/W（覆铜面积最小时的值）。
(2) 脉宽≤100μs，占空比≤1%。
Source
0
0
1
2
3
4
-VGS - Gate-to-Source Voltage (V)
5
6
G
D007
1.2 mm
R
DS(on) 与VGS 之间的关系
S
D
Gate
D
4.5
4
ID = -1 A
VDS = -4 V
Drain
3.5
3
1.2 mm.
2.5
2
图3-1. 顶视图和电路配置
1.5
1
0.5
0
0
1
2
3
4
Qg - Gate Charge (nC)
5
6
7
D004
R
DS(on) 与VGS 之间的关系
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLPS690
CSD22205L
ZHCSGI4B –AUGUST 2017 –REVISED FEBRUARY 2022
www.ti.com.cn
Table of Contents
6 Device and Documentation Support..............................7
6.1 Receiving Notification of Documentation Updates......7
6.2 Trademarks.................................................................7
7 Mechanical, Packaging, and Orderable Information....8
7.1 CSD22205L Package Dimensions..............................8
7.2 Land Pattern Recommendation.................................. 9
7.3 Stencil Recommendation............................................9
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Specifications.................................................................. 3
5.1 Electrical Characteristics.............................................3
5.2 Thermal Information....................................................4
5.3 Typical MOSFET Characteristics................................4
4 Revision History
Changes from Revision A (August 2017) to Revision B (February 2022)
Page
• 将超薄型封装要点中的厚度从0.35mm 更改为0.36mm..................................................................................... 1
• Changed CSD22205L Package Dimensions image height from 0.35 mm to 0.36 mm......................................8
Changes from Revision * (May 2017) to Revision A (August 2017)
Page
• Changed the units for timing parameters from µs : to ns (nanoseconds) in the 节5.1 table..............................3
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5 Specifications
5.1 Electrical Characteristics
TA = 25°C (unless otherwise stated)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
STATIC CHARACTERISTICS
BVDSS
IDSS
Drain-to-source voltage
V
nA
nA
V
VGS = 0 V, ID = –250 μA
VGS = 0 V, VDS = –6.4 V
VDS = 0 V, VGS = –6 V
VDS = VGS, ID = –250 μA
VGS = –1.5 V, ID = –0.2 A
VGS = –1.8 V, ID = –1 A
VGS = –2.5 V, ID = –1 A
VGS = –4.5 V, ID = –1 A
VDS = –0.8 V, ID = –1 A
–8
Drain-to-source leakage current
Gate-to-source leakage current
Gate-to-source threshold voltage
–100
–100
–1.05
IGSS
VGS(th)
–0.4
–0.7
30
20
40
15.0
9.9
RDS(on)
Drain-to-source on-resistance
mΩ
11.5
8.2
gfs
Transconductance
10.4
S
DYNAMIC CHARACTERISTICS
CISS
COSS
CRSS
RG
Input capacitance
1070
560
190
30
1390
730
pF
pF
pF
Output capacitance
Reverse transfer capacitance
Series gate resistance
Gate charge total (–4.5 V)
Gate charge gate-to-drain
Gate charge gate-to-source
Gate charge at Vth
Output charge
VGS = 0 V, VDS = –4 V, ƒ= 1 MHz
250
Ω
nC
nC
nC
nC
nC
ns
Qg
6.5
1.0
1.2
0.7
4.1
30
8.5
Qgd
Qgs
Qg(th)
QOSS
td(on)
tr
VDS = –4 V, ID = –1 A
VDS = –4 V, VGS = 0 V
Turnon delay time
Rise time
14
ns
VDS = –4 V, VGS = –4.5 V,
ID = –1 A , RG = 0 Ω
td(off)
tf
Turnoff delay time
Fall time
70
ns
32
ns
DIODE CHARACTERISTICS
VSD
Qrr
trr
Diode forward voltage
Reverse recovery charge
Reverse recovery time
V
IS = –1 A, VGS = 0 V
–0.68
16
–1.0
nC
ns
VDS= –4 V, IF = –1 A,
di/dt = 200 A/μs
38
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5.2 Thermal Information
TA = 25°C (unless otherwise stated)
THERMAL METRIC
MIN
TYP MAX UNIT
Junction-to-ambient thermal resistance(2)
Junction-to-ambient thermal resistance(1)
75
RθJA
°C/W
225
(1) Device mounted on FR4 material with minimum Cu mounting area.
(2) Device mounted on FR4 material with 1-in2 (6.45-cm2), 2-oz (0.071-mm) thick Cu.
Typ RθJA = 225°C/W
when mounted on
minimum pad area of 2-
oz Cu.
Typ RθJA =75°C/W when
mounted on 1 in2 of 2-oz Cu.
5.3 Typical MOSFET Characteristics
TA = 25°C (unless otherwise stated)
50
45
40
35
30
25
20
15
10
5
50
45
40
35
30
25
20
15
10
5
VGS = -1.5 V
VGS = -1.8 V
VGS = -2.5 V
VGS = -4.5 V
TC = 125°C
TC = 25°C
TC = -55°C
0
0
0
0.5
1
1.5
2
2.5
3
3.5
-VDS - Drain-to-Source Voltage (V)
4
4.5
5
0
0.5
1
1.5
2
-VGS - Gate-to-Source Voltage (V)
2.5
3
D002
D003
图5-1. Saturation Characteristics
VDS = –5 V
图5-2. Transfer Characteristics
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12
4.5
4
ID = -1 A
VDS = -4 V
10
8
3.5
3
2.5
2
6
1.5
1
4
2
0.5
0
0
0
1
2
3
4
Qg - Gate Charge (nC)
5
6
7
-50
-25
0
25
50
TA - Ambient Temperature (° C)
75
100 125 150 175
D004
D011
ID = –1 A
VDS = –4 V
图5-3. Maximum Drain Current vs Temperature
图5-4. Gate Charge
10000
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
Ciss = Cgd + Cgs
Coss = Cds + Cgd
Crss = Cgd
1000
100
10
0
1
2
3
4
5
6
-VDS -Drain-to-Source Voltage (V)
7
8
-75 -50 -25
0
25
50
TC - Case Temperature (°C)
75 100 125 150 175
D005
D006
图5-5. Capacitance
ID = –250 µA
图5-6. Threshold Voltage vs Temperature
40
35
30
25
20
15
10
5
1.4
TC = 25°C, ID = -1 A
TC = 125°C, ID = -1 A
VGS = -1.8 V
VGS = -2.5 V
VGS = -4.5 V
1.3
1.2
1.1
1
0.9
0.8
0.7
0
-75 -50 -25
0
25
50
75 100 125 150 175
0
1
2
3
4
-VGS - Gate-to-Source Voltage (V)
5
6
TC - Case Temperature (èC)
D008
D007
ID = –1 A
图5-7. On-State Resistance vs Gate-to-Source
Voltage
图5-8. Normalized On-State Resistance vs
Temperature
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10
200
100
TC = -55èC
TC = -40èC
TC = 25èC
1
TC = 125èC
TC = 150èC
0.1
0.01
10
1
0.001
0.0001
100 ms
10 ms
1 ms
100 µs
0.1
0.1
0
0.2
0.4
0.6
-VSD - Source-to-Drain Voltage (V)
0.8
1
1
-VDS - Drain-to-Source Voltage (V)
10
20
D009
D010
图5-9. Typical Diode Forward Voltage
Single pulse, typical RθJA = 225°C/W
图5-10. Maximum Safe Operating Area
图5-11. Transient Thermal Impedance
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6 Device and Documentation Support
6.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
6.2 Trademarks
NexFET™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
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7 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
7.1 CSD22205L Package Dimensions
1.20
1.12
B
A
PIN 1 INDEX AREA
1.20
1.12
C
0.36 MAX
SEATING PLANE
0.7
3X 0.35
(R) TYP0.05
4
3
2
0.41
0.39
0.015
C B A
0.225
0.3
0.86
2X
0.015
C B A
0.84
1
0.26
0.24
0.16
0.14
4X
0.015
C B A
4222872/A 04/2016
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning
and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This package is a lead-free bump design. Bump finish may vary. To determine the exact finish, refer to the
device data sheet or contact a local TI representative.
表7-1. Pin Configuration
Table
POSITION
DESIGNATION
1
2
3
4
Gate
Drain
Source
Drain
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7.2 Land Pattern Recommendation
3X (0.35)
0.05 MIN
ALL AROUND
TYP
4X (0.15)
(0.25)
(R0.05)
1
(0.3)
PKG
2X (0.85)
(0.225)
(0.4)
2
3
4
SOLDER MASK
OPENING
TYP
METAL UNDER
SOLDER MASK
TYP
PKG
7.3 Stencil Recommendation
3X (0.35)
4X (0.15)
(R0.05) TYP
(0.25)
1
0.3
PKG
2X (0.85)
0.225
(0.4)
2
3
4
PKG
A. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design
recommendations.
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PACKAGE OPTION ADDENDUM
www.ti.com
11-Jan-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
CSD22205L
ACTIVE
ACTIVE
PICOSTAR
PICOSTAR
YMG
YMG
4
4
3000 RoHS & Green
250 RoHS & Green
NIAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-55 to 150
-55 to 150
205
205
CSD22205LT
NIAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
11-Jan-2022
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Sep-2021
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
CSD22205L
PICOST
AR
YMG
YMG
4
4
3000
250
180.0
8.4
1.26
1.26
0.42
4.0
8.0
Q1
CSD22205LT
PICOST
AR
180.0
8.4
1.26
1.26
0.42
4.0
8.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Sep-2021
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
CSD22205L
PICOSTAR
PICOSTAR
YMG
YMG
4
4
3000
250
182.0
182.0
182.0
182.0
20.0
20.0
CSD22205LT
Pack Materials-Page 2
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