CSD86350Q5D_V01 [TI]
CSD86350Q5D Synchronous Buck NexFET⢠Power Block;
| 型号： | CSD86350Q5D_V01 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | CSD86350Q5D Synchronous Buck NexFET⢠Power Block |
| 文件： | 总15页 (文件大小：906K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CSD86350Q5D
www.ti.com
SLPS223A –MAY 2010–REVISED MAY 2010
Synchronous Buck NexFET™ Power Block
1
FEATURES
DESCRIPTION
2
•
•
•
•
•
•
•
•
•
•
•
Half-Bridge Power Block
90% system Efficiency at 25A
Up To 40A Operation
The CSD86350Q5D NexFET™ power block is an
optimized design for synchronous buck applications
offering high current, high efficiency, and high
frequency capability in a small 5-mm × 6-mm outline.
Optimized for 5V gate drive applications, this product
offers a flexible solution capable of offering a high
density power supply when paired with any 5V gate
drive from an external controller/driver.
High Frequency Operation (Up To 1.5MHz)
High Density – SON 5-mm × 6-mm Footprint
Optimized for 5V Gate Drive
Low Switching Losses
Ultra Low Inductance Package
RoHS Compliant
TEXT ADDED FOR SPACING
Top View
Halogen Free
VIN
VIN
TG
VSW
VSW
VSW
1
2
3
4
8
7
6
5
Pb-Free Terminal Plating
PGND
(Pin 9)
APPLICATIONS
•
Synchronous Buck Converters
TGR
BG
–
–
High Frequency Applications
High Current, Low Duty Cycle Applications
P0116-01
TEXT ADDED FOR SPACING
ORDERING INFORMATION
•
•
•
Multiphase Synchronous Buck Converters
POL DC-DC Converters
Device
Package
Media
Qty
Ship
IMVP, VRM, and VRD Applications
SON 5-mm × 6-mm
Plastic Package
13-Inch
Reel
Tape and
Reel
CSD86350Q5D
2500
TEXT ADDED FOR SPACING
TEXT ADDED FOR SPACING
TEXT ADDED FOR SPACING
TYPICAL POWER BLOCK EFFICIENCY
and POWER LOSS
TYPICAL CIRCUIT
CSD86350Q5D
Driver IC
100
90
80
70
60
50
40
6
5
4
3
2
1
VDD
VI
VIN
VDD
BST
DRVH
LL
Control
FET
TG
ENABLE
PWM
ENABLE
PWM
VGS = 5V
VIN = 12V
VOUT = 1.3V
LOUT = 0.3ꢀH
fSW = 500kHz
TA = 25°C
VO
TGR
VSW
Sync
FET
BG
GND
DRVL
PGND
S0474-01
0
0
5
10
15
20
25
Output Current (A)
G029
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
NexFET is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2010, Texas Instruments Incorporated
CSD86350Q5D
SLPS223A –MAY 2010–REVISED MAY 2010
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ABSOLUTE MAXIMUM RATINGS
(1)
TA = 25°C (unless otherwise noted)
Parameter
Conditions
VALUE
-0.8 to 25
-8 to 10
-8 to 10
120
UNIT
V
VIN to PGND
TG to TGR
Voltage range
V
BG to PGND
V
Pulsed Current Rating, IDM
Power Dissipation, PD
A
13
W
Sync FET, ID = 100A, L = 0.1mH
Control FET, ID = 58A, L = 0.1mH
500
Avalanche Energy EAS
mJ
°C
168
Operating Junction and Storage Temperature Range, TJ, TSTG
-55 to 150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
TA = 25° (unless otherwise noted)
Parameter
Gate Drive Voltage, VGS
Conditions
MIN
MAX
8
UNIT
V
4.5
Input Supply Voltage, VIN
Switching Frequency, fSW
Operating Current
22
V
CBST = 0.1mF (min)
200
1500
40
kHz
A
Operating Temperature, TJ
125
°C
POWER BLOCK PERFORMANCE
TA = 25° (unless otherwise noted)
Parameter
Conditions
VIN = 12V, VGS = 5V,
MIN
TYP
MAX
UNIT
VOUT = 1.3V, IOUT = 25A,
fSW = 500kHz,
LOUT = 0.3µH, TJ = 25ºC
(1)
Power Loss, PLOSS
2.8
10
W
TG to TGR = 0V
BG to PGND = 0V
VIN Quiescent Current, IQVIN
µA
(1) Measurement made with six 10µF (TDK C3216X5R1C106KT or equivalent) ceramic capacitors placed across VIN to PGND pins and
using a high current 5V driver IC.
THERMAL INFORMATION
TA = 25°C (unless otherwise stated)
THERMAL METRIC
MIN
TYP
MAX UNIT
(1)(2)
Junction to ambient thermal resistance (Min Cu)
102
RqJA
(1)(2)
Junction to ambient thermal resistance (Max Cu)
50
°C/W
20
(2)
Junction to case thermal resistance (Top of package)
RqJC
(2)
Junction to case thermal resistance (PGND Pin)
2
(1) Device mounted on FR4 material with 1-inch2 (6.45-cm2) Cu.
(2)
R
qJC is determined with the device mounted on a 1-inch2 (6.45-cm2), 2 oz. (0.071-mm thick) Cu pad on a 1.5-inch × 1.5-inch
(3.81-cm × 3.81-cm), 0.06-inch (1.52-mm) thick FR4 board. RqJC is specified by design while RqJA is determined by the user’s board
design.
2
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Copyright © 2010, Texas Instruments Incorporated
CSD86350Q5D
www.ti.com
SLPS223A –MAY 2010–REVISED MAY 2010
ELECTRICAL CHARACTERISTICS
TA = 25°C (unless otherwise stated)
Q1 Control FET
Q2 Sync FET
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX UNIT
Static Characteristics
BVDSS
IDSS
Drain to Source Voltage
VGS = 0V, IDS = 250mA
25
25
V
Drain to Source Leakage
Current
VGS = 0V, VDS = 20V
1
100
2.1
1
100
1.6
mA
nA
V
Gate to Source Leakage
Current
IGSS
VDS = 0V, VGS = +10 / -8
Gate to Source Threshold
Voltage
VGS(th)
VDS = VGS, IDS = 250mA
0.9
1.4
0.9
1.1
VGS = 4.5V, IDS = 20A
VGS = 8V, IDS = 20A
VDS = 10V, IDS = 20A
5
4.5
6.6
6
2
1.8
2.7
2.5
mΩ
mΩ
S
Drain to Source On
Resistance
RDS(on)
gfs
Transconductance
103
132
Dynamic Characteristics
(1)
CISS
Input Capacitance
Output Capacitance
1440
645
1870
840
3080
1550
4000
2015
pF
pF
(1)
COSS
VGS = 0V, VDS = 12.5V,
f = 1MHz
Reverse Transfer
CRSS
RG
22
1.4
8.2
29
2.8
45
1.4
59
2.8
25
pF
Ω
(1)
Capacitance
(1)
Series Gate Resistance
Gate Charge Total (4.5V)
Qg
10.7
19.4
nC
(1)
Gate Charge - Gate to
Drain
Qgd
Qgs
1
2.5
5.1
nC
nC
VDS = 12.5V,
IDS = 20A
Gate Charge - Gate to
Source
3.2
Qg(th)
QOSS
td(on)
tr
Gate Charge at Vth
Output Charge
Turn On Delay Time
Rise Time
1.9
9.9
8
2.8
28
9
nC
nC
ns
ns
ns
ns
VDS = 12V, VGS = 0V
21
9
23
24
21
VDS = 12.5V, VGS = 4.5V,
IDS = 20A, RG = 2Ω
td(off)
tf
Turn Off Delay Time
Fall Time
2.3
Diode Characteristics
VSD
Qrr
trr
Diode Forward Voltage
IDS = 20A, VGS = 0V
0.85
16
1
0.77
40
1
V
Reverse Recovery Charge
Reverse Recovery Time
nC
ns
Vdd = 12V, IF = 20A,
di/dt = 300A/ms
22
32
(1) Specified by design
HD
LD
HD
LD
Max RqJA = 50°C/W
when mounted on
1 inch2 (6.45 cm2) of
2-oz. (0.071-mm thick)
Cu.
Max RqJA = 102°C/W
when mounted on
minimum pad area of
2-oz. (0.071-mm thick)
Cu.
LG HS
HG
LG HS
LS
HG
LS
M0189-01
M0190-01
Copyright © 2010, Texas Instruments Incorporated
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CSD86350Q5D
SLPS223A –MAY 2010–REVISED MAY 2010
www.ti.com
TYPICAL POWER BLOCK DEVICE CHARACTERISTICS
TJ = 125°C, unless stated otherwise.
10
9
8
7
6
5
4
3
2
1
0
1.2
VIN = 12V
VGS = 5V
VOUT = 1.3V
fSW = 500kHz
LOUT = 0.3ꢀH
VIN = 12V
VGS = 5V
VOUT = 1.3V
fSW = 500kHz
LOUT = 0.3ꢁH
1.1
1
0.9
0.8
0.7
0.6
0.5
0
5
10
15
20
25
30
35
40
ꢀ50
ꢀ25
0
25
50
75
100
125
150
Output Current (A)
Junction Temperature (°C)
G001
G002
Figure 1. Power Loss vs Output Current
Figure 2. Power Loss vs Temperature
50
45
40
35
30
25
20
15
10
5
50
45
40
35
30
25
20
15
10
5
400LFM
400LFM
VIN = 12V
VGS = 5V
VOUT = 1.3V
fSW = 500kHz
LOUT = 0.3ꢀH
VIN = 12V
VGS = 5V
VOUT = 1.3V
fSW = 500kHz
LOUT = 0.3ꢀH
200LFM
100LFM
Nat Conv
200LFM
100LFM
Nat Conv
0
0
0
10
20
30
40
50
60
70
80
90
0
10
20
30
40
50
60
70
80
90
Ambient Temperature (°C)
Ambient Temperature (°C)
G003
G004
Figure 3. Safe Operating Area – PCB Vertical Mount(1)
Figure 4. Safe Operating Area – PCB Horizontal Mount(1)
50
45
40
35
30
25
20
VIN = 12V
VGS = 5V
VOUT = 1.3V
fSW = 500kHz
LOUT = 0.3ꢀH
15
10
5
0
0
20
40
60
80
100
120
140
Board Temperature (°C)
G005
Figure 5. Typical Safe Operating Area(1)
(1) The Typical Power Block System Characteristic curves are based on measurements made on a PCB design with
dimensions of 4.0” (W) × 3.5” (L) x 0.062” (H) and 6 copper layers of 1 oz. copper thickness. See Application Section
for detailed explanation.
4
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Copyright © 2010, Texas Instruments Incorporated
CSD86350Q5D
www.ti.com
SLPS223A –MAY 2010–REVISED MAY 2010
TYPICAL POWER BLOCK DEVICE CHARACTERISTICS (continued)
TJ = 125°C, unless stated otherwise.
TEXT ADDED FOR SPACING
TEXT ADDED FOR SPACING
1.6
1.5
1.4
1.3
1.2
1.1
1
15.7
13.1
10.5
7.9
1.6
1.5
1.4
1.3
1.2
1.1
1
15.7
VGS = 5V
VGS = 5V
VOUT = 1.3V
13.1
VIN = 12V
VOUT = 1.3V
LOUT = 0.3µH
IO = 40A
LOUT = 0.3µH
fSW = 500kHz
IO = 40A
10.5
7.9
5.3
5.3
2.7
2.7
0.1
0.1
0.9
0.8
0.7
0.6
-2.5
-5.1
-7.7
-10.3
0.9
0.8
0.7
0.6
-2.5
-5.1
-7.7
-10.3
200
400
600
800
1000
1200
1400
1600
3
5
7
9
11
13
15
17
19
21
23
Switching Frequency (kHz)
Input Voltage (V)
G006
G007
Figure 6. Normalized Power Loss vs Switching Frequency
TEXT ADDED FOR SPACING
Figure 7. Normalized Power Loss vs Input Voltage
TEXT ADDED FOR SPACING
1.8
20.8
18.2
15.6
13
1.6
1.5
1.4
1.3
1.2
1.1
1
15.7
VGS = 5V
VIN = 12V
VGS = 5V
VIN = 12V
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1
13.1
VOUT = 1.3V
10.5
LOUT = 0.3µH
fSW = 500kHz
IO = 40A
fSW = 500kHz
IO = 40A
7.9
10.4
7.8
5.3
2.7
5.2
0.1
2.6
0.9
0.8
0.7
0.6
-2.5
-5.1
-7.7
-10.3
0
0.9
0.8
-2.6
-5.2
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
1
1.1
Output Inductance (µH)
Output Voltage (V)
G008
G009
Figure 8. Normalized Power Loss vs. Output Voltage
Figure 9. Normalized Power Loss vs. Output Inductance
Copyright © 2010, Texas Instruments Incorporated
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SLPS223A –MAY 2010–REVISED MAY 2010
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TYPICAL POWER BLOCK MOSFET CHARACTERISTICS
TA = 25°C, unless stated otherwise.
TEXT ADDED FOR SPACING
TEXT ADDED FOR SPACING
80
70
60
50
40
30
20
10
0
80
70
60
50
40
30
20
10
0
VGS = 8V
VGS = 8V
VGS = 4.5V
VGS = 4.5V
VGS = 4V
VGS = 4V
0
0.2
0.4
0.6
0.8
1
0
0.1
0.2
0.3
0.4
0.5
VDS - Drain-to-Source Voltage - V
VDS - Drain-to-Source Voltage - V
G010
G011
Figure 10. Control MOSFET Saturation
TEXT ADDED FOR SPACING
Figure 11. Sync MOSFET Saturation
TEXT ADDED FOR SPACING
100
10
100
10
VDS = 5V
VDS = 5V
TC = 125°C
TC = 25°C
1
1
TC = 125°C
0.1
0.1
TC = 25°C
TC = -55°C
0.01
0.001
0.0001
0.01
0.001
0.0001
TC = -55°C
0
0.5
1
1.5
2
2.5
3
3.5
4
0
0.5
1
1.5
2
2.5
VGS - Gate-to-Source Voltage - V
VGS - Gate-to-Source Voltage - V
G012
G013
Figure 12. Control MOSFET Transfer
TEXT ADDED FOR SPACING
Figure 13. Sync MOSFET Transfer
TEXT ADDED FOR SPACING
8
7
6
5
4
3
2
1
8
7
6
5
4
3
2
1
ID = 20A
VDS = 12.5V
ID = 20A
VDS = 12.5V
0
0
0
0
2
4
6
8
10
12
14
5
10
15
20
25
30
Qg - Gate Charge - nC
Qg - Gate Charge - nC
G014
G015
Figure 14. Control MOSFET Gate Charge
Figure 15. Sync MOSFET Gate Charge
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Copyright © 2010, Texas Instruments Incorporated
CSD86350Q5D
www.ti.com
SLPS223A –MAY 2010–REVISED MAY 2010
TYPICAL POWER BLOCK MOSFET CHARACTERISTICS (continued)
TA = 25°C, unless stated otherwise.
TEXT ADDED FOR SPACING
TEXT ADDED FOR SPACING
10
10
1
f = 1MHz
VGS = 0V
Ciss = Cgd + Cgs
1
Coss = Cds + Cgd
Ciss = Cgd + Cgs
Coss = Cds + Cgd
Crss = Cgd
0.1
0.01
0.1
0.01
Crss = Cgd
f = 1MHz
VGS = 0V
0
5
10
15
20
25
0
5
10
15
20
25
VDS - Drain-to-Source Voltage - V
VDS - Drain-to-Source Voltage - V
G016
G017
Figure 16. Control MOSFET Capacitance
TEXT ADDED FOR SPACING
ID = 250µA
Figure 17. Sync MOSFET Capacitance
TEXT ADDED FOR SPACING
1.8
1.6
1.4
1.2
1
1.8
1.6
1.4
1.2
1
ID = 250µA
0.8
0.6
0.4
0.2
0
0.8
0.6
0.4
0.2
0
-75
-25
25
75
125
175
-75
-25
25
75
125
175
TC - Case Temperature - °C
TC - Case Temperature - °C
G018
G019
Figure 18. Control MOSFET VGS(th)
TEXT ADDED FOR SPACING
Figure 19. Sync MOSFET VGS(th)
TEXT ADDED FOR SPACING
12
12
ID = 20A
ID = 20A
10
8
10
8
TC = 125°C
6
6
TC = 125°C
4
4
TC = 25°C
2
2
TC = 25°C
0
0
0
1
2
3
4
5
6
7
8
9
10
0
1
2
3
4
5
6
7
8
9
10
VGS - Gate-to-Source Voltage - V
VGS - Gate-to-Source Voltage - V
G020
G021
Figure 20. Control MOSFET RDS(on) vs VGS
Figure 21. Sync MOSFET RDS(on) vs VGS
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TYPICAL POWER BLOCK MOSFET CHARACTERISTICS (continued)
TA = 25°C, unless stated otherwise.
TEXT ADDED FOR SPACING
TEXT ADDED FOR SPACING
1.6
1.4
1.2
1
1.6
1.4
1.2
1
ID = 20A
VGS = 8V
ID = 20A
VGS = 8V
0.8
0.6
0.4
0.2
0
0.8
0.6
0.4
0.2
0
-75
-25
25
75
125
175
-75
-25
25
75
125
175
TC - Case Temperature - °C
TC - Case Temperature - °C
G022
G023
Figure 22. Control MOSFET Normalized RDS(on)
TEXT ADDED FOR SPACING
Figure 23. Sync MOSFET Normalized RDS(on)
TEXT ADDED FOR SPACING
100
100
10
1
10
1
TC = 125°C
TC = 125°C
0.1
0.1
TC = 25°C
TC = 25°C
0.01
0.001
0.0001
0.01
0.001
0.0001
0
0.2
0.4
0.6
0.8
1
1.2
0
0.2
0.4
0.6
0.8
1
1.2
VSD - Source-to-Drain Voltage - V
VSD - Source-to-Drain Voltage - V
G024
G025
Figure 24. Control MOSFET Body Diode
TEXT ADDED FOR SPACING
I(AV) = t(AV) ÷ (0.021 × L)
Figure 25. Sync MOSFET Body Diode
TEXT ADDED FOR SPACING
I(AV) = t(AV) ÷ (0.021 × L)
1k
100
10
1k
100
10
TC = 25°C
TC = 25°C
TC = 125°C
TC = 125°C
1
1
0.01
0.1
1
10
0.01
0.1
1
10
t(AV) - Time in Avalanche - ms
t(AV) - Time in Avalanche - ms
G026
G027
Figure 26. Control MOSFET Unclamped Inductive
Switching
Figure 27. Sync MOSFET Unclamped Inductive Switching
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CSD86350Q5D
www.ti.com
SLPS223A –MAY 2010–REVISED MAY 2010
APPLICATION INFORMATION
The CSD86350Q5D NexFET™ power block is an optimized design for synchronous buck applications using 5V
gate drive. The Control FET and Sync FET silicon are parametrically tuned to yield the lowest power loss and
highest system efficiency. As a result, a new rating method is needed which is tailored towards a more systems
centric environment. System level performance curves such as Power Loss, Safe Operating Area, and
normalized graphs allow engineers to predict the product performance in the actual application.
Power Loss Curves
MOSFET centric parameters such as RDS(ON) and Qgd are needed to estimate the loss generated by the devices.
In an effort to simplify the design process for engineers, Texas Instruments has provided measured power loss
performance curves. Figure 1 plots the power loss of the CSD86350Q5D as a function of load current. This curve
is measured by configuring and running the CSD86350Q5D as it would be in the final application (see
Figure 28).The measured power loss is the CSD86350Q5D loss and consists of both input conversion loss and
gate drive loss. Equation 1 is used to generate the power loss curve.
(VIN x IIN) + (VDD x IDD) – (VSW_AVG x IOUT) = Power Loss
(1)
The power loss curve in Figure 1 is measured at the maximum recommended junction temperatures of 125°C
under isothermal test conditions.
Safe Operating Curves (SOA)
The SOA curves in the CSD86350Q5D data sheet provides guidance on the temperature boundaries within an
operating system by incorporating the thermal resistance and system power loss. Figure 3 to Figure 5 outline the
temperature and airflow conditions required for a given load current. The area under the curve dictates the safe
operating area. All the curves are based on measurements made on a PCB design with dimensions of 4” (W) x
3.5” (L) x 0.062” (T) and 6 copper layers of 1 oz. copper thicknes
Normalized Curves
The normalized curves in the CSD86350Q5D data sheet provides guidance on the Power Loss and SOA
adjustments based on their application specific needs. These curves show how the power loss and SOA
boundaries will adjust for a given set of systems conditions. The primary Y-axis is the normalized change in
power loss and the secondary Y-axis is the change is system temperature required in order to comply with the
SOA curve. The change in power loss is a multiplier for the Power Loss curve and the change in temperature is
subtracted from the SOA curve.
Input Current (IIN
)
Gate Drive
Current (IDD
)
VI
CSD86350Q5D
Driver IC
VDD
A
VIN
VDD
A
BST
DRVH
LL
V
Input Voltage (VIN)
Control
FET
TG
Gate Drive
Voltage (VDD
V
ENABLE
PWM
Output Current (IOUT
)
)
VO
TGR
VSW
A
Sync
FET
PWM
BG
GND
DRVL
PGND
Averaged Switched
Node Voltage
Averaging
Circuit
V
(VSW_AVG
)
S0475-01
Figure 28. Typical Application
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CSD86350Q5D
SLPS223A –MAY 2010–REVISED MAY 2010
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Calculating Power Loss and SOA
The user can estimate product loss and SOA boundaries by arithmetic means (see Design Example). Though
the Power Loss and SOA curves in this data sheet are taken for a specific set of test conditions, the following
procedure will outline the steps the user should take to predict product performance for any set of system
conditions.
Design Example
Operating Conditions:
•
•
•
•
•
Output Current = 25A
Input Voltage = 7V
Output Voltage = 1V
Switching Frequency = 800kHz
Inductor = 0.2µH
Calculating Power Loss
•
•
•
•
•
•
Power Loss at 25A = 3.5W (Figure 1)
Normalized Power Loss for input voltage ≈ 1.07 (Figure 7)
Normalized Power Loss for output voltage ≈ 0.95 (Figure 8)
Normalized Power Loss for switching frequency ≈ 1.11 (Figure 6)
Normalized Power Loss for output inductor ≈ 1.07 (Figure 9)
Final calculated Power Loss = 3.5W x 1.07 x 0.95 x 1.11 x 1.07 ≈ 4.23W
Calculating SOA Adjustments
•
•
•
•
•
SOA adjustment for input voltage ≈ 2ºC (Figure 7)
SOA adjustment for output voltage ≈ -1.3ºC (Figure 8)
SOA adjustment for switching frequency ≈ 2.8ºC (Figure 6)
SOA adjustment for output inductor ≈ 1.6ºC (Figure 9)
Final calculated SOA adjustment = 2 + (-1.3) + 2.8 + 1.6 ≈ 5.1ºC
In the design example above, the estimated power loss of the CSD86350Q5D would increase to 4.23W. In
addition, the maximum allowable board and/or ambient temperature would have to decrease by 5.1ºC. Figure 29
graphically shows how the SOA curve would be adjusted accordingly.
1. Start by drawing a horizontal line from the application current to the SOA curve.
2. Draw a vertical line from the SOA curve intercept down to the board/ambient temperature.
3. Adjust the SOA board/ambient temperature by subtracting the temperature adjustment value.
In the design example, the SOA temperature adjustment yields a reduction in allowable board/ambient
temperature of 5.1ºC. In the event the adjustment value is a negative number, subtracting the negative number
would yield an increase in allowable board/ambient temperature.
50
45
40
35
30
1
25
20
VIN = 12V
VGS = 5V
VOUT = 1.3V
fSW = 500kHz
LOUT = 0.3 µH
2
15
10
5
3
0
0
20
40
60
80
100
120
140
Board Temperature (°C)
G028
Figure 29. Power Block SOA
10
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CSD86350Q5D
www.ti.com
SLPS223A –MAY 2010–REVISED MAY 2010
RECOMMENDED PCB DESIGN OVERIEW
There are two key system-level parameters that can be addressed with a proper PCB design: Electrical and
Thermal performance. Properly optimizing the PCB layout will yield maximum performance in both areas. A brief
description on how to address each parameter is provided.
Electrical Performance
The Power Block has the ability to switch voltages at rates greater than 10kV/µs. Special care must be then
taken with the PCB layout design and placement of the input capacitors, Driver IC, and output inductor.
•
The placement of the input capacitors relative to the Power Block’s VIN and PGND pins should have the
highest priority during the component placement routine. It is critical to minimize these node lengths. As such,
ceramic input capacitors need to be placed as close as possible to the VIN and PGND pins (see Figure 30).
The example in Figure 30 uses 6x10µF ceramic capacitors (TDK Part # C3216X5R1C106KT or equivalent).
Notice there are ceramic capacitors on both sides of the board with an appropriate amount of vias
interconnecting both layers. In terms of priority of placement next to the Power Block, C5, C7, C19, and C8
should follow in order.
•
•
The Driver IC should be placed relatively close to the Power Block Gate pins. TG and BG should connect to
the outputs of the Driver IC. The TGR pin serves as the return path of the high-side gate drive circuitry and
should be connected to the Phase pin of the IC (sometimes called LX, LL, SW, PH, etc.). The bootstrap
capacitor for the Driver IC will also connect to this pin.
The switching node of the output inductor should be placed relatively close to the Power Block VSW pins.
Minimizing the node length between these two components will reduce the PCB conduction losses and
actually reduce the switching noise level.(1)
Thermal Performance
The Power Block has the ability to utilize the GND planes as the primary thermal path. As such, the use of
thermal vias is an effective way to pull away heat from the device and into the system board. Concerns of solder
voids and manufacturability problems can be addressed by the use of three basic tactics to minimize the amount
of solder attach that will wick down the via barrel:
•
•
Intentionally space out the vias from each other to avoid a cluster of holes in a given area.
Use the smallest drill size allowed in your design. The example in Figure 30 uses vias with a 10 mil drill hole
and a 16 mil capture pad.
•
Tent the opposite side of the via with solder-mask.
In the end, the number and drill size of the thermal vias should align with the end user’s PCB design rules and
manufacturing capabilities.
K001
Figure 30. Recommended PCB Layout (Top Down View)
(1) Keong W. Kam, David Pommerenke, “EMI Analysis Methods for Synchronous Buck Converter EMI Root Cause Analysis”, University of
Missouri – Rolla
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CSD86350Q5D
SLPS223A –MAY 2010–REVISED MAY 2010
www.ti.com
MECHANICAL DATA
Q5D Package Dimensions
E2
d2
K
L
E1
c1
L
d1
q
9
f
Top View
Side View
Bottom View
Pinout
Exposed Tie Bar May Vary
Position
Pin 1
Pin 2
Pin 3
Pin 4
Pin 5
Pin 6
Pin 7
Pin 8
Pin 9
Designation
VIN
q
VIN
TG
TGR
BG
VSW
VSW
VSW
PGND
E1
Front View
M0187-01
MILLIMETERS
MIN
INCHES
DIM
MAX
MIN
MAX
a
b
1.40
1.55
0.055
0.014
0.006
0.006
0.064
0.011
0.008
0.012
0.193
0.168
0.193
0.232
0.122
0.061
0.018
0.010
0.010
0.068
0.015
0.012
0.015
0.201
0.172
0.201
0.240
0.126
0.360
0.460
0.250
0.250
1.730
0.380
0.300
0.391
5.100
4.369
5.100
6.100
3.206
c
0.150
c1
d
0.150
1.630
d1
d2
d3
D1
D2
E
0.280
0.200
0.291
4.900
4.269
4.900
E1
E2
e
5.900
3.106
1.27 TYP
0.396
0.050
0.032
f
0.496
0.710
--
0.016
0.020
--
0.020
0.028
--
L
0.510
q
0.00
K
0.812
12
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CSD86350Q5D
www.ti.com
SLPS223A –MAY 2010–REVISED MAY 2010
Land Pattern Recommendation
3.480
0.415
0.530
0.345
0.650
0.650
0.620
4.460
0.620
4.460
1.270
1.920
0.850
0.400
0.850
6.240
M0188-01
NOTE: All dimensions are in mm, unless otherwise specified.
For recommended circuit layout for PCB designs, see application note SLPA005 – Reducing Ringing Through
PCB Layout Techniques.
Q5D Tape and Reel Information
K0
4.00 0.10 ꢀ(SS ꢁNoS 1ꢂ
0.30 0.05
2.00 0.05
+0.10
–0.00
Ø 1.50
B0
R 0.20 MAX
A0
8.00 0.10
Ø 1.50 MIꢁ
R 0.30 TYP
A0 = 5.30 0.10
B0 = 6.50 0.10
K0 = 1.90 0.10
M0191-01
NOTES: 1. 10-sprocket hole-pitch cumulative tolerance ±0.2
2. Camber not to exceed 1mm in 100mm, noncumulative over 250mm
3. Material: black static-dissipative polystyrene
4. All dimensions are in mm, unless otherwise specified.
5. Thickness: 0.30 ±0.05mm
6. MSL1 260°C (IR and convection) PbF reflow compatible
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CSD86350Q5D
SLPS223A –MAY 2010–REVISED MAY 2010
www.ti.com
REVISION HISTORY
Changes from Original (May 2010) to Revision A
Page
•
•
Changed graph title From: TYPICAL EFFICIENCY vs POWER LOSS To: TYPICAL POWER BLOCK EFFICIENCY
and POWER LOSS ............................................................................................................................................................... 1
Updated the Land Pattern Recommendation illustration .................................................................................................... 13
14
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