CSD87312Q3E [TI]
Dual 30-V N-Channel NexFET Power MOSFETs; 双30 -V N通道NexFET功率MOSFET
| 型号： | CSD87312Q3E |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Dual 30-V N-Channel NexFET Power MOSFETs |
| 文件： | 总12页 (文件大小：789K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CSD87312Q3E
www.ti.com
SLPS333 –NOVEMBER 2012
Dual 30-V N-Channel NexFET™ Power MOSFETs
.
1
FEATURES
PRODUCT SUMMARY
•
•
•
Common Source Connection
TA = 25°C
VDS
TYPICAL VALUE
UNIT
V
Ultra Low Drain to Drain On-Resistance
Drain to Source Voltage
Gate Charge Total (4.5V)
Gate Charge Gate to Drain
30
6.3
0.7
Space Saving SON 3.3 x 3.3mm Plastic
Package
Qg
nC
nC
mΩ
mΩ
V
Qgd
VGS = 4.5V
VGS = 8V
31
27
•
•
•
•
•
•
Optimized for 5V Gate Drive
Low Thermal Resistance
Avalanche Rated
Drain to Drain On Resistance
(Q1+Q2)
RDD(on)
VGS(th)
Threshold Voltage
1.0
Pb Free Terminal Plating
RoHS Compliant
ORDERING INFORMATION
Device
Package
Media
Qty
Ship
Halogen Free
SON 3.3 x 3.3mm
Plastic Package
13-Inch
Reel
Tape and
Reel
CSD87312Q3E
2500
APPLICATIONS
ABSOLUTE MAXIMUM RATINGS
•
Adaptor/USB Input Protection for Notebook
PCs and Tablets
TA = 25°C
VALUE
UNIT
V
VDS
VGS
ID
Drain to Source Voltage
30
+10/-8
27
Gate to Source Voltage
V
DESCRIPTION
Continuous Drain Current, TC = 25°C(1)
Pulsed Drain Current (2)
A
The CSD87312Q3E is a 30V common-source, dual
N-channel device designed for adaptor/USB input
protection. This SON 3.3 x 3.3mm device has low
drain to drain on-resistance that minimizes losses and
offers low component count for space constrained
multi-cell battery charging applications.
IDM
PD
45
A
Power Dissipation
2.5
W
TJ,
Operating Junction and Storage
TSTG Temperature Range
–55 to 150
29
°C
Avalanche Energy, single pulse
ID = 24A, L = 0.1mH, RG = 25Ω
EAS
mJ
(1) Typical R =63°C/W on 1in² (2 oz.) on 0.060" thick FR4PCB
TEXT ADDED FOR SPACING
Top View
(2) Pulse duration ≤300μs, duty cycle ≤2%
TEXT ADDED FOR SPACING
VGS vs. RDDon
D1
D2
D2
D2
G
D1
D1
D1
S
60
TC = 25°C Id = 7A
TC = 125ºC Id = 7A
55
50
45
40
35
30
25
20
TEXT ADDED FOR SPACING
Circuit Image
0
2
4
6
8
10
VGS - Gate-to- Source Voltage (V)
G001
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2012, Texas Instruments Incorporated
CSD87312Q3E
SLPS333 –NOVEMBER 2012
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ELECTRICAL CHARACTERISTICS
(TA = 25°C unless otherwise stated)
PARAMETER
Static Characteristics
TEST CONDITIONS
MIN
TYP
MAX UNIT
BVDSS
IDSS
Drain to Source Voltage
VGS = 0V, ID = 250μA
30
V
Drain to Source Leakage Current
Gate to Source Leakage Current
Gate to Source Threshold Voltage
VGS = 0V, VDS = 24V
VDS = 0V, VGS = +10/-8V
VDS = VGS, ID = 250μA
VGS = 4.5V, ID = 7A
VGS = 8V, ID = 7A
1
100
1.3
38
μA
nA
V
IGSS
VGS(th)
0.8
1.0
31
27
39
mΩ
mΩ
S
Drain to Drain On Resistance (Q1 +
Q2)
RDD(on)
33
gfs
Transconductance
VDS = 15V, ID = 7A
Dynamic Characteristics(1)
Ciss
Coss
Crss
RG
Input Capacitance
960
190
12
1250
247
16
pF
pF
pF
Ω
Output Capacitance
Reverse Transfer Capacitance
Series Gate Resistance
Gate Charge Total (4.5V)
Gate Charge Gate to Drain
Gate Charge Gate to Source
Gate Charge at Vth
Output Charge
VGS = 0V, VDS = 15V, f = 1MHz
5
10
Qg
6.3
0.7
1.9
1.0
4.0
7.8
16
8.2
nC
nC
nC
nC
nC
ns
ns
ns
ns
Qgd
Qgs
Qg(th)
Qoss
td(on)
tr
VDS = 15V, ID = 7A
VDS = 15V, VGS = 0V
Turn On Delay Time
Rise Time
VDS = 15V, VGS = 4.5V, IDS = 7A, RG = 2Ω
td(off)
tf
Turn Off Delay Time
Fall Time
17
2.9
Diode Characteristics(1)
VSD
Qrr
trr
Diode Forward Voltage
ISD = 7A, VGS = 0V
0.8
5.3
1
V
Reverse Recovery Charge
Reverse Recovery Time
nC
ns
VDS= 15V, IF = 7A, di/dt = 300A/μs
12.2
(1) All Dynamic and Diode Characteristics were measured with respect to one of the two drains, with the other left floating.
THERMAL CHARACTERISTICS
(TA = 25°C unless otherwise stated)
PARAMETER
Thermal Resistance Junction to Case(1)
Thermal Resistance Junction to Ambient(1)(2)
MIN
TYP
MAX
UNIT
°C/W
°C/W
RθJC
RθJA
4.2
63
(1)
R
θJC is determined with the device mounted on a 1-inch2 (6.45-cm2), 2-oz. (0.071-mm thick) Cu pad on a 1.5-inch × 1.5-inch (3.81-cm ×
3.81-cm), 0.06-inch (1.52-mm) thick FR4 PCB. RθJC is specified by design, whereas RθJA is determined by the user’s board design.
(2) Device mounted on FR4 material with 1-inch2 (6.45-cm2), 2-oz. (0.071-mm thick) Cu.
2
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Copyright © 2012, Texas Instruments Incorporated
CSD87312Q3E
www.ti.com
SLPS333 –NOVEMBER 2012
GATE
DRAIN
GATE
DRAIN
Max RθJA = 63°C/W
when mounted on
1 inch2 (6.45 cm2) of 2-
oz. (0.071-mm thick)
Cu.
Max RθJA = 165°C/W
when mounted on a
minimum pad area of
2-oz. (0.071-mm thick)
Cu.
SOURCE
SOURCE
M0137-02
M0137-01
TYPICAL MOSFET CHARACTERISTICS
(TA = 25°C unless otherwise stated)
Figure 1. Transient Thermal Impedance
TEXT ADDED FOR SPACING
TEXT ADDED FOR SPACING
100
60
40
20
0
VDS = 5V
80
60
40
20
0
VGS =8V
VGS =6V
VGS =4.5V
TC = 125°C
TC = 25°C
TC = −55°C
0
1
2
3
4
5
0
1
2
3
4
5
VDS - Drain-to-Source Voltage (V)
VGS - Gate-to-Source Voltage (V)
G001
G001
Figure 2. Saturation Characteristics
Figure 3. Transfer Characteristics
Copyright © 2012, Texas Instruments Incorporated
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3
CSD87312Q3E
SLPS333 –NOVEMBER 2012
www.ti.com
TYPICAL MOSFET CHARACTERISTICS (continued)
(TA = 25°C unless otherwise stated)
TEXT ADDED FOR SPACING
TEXT ADDED FOR SPACING
10
8
10000
1000
100
10
ID = 7A
VDS =15V
6
4
Ciss = Cgd + Cgs
Coss = Cds + Cgd
Crss = Cgd
2
0
1
0
2
4
6
8
10
12
14
0
3
6
9
12
15
18
21
24
27
30
Qg - Gate Charge (nC)
VDS - Drain-to-Source Voltage (V)
G001
G001
Figure 4. Gate Charge
Figure 5. Capacitance
TEXT ADDED FOR SPACING
TEXT ADDED FOR SPACING
1.5
1.25
1
60
55
50
45
40
35
30
25
20
ID = 250uA
TC = 25°C Id = 7A
TC = 125ºC Id = 7A
0.75
0.5
0.25
0
−75
−25
25
75
125
175
0
2
4
6
8
10
TC - Case Temperature (ºC)
VGS - Gate-to- Source Voltage (V)
G001
G001
Figure 6. Threshold Voltage vs. Temperature
TEXT ADDED FOR SPACING
Figure 7. On-State Resistance vs. Gate-to-Source Voltage
TEXT ADDED FOR SPACING
2
1.75
1.5
100
VGS = 4.5V
VGS = 8V
ID =7A
TC = 25°C
TC = 125°C
10
1
0.1
1.25
1
0.01
0.75
0.5
0.001
0.0001
0.25
−75
−25
25
75
125
175
0
0.2
0.4
0.6
0.8
1
TC - Case Temperature (ºC)
VSD − Source-to-Drain Voltage (V)
G001
G001
Figure 8. Normalized On-State Resistance vs. Temperature
Figure 9. Typical Diode Forward Voltage
4
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Copyright © 2012, Texas Instruments Incorporated
CSD87312Q3E
www.ti.com
SLPS333 –NOVEMBER 2012
TYPICAL MOSFET CHARACTERISTICS (continued)
(TA = 25°C unless otherwise stated)
TEXT ADDED FOR SPACING
TEXT ADDED FOR SPACING
1000
100
10
100
10
1
TC = 25ºC
TC = 125ºC
1ms
10ms
100ms
1s
DC
1
0.1
0.01
Single Pulse
TypicalRthetaJA =130ºC/W(min Cu)
0.01
0.1
1
10
50
0.01
0.1
1
VDS - Drain-to-Source Voltage (V)
TAV - Time in Avalanche (mS)
G001
G001
Figure 10. Maximum Safe Operating Area
Figure 11. Single Pulse Unclamped Inductive Switching
TEXT ADDED FOR SPACING
40.0
35.0
30.0
25.0
20.0
15.0
10.0
5.0
0.0
−50 −25
0
25
50
75
100 125 150 175
TC - Case Temperature (ºC)
G001
Figure 12. Maximum Drain Current vs. Temperature
Copyright © 2012, Texas Instruments Incorporated
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5
CSD87312Q3E
SLPS333 –NOVEMBER 2012
www.ti.com
MECHANICAL DATA
Q3E Package Dimensions
MILLIMETERS
DIM
MIN
MAX
1.050
0.400
0.250
0.250
1.040
0.260
0.250
0.350
3.400
2.750
3.400
3.400
1.850
A
b
0.850
0.280
0.150
0.150
0.940
0.160
0.150
0.250
3.200
2.650
3.200
3.200
1.750
c
c1
d
d1
d2
d3
D1
D2
E
E1
E2
e
0.650 TYP
0.300 Typ
L
0.400
0°
0.500
-
θ
K
Notes:
1. Pin 1-4: Drain 1
2. Pin 5: Gate
3. Pin 6-8: Drain 2
4. Pin 9: Source
6
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Copyright © 2012, Texas Instruments Incorporated
CSD87312Q3E
www.ti.com
SLPS333 –NOVEMBER 2012
Recommended PCB Pattern
Recommended Stencil Opening
For recommended circuit layout for PCB designs, see application note SLPA005 – Reducing Ringing Through
PCB Layout Techniques.
Copyright © 2012, Texas Instruments Incorporated
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CSD87312Q3E
SLPS333 –NOVEMBER 2012
www.ti.com
Q3E Tape and Reel Information
4.00 0.ꢀ0 ꢁ(SS ꢂNoS ꢀ1
8.00 0.ꢀ0
2.00 0.0ꢃ
Ø ꢀ.ꢃ0
+0.ꢀ0
–0.00
3.60
M0ꢀ44-0ꢀ
Notes:
1. 10 sprocket hole pitch cumulative tolerance ±0.2
2. Camber not to exceed 1mm IN 100mm, noncumulative over 250mm
3. Material:black static dissipative polystyrene
4. All dimensions are in mm (unless otherwise specified)
5. Thickness: 0.30 ±0.05mm
6. MSL1 260°C (IR and Convection) PbF Reflow Compatible
8
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Copyright © 2012, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
24-Jan-2013
PACKAGING INFORMATION
Orderable Device
CSD87312Q3E
Status Package Type Package Pins Package Qty
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
Samples
Drawing
(1)
(2)
(3)
(4)
ACTIVE
VSON
VSON
DPB
8
8
2500
Pb-Free (RoHS CU NIPDAU
Exempt)
Level-1-260C-UNLIM
-55 to 150 87312E
-55 to 150
CSD87312Q3E-ASY
PREVIEW
DPB
TBD
Call TI
Call TI
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) Only one of markings shown within the brackets will appear on the physical device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Feb-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
CSD87312Q3E
VSON
DPB
8
2500
330.0
16.4
3.6
3.6
1.2
4.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Feb-2013
*All dimensions are nominal
Device
Package Type Package Drawing Pins
VSON DPB
SPQ
Length (mm) Width (mm) Height (mm)
367.0 367.0 38.0
CSD87312Q3E
8
2500
Pack Materials-Page 2
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