CSD86356Q5D [TI]
采用 5mm x 6mm SON 封装的 40A、25V、N 沟道同步降压 NexFET™ 功率 MOSFET 电源块;型号: | CSD86356Q5D |
厂家: | TEXAS INSTRUMENTS |
描述: | 采用 5mm x 6mm SON 封装的 40A、25V、N 沟道同步降压 NexFET™ 功率 MOSFET 电源块 |
文件: | 总28页 (文件大小:1110K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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CSD86356Q5D
ZHCSHY1 –MARCH 2018
CSD86356Q5D 同步降压 NexFET™电源块
1 特性
3 说明
1
•
•
•
•
•
•
•
•
•
•
•
半桥电源块
CSD86356Q5D NexFET™电源块是面向同步降压 应
用 的优化设计方案,能够以 5mm × 6mm 的小巧外形
提供高电流、高效率以及高频率性能。该产品针对 5V
栅极驱动 应用进行了优化,在与外部控制器/驱动器的
任一 5V 栅极驱动配套使用时,可提供一套灵活的解决
方案来实现高密度电源。
25A 电流下系统效率高达 93.0%
工作电流高达 40A
高频工作(高达 1.5MHz)
高密度 SON 5mm × 6mm 封装
针对 5V 栅极驱动进行了优化
开关损耗较低
超低电感封装
符合 RoHS 标准
俯视图
无卤素
VIN
VIN
TG
VSW
VSW
VSW
1
2
3
4
8
7
6
5
无铅引脚镀层
PGND
(Pin 9)
2 应用
•
同步降压转换器
TGR
BG
–
–
高频 应用
P0116-01
高电流、低占空比 应用
器件信息(1)
数量
•
•
•
多相位同步降压转换器
器件
介质
封装
发货
负载点 (POL) 直流/直流转换器
IMVP、VRM 和 VRD 应用
CSD86356Q5D 13 英寸卷带 2500
CSD86356Q5DT 7 英寸卷带 250
5.00mm × 6.00mm
SON 塑料封装
卷带封
装
(1) 如需了解所有可用封装,请参阅数据表末尾的可订购产品附
录。
典型电路
典型电源块效率与功率损耗
100
95
90
85
80
75
70
65
7
6
5
4
3
2
1
0
VIN
BOOT
VDD
VDD
GND
VIN
TG
Control
FET
DRVH
LL
VSW
TGR
VIN = 12 V
OUT = 1.3 V
VSW = 5 V
VOUT
ENABLE
PWM
ENABLE
PWM
V
Sync
FET
BG
fSW = 500 kHz
DRVL
PGND
LOUT = 0.3
mH
TA = 25
èC
CSD86356Q5D
Driver IC
Copyright © 2017, Texas Instruments Incorporated
0
5
10
15
20
25
30
35
40
Output Current (A)
D000
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SLPS665
CSD86356Q5D
ZHCSHY1 –MARCH 2018
www.ti.com.cn
目录
6.2 Typical Application .................................................. 14
Layout ................................................................... 17
7.1 Recommended Schematic Overview...................... 17
7.2 Recommended PCB Design Overview................... 18
器件和文档支持...................................................... 20
8.1 接收文档更新通知 ................................................... 20
8.2 社区资源.................................................................. 20
8.3 商标......................................................................... 20
8.4 静电放电警告........................................................... 20
8.5 Glossary.................................................................. 20
机械、封装和可订购信息 ....................................... 21
9.1 Q5D 封装尺寸 ......................................................... 21
9.2 引脚配置.................................................................. 21
9.3 焊盘图案建议........................................................... 22
9.4 模版建议.................................................................. 23
1
2
3
4
5
特性.......................................................................... 1
7
8
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Specifications......................................................... 3
5.1 Absolute Maximum Ratings ...................................... 3
5.2 Recommended Operating Conditions....................... 3
5.3 Thermal Information.................................................. 3
5.4 Power Block Performance ........................................ 3
5.5 Electrical Characteristics – Q1 Control FET ............. 4
5.6 Electrical Characteristics – Q2 Sync FET................. 5
5.7 Typical Power Block Device Characteristics............. 6
5.8 Typical Power Block MOSFET Characteristics......... 8
Application and Implementation ........................ 11
6.1 Application Information............................................ 11
9
6
4 修订历史记录
日期
修订版本
说明
2018 年 3 月
*
最初发布版本。
2
Copyright © 2018, Texas Instruments Incorporated
CSD86356Q5D
www.ti.com.cn
ZHCSHY1 –MARCH 2018
5 Specifications
5.1 Absolute Maximum Ratings
TA = 25°C (unless otherwise noted)(1)
MIN
MAX
25
UNIT
VIN to PGND
VSW to PGND
–0.8
25
Voltage
VSW to PGND (10 ns)
TG to TGR
27
V
–8
–8
10
BG to PGND
10
Pulsed current rating, IDM(2)
120
12
A
Power dissipation, PD
W
Sync FET, ID = 88 A, L = 0.1 mH
387
101
150
Avalanche
energy, EAS
mJ
°C
Control FET, ID = 45 A, L = 0.1 mH
TJ and TSTG
Operating junction and storage temperature
–55
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated is not implied. Exposure to absolute-
maximum-rated conditions for extended periods may affect device reliability.
(2) Pulse duration = 50 µS. Duty cycle = 0.01.
5.2 Recommended Operating Conditions
TA = 25°C (unless otherwise noted)
MIN
MAX
8
UNIT
V
VGS
VIN
Gate drive voltage
4.5
Input supply voltage(1)
Switching frequency CBST = 0.1 µF (min)
Operating current
22
V
ƒSW
1500
40
kHz
A
TJ
Operating temperature
Storage temperature
125
125
°C
°C
TSTG
(1) Operating at high VIN can create excessive AC voltage overshoots on the switch node (VSW) during MOSFET switching transients. For
reliable operation, the switch node (VSW) to ground voltage must remain at or below the Absolute Maximum Ratings.
5.3 Thermal Information
TA = 25°C (unless otherwise noted)
THERMAL METRIC
MIN
MAX
125
50
UNIT
°C/W
°C/W
°C/W
°C/W
RθJA
RθJA
RθJC
RθJC
Junction-to-ambient thermal resistance (min Cu)(1)
Junction-to-ambient thermal resistance (max Cu)(1) (2)
Junction-to-case thermal resistance (top of package)(1)
Junction-to-case thermal resistance (PGND pin)(1)
12
1.8
(1)
R
θJC is determined with the device mounted on a 1-in2 (6.45-cm2), 2-oz (0.071-mm) thick Cu pad on a 1.5-in × 1.5-in
(3.81-cm × 3.81-cm), 0.06-in (1.52-mm) thick FR4 board. RθJC is specified by design while RθJA is determined by the user’s board
design.
(2) Device mounted on FR4 material with 1-in2 (6.45-cm2) Cu.
5.4 Power Block Performance
TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
2.8
10
MAX
UNIT
W
VIN = 12 V, VGS = 5 V, VOUT = 1.3 V, IOUT = 25 A,
ƒSW = 500 kHz, LOUT = 0.3 μH, TJ = 25°C
PLOSS
IQVIN
Power loss(1)
VIN quiescent current(1)
TG to TGR = 0 V, BG to PGND = 0 V
µA
(1) Measurement made with six 10-μF (TDK C3216X5R1C106KT or equivalent) ceramic capacitors placed across VIN to PGND pins and
using a high-current 5-V driver IC.
Copyright © 2018, Texas Instruments Incorporated
3
CSD86356Q5D
ZHCSHY1 –MARCH 2018
www.ti.com.cn
5.5 Electrical Characteristics – Q1 Control FET
Tj = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
STATIC CHARACTERISTICS
BVDSS
IDSS
Drain-to-source voltage
VGS = 0 V, IDS = 250 µA
25
V
Drain-to-source leakage current
Gate-to-source leakage current
Gate-to-source threshold voltage
VGS = 0 V, VDS = 20 V
1
100
µA
nA
V
IGSS
VDS = 0 V, VGS = +10 / –8 V
VDS = VGS, IDS = 250 µA
VGS(th)
0.95
1.85
VIN = 12 V, VGS = 5 V, VOUT = 1.3 V,
IOUT = 20 A, ƒSW = 500 kHz,
LOUT = 300 nH
ZDS(on) Effective AC on-impedance
4.5
70
mΩ
gfs
Transconductance
VDS = 2.5 V, IDS = 20 A
S
DYNAMIC CHARACTERISTICS
CISS
COSS
CRSS
RG
Input capacitance
803
548
27
1040
712
35
pF
pF
pF
Ω
Output capacitance
Reverse transfer capacitance
Series gate resistance
Gate charge total (4.5 V)
Gate charge – gate-to-drain
Gate charge – gate-to-source
Gate charge at Vth
Output charge
VGS = 0 V, VDS = 12.5 V, ƒ = 1 Mhz
2.1
6.0
1.3
2.6
1.2
10.3
7
4.2
Qg
7.9
nC
nC
nC
nC
nC
ns
ns
ns
ns
Qgd
Qgs
Qg(th)
QOSS
td(on)
tr
VDS = 12.5 V, IDS = 20 A
VDS = 12.5 V, VGS = 0 V
Turn on delay time
Rise time
26
VDS = 12.5 V, VGS = 4.5 V, IDS = 20 A,
RG = 0 Ω
td(off)
tf
Turn off delay time
Fall time
12
3
DIODE CHARACTERISTICS
VSD
Qrr
trr
Diode forward voltage
Reverse recovery charge
Reverse recovery time
IDS = 20 A, VGS = 0 V
0.84
34
0.95
V
nC
ns
VDD = 12.5 V, IF = 20 A, di/dt = 300 A/µs
23
4
Copyright © 2018, Texas Instruments Incorporated
CSD86356Q5D
www.ti.com.cn
ZHCSHY1 –MARCH 2018
5.6 Electrical Characteristics – Q2 Sync FET
Tj = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
STATIC CHARACTERISTICS
BVDSS
IDSS
Drain-to-source voltage
VGS = 0 V, IDS = 250 µA
25
V
Drain-to-source leakage current
Gate-to-source leakage current
Gate-to-source threshold voltage
VGS = 0 V, VDS = 20 V
1
100
1.5
µA
nA
V
IGSS
VDS = 0 V, VGS = +10 / –8 V
VDS = VGS, IDS = 250 µA
VGS(th)
0.9
VIN = 12 V, VGS = 5 V, VOUT = 1.3 V,
IOUT = 20 A, ƒSW = 500 kHz,
LOUT = 300 nH
ZDS(on) Effective AC on-impedance
0.8
mΩ
gfs
Transconductance
VDS = 2.5 V, IDS = 20 A
106
S
DYNAMIC CHARACTERISTICS
CISS
COSS
CRSS
RG
Input capacitance
1930
1350
64
2510
1760
83
pF
pF
pF
Ω
Output capacitance
Reverse transfer capacitance
Series gate resistance
Gate charge total (4.5 V)
Gate charge – gate-to-drain
Gate charge – gate-to-source
Gate charge at Vth
Output charge
VGS = 0 V, VDS = 12.5 V, ƒ = 1 Mhz
0.8
14.8
3.3
5.2
2.5
24.9
10
1.6
Qg
19.3
nC
nC
nC
nC
nC
ns
ns
ns
ns
Qgd
Qgs
Qg(th)
QOSS
td(on)
tr
VDS = 12.5 V, IDS = 20 A
VDS = 12.5 V, VGS = 0 V
Turn on delay time
Rise time
25
VDS = 12.5 V, VGS = 4.5 V, IDS = 20 A,
RG = 0 Ω
td(off)
tf
Turn off delay time
Fall time
18
4
DIODE CHARACTERISTICS
VSD
Qrr
trr
Diode forward voltage
Reverse recovery charge
Reverse recovery time
IDS = 20 A, VGS = 0 V
0.79
60
0.95
V
nC
ns
VDS = 12.5 V, IF = 20 A, di/dt = 300 A/µs
30
HD
LD
HD
LD
Max RθJA = 50°C/W
when mounted on 1-in2
(6.45-cm2) of
2-oz (0.071-mm) thick
Cu.
Max RθJA = 125°C/W
when mounted on
minimum pad area of
2-oz (0.071-mm) thick
Cu.
LG HS
LG HS
HG
LS
HG
LS
M0189-01
M0190-01
版权 © 2018, Texas Instruments Incorporated
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CSD86356Q5D
ZHCSHY1 –MARCH 2018
www.ti.com.cn
5.7 Typical Power Block Device Characteristics
TJ = 125°C, unless stated otherwise. The typical power block system characteristic curves and 图 3 are based on
measurements made on a PCB design with dimensions of 4 in (W) × 3.5 in (L) × 0.062 in (H) and 6 copper layers of 1-oz
copper thickness. See Application and Implementation section for detailed explanation.
8
7
6
5
4
3
2
1
0
1.05
1
0.95
0.9
0.85
0.8
0.75
0
5
10
15
20
25
30
35
40
-50
-25
0
25
50
75
100
125
150
Output Current (A)
Junction Temperature (èC)
D001
D002
VIN = 12 V
ƒSW = 500 kHz
VGS = 5 V
VOUT = 1.3 V
VIN = 12 V
ƒSW = 500 kHz
VGS = 5 V
VOUT = 1.3 V
IOUT = 40 A
LOUT = 0.3 µH
LOUT = 0.3 µH
图 1. Power Loss vs Output Current
图 2. Normalized Power Loss vs Temperature
50
45
40
35
30
25
20
15
10
5
0
0
20
40
60
80
100
120
140
Board Temperature (èC)
D005
VIN = 12 V
VGS = 5 V
VOUT = 1.3 V
ƒSW = 500 kHz
LOUT = 0.3 µH
图 3. Typical Safe Operating Area (SOA)
6
版权 © 2018, Texas Instruments Incorporated
CSD86356Q5D
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ZHCSHY1 –MARCH 2018
Typical Power Block Device Characteristics (接下页)
TJ = 125°C, unless stated otherwise. The typical power block system characteristic curves and 图 3 are based on
measurements made on a PCB design with dimensions of 4 in (W) × 3.5 in (L) × 0.062 in (H) and 6 copper layers of 1-oz
copper thickness. See Application and Implementation section for detailed explanation.
1.6
1.5
1.4
1.3
1.2
1.1
1
6.6
5.5
4.4
3.3
2.2
1.1
0.0
-1.1
-2.2
1.30
1.25
1.20
1.15
1.10
1.05
1.00
0.95
0.90
3.4
2.8
2.3
1.7
1.1
0.6
0.0
-0.6
-1.1
0.9
0.8
100
300
500
700
900 1100 1300 1500 1700
0
2
4
6
8
10
12
14
16
18
Switching Frequency (kHz)
Input Voltage (V)
D006
D007
VIN = 12 V
LOUT = 0.3 µH
VGS = 5 V
VOUT = 1.3 V
VGS = 5 V
ƒSW = 500 kHz
VOUT = 1.3 V
IOUT = 40 A
LOUT = 0.3 µH
IOUT = 40 A
图 4. Normalized Power Loss vs Switching Frequency
图 5. Normalized Power Loss vs Input Voltage
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1
9.0
1.04
1.03
1.02
1.01
1
0.4
7.9
6.7
5.6
4.5
3.4
2.2
1.1
0.0
-1.1
0.3
0.2
0.1
0.0
-0.1
-0.2
0.99
0.98
0.9
0.3 0.8 1.3 1.8 2.3 2.8 3.3 3.8 4.3 4.8 5.3
Output Voltage (V)
0
150
300
450
600
750
900 1050 1200
Output Inductance (nH)
D008
D009
VIN = 12 V
VGS = 5 V ƒSW = 500 kHz
IOUT = 40 A
VIN = 12 V
ƒSW = 500 kHz
VGS = 5 V
VOUT = 1.3 V
LOUT = 0.3 µH
IOUT = 40 A
图 6. Normalized Power Loss vs Output Voltage
图 7. Normalized Power Loss vs Output Inductance
版权 © 2018, Texas Instruments Incorporated
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ZHCSHY1 –MARCH 2018
www.ti.com.cn
5.8 Typical Power Block MOSFET Characteristics
TA = 25°C, unless stated otherwise.
100
90
80
70
60
50
40
30
100
90
80
70
60
50
40
30
20
10
0
20
VGS = 4.5 V
VGS = 6 V
VGS = 8 V
VGS = 4.5 V
VGS = 6 V
VGS = 8 V
10
0
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0
0.05
0.1
0.15
0.2
0.25
0.3
VDS - Drain-to-Source Voltage (V)
VDS - Drain-to-Source Voltage (V)
D010
D011
图 8. Control MOSFET Saturation
图 9. Sync MOSFET Saturation
100
100
10
TC = 125°C
TC = 25°C
TC = -55°C
TC = 125°C
TC = 25°C
TC = -55°C
10
1
1
0.1
0.1
0.01
0.001
0.01
0.001
0
0.5
1
1.5
2
2.5
3
3.5
0
0.5
1
1.5
2
2.5
3
VGS - Gate-to-Source Voltage (V)
VGS - Gate-to-Source Voltage (V)
D012
D013
VDS = 5 V
VDS = 5 V
图 10. Control MOSFET Transfer
图 11. Sync MOSFET Transfer
8
7
6
5
4
3
2
1
8
7
6
5
4
3
2
1
0
0
0
0
2
4
6
8
10
12
2.5
5
7.5 10 12.5 15 17.5 20 22.5 25
Qg - Gate Charge (nC)
Qg - Gate Charge (nC)
D014
D015
ID = 20 A
VDS = 12.5 V
ID = 20 A
VDS = 12.5 V
图 12. Control MOSFET Gate Charge
图 13. Sync MOSFET Gate Charge
8
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CSD86356Q5D
www.ti.com.cn
ZHCSHY1 –MARCH 2018
Typical Power Block MOSFET Characteristics (接下页)
TA = 25°C, unless stated otherwise.
10000
1000
100
10
10000
1000
100
10
Ciss = Cgd + Cgs
Coss = Cds + Cgd
Crss = Cgd
Ciss = Cgd + Cgs
Coss = Cds + Cgd
Crss = Cgd
1
1
0
5
10
15
20
25
0
5
10
15
20
25
VDS - Drain-to-Source Voltage (V)
VDS - Drain-to-Source Voltage (V)
D016
D017
ƒ = 1 MHz
VGS = 0
ƒ = 1 MHz
VGS = 0
图 14. Control MOSFET Capacitance
图 15. Sync MOSFET Capacitance
1.8
1.6
1.4
1.2
1
1.6
1.4
1.2
1
0.8
0.6
0.4
0.8
0.6
-75 -50 -25
0
25
50
75 100 125 150 175
-75 -50 -25
0
25
50
75 100 125 150 175
TC - Case Temperature (°C)
TC - Case Temperature (°C)
D018
D019
ID = 250 µA
ID = 250 µA
图 16. Control MOSFET VGS(th)
图 17. Sync MOSFET VGS(th)
12
10
8
5
4
3
2
1
0
TC = 25°C, I D = 20 A
TC = 125°C, I D = 20 A
TC = 25°C, I D = 20 A
TC = 125°C, I D = 20 A
6
4
2
0
0
1
2
3
4
5
6
7
8
9
10
0
1
2
3
4
5
6
7
8
9
10
VGS - Gate-to-Source Voltage (V)
VGS - Gate-to-Source Voltage (V)
D020
D021
图 18. Control MOSFET RDS(ON) vs VGS
图 19. Sync MOSFET RDS(ON) vs VGS
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Typical Power Block MOSFET Characteristics (接下页)
TA = 25°C, unless stated otherwise.
1.5
1.4
1.3
1.2
1.1
1
1.5
VGS = 4.5 V
VGS = 8.0 V
VGS = 4.5 V
VGS = 8.0 V
1.4
1.3
1.2
1.1
1
0.9
0.8
0.7
0.9
0.8
0.7
-75 -50 -25
0
25
50
75 100 125 150 175
-75 -50 -25
0
25
50
75 100 125 150 175
TC - Case Temperature (°C)
TC - Case Temperature (°C)
D022
D023
ID = 20 A
ID = 20 A
图 20. Control MOSFET Normalized RDS(ON)
图 21. Sync MOSFET Normalized RDS(ON)
100
100
TC = 25°C
TC = 25°C
TC = 125°C
TC = 125°C
10
1
10
1
0.1
0.1
0.01
0.001
0.0001
0.01
0.001
0.0001
0
0.2
0.4
0.6
0.8
1
0
0.2
0.4
0.6
0.8
1
VSD - Source-to-Drain Voltage (V)
VSD - Source-to-Drain Voltage (V)
D024
D025
图 22. Control MOSFET Body Diode
图 23. Sync MOSFET Body Diode
100
200
100
TC = 25è C
TC = 125è C
TC = 25è C
TC = 125è C
10
0.01
10
0.01
0.1
1
0.1
1
TAV - Time in Avalanche (ms)
TAV - Time in Avalanche (ms)
D026
D027
图 24. Control MOSFET Unclamped Inductive Switching
图 25. Sync MOSFET Unclamped Inductive Switching
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ZHCSHY1 –MARCH 2018
6 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
6.1 Application Information
The CSD86356Q5D NexFET power block is an optimized design for synchronous buck applications using 5-V
gate drive. The control FET and sync FET silicon are parametrically tuned to yield the lowest power loss and
highest system efficiency. As a result, a new rating method is needed which is tailored towards a more systems-
centric environment. System-level performance curves such as power loss, Safe Operating Area (SOA), and
normalized graphs allow engineers to predict the product performance in the actual application.
6.1.1 Equivalent System Performance
Many of today's high-performance computing systems require low-power consumption in an effort to reduce
system operating temperatures and improve overall system efficiency. This has created a major emphasis on
improving the conversion efficiency of today’s synchronous buck topology. In particular, there has been an
emphasis in improving the performance of the critical power semiconductor in the power stage of this application
(see 图 26). As such, optimization of the power semiconductors in these applications, needs to go beyond simply
reducing RDS(ON)
.
Power Stage
Components
Power Block
Components
Ci
+
-
Input
Supply
Control
FET
Driver
Driver
PWM
Lo
IL
Switch
Node
Co
Sync
FET
Load
图 26. Synchronous Buck Topology
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Application Information (接下页)
The CSD86356Q5D is part of TI’s power block product family which is a highly optimized product for use in a
synchronous buck topology requiring high current, high efficiency, and high frequency. It incorporates TI’s latest
generation silicon which has been optimized for switching performance, as well as minimizing losses associated
with QGD, QGS, and QRR. Furthermore, TI’s patented packaging technology has minimized losses by nearly
eliminating parasitic elements between the control FET and sync FET connections (see 图 27). A key challenge
solved by TI’s patented packaging technology is the system-level impact of Common Source Inductance (CSI).
CSI greatly impedes the switching characteristics of any MOSFET which in turn increases switching losses and
reduces system efficiency. As a result, the effects of CSI need to be considered during the MOSFET selection
process. In addition, standard MOSFET switching loss equations used to predict system efficiency need to be
modified in order to account for the effects of CSI. Further details behind the effects of CSI and modification of
switching loss equations are outlined in TI’s Application Note Power Loss Calculation With Common Source
Inductance Consideration for Synchronous Buck Converters (SLPA009).
Input
Supply
RPCB
CESR
LDRAIN
CINPUT
Control
FET
Driver
PWM
CESL
LSOURCE
Lo
Co
IL
Switch
Node
Load
LDRAIN
CTOTAL
Sync
FET
Driver
LSOURCE
图 27. Elimination of Common Source Inductance
The combination of TI’s latest generation silicon and optimized packaging technology has created a
benchmarking solution that outperforms industry standard MOSFET chipsets of similar RDS(ON) and MOSFET
chipsets with lower RDS(ON). 图 28 and 图 29 compare the efficiency and power loss performance of the
CSD86356Q5D versus industry standard MOSFET chipsets commonly used in this type of application. This
comparison purely focuses on the efficiency and generated loss of the power semiconductors only. The
performance of CSD86356Q5D clearly highlights the importance of considering the Effective AC On-Impedance
(ZDS(ON)) during the MOSFET selection process of any new design. Simply normalizing to traditional MOSFET
RDS(ON) specifications is not an indicator of the actual in-circuit performance when using TI’s Power Block
technology.
12
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Application Information (接下页)
96
94
92
90
88
86
10
9
8
7
6
5
4
3
2
1
0
PowerBlock HS/LS RDS(ON) = 4.5 mW/1.8 mW
Discrete HS/LS RDS(ON) = 4.5 mW/1.8 mW
Discrete HS/LS RDS(ON) = 4.5 mW/0.8 mW
84
PowerBlock HS/LS RDS(ON) = 4.5 mW/1.8 mW
Discrete HS/LS RDS(ON) = 4.5 mW/1.8 mW
Discrete HS/LS RDS(ON) = 4.5 mW/0.8 mW
82
80
0
5
10
15
20
25
30
35
40
0
5
10
15
20
25
30
35
40
Output Current (A)
VOUT = 1.3 V
VDD= 5 V
Output Current (A)
VOUT = 1.3 V
VDD = 5 V
D030
D031
VIN = 12 V
LOUT = 0.3 µH
TA = 25°C
VIN = 12 V
LOUT = 0.3 µH
TA = 25°C
ƒSW = 500 kHz
ƒSW = 500 kHz
图 28. Efficiency
图 29. Power Loss
Comparison of RDS(ON) vs ZDS(ON) compares the traditional DC measured RDS(ON) of CSD86356Q5D versus its
ZDS(ON). This comparison takes into account the improved efficiency associated with TI’s patented packaging
technology. As such, when comparing TI’s Power Block products to individually packaged discrete MOSFETs or
dual MOSFETs in a standard package, the in-circuit switching performance of the solution must be considered.
In this example, individually packaged discrete MOSFETs or dual MOSFETs in a standard package would need
to have DC measured RDS(ON) values that are equivalent to CSD86356Q5D’s ZDS(ON) value in order to have the
same efficiency performance at full load. Mid to light-load efficiency will still be lower with individually packaged
discrete MOSFETs or dual MOSFETs in a standard package.
6.1.1.1 Comparison of RDS(ON) vs ZDS(ON)
HS
TYP
LS
TYP
PARAMETER
UNIT
MAX
—
MAX
Effective AC on-impedance ZDS(ON) (VGS = 5 V)
DC measured RDS(ON) (VGS = 4.5 V)
4.5
4.5
0.8
1.8
—
mΩ
5.6
2.2 mΩ
6.1.2 Power Loss Curves
MOSFET centric parameters such as RDS(ON) and Qgd are needed to estimate the loss generated by the devices.
In an effort to simplify the design process for engineers, Texas Instruments has provided measured power loss
performance curves. 图 1 plots the power loss of the CSD86356Q5D as a function of load current. This curve is
measured by configuring and running the CSD86356Q5D as it would be in the final application (see 图 30).The
measured power loss is the CSD86356Q5D loss and consists of both input conversion loss and gate drive loss.
公式 1 is used to generate the power loss curve.
(VIN × IIN) + (VDD × IDD) – (VSW_AVG × IOUT) = Power loss
(1)
The power loss curve in 图 1 is measured at the maximum recommended junction temperatures of 125°C under
isothermal test conditions.
6.1.3 Safe Operating Area (SOA) Curves
The SOA curves in the CSD86356Q5D data sheet provides guidance on the temperature boundaries within an
operating system by incorporating the thermal resistance and system power loss. to 图 3 outline the temperature
and airflow conditions required for a given load current. The area under the curve dictates the safe operating
area. All the curves are based on measurements made on
a PCB design with dimensions of
4 in (W) × 3.5 in (L) × 0.062 in (T) and 6 copper layers of 1-oz copper thickness.
版权 © 2018, Texas Instruments Incorporated
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6.1.4 Normalized Curves
The normalized curves in the CSD86356Q5D data sheet provides guidance on the power loss and SOA
adjustments based on their application specific needs. These curves show how the power loss and SOA
boundaries will adjust for a given set of system conditions. The primary Y-axis is the normalized change in power
loss and the secondary Y-axis is the change in system temperature required in order to comply with the SOA
curve. The change in power loss is a multiplier for the power loss curve and the change in temperature is
subtracted from the SOA curve.
6.2 Typical Application
Input Current (IIN)
Gate Drive
Current (IDD)
VIN
A
BOOT
DRVH
LL
VDD
A
VDD
V
Input Voltage (VIN)
VIN
Control
FET
Gate Drive
Voltage (VDD)
V
TG
ENABLE
PWM
Output Current (IOUT
VOUT
)
VSW
A
TGR
Sync
FET
PWM
BG
DRVL
GND
PGND
Averaged Switch
V Node Voltage
Averaging
Circuit
CSD86356Q5D
Driver IC
(VSW_AVG
)
Copyright © 2018, Texas Instruments Incorporated
图 30. Typical Application
14
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Typical Application (接下页)
6.2.1 Design Example: Calculating Power Loss and SOA
The user can estimate product loss and SOA boundaries by arithmetic means (see Operating Conditions).
Though the power loss and SOA curves in this data sheet are taken for a specific set of test conditions, the
following procedure will outline the steps the user should take to predict product performance for any set of
system conditions.
6.2.2 Operating Conditions
•
•
•
•
•
Output current = 35 A
Input voltage = 5 V
Output voltage = 2 V
Switching frequency = 950 kHz
Inductor = 0.3 µH
6.2.2.1 Calculating Power Loss
•
•
•
•
•
•
Power loss at 35 A = 5.57 W (图 1)
Normalized power loss for input voltage ≈ 1.12 (图 5)
Normalized power loss for output voltage ≈ 1.13 (图 6)
Normalized power loss for switching frequency ≈ 1.21 (图 4)
Normalized power loss for output inductor ≈ 1 (图 7)
Final calculated power loss = 5.57 W × 1.12 × 1.13 × 1.21 × 1 ≈ 8.5 W
6.2.2.2 Calculating SOA Adjustments
•
•
•
•
•
SOA adjustment for input voltage ≈ 1.37°C (图 5)
SOA adjustment for output voltage ≈ 1.48°C (图 6)
SOA adjustment for switching frequency ≈ 2.34°C (图 4)
SOA adjustment for output inductor ≈ 0.03°C (图 7)
Final calculated SOA adjustment = 1.37 + 1.48 + 2.34 + 0.03 ≈ 5.2°C
In the previous design example, the estimated power loss of the CSD58915Q5D would increase to 8.5 W. In
addition, the maximum allowable board and/or ambient temperature would have to decrease by 5.2°C. 图 31
graphically shows how the SOA curve would be adjusted accordingly.
1. Start by drawing a horizontal line from the application current to the SOA curve.
2. Draw a vertical line from the SOA curve intercept down to the board/ambient temperature.
3. Adjust the SOA board/ambient temperature by subtracting the temperature adjustment value.
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Typical Application (接下页)
In the design example, the SOA temperature adjustment yields a reduction in allowable board/ambient
temperature of 5.2°C. In the event the adjustment value is a negative number, subtracting the negative number
would yield an increase in allowable board/ambient temperature.
图 31. Power Block SOA
16
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7 Layout
7.1 Recommended Schematic Overview
There are several critical components that must be used in conjunction with this power block device. 图 32
shows a portion of a schematic with the critical components needed for proper operation.
•
C22: Bypass capacitor for VIN to help with ringing reduction (recommend 3.3-nF, 0402, 50-V ceramic
capacitor)
•
•
•
•
•
•
•
C20: Bootstrap capacitor
C21: Bypass capacitor for VDD
C7-C14: Bypass capacitors for VIN (minimum of 40 µF)
C15: Electrolytic capacitor for VIN
R14, R16: Place holder for gate resistor (optional)
R15: Place holder for bootstrap resistor (optional)
R17, C16: Place holder for snubber (optional)
+VIN
GND
GND
GND
GND
8
GND
GND
GND
GND
GND
GND
Q1
Vin
Vsw
1
0603
R15
L1
0603
HS
V_OUT
0
Vsw
Vsw
7
6
LS
C20
0.1µF
U2
BOOT
R16
0
0603
Tg
1
2
3
4
8
7
6
5
3
4
HG
+PWM
PWM PHASE
R9
0
Bg
ENABLE
Tgr
5
GND
LG
FCCM
VCC
Pgnd
0603
+VDD
GND
GND
GND
CSD86356Q5D
C21
10µF
0603
GND
GND
GND
R14
0
0603
Copyright © 2017, Texas Instruments Incorporated
图 32. Recommended Schematic
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ZHCSHY1 –MARCH 2018
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7.2 Recommended PCB Design Overview
There are two key system-level parameters that can be addressed with a proper PCB design: electrical and
thermal performance. Properly optimizing the PCB layout yields maximum performance in both areas. A brief
description on how to address each parameter follows.
7.2.1 Electrical Performance
The power block has the ability to switch at voltage rates greater than 10 kV/μs. Special care must be taken with
the PCB layout design and placement of the input capacitors, inductor, driver IC and output capacitors.
•
The placement of the input capacitors relative to the power block’s VIN and PGND pins should have the
highest priority during the component placement routine. It is critical to minimize these node lengths. As such,
ceramic input capacitors need to be placed as close as possible to the VIN and PGND pins (see 图 33 and 图
34). It is recommended that one 3.3-nF (or similar), 0402, 50-V ceramic capacitor be placed on the top side
of the board as close as possible to VIN and PGND pins. In addition, a minimum of 40 μF of bulk ceramic
capacitance should be placed as close as possible to the power block in a design. For high-density design,
some of these ceramic capacitors can be placed on the bottom layer of PCB with appropriate number of vias
interconnecting both layers.
•
•
The driver IC should be placed relatively close to the power block gate pins. TG and BG should connect to the
outputs of the driver IC. The TGR pin serves as the return path of the high-side gate drive circuitry and should
be connected to the phase pin of the IC (sometimes called LX, LL, SW, PH, etc.). The bootstrap capacitor for
the driver IC will also connect to this pin.
The switching node of the output inductor should be placed relatively close to the power block VSW pins.
Minimizing the node length between these two components will reduce the PCB conduction losses and
actually reduce the switching noise level. In the event the switch node waveform exhibits ringing that reaches
undesirable levels, the use of a boost resistor or RC snubber can be an effective way to easily reduce the
peak ring level. The recommended boost resistor value will range between 1.0 Ω to 4.7 Ω depending on the
output characteristics of driver IC used in conjunction with the power block. The RC snubber values can
range from 0.5 Ω to 2.2 Ω for the R and 330 pF to 2200 pF for the C. Please refer to Snubber Circuits:
Theory, Design and Application (SLUP100) for more details on how to properly tune the RC snubber values.
The RC snubber should be placed as close as possible to the VSW node and PGND (see 图 33 and 图 34).
(1)
(1) Keong W. Kam, David Pommerenke, “EMI Analysis Methods for Synchronous Buck Converter EMI Root Cause Analysis”, University of
Missouri – Rolla
18
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ZHCSHY1 –MARCH 2018
Recommended PCB Design Overview (接下页)
7.2.2 Thermal Performance
The power block has the ability to utilize the GND planes as the primary thermal path. As such, the use of
thermal vias is an effective way to pull away heat from the device and into the system board. Concerns of solder
voids and manufacturability problems can be addressed by the use of three basic tactics to minimize the amount
of solder attach that will wick down the via barrel:
•
•
Intentionally space out the vias from each other to avoid a cluster of holes in a given area.
Use the smallest drill size allowed in your design. The examples in 图 33 and 图 34 use vias with a 10-mil drill
hole and a 16-mil capture pad.
•
Tent the opposite side of the via with solder-mask.
In the end, the number and drill size of the thermal vias should align with the end user’s PCB design rules and
manufacturing capabilities.
图 33. Recommended PCB Layout (Top Down View)
(2)
图 34. Recommended PCB Layout (Bottom View)
(2) The yellow box on 图 34 signifies an approximate location of the power block on the upper layer.
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19
CSD86356Q5D
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8 器件和文档支持
8.1 接收文档更新通知
要接收文档更新通知,请导航至 TI.com.cn 上的器件产品文件夹。请单击右上角的提醒我 进行注册,即可每周接收
产品信息更改摘要。有关更改的详细信息,请查看任何已修订文档中包含的修订历史记录。
8.2 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范,
并且不一定反映 TI 的观点;请参阅 TI 的 《使用条款》。
TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在
e2e.ti.com 中,您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。
设计支持
TI 参考设计支持 可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。
8.3 商标
NexFET, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
8.4 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时,应将导线一起截短或将装置放置于导电泡棉中,以防止 MOS 门极遭受静电损
伤。
8.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
20
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ZHCSHY1 –MARCH 2018
9 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更,恕不另行通知,且
不会对此文档进行修订。如需获取此数据表的浏览器版本,请参阅左侧的导航栏。
9.1 Q5D 封装尺寸
6.1
5.9
A
B
PIN 1 INDEX AREA
5.1
4.9
C
1.05 MAX
SEATING PLANE
0.08
0.05
0.00
C
3.16 0.1
EXPOSED
THERMAL PAD
4X (0.25)
4X (1)
(0.2) TYP
6X 1.27
4
5
2X
9
SYMM
3.81
4.32 0.1
8
1
0.46
0.36
8X
0.5
0.4
SYMM
0.71
0.51
6X
0.71
0.51
0.1
0.05
C A B
C
4223291/A 10/2016
1. 所有线性尺寸的单位均为毫米。括号中的任何尺寸仅供参考。尺寸和公差值符合 ASME Y14.5M 标准。
2. 本图如有变更,恕不另行通知。
3. 封装散热焊盘必须焊接在印刷电路板上,以实现最佳的散热和机械性能。
9.2 引脚配置
位置
名称
VIN
引脚 1
引脚 2
引脚 3
引脚 4
引脚 5
引脚 6
引脚 7
引脚 8
引脚 9
VIN
TG
TGR
BG
VSW
VSW
VSW
PGND
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ZHCSHY1 –MARCH 2018
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9.3 焊盘图案建议
(3.16)
0.05 MIN
TYP
4X (1.33)
2X (0.81)
(0.45)
6X (0.81)
6X
1
8
(0.41)
2X (0.41)
METAL UNDER
SOLDER MASK
TYP
(0.7)
TYP
9
PKG
3
3X
(1.41)
(4.32)
2X
(1.91)
6X (1.27)
4
5
(R0.05) TYP
4X (0.54)
PKG
SOLDER MASK
OPENING
TYP
4X (0.25)
(
0.2) VIA
TYP
2X (2.25)
(5.59)
1. 所有线性尺寸的单位均为毫米。括号中的任何尺寸仅供参考。尺寸和公差值符合 ASME Y14.5M 标准。
2. 此封装设计用于焊接到电路板的散热焊盘上。有关更多信息,请参阅《QFN/SON
(SLUA271)。
PCB
连接》应用报告
3. 根据应用决定是否选用过孔,详情请参见器件数据表。如果实现了部分或全部过孔,则会显示建议的过孔位
置。
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ZHCSHY1 –MARCH 2018
9.4 模版建议
6X (1.37)
METAL UNDER
SOLDER MASK
TYP
8X (0.81)
8X (0.41)
(0.79) TYP
(0.45)
9
2X (0.15)
1
8
6X
(1.21)
(0.56)
4X
(1.41)
PKG
2X (4.92)
3
4
SOLDER MASK
EDGE
6X (1.27)
TYP
5
(R0.05) TYP
4X
(0.49)
EXPOSED METAL
TYP
PKG
4X (0.25)
2X (2.25)
(5.59)
1. 所有线性尺寸的单位均为毫米。括号中的任何尺寸仅供参考。尺寸和公差值符合 ASME Y14.5M 标准。
2. 具有漏斗形壁和圆角的激光切割孔可提供更佳的锡膏脱离。IPC-7525 可能提供替代设计建议。
版权 © 2018, Texas Instruments Incorporated
23
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
2500
250
(1)
(2)
(3)
(4/5)
(6)
CSD86356Q5D
CSD86356Q5DT
ACTIVE
VSON-CLIP
VSON-CLIP
DMV
8
8
RoHS-Exempt
& Green
SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-55 to 150
-55 to 150
86356D
86356D
ACTIVE
DMV
RoHS-Exempt
& Green
SN
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
CSD86356Q5DT
VSON-
CLIP
DMV
8
250
330.0
12.4
5.3
6.3
1.2
8.0
12.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
VSON-CLIP DMV
SPQ
Length (mm) Width (mm) Height (mm)
336.6 336.6 41.3
CSD86356Q5DT
8
250
Pack Materials-Page 2
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