CSD88539NDT [TI]
采用 SO-8 封装的双路、28mΩ、60V、N 沟道 NexFET™ 功率 MOSFET | D | 8 | -55 to 150;型号: | CSD88539NDT |
厂家: | TEXAS INSTRUMENTS |
描述: | 采用 SO-8 封装的双路、28mΩ、60V、N 沟道 NexFET™ 功率 MOSFET | D | 8 | -55 to 150 局域网 PC 开关 脉冲 光电二极管 晶体管 |
文件: | 总15页 (文件大小:919K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
CSD88539ND
ZHCSC33 –FEBRUARY 2014
CSD88539ND,双路 60V N 通道 NexFET™ 功率 MOSFET
1 特性
产品概要
1
•
•
•
•
•
超低 Qg 和 Qgd
TA = 25°C
典型值
60
单位
V
雪崩额定值
无铅
VDS
Qg
漏源电压
栅极电荷总量 (10V)
栅漏栅极电荷
7.2
nC
nC
mΩ
mΩ
V
符合 RoHS 环保标准
无卤素
Qgd
1.1
VGS = 6V
VGS = 10V
3.0
27
23
RDS(on) 漏源导通电阻
VGS(th) 阀值电压
2 应用范围
•
•
用于电机控制的半桥
同步降压转换器
订购信息
介质
器件
数量
2500
250
封装
出货
CSD88539ND
CSD88539NDT
13 英寸卷带
7 英寸卷带
3 说明
SO-8 塑料封装
卷带封装
这款双路小外形尺寸 (SO)-8,60V,23mΩ NexFET™
功率 MOSFET 被设计运行为低电流电机控制应用中的
半桥。
最大绝对额定值
TA = 25°C
值
60
单位
V
顶视图
VDS
VGS
漏源电压
栅源电压
±20
15
V
持续漏极电流(受封装限制)
1
8
S1
D1
持续漏极电流(受芯片限制),TC = 25°C
ID
11.7
A
时测得
持续漏极电流(1)
6.3
46
2
3
7
6
G1
S2
D1
D2
(2)
IDM
PD
脉冲漏极电流
A
功率耗散(1)
2.1
W
TJ,
TSTG
运行结温和储存温度范围
-55 至 150
°C
4
5
雪崩能量,单脉冲
ID = 22A,L = 0.1mH,RG = 25Ω
G2
D2
EAS
24
mJ
(1) RθJA = 60°C/W,这是在一个厚度 0.06 英寸环氧树脂 (FR4) 印
刷电路板 (PCB) 上的 1 英寸2,2 盎司 的铜过渡垫片上测得的
典型值
(2) 脉冲持续时间 ≤ 300μs,占空比 ≤ 2%
RDS(on) 与 VGS 间的关系
栅极电荷
60
54
48
42
36
30
24
18
12
6
10
TC = 25°C,I D = 5A
TC = 125°C,I D = 5A
ID = 5A
VDS = 30V
9
8
7
6
5
4
3
2
1
0
0
0
2
4
6
8
10
12
14
16
18
20
0
1
2
3
4
5
6
7
8
Qg - Gate Charge (nC)
VGS - Gate-to- Source Voltage (V)
G001
G001
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SLPS456
CSD88539ND
ZHCSC33 –FEBRUARY 2014
www.ti.com.cn
4 Specifications
4.1 Electrical Characteristics
(TA = 25°C unless otherwise stated)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
Static Characteristics
BVDSS
IDSS
Drain-to-Source Voltage
VGS = 0 V, ID = 250 μA
60
V
Drain-to-Source Leakage Current
Gate-to-Source Leakage Current
Gate-to-Source Threshold Voltage
VGS = 0 V, VDS = 48 V
VDS = 0 V, VGS = 20 V
VDS = VGS, ID = 250 μA
VGS = 6 V, ID = 5 A
1
100
3.6
34
μA
nA
V
IGSS
VGS(th)
2.6
3.0
27
23
19
mΩ
mΩ
S
RDS(on)
gfs
Drain-to-Source On Resistance
Transconductance
VGS = 10 V, ID = 5 A
VDS = 30 V, ID = 5 A
28
Dynamic Characteristics
Ciss
Coss
Crss
RG
Input Capacitance
570
70
2.0
6.6
7.2
1.1
2.7
1.8
9.6
5
741
91
pF
pF
pF
Ω
Output Capacitance
Reverse Transfer Capacitance
Series Gate Resistance
Gate Charge Total (10 V)
Gate Charge Gate to Drain
Gate Charge Gate to Source
Gate Charge at Vth
Output Charge
VGS = 0 V, VDS = 30 V, f = 1 MHz
2.6
13.2
9.4
Qg
nC
nC
nC
nC
nC
ns
ns
ns
ns
Qgd
Qgs
Qg(th)
Qoss
td(on)
tr
VDS = 30 V, ID = 5 A
VDS = 30 V, VGS = 0 V
Turn On Delay Time
Rise Time
9
VDS = 30 V, VGS = 10 V, IDS = 5 A, RG = 0 Ω
td(off)
tf
Turn Off Delay Time
Fall Time
14
4
Diode Characteristics
VSD
Qrr
trr
Diode Forward Voltage
ISD = 5 A, VGS = 0 V
0.8
37
21
1
V
Reverse Recovery Charge
Reverse Recovery Time
nC
ns
VDS= 30 V, IF = 5A, di/dt = 300A/μs
4.2 Thermal Characteristics
(TA = 25°C unless otherwise stated)
PARAMETER
Junction-to-Lead Thermal Resistance(1)
Junction-to-Ambient Thermal Resistance(1)(2)
MIN
TYP
MAX
UNIT
°C/W
°C/W
RθJL
RθJA
20
75
(1)
R
θJC is determined with the device mounted on a 1-inch2 (6.45-cm2), 2-oz. (0.071-mm thick) Cu pad on a 1.5-inch × 1.5-inch (3.81-cm ×
3.81-cm), 0.06-inch (1.52-mm) thick FR4 PCB. RθJC is specified by design, whereas RθJA is determined by the user’s board design.
(2) Device mounted on FR4 material with 1-inch2 (6.45-cm2), 2-oz. (0.071-mm thick) Cu.
2
Copyright © 2014, Texas Instruments Incorporated
CSD88539ND
www.ti.com.cn
ZHCSC33 –FEBRUARY 2014
4.3 Typical MOSFET Characteristics
(TA = 25°C unless otherwise stated)
Figure 1. Transient Thermal Impedance
50
45
40
35
30
25
20
15
10
5
40
36
32
28
24
20
16
12
8
VDS = 5V
VGS =10V
VGS =8V
VGS =6V
TC = 125°C
TC = 25°C
TC = −55°C
4
0
0
0
0.2 0.4 0.6 0.8
1
1.2 1.4 1.6 1.8
2
0
1
2
3
4
5
6
VDS - Drain-to-Source Voltage (V)
VGS - Gate-to-Source Voltage (V)
G001
G001
Figure 2. Saturation Characteristics
Figure 3. Transfer Characteristics
Copyright © 2014, Texas Instruments Incorporated
3
CSD88539ND
ZHCSC33 –FEBRUARY 2014
www.ti.com.cn
Typical MOSFET Characteristics (continued)
(TA = 25°C unless otherwise stated)
10
10000
1000
100
10
Ciss = Cgd + Cgs
Coss = Cds + Cgd
Crss = Cgd
ID = 5A
VDS = 30V
9
8
7
6
5
4
3
2
1
0
1
0
1
2
3
4
5
6
7
8
0
6
12
18
24
30
36
42
48
54
60
Qg - Gate Charge (nC)
VDS - Drain-to-Source Voltage (V)
G001
G001
Figure 4. Gate Charge
Figure 5. Capacitance
3.6
3.4
3.2
3
60
54
48
42
36
30
24
18
12
6
ID = 250uA
TC = 25°C,I D = 5A
TC = 125°C,I D = 5A
2.8
2.6
2.4
2.2
2
0
−75
−25
25
75
125
175
0
2
4
6
8
10
12
14
16
18
20
TC - Case Temperature (ºC)
VGS - Gate-to- Source Voltage (V)
G001
G001
Figure 6. Threshold Voltage vs Temperature
Figure 7. On-State Resistance vs Gate-to-Source Voltage
2.2
2
100
VGS = 6V
VGS = 10V
TC = 25°C
TC = 125°C
10
1.8
1.6
1.4
1.2
1
1
0.1
0.01
0.8
0.6
0.4
0.001
0.0001
ID = 5A
175
−75
−25
25
75
125
0
0.2
0.4
0.6
0.8
1
TC - Case Temperature (ºC)
VSD − Source-to-Drain Voltage (V)
G001
G001
Figure 8. Normalized On-State Resistance vs Temperature
Figure 9. Typical Diode Forward Voltage
4
Copyright © 2014, Texas Instruments Incorporated
CSD88539ND
www.ti.com.cn
ZHCSC33 –FEBRUARY 2014
Typical MOSFET Characteristics (continued)
(TA = 25°C unless otherwise stated)
1000
100
10
1
TC = 25ºC
TC = 125ºC
10us
100us
1ms
10ms
DC
100
10
1
Single Pulse
Max RthetaJL = 20ºC/W
0.1
0.1
1
10
100
0.01
0.1
TAV - Time in Avalanche (mS)
1
VDS - Drain-to-Source Voltage (V)
G001
G001
Figure 10. Maximum Safe Operating Area
Figure 11. Single Pulse Unclamped Inductive Switching
18
15
12
9
6
3
0
−50 −25
0
25
50
75
100 125 150 175
TC - Case Temperature (ºC)
G001
Figure 12. Maximum Drain Current vs Temperature
Copyright © 2014, Texas Instruments Incorporated
5
CSD88539ND
ZHCSC33 –FEBRUARY 2014
www.ti.com.cn
5 Mechanical Data
5.1 SO-8 Package Dimensions
1. All linear dimensions are in inches (millimeters).
2. This drawing is subject to change without notice.
3. Body length does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs
shall not exceed 0.006 (0,15) each side.
4. Body width does not include interlead flash. Interlead flas shall not exceed 0.017 (0,43) each side.
5. Reference JEDEC MS-012 variation AA.
6
Copyright © 2014, Texas Instruments Incorporated
CSD88539ND
www.ti.com.cn
ZHCSC33 –FEBRUARY 2014
5.2 Recommended PCB Pattern and Stencil Opening
1. All linear dimensions are in millimeters.
2. This drawing is subject to change without notice.
3. Publication IPC-7351 is recommended for alternate designs.
4. Laser cutting apertures with trapezoidal walls and also rounding corners will offer better paste release.
Customers should contact their board assembly site for stencil design recommendations. Refer to IPC-7525
for other stencil recommendations.
5. Customers should contact their board fabrication site for solder mask tolerances between and around signal
pads.
Copyright © 2014, Texas Instruments Incorporated
7
CSD88539ND
ZHCSC33 –FEBRUARY 2014
www.ti.com.cn
6 Device and Documentation Support
6.1 Trademarks
NexFET is a trademark of Texas Instruments.
6.2 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
8
Copyright © 2014, Texas Instruments Incorporated
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Copyright © 2014, 德州仪器半导体技术(上海)有限公司
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
CSD88539ND
CSD88539NDT
ACTIVE
ACTIVE
SOIC
SOIC
D
D
8
8
2500 RoHS & Green
250 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-55 to 150
-55 to 150
88539N
88539N
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
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lines if the finish value exceeds the maximum column width.
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Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.189-.197
[4.81-5.00]
NOTE 3
.150
[3.81]
4X (0 -15 )
4
5
8X .012-.020
[0.31-0.51]
B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.010 [0.25]
C A B
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 - 8
.016-.050
[0.41-1.27]
DETAIL A
TYPICAL
(.041)
[1.04]
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED
METAL
EXPOSED
METAL
.0028 MAX
[0.07]
.0028 MIN
[0.07]
ALL AROUND
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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