DLPA100PT [TI]

DLP® driver for DLP660TE (0.66 4K UHD) DMD | DLP | 48 | 0 to 75;


型号：	DLPA100PT
厂家：	TEXAS INSTRUMENTS
描述：	DLP® driver for DLP660TE (0.66 4K UHD) DMD \| DLP \| 48 \| 0 to 75
文件：	总27页 (文件大小：1212K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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DLPA100

ZHCSFY9 –FEBRUARY 2017

DLPA100 电源管理和电机驱动器

1 特性

3 说明

•

3.3V 开关稳压器 - 逻辑电源

DLPA100 是一款专用电源管理和电机控制驱动器，适

用于 DLP^®4K UHD TRP 显示芯片组。DLPA100 与

DLP660TE 数字微镜器件和 DLPC4422 显示控制器共

同构成芯片组。这款解决方案非常适合需要高分辨率、

高亮度和系统简易性的显示系统。为了确保操作可靠

性，DLP660TE DMD 和 DLPC4422 显示控制器必须

始终与 DLPA100 电源管理和电机驱动器件搭配使用。

具有使能功能的 5V 开关稳压器 - 模拟电路电源

1.0V 至 3.3V 可调节开关稳压器 - 内核电源

具有使能功能的可调节线性稳压器 - 锁相环 (PLL)

电源

•

具有使能功能的可调节线性稳压器控制 - 模拟电源

2.5V 开关稳压器数字电源

电源序列控制

器件信息⁽¹⁾

电源监控电路

器件型号

DLPA100

封装

PT (48)

封装尺寸（标称值）

适用于高侧驱动的集成电荷泵

三个风扇驱动器

0.276mm x 0.276mm

(1) 要了解所有可用封装，请见数据表末尾的可订购产品附录。

热关断电路

串行通信接口

图 1. 典型应用图

三相反电动势 (BEMF) 电动机驱动器/控制器

电机电源开关稳压器

2 应用

•

4K 超高清 (UHD) 显示屏

激光电视 (TV)

数字标牌

投影映射

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

English Data Sheet: DLPS082

DLPA100

ZHCSFY9 –FEBRUARY 2017

www.ti.com.cn

特性.......................................................................... 1

Application and Implementation ........................ 17

8.1 Application Information............................................ 17

8.2 Typical Application ................................................. 17

Power Supply Recommendations...................... 19

应用.......................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 3

Pin Configuration and Functions......................... 4

Specifications......................................................... 7

6.1 Absolute Maximum Ratings ...................................... 7

6.2 Storage Conditions.................................................... 7

6.3 ESD Ratings ............................................................ 7

6.4 Recommended Operating Conditions....................... 7

6.5 Thermal Information.................................................. 7

6.6 Electrical Characteristics........................................... 8

Detailed Description ............................................ 11

7.1 Overview ................................................................. 11

7.2 Functional Block Diagram ....................................... 11

7.3 Feature Description................................................. 12

7.4 Device Functional Modes........................................ 16

10 Layout................................................................... 20

10.1 Layout Guidelines ................................................. 20

10.2 Grounding Guidelines ........................................... 20

10.3 Thermal Guidelines............................................... 22

10.4 Motor Control Guidelines ...................................... 22

10.5 Layout Example .................................................... 23

11 器件和文档支持 ..................................................... 24

11.1 器件标记................................................................ 24

11.2 文档支持 ............................................................... 24

11.3 社区资源................................................................ 24

11.4 商标....................................................................... 24

11.5 静电放电警告......................................................... 24

11.6 Glossary................................................................ 24

12 机械、封装和可订购信息....................................... 25

DLPA100

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ZHCSFY9 –FEBRUARY 2017

4 修订历史记录

日期

修订版本

注释

首次发布。

DLPA100

ZHCSFY9 –FEBRUARY 2017

www.ti.com.cn

5 Pin Configuration and Functions

( PT package)

(48 pin QFP)

Top View

DLPA100

www.ti.com.cn

ZHCSFY9 –FEBRUARY 2017

Pin Functions

I/O

DESCRIPTION

NAME

DOUT

CLK

NO.

Output

Input

Data Out for Serial Port

Clock for Serial Port

DIN

Input

Data In for Serial Port

Chip Select for Serial Port

Motor Speed Indication

CSZ

Input

TACH

OSC

Output

Input

Master Osc for Digital Timing – 2 MHz typical

Ground

GND

Ground

Input

GMIN

VBB

Motor Gm Input

Power

Output

Input

VBB Load Supply

VMSW

Motor Supply Switching Node

Motor Supply INPUT/FB

Motor Phase A

OUTA

CTAP

SENSE

OUTB

OUTC

CP2

Output

Input/Output Motor Centertap

Input

Output

Power

Ground

Power

Output

Motor Current Sensing

Motor Phase B

Motor Phase C

Charge Pump

CP1

Charge Pump

GND

Ground

VREG

VCP

Internal Bias Regulator Terminal

Charge Pump Reservoir Capacitor Terminal

VBB Load Supply

VBB

LX5

5V Regulator Switching Node

Power Input 5V Feedback and Logic Supply Input

Power Output Adjustable Core Regulator Switching Node

Power Output Gate Drive for Core Regulator

LXC

GDC

ISENK

ISEN

VLIN1

FBC

Input

Kelvin Sense for Core Regulator

Current Sense for Core Regulator

Power Output VLIN1 Linear Regulator Output

Power Input Adjustable Core Switching Regulator Feedback Node

Power Input VLIN1 Adjustable Feedback Node

Power Input VLIN2 Adjustable Feedback Node

Power Output VLIN2 Linear Gate Drive Output

FB1

FB2

GD2

POSENSE

PWRGOOD

PMDINTZ

VBB

Output

Power

Output

Power On Reset Output

Power Good Output

Interrupt Flag

Motor Supply Terminal

Fan 3 Switching Node Output

Fan 2 Switching Node Output

Fan 1 Switching Node Output

F3SW

F2SW

F1SW

LX25

VBB

Power Output 2.5V Regulator Switching Node

Power VBB Load Supply

Power Output 3.3V Regulator Switching Node

Ground Ground

LX33

GND

V3P3

V2P5

Power Input 3.3V Feedback

Power Input 2.5V Feedback

DLPA100

ZHCSFY9 –FEBRUARY 2017

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Pin Functions (continued)

I/O

DESCRIPTION

NAME

TRIM

NO.

Power

Input

Trim Pin (must be tied to VREG)

Forced Reset

RESETZ

DLPA100

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ZHCSFY9 –FEBRUARY 2017

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

PARAMETER

MIN

MAX

UNIT

VBB

t_ramp

Load Supply Voltage

Time to ramp from 0V to VBB

200

-1

µs

LX33, LXC, LX5, OUTA, OUTB, OUTC

Vin

Logic Inputs (RESETZ, CLK, DIN, CSZ, OSC)

Open Drain Logic Outputs (PWRGOOD, DOUT, POSENSE, PMDINTZ, TACH)

-0.3

Vout

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 Storage Conditions

MIN

MAX

UNIT

T_stg

Storage temperature

-55

150

°C

6.3 ESD Ratings

VALUE

UNIT

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

±2000

V_(ESD)

Electrostatic discharge

Charged-device model (CDM), per JEDEC specification JESD22-

C101⁽²⁾

±1000

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.4 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

NOM

MAX

UNIT

VBB

T_a

Load supply voltage

Operational ambient temperature

Maximum Operational junction temperature

°C

T_j

150

°C

6.5 Thermal Information

DLPA100

THERMAL METRIC⁽¹⁾

LQFP

48 PINS

UNIT

R_θJA

Junction-to-ambient thermal resistance

°C/W

R_θJC(top)

Junction-to-case (top) thermal resistance

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

DLPA100

ZHCSFY9 –FEBRUARY 2017

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6.6 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER

Supply Current

TEST CONDITIONS

MIN

TYP

MAX

UNIT

I_BB1

I_BB2

Motors and fans off

All Regulators Operating, I_load= 0

Supply Current

x3 fans = 100% mode @ 200 mA

load, VM = 100% mode @ 200 mA

I_BB3

2.7

CONTROL LOGIC

V_IL

Logic Input Voltage

(RESETZ, CLK, DIN, CSZ,

OSC)

0.8

V_IH

2.0

I_IL

V_IN= 5

V_IN= 0

-20

<1.0

µA

Logic Input Current

I_IH

<-1.0

Open Drain Logic Outputs

(PWRGOOD, DOUT,

POSENSE,PMDINTZ,

TACH)

Vlow

I = 4 mA

0.4

Logic Output Leakage

Current

Iout

V = 3.3 V

µA

CHARGE PUMP

V_CP

Output Voltage

Relative to VBB

7.25

5.5

VCP_uvlo

VCP Undervoltage

SWITCHING REGULATORS

Average Voltage, I_out = 0 mA to

1.6 A

V₅

Output Voltage V5

4.75

5.25

Rds5

Icl5

Buck Switch Rdson

Buck Switch Current Limit

Switching Frequency

Soft Start

T_j= 25°C

150

3.4

500

mΩ

2.8

450

4.0

525

Fsw

tss

kHz

Average Voltage, I_out = 0 mA to

1.6 A

V₃₃

Output Voltage V3P3

3.168

3.3

3.432

Rds33

Icl33

Fsw

Buck Switch Rdson

Buck Switch Current Limit

Switching Frequency

Soft Start

T_j= 25°C

300

2.8

500

mΩ

2.4

450

3.4

525

kHz

tss

Output Voltage VCORE

Range

V_core

1.0

3.3

Average Voltage, I_out = 200 mA to

3.7 A, using 0.5% tolerance

feedback resistors

V_c1

Output Voltage VCORE

-4.0

4.0

Average Voltage, I_out = 0 mA to

200 mA, using 0.5% tolerance

feedback resistors

V_c2

-4.0

4.8

6.0

6.5

Iclc

Buck Switch Current Limit

Gate Drive Rise Time

Isense Resistor = 100 mΩ

5.5

Cl = 500 pF, Vgs = 7 V (10% to

90%)

T_RISE

Cl = 500 pF, Vgs = 0 V (90% to

10%)

T_FALL

Gate Drive Fall Time

Fsw

tss

Switching Frequency

Soft Start

450

500

525

kHz

Average Voltage, I_out = 0 mA to

1.2 A

V₂₅

Output Voltage V2P5

2.4

2.5

2.6

Rds5

Icl5

Buck Switch Rdson

T_j= 25°C

300

2.1

mΩ

Buck Switch Current Limit

1.7

2.5

DLPA100

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ZHCSFY9 –FEBRUARY 2017

Electrical Characteristics (continued)

over operating free-air temperature range (unless otherwise noted)

PARAMETER

Switching Frequency

Soft Start

TEST CONDITIONS

MIN

450

TYP

500

MAX

525

UNIT

kHz

Fsw

tss

LINEAR REGULATORS

Output Voltage

VLIN1 Range

1.0

3.3

Average voltage relative to target, I

_load =2 mA to 75 mA, using 0.5%

tolerance feedback resistors

Vout

Output Voltage VLIN1

-3%

I_LIM

VLIN1 Current Limit

Ripple rejection

100

150

f = 120 Hz, Cout = 10 µF

Feedback Input Bias

Current

I_FB

tss

-400

-100

100

Soft Start

VLIN2 External

FET Supply

Voltage

1.7

1.0

5.5

3.3

Output Voltage

VLIN2 Range

Average voltage relative to target, I

_load = 10 mA to 1.2 mA, using

0.5% tolerance feedback resistors

Vout

Output Voltage VLIN1

Ripple rejection

-3%

I_FB

f = 120 Hz, Cout = 10 µF

-400

Feedback Input Bias

Current

-100

100

tss

Soft Start

FAN CONTROLLERS

F_pwm

PWM switching frequency

Controlled by DLPC4422 Software

100

kHz

F_pwm

Duty Cycle LSB

Rds

500

875

Rdson Buck Switch

I = 200 mA

Current Limit

550

Current Limit

Blanking

Controlled by DLPC4422 Software

µs

COLOR WHEEL SWITCHING REGULATOR SUPPLY

Average Voltage, I_out = 0 mA to

Output Voltage

maximum programmed load current.

Buck inductor = 33 µH

-5%

Rds

Icl

Buck Switch Rdson

Buck Switch Current Limit

Fixed off-time

T_j= 25°C

500

1.33

4.7

mΩ

relative to target programmed value

VM >6 V

-20%

20%

T_off

tss

µs

Fixed off-time

2.6 V < VM <4.0 V

VM < 1.5 V

Fixed off-time

Soft Start

COLOR WHEEL MOTOR DRIVER

Pdm

Rdson

Power Dissipation

Source Driver Rdson

Sink Driver

1.0

600

700

1.4

mΩ

I = 1 A

400

500

Drive Current

Brake Current

2.5

DLPA100

ZHCSFY9 –FEBRUARY 2017

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Electrical Characteristics (continued)

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

For brake current to change from

maximum value (2.5 A) to the

maximum drive current (1.4 A)

Brake Period

800

Controlled by DLPC4422 Software

125

250

0.5

Kgm

Vos

Gm Constant

Offset

MHz

Bemf Comp Hysteresis

OSC (Motor Oscillator)

OSC High Period

OSC Low Period

Vctap = 1.5 V to 6 V

Fosc

100

MOTOR CHARACTERISTICS

Rload

Load Resistance

Phase to Phase

1.5

Poles

rpm

µs

Poles

7200

Poles = 12 or 16

Poles = 4 or 8

2880

11160

14880

1736

Speed

Commutation Period -

(60/[Speed(rpm) × 3 ×

#Poles])

4-Pole at 2880 rpm

16-Pole at 11160 rpm

112

µs

4-Pole at 14880 rpm

8-Pole at 14880 rpm

12-Pole at 11160 rpm

16-Pole at 11160 rpm

112

µs

Time Constant - Phase to

Phase inductance divided

by Phase-to-Phase

resistance

L/R

DLPA100

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ZHCSFY9 –FEBRUARY 2017

7 Detailed Description

7.1 Overview

The DLPA100 is a power management and motor driver IC optimized for DLP video and data display systems

and meant for use in either embedded or accessory projector applications. DLPA100 is part of the chipset

comprising of the DLP660TE DMD and DLPC4422 controller.

7.2 Functional Block Diagram

DLPA100

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7.3 Feature Description

7.3.1 Power Up Sequencing

Once the VBB voltage reaches the VBB_uvsdthreshold (specification defined in Shutdown), the VCORE channel

soft-starts within a period of 5 ms typical (tss). Once this period is completed and the VCORE_uvlohas been

reached, the V3P3 and V2P5 rails soft-start, ramping up ratiometrically. Once each of the three rails are above

their respective undervoltage lockout levels (VCORE_uvlo, V3P3_uvlo, V2P5_uvlo), the POSENSE flag will go high after

a period of 150 ms typical (T_por) and also, the VLIN1, VLIN2, V5 and VM rails soft-start, ramping up

ratiometrically. Note that VLIN1, VLIN2, V5 and VM can be individually disabled via the serial port, although

VLIN1 and VLIN2 require V5 to be present.

The PWRGOOD flag will go high once the POSENSE is high and the VBB voltage is above the undervoltage

lockout threshold VBB_uvlo

Figure 2. Power Up Sequencing Timing Diagram

DLPA100

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ZHCSFY9 –FEBRUARY 2017

Feature Description (continued)

7.3.2 Power Down Sequencing

If VBB drops below the undervoltage level (VBB_uvlo), the PWRGOOD will flag. If VBB drops below the

undervoltage level (VBB_uvsd), all the switcher and linear channels will turn off and the output rails will be supplied

by the output filter capacitors. The duration between VBB_uvloand VBB_uvsdallows sufficient ‘hold up’ time to ‘park’

the DMD mirrors. Although the regulators can supply rated current down to VBB_uvsd, they can only provide this

power for a maximum of 0.5 ms.

If either of the rails: VCORE or V3P3 or V2P5 drop below their respective undervoltage levels, the POSENSE

and PWRGOOD will flag immediately.

Figure 3. Power Down Sequencing Timing Diagram

7.3.3 Shutdown

In the event of a fault either due to excessive junction temperature, or low voltage on VCP, or low voltage on

VREG, or low VBB voltage, each switcher and linear channel is disabled.

A low VBB voltage, VBB_uvsdin this case, shuts down the DLPA100, protecting it from excessive power

dissipation. An undervoltage power monitoring flag, PWRGOOD is also provided, to indicate when the VBB

voltage is operating in and out of normal operating range.

7.3.3.1 Thermal

An overtemperature monitor provides a warning when the junction temperature reaches 130°C. The DLPA100 is

protected from excessive temperatures by an internal circuit that will shut the device down immediately the

junction temperature reaches 165°C. As soon as the temperature drops below the hysteresis level, the regulators

will start-up again under soft-start control, assuming all other conditions are met (VCP, VBB etc.).

7.3.4 System Reset

The DLPA100 device can be reset by using the RESETZ input. This feature can be used during start-up

conditions to reset the serial port registers to a known set of states. It can also be used during power-down

conditions to disable certain features before complete shutdown occurs. The DLPC4422 display controller

software controls which functions are reset to the power on reset (POR) state when RESETZ is initiated.

•

MSKFAN: Masks the reset of the 3 fan drivers (POR state = disabled, PWM=0%).

MSKREG: Masks the reset of linear regulators VLIN1 & VLIN2, and 5V switcher (POR state = enabled).

MSKMOT: Masks the reset of the motor controller configuration registers (POR state = 0).

MSKMOTE: Masks the reset of the motor controller output enable bit (POR state = disabled).

DLPA100

ZHCSFY9 –FEBRUARY 2017

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Feature Description (continued)

7.3.5 Interrupt Logic

PMDINTZ is an active low open drain output that will be asserted if the DLPA100 goes into thermal shutdown at

165°C. The open drain output is held low by using the DLPA100 internal regulator even though the rest of the

DLPA100 device is shut down. This internal regulator only depends on 12 V being operational to allow retention

of the data in the latched status registers if any of the supplies are lost. PMDINTZ is primarily used as an

interrupt to the DLP controller but can also be used to drive an LED overtemp indicator on the projector.

The thermal warning signal (TWARN) can also trigger an interrupt if enabled. Over-current events for the three

DLP controller supplies can also cause PMDINTZ to go low. The DLP controller processor can clear or set

PMDINTZ by writing to the latches that capture the interrupts. The DLP controller can also mask any of the

interrupts (except TSD) via the enable interrupt register.

The raw status register can be read back in real time to monitor the fault condition. If the faults are present for a

valid time, they will be latched into the latched status register.

7.3.6 Serial Communications Port

The Serial communications port (SCP) is a full duplex, synchronous, character-oriented byte port that allows

exchange of data between the DLP controller (master) and the DLPA100.

Table 1. Serial Communications Port Signal Definitions

SIGNAL

I/O

FROM/TO

TYPE

DESCRIPTION

SCP bus master to

slave

SCP bus serial transfer clock. The host processor (master)

generates this clock.

SCPK

LVTTL compatible

SCP bus access enable (low true). When high, slave will

reset to idle state, and SCPDO output will tri-state. Pulling

SCPENZ low initiates a read or write access. SCPENZ must

remain low for an entire read/write access, and must be

pulled high after the last data cycle. To abort a read or write

cycle, pull SCPENZ high at any point.

SCP bus master to

slave

SCPENZ

LVTTL compatible

SCP bus master to

slave

SCP bus serial data input. Data bits are valid and must be

clocked in on the falling edge of SCPCK.

SCPDI

LVTTL compatible

SCP bus slave to

master

LVTTL open drain w/tri- SCP bus serial data output. Data bits must clocked out on the

state rising edge of SCPCK.

SCPDO

Table 2. Serial Interface Timing Requirements

SYMBOL

CHARACTERISTICS

TEST CONDITIONS

MIN

NOM

MAX

UNIT

Setup CSZ low to CLK

Reference to rising edge of CLK

360

Nominally 1 CLK cycle rising edge to

rising edge

Byte to Byte Delay

1.9

µs

Setup DIN to CSZ High

CLK Frequency

Last byte to slave disable

360

kHz

µs

526

CLK Period

1.9

300

CLK High or Low Time

DIN Set-Up Time

Reference to falling edge of CLK

Reference from falling edge of CLK

Reference from rising edge of CLK

DIN Hold Time

DOUT Propogation Delay

CLK Filter (pulse reject)

300

200

DLPA100

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ZHCSFY9 –FEBRUARY 2017

Figure 4. Serial Communications Port Timing Diagram

7.3.7 Switching Regulators

The DLPA100 has four fixed frequency current mode control buck regulators that are used to provide power to

integrated circuits in the system. The V5 regulator is used to power control functions in the DLPA100, as well as

power the VLIN1 and VLIN2 linear regulators.

The regulators require external fly back diodes, inductors and filter capacitors. Due to the high currents in the

VCORE regulator, an external FET and sense resistor are required. The regulators will operate in both

continuous and discontinuous mode. An internal blanking circuit will be used to filter out transients due to the

reverse recovery of the external clamp diode.

7.3.7.1 Output Voltage - VOUT

All of the switchers apart from VCORE are regulated with respect to a 1.2 V reference (V_FB). As the Core

Regulator (VCORE) output voltage is adjustable from 1.0 V to 3.3 V the internal reference for this output is 0.8 V.

Vout = V_FB× (1 + R1/R2)

(1)

7.3.7.2 Adjustable Linear Regulator - VLIN1

This low dropout type regulator features current limit for a shorted load. It includes an integrated n-channel pass

element and can work with either ceramic or electrolytic output capacitors. The output can range between 1.0 V

and 3.3 V. The output voltage of the adjustable regulator is set by:

VLIN1 = V_FB× (1+R1/R2) + (I_FB× R2)

where

•

V_FB= 0.8 V

(2)

7.3.7.3 Adjustable Linear Regulator Control - VLIN2

An additional linear regulator is implemented with external n-channel pass element. The output can range

between 1.0 V and 3.3 V. The output voltage of the adjustable regulator is set by:

VLIN2 = V_FB× (1+R3/R4) + (I_FB× R4)

where

•

V_FB= 0.8 V

(3)

DLPA100

ZHCSFY9 –FEBRUARY 2017

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7.3.8 Fan Controllers

The DLPA100 has three outputs available to be used as the switching node for either voltage mode step down

switcher or ‘direct drive’ schemes. The output voltage is determined by a PWM value programmed using the

DLPC4422 display controller software. The switching frequency for each output can be programmed using the

DLPC4422 display controller software for either 100 kHz for applications requiring a step-down switcher, or 24

Hz in applications that can utilize a direct drive scheme. The drivers in the ‘direct drive’ scheme are connected to

the corresponding fans via a series resistor.

The default condition at start-up will be separate control of each fan control channel and 100kHz switching

frequency.

7.3.9 Color Wheel Motor Driver

The driver system is a three phase BEMF sensing motor controller and driver. Commutation is controlled by a

proprietary BEMF sensing technique. It eliminates many external passive components and provides flexibility by

allowing various timing parameters to be programmed via the serial port.

7.3.9.1 Color Wheel Motor Driver Power Dissipation

The maximum allowable power dissipation on motor driver is specified in the color wheel motor driver table.

Motor driver power dissipation can be calculated as follows:

Pdm = [VM – (KE × Sm) – Ispd × Rpp] × Ispd

where

•

Pdm = Power dissipation of motor driver

VM = Programmed output voltage of the motor supply

KE = Motor voltage constant in Volts/(rad/sec)

Sm = Motor speed in rad/sec

Ispd = Motor current at Sm speed

Rpp = Phase-to-phase motor resistance

(4)

7.3.10 Color Wheel Switching Regulator Supply

A fixed off time switching regulator is included to manage power dissipation for driving color wheels. For highly

resistive motors requiring a low running current, Irun < 75 mA, using this regulator may not be required, in which

case VM should be connected directly to VBB and the external inductor, capacitor & Schottky diode do not need

to be fitted.

7.4 Device Functional Modes

DLPA100 device functional modes are controlled by the DLPC4422 display controller. See the DLPC4422

display controller datasheet or contact a TI applications engineer.

DLPA100

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8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

8.1 Application Information

Texas Instruments DLP technology is a micro-electro-mechanical systems (MEMS) technology that modulates

light using a digital micromirror device (DMD). DMDs vary in resolution and size and can contain over 8 million

micromirrors. Each micromirror of a DMD can represent either one or more pixels on the display and is

independently controlled, synchronized with color sequential illumination, to create stunning images on any

surface. DLP technology enables a wide variety of display products worldwide, from tiny projection modules

embedded in smartphones to high powered digital cinema projectors, and emerging display products such as

digital signage and laser TV.

In display applications using the DLP660TE DMD the DLPA100 provides all needed analog functions including

the analog power supplies and the color wheel motor driver to provide a robust and efficient display solution.

8.2 Typical Application

When the DLPA100 power management device is combined with two display controllers (DLPC4422), an FPGA,

and other electrical, optical and mechanical components the chipset enables bright, affordable, full 4K UHD

display solutions. The DLPA100 power management and motor driver provides power supply sequencing and

controls the color wheel motors, laser and LED currents as required by the application. A typical 4K UHD system

application is shown in Figure 5.

Figure 5. Typical 4K UHD Projector Application

8.2.1 Design Requirements

At the high level, DLP660TE DMD systems will include an illumination source, a light engine, electronic

components, and software. The designer must first choose an illumination source and design the optical engine

taking into consideration the relationship between the optics and the illumination source. The designer must then

understand the electronic components of a DLP660TE DMD system. A display projector is created by using a

DLP chipset comprised of DLP660TE DMD, DLPC4422 controller and DLPA100 power and motor driver. The

DLPC4422 does the digital image processing, the DLPA100 provides the needed analog functions for the

projector, and the DMD is the display device for producing the projected image.

DLPA100

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Typical Application (continued)

8.2.2 Detailed Design Procedure

For connecting together the DLPC4422 digital display controller, the DLP660TE DMD, and the DLPA100, see the

reference design schematic. Layout guidelines should be followed to achieve a reliable projector. To complete

the DLP system an optical module or light engine is required that contains the DLP660TE DMD, associated

illumination sources, optical elements, and necessary mechanical components.

8.2.3 Application Curves

Figure 6. Luminance vs. Current

DLPA100

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9 Power Supply Recommendations

The DLPA100 is designed to operate from a 12-V input voltage supply or battery. To avoid insufficient supply

current due to line drop, ringing due to trace inductance at the VIN terminal, or supply peak current limitations,

additional bulk capacitance may be required. If ringing occurs an electrolytic or tantalum type capacitor may be

needed for damping. The amount of bulk capacitance required should be evaluated such that the input voltage

can remain in specification long enough for a proper fast shutdown to occur as shown in Figure 3. The shutdown

begins when the input voltage drops below the programmable UVLO threshold, such as when the external power

supply or battery supply is suddenly removed from the system.

DLPA100

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10 Layout

10.1 Layout Guidelines

The 12-V supply, VBB, should be provided on a separate plane, or portion of a shared power distribution plane.

Each ceramic filter capacitor should be placed as close as possible to each VBB terminal: pins 9, 22, 37 and 42.

The additional reservoir capacitor should also be placed as close as possible to the VBB terminals. The ground

for VBB should be routed directly to the DLPA100 thermal pad connection.

The PWB traces used on the switching regulators should be as short and wide as possible. The electrical loops

formed between the VBB filter capacitors, input switch (LX pins), inductor, output capacitor and the diode should

be as small as possible.

An adjacent layer ground region covering the entire switching node should be provided for the pins: LXC (pin 25),

LX5 (pin 23), LX33 (pin 43), LX25 (pin 41), and VMSW (pin10). Each of the switching nodes and all associated

components should be located as near the DLPA100 device as possible.

Avoid routing any noise sensitive signals near the DLPA100 device switching nodes and associated ground

regions. The sensitive pins on the DLPA100 device consist of pins 1, 2, 3, 4, 5, 6, 8, and 48. If sensitive signals

must be routed across the switching loops, use subdivided planes and/or multiple ground planes to avoid

interference. Use of shielded inductors on the switching regulator circuits will minimize the possibility of crosstalk

and interference.

High current paths should have an adequate number of vias to minimize resistance and inductance. Placement

and routing priority should be given to the higher current circuits. For example, the VCORE supply should take

precedence over a fan PWM output. The following is the order of precedence from highest to lowest:

1. VCORE

2. V5

3. V3P3

4. V2P5

5. VM

6. VLIN2

7. VLIN1

8. FAN1, FAN2, FAN3

Suitable kelvin connections should be provided for the regulator feedback pins: FBC (pin 30), V2P5 (pin 46),

V3P3 (pin 45), V5 (pin 24), FB1 (pin 31) & FB2 (pin 32) and for sense pins: SENSE (pin 14), ISEN (pin 28) &

ISENK (pin 27). Also note that the external feedback networks used for the VCORE and VLIN1 regulators should

also deploy kelvin connections. The feedback pin traces FBC, FB1, FB2 are most prone to interference and

should be located near the DLPA100 device.

10.2 Grounding Guidelines

Ground pin 19 is isolated internally to the DLPA100 from pins 7 and 44. All three ground pins should be tied

together on the PWB at the DLPA100 thermal pad connection. Depending on the application there are three

grounding approaches for board layout:

1. Completely isolated ground regions for the DLPA100 subcircuits.

2. Single isolated ground region for the collective DLPA100 circuit.

3. Non-isolated common ground region for the entire board.

The most favorable approach should be carefully considered for the specific application.

DLPA100

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Grounding Guidelines (continued)

10.2.1 Completely Isolated Ground Regions

In this case, the PWB has an isolated ground layer around the DLPA100 circuit which serves as a “noisy” ground

for the motor driver, switchers, and linear regulators. This plane can be subdivided into isolated sections around

each switcher, linear regulator and motor block to minimize the possibility of noise crosstalk between the

regulator circuits. See Figure 7. Each isolated section should be connected in a “star” configuration at the

DLPA100 thermal pad position. An additional “quiet” solid ground plane should be provided on a separate layer

for reference to the sensitive blocks of the DLPA100 device and other sensitive external circuitry. The sensitive

pins on the DLPA100 device are pins 1, 2, 3, 4, 5, 6, 8, and 48. The quiet ground plane should connect to the

DLPA100 device with the array of thermal vias.

Figure 7. Noisy Ground Layer

Figure 8. PWB Planes

10.2.2 Single Isolated Ground Region

In this case, the PWB has a single isolated ground layer around the DLPA100 circuit. This ground layer serves

as a “noisy” ground for the switchers, linear regulators, and motor driver. An additional “quiet” solid ground plane

should be provided on a separate layer for reference to the sensitive blocks of the DLPA100 and other sensitive

external circuitry. Connect the “quiet” and “noisy” ground planes at the DLPA100 thermal pad array of vias.

10.2.3 Non-isolated Common Ground Region

In this case, the PWB has a solid non-isolated common ground layer for the entire board. In this configuration,

use particular care during component placement and separate the noisy portions of the DLPA100 circuit from

other sensitive signals on the board. The ground plane should connect to the DLPA100 with the array of thermal

vias.

DLPA100

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10.3 Thermal Guidelines

The PWB should have a thermal pad underneath the DLPA100 on both the top and bottom layers. The thermal

pad on the top layer should extend to the edge of the terminal pads and include a 4x4 array of thermal vias.

These thermal pads should connect to the internal ground planes via the thermal vias. It is recommended that

the internal ground plane should extend for at least 20 square inches.

Careful consideration should be taken in providing an adequate amount of copper traces around the discrete

Schottky diodes and MOSFET terminals used in the switching and linear converters to ensure proper thermal

management. The thermal impedance (T_j-a) of each component should be calculated to determine the

corresponding amount of copper required. If using an internal plane, it is important to use an array of thermal

vias underneath the device tab or terminal to assist in the transfer of the heat.

10.4 Motor Control Guidelines

The DLPA100 motor control terminals should be filtered with voltage transient suppressing devices for improved

startup reliability and noise immunity. Schottky diodes should be placed cathode to anode between VBB to motor

terminals OUTA (pin 12), OUTB (pin 15), OUTC (pin 16) and CTAP (pin 13). Schottky diodes should also be

placed cathode to anode between motor terminals OUTA (pin 12), OUTB (pin 15), OUTC (pin 16) and CTAP (pin

13) to ground. Series RC snubbers consisting of a capacitor (0.001 μF) in series with a resistor (150 Ω) should

be placed between the motor terminals OUTA (pin12), OUTB (pin 15), and OUTC (pin 16) to CTAP (pin 13).

The value of the motor current sensing resistor on SENSE (pin 14) should be thoroughly evaluated for the

application. Careful consideration should be taken in the amount of current draw during motor startup and

braking with respect to the speed range and speed change timing requirements. It is recommended that the

SENSE (pin 14) voltage does not exceed 450 mV. Most motors from today’s modern technology have relatively

low operating currents but higher start-up currents which make it very difficult to achieve good signal to noise

ratio during operating range and meet the 450 mV maximum on SENSE (pin 14). Most motors have

demonstrated success well below 100 mV steady-state SENSE (pin 14) voltage. As long as good layout and

component selection practices are followed, acceptable signal to noise ratios can be achieved at such low

operating SENSE (pin 14) voltages. The typical SENSE resistor value ranges from 0.47 Ω to 2.2 Ω. A 1.0-Ω

SENSE resistor value is suggested as a good starting point. Typically the steady-state SENSE (pin 14) voltage

with a 1.0-Ω resistor will be near 100 mV.

DLPA100

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10.5 Layout Example

Figure 9. Top Layer

DLPA100

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11 器件和文档支持

11.1 器件标记

图 10. 器件标记

11.2 文档支持

11.2.1 相关文档ꢀ

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