DS90UB914QSQ/NOPB [TI]
10MHz 至 100MHz、10/12 位 FPD-Link III 解串器 | RHS | 48 | -40 to 105;
| 型号： | DS90UB914QSQ/NOPB |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 10MHz 至 100MHz、10/12 位 FPD-Link III 解串器 | RHS | 48 | -40 to 105 光电二极管 |
| 文件： | 总72页 (文件大小：1227K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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DS90UB913Q-Q1, DS90UB914Q-Q1
ZHCSDZ6D –JULY 2012–REVISED JULY 2015
DS90UB91xQ-Q1 具有双向控制通道的 10MHz 至 100MHz、10 位和 12
位直流均衡 FPD-Link III 串行器和解串器
1 特性
– 接收器交错输出
1
•
•
•
10MHz 至 100MHz 输入像素时钟支持
2 应用
单个差分对互连
•
•
前置摄像头或后置摄像头，实现碰撞缓解
停车辅助系统环视
可编程的数据有效载荷：
–
–
10 位有效载荷，高达 100MHz
12 位有效载荷，高达 75MHz
3 说明
•
•
•
连续低延迟双向控制接口通道，支持 I2C，频率达
DS90UB91xQ-Q1 芯片组提供一个具有高速正向通道
和双向控制通道的 FPD-Link III 接口，用来实现单一差
分对上的数据传输。 DS90UB91xQ-Q1 芯片组的高速
正向通道和双向控制通道数据路径上均包含差分信令。
串行器和解串器对主要用于电子控制单元 (ECU) 中成
像器与视频处理器的连接。 该芯片组非常适用于驱动
需要高达 12 位像素深度、2 个同步信号以及双向控制
通道总线的视频数据。
400kHz
2:1 多路复用器，可在两个输入成像器之间进行选
择
具有直流均衡编码的嵌入式时钟，支持交流耦合互
连
•
•
•
能够驱动长达 25 米的屏蔽双绞线
接收均衡器自动适应电缆损耗的变化
串行器和解串器上均提供有 4 个专用通用输入/输出
引脚 (GPIO)
解串器上有一个多路复用器，可用于在两个输入成像器
之间进行选择。 解串器只能激活一个输入成像器。 主
视频传输将 10 位和 12 位数据转换为单条高速串行数
据流，另外一个独立的低延迟双向控制通道传输负责接
收来自 I2C 端口的控制信息，与视频消隐期无关。
•
LOCK 输出报告引脚和 AT-SPEED BIST（全速内
置自检）诊断特性，可验证链路完整性
•
•
•
串行器上提供 1.8V、2.8V 或 3.3V 兼容并行输入
1.8V 单电源
符合 ISO 10605 和 IEC 61000-4-2 静电放电
(ESD) 标准
器件信息(1)
•
•
•
•
汽车级产品：符合 AEC-Q100 2 级要求
温度范围：-40°C 至 +105°C
器件型号
封装
WQFN (32)
WQFN (48)
封装尺寸（标称值）
5.00mm x 5.00mm
7.00mm x 7.00mm
DS90UB913Q-Q1
DS90UB914Q-Q1
小尺寸串行器 (5mm × 5mm)
解串器上提供 EMI/EMC 缓解功能
(1) 要了解所有可用封装，请见数据表末尾的可订购产品附录。
–
可编程扩频 (SSCG) 输出
典型应用电路
Parallel
Data In
Parallel
Data Out
FPD-Link III
10 or 12
10 or 12
2
2
DSP, FPGA/
µ-Processor/
ECU
HSYNC,
VSYNC
4
Megapixel
Imager/Sensor
HSYNC,
VSYNC
4
DS90UB913Q
DS90UB914Q
Bidirectional
Control Channel
GPO
2
GPIO
2
Bidirectional
Control Bus
Bidirectional
Control Bus
Serializer
Deserializer
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SNLS420
DS90UB913Q-Q1, DS90UB914Q-Q1
ZHCSDZ6D –JULY 2012–REVISED JULY 2015
www.ti.com.cn
目录
9.1 AC Timing Diagrams and Test Circuits................... 20
10 Detailed Description ........................................... 25
10.1 Overview ............................................................... 25
10.2 Functional Block Diagram ..................................... 25
10.3 Feature Description............................................... 26
10.4 Device Functional Modes...................................... 33
10.5 Register Maps....................................................... 41
11 Application and Implementation........................ 56
11.1 Applications Information........................................ 56
11.2 Typical Application ................................................ 56
12 Power Supply Recommendations ..................... 60
13 Layout................................................................... 60
13.1 Layout Guidelines ................................................. 60
13.2 Layout Example .................................................... 61
14 器件和文档支持 ..................................................... 63
14.1 文档支持 ............................................................... 63
14.2 相关链接................................................................ 63
14.3 社区资源................................................................ 63
14.4 商标....................................................................... 63
14.5 静电放电警告......................................................... 63
14.6 Glossary................................................................ 63
15 机械、封装和可订购信息....................................... 63
1
2
3
4
5
6
7
8
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
说明（续）............................................................... 3
器件比较表............................................................... 3
Pin Configuration and Functions......................... 4
Specifications......................................................... 9
8.1 Absolute Maximum Ratings ...................................... 9
8.2 ESD Ratings.............................................................. 9
8.3 Recommended Operating Conditions....................... 9
8.4 Thermal Information................................................ 10
8.5 Electrical Characteristics ........................................ 10
8.6 Timing Requirements: Recommended for Serializer
PCLK ....................................................................... 14
8.7 AC Timing Specifications (SCL, SDA) - I2C
Compliant................................................................. 15
8.8 Bidirectional Control Bus DC Timing Specifications
(SCL, SDA) - I2C Compliant..................................... 15
8.9 Switching Characteristics: Serializer....................... 16
8.10 Switching Characteristics: Deserializer................. 17
8.11 Typical Characteristics.......................................... 19
Parameter Measurement Information ................ 20
9
4 修订历史记录
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (January 2014) to Revision D
Page
•
已添加引脚配置和功能部分，ESD 额定值表，特性描述部分，器件功能模式，应用和实施部分，电源相关建议部分，
布局部分，器件和文档支持部分以及机械、封装和可订购信息部分........................................................................................ 1
已更新数据表以符合新的 TI 布局............................................................................................................................................ 1
Added text and graphic to Power Up Requirements ........................................................................................................... 39
•
•
Changes from Revision B (April 2013) to Revision C
Page
•
Changed "PCLK from imager mode" value in DS90UB913Q Serializer MODE Resistor Value table from 0 kΩ to 100
kΩ ......................................................................................................................................................................................... 35
Changed Falling to Rising in RRFB...................................................................................................................................... 47
Changed Rising to Falling in RRFB...................................................................................................................................... 47
•
•
Changes from Revision A (April 2013) to Revision B
Page
•
Changed layout of National Data Sheet to TI format ........................................................................................................... 61
2
版权 © 2012–2015, Texas Instruments Incorporated
DS90UB913Q-Q1, DS90UB914Q-Q1
www.ti.com.cn
ZHCSDZ6D –JULY 2012–REVISED JULY 2015
5 说明（续）
凭借德州仪器 (TI) 的嵌入式时钟技术，可在单一差分对上进行透明的全双工通信，两个方向上运载不对称的双向控
制通道信息。 这种单一串行数据流通过消除并行数据与时钟路径间的偏差，简化了印刷电路板 (PCB) 走线和电缆
上的宽数据总线传输。 这样，通过限制路径的宽度，大大节省了系统成本，相应地减少了 PCB 层数、电缆宽度以
及连接器尺寸和引脚数量。 此外，解串器输入还提供自适应均衡功能来补偿较长距离介质上的损耗。 内部直流均
衡编码和解码被用来支持交流耦合互连。 此串化器采用 32 引脚超薄型四方扁平无引线 (WQFN) 封装，而解串器采
用 48 引脚 WQFN 封装。
6 器件比较表
器件编号
FPD-III 功能
串行器
封装
传输介质
STP
PCLK 频率
DS90UB913Q-Q1
DS90UB913A-Q1
DS90UB914Q-Q1
DS90UB914A-Q1
32 引脚 RTV (WQFN)
32 引脚 RTV (WQFN)
48 引脚 RHS (WQFN)
48 引脚 RHS (WQFN)
10MHz 至 100MHz
25MHz 至 100MHz
10MHz 至 100MHz
25MHz 至 100MHz
串行器
同轴或屏蔽双绞线 (STP)
STP
解串器
解串器
同轴或 STP
Copyright © 2012–2015, Texas Instruments Incorporated
3
DS90UB913Q-Q1, DS90UB914Q-Q1
ZHCSDZ6D –JULY 2012–REVISED JULY 2015
www.ti.com.cn
7 Pin Configuration and Functions
RTV Package
32-Pin WQFN
Top View
24
23
22
21
20
19
18
17
VDDIO
DIN[6]
GPO[1]
GPO[0]
VDDCML
DOUT+
DOUT-
VDDT
DAP = GND
DIN[7]
VDDD
DS90UB913Q
Serializer
DIN[8]
DIN[9]
VDDPLL
DIN[10]
DIN[11]
PDB
1
2
3
4
5
6
7
8
DS90UB913Q-Q1 Serializer Pin Functions
PIN
I/O
DESCRIPTION
NAME
NO.
LVCMOS PARALLEL INTERFACE
19, 20, 21,
22, 23, 24,
26, 27, 29,
30, 31, 32
Inputs,
LVCMOS
with pulldown
DIN[0:11]
Parallel data inputs
Inputs,
LVCMOS
with pulldown
HSYNC
PCLK
1
Horizontal SYNC input
Input, LVCMOS Pixel clock input pin
with pulldown
3
2
Strobe edge set by TRFB control register.
Inputs,
LVCMOS
VSYNC
Vertical SYNC input
with pulldown
4
Copyright © 2012–2015, Texas Instruments Incorporated
DS90UB913Q-Q1, DS90UB914Q-Q1
www.ti.com.cn
ZHCSDZ6D –JULY 2012–REVISED JULY 2015
DS90UB913Q-Q1 Serializer Pin Functions (continued)
PIN
I/O
DESCRIPTION
NAME
NO.
GENERAL-PURPOSE OUTPUT (GPO)
General-purpose output pins can be configured as outputs; used to control and respond
to various commands. GPO[0:1] can be configured to be the outputs for input signals
coming from GPIO[0:1] pins on the deserializer or can be configured to be outputs of
the local register on the serializer.
Output,
LVCMOS
GPO[1:0]
16, 15
GPO2 pin can be configured to be the output for input signal coming from the GPIO2
pin on the deserializer or can be configured to be the output of the local register on the
serializer. It can also be configured to be the output clock pin when the DS90UB913Q-
Q1 device is used in the External Oscillator mode. See Applications Information for a
detailed description of the DS90UB91xQ-Q1 chipsets working with the external
oscillator.
GPO[2]/
CLKOUT
Output,
LVCMOS
17
GPO3 can be configured to be the output for input signals coming from the GPIO3 pin
on the deserializer or can be configured to be the output of the local register setting on
the serializer. It can also be configured to be the input clock pin when the
DS90UB913Q-Q1 serializer is working with an external oscillator. See Applications
Information section for a detailed description of the DS90UB91xQ-Q1 chipsets working
with an external oscillator.
GPO[3]/
CLKIN
Input/Output,
LVCMOS
18
BIDIRECTIONAL CONTROL BUS - I2C COMPATIBLE
Input/Output,
Open-Drain
Clock line for the bidirectional control bus communication
SCL requires an external pullup resistor to VDDIO
SCL
SDA
4
5
.
Input/Output,
Open-Drain
Data line for the bidirectional control bus communication
SDA requires an external pullup resistor to VDDIO
.
Device mode select
Input, LVCMOS Resistor to Ground and 10-kΩ pullup to 1.8-V rail. MODE pin on the serializer can be
MODE
8
with pulldown
Input, analog
used to select whether the system is running off the PCLK from the imager or an
external oscillator. See details in Table 3.
Device ID address select
ID[x]
6
The ID[x] pin on the serializer is used to assign the I2C device address. Resistor to
Ground and 10-kΩ pullup to 1.8-V rail. See Table 1.
CONTROL AND CONFIGURATION
Power down Mode Input Pin
PDB = H, serializer is enabled and is ON.
Input, LVCMOS
with pulldown
PDB
RES
9
7
PDB = L, Serailizer is in power-down mode. When the serializer is in power-down, the
PLL is shutdown, and IDD is minimized. Programmed control register data are NOT
retained and reset to default values
Input, LVCMOS Reserved
with pulldown
This pin MUST be tied LOW.
FPD-Link III INTERFACE
Input/Output,
CML
Noninverting differential output, bidirectional control channel input. The interconnect
must be AC-coupled with a 100-nF capacitor.
DOUT+
DOUT–
13
12
Input/Output,
CML
Inverting differential output, bidirectional control channel input. The interconnect must be
AC-coupled with a 100-nF capacitor.
POWER AND GROUND
VDDPLL
VDDT
10
11
14
28
Power, Analog PLL Power, 1.8 V ±5%
Power, Analog Tx Analog Power, 1.8 V ±5%
Power, Analog CML and bidirectional channel driver power, 1.8 V ±5%
Power, Digital Digital power, 1.8 V ±5%
VDDCML
VDDD
Power for I/O stage. The single-ended inputs and SDA, SCL are powered from VDDIO
VDDIO can be connected to a 1.8 V ±5% or 2.8 V ±10% or 3.3 V ±10%
.
VDDIO
25
Power, Digital
DAP must be grounded. DAP is the large metal contact at the bottom side, located at
VSS
DAP
Ground, DAP
the center of the WQFN package. Connected to the ground plane (GND) with at least 9
vias.
Copyright © 2012–2015, Texas Instruments Incorporated
5
DS90UB913Q-Q1, DS90UB914Q-Q1
ZHCSDZ6D –JULY 2012–REVISED JULY 2015
www.ti.com.cn
RHS Package
48-Pin WQFN
Top View
MODE
CMLOUTP
CMLOUTN
ROUT[0]
ROUT[1]
ROUT[2]
ROUT[3]
37
38
39
40
41
42
43
44
45
46
47
48
24
23
22
21
20
19
18
17
16
15
14
13
DAP = GND
VDDCML0
RIN0+
RIN0-
VDDIO2
ROUT[4]
DS90UB914Q
Deserializer
RES
ROUT[5]
VDDD
RES
ROUT[6]
ROUT[7]
ROUT[8]
ROUT[9]
VDDPLL
SEL
PASS
LOCK
DS90UB914Q-Q1 Deserializer Pin Functions
PIN
I/O
DESCRIPTION
NAME
NO.
LVCMOS PARALLEL INTERFACE
11, 12, 13,
14, 15, 16,
18, 19, 21,
Outputs,
LVCMOS
ROUT[11:0]
Parallel data outputs
22, 23, 24
Output,
LVCMOS
HSYNC
PCLK
10
8
Horizontal SYNC output
Pixel clock output pin
Output,
LVCMOS
Strobe edge set by RRFB control register
Output,
LVCMOS
VSYNC
9
Vertical SYNC output
GENERAL-PURPOSE INPUT/OUTPUT (GPIO)
General-purpose input/output pins can be used to control and respond to various
commands. They may be configured to be the input signals for the corresponding
GPOs on the serializer or they may be configured to be outputs to follow local
register settings.
Digital
Input/Output,
LVCMOS
GPIO[1:0]
GPIO[3:2]
27, 28
25, 26
General-purpose input/output pins GPO[2:3] can be configured to be input signals
for GPOs on the serializer. In addition they can also be configured to be outputs
to follow the local register settings. When the SerDes chipsets are working with
an external oscillator, these pins can be configured only to be outputs to follow
the local register settings.
Digital
Input/Output
LVCMOS
6
Copyright © 2012–2015, Texas Instruments Incorporated
DS90UB913Q-Q1, DS90UB914Q-Q1
www.ti.com.cn
ZHCSDZ6D –JULY 2012–REVISED JULY 2015
DS90UB914Q-Q1 Deserializer Pin Functions (continued)
PIN
I/O
DESCRIPTION
NAME
NO.
BIDIRECTIONAL CONTROL BUS - I2C COMPATIBLE
Input/Output,
Open-Drain
Clock line for the bidirectional control bus communication
SCL
SDA
2
1
SCL requires an external pullup resistor to VDDIO
.
Input/Output,
Open-Drain
Data line for bidirectional control bus communication
SDA requires an external pullup resistor to VDDIO
.
Device mode select pin
Resistor-to-Ground and 10-kΩ pullup to 1.8-V rail. The MODE pin on the
deserializer can be used to configure the serializer and deserializer to work in
different input PCLK range. See details in Table 8.
12-bit low-frequency mode (10- to 50-MHz operation):
In this mode, the serializer and deserializer can accept up to 12 bits DATA+2
SYNC. Input PCLK range is from 10 MHz to 50 MHz.
12-bit high-frequency mode (15- to 75-MHz operation): In this mode, the
serializer and deserializer can accept up to 12 bits DATA + 2 SYNC. Input PCLK
range is from 15 MHz to 75 MHz.
Input, LVCMOS
with pullup
MODE
37
10-bit mode (20- to 100-MHz operation):
In this mode, the serializer and deserializer can accept up to 10 bits DATA + 2
SYNC. Input PCLK frequency can range from 20 MHz to 100 MHz.
Refer to Table 4 in the Applications Information section on how to configure the
MODE pin on the deserializer.
The IDx[0] and IDx[1] pins on the deserializer are used to assign the I2C device
address. Resistor-to-Ground and 10-kΩ pullup to 1.8-V rail. See Table 2
Input pin to select the slave device address.
IDx[0:1]
35, 34
Input, analog
Input is connect to external resistor divider to set programmable Device ID
address.
CONTROL AND CONFIGURATION
Power-down mode input pin
PDB = H, deserializer is enabled and is ON.
PDB = L, deserializer is in sleep (power-down mode). When the deserializer is in
sleep, programmed control register data are NOT retained and reset to default
values.
Input, LVCMOS
with pulldown
PDB
30
LOCK status output pin
Output,
LVCMOS
LOCK = H, PLL is Locked, outputs are active
LOCK = L, PLL is unlocked, ROUT and PCLK output states are controlled by
OSS_SEL control register. May be used as link status.
LOCK
48
6
Input
BIST enable pin
BISTEN
LVCMOS with BISTEN=H, BIST mode enabled
pulldown
BISTEN=L, BIST mode is disabled
PASS output pin for BIST mode.
PASS = H, ERROR FREE transmission
Output,
LVCOMS
PASS
47
PASS = L, one or more errors were detected in the received payload.
See Built-In Self Test section for more information. Leave open if unused. Route
to test point (pad) recommended.
Input
LVCMOS with
pulldown
Output enable input
Refer to Table 5
OEN
5
4
Input
LVCMOS with
pulldown
Output sleep state select pin
Refer to Table 5
OSS_SEL
MUX select line
Input
SEL = L, RIN0± input. This selects input A as the active channel on the
SEL
46
LVCMOS with deserializer.
pulldown SEL = H, RIN1± input. This selects input B as the active channel on the
deserializer.
Copyright © 2012–2015, Texas Instruments Incorporated
7
DS90UB913Q-Q1, DS90UB914Q-Q1
ZHCSDZ6D –JULY 2012–REVISED JULY 2015
www.ti.com.cn
DS90UB914Q-Q1 Deserializer Pin Functions (continued)
PIN
I/O
DESCRIPTION
NAME
NO.
FPD-LINK III INTERFACE
Input/Output,
CML
Noninverting differential input, bidirectional control channel. The IO must be AC
coupled with a 100-nF capacitor
RIN0+
RIN0-
RIN1+
RIN1-
41
Input/Output,
CML
Inverting differential input, bidirectional control channel. The IO must be AC
coupled with a 100-nF capacitor
42
32
33
Input/Output,
CML
Noninverting differential input, bidirectional control channel. The IO must be AC
coupled with a 100-nF capacitor
Input/Output,
CML
Inverting differential input, bidirectional control channel. The IO must be AC
coupled with a 100-nF capacitor
RES
43, 44
38, 39
—
—
Reserved; This pin must always be tied low.
CMLOUTP/N
Route to test point or leave open if unused
POWER AND GROUND
LVCMOS I/O buffer power, The single-ended outputs and control input are
powered from VDDIO. VDDIO can be connected to a 1.8 V ±5% or 3.3 V ±10%
VDDIO1/2/3
29, 20, 7
Power, Digital
VDDD
17
3
Power, Digital Digital core power, 1.8 V ±5%
Power, Analog SSCG PLL power, 1.8 V ±5%
VDDSSCG
VDDR
36
Power, Analog RX analog power, 1.8 V ±5%
VDDCML0/1
VDDPLL
40, 31
45
Power, Analog CML and bidirectional control channel drive power, 1.8 V±5%
Power, Analog PLL Power, 1.8 V ±5%
DAP must be grounded. DAP is the large metal contact at the bottom side,
Ground, DAP located at the center of the WQFN package. Connected to the ground plane
(GND) with at least 16 vias.
VSS
DAP
8
Copyright © 2012–2015, Texas Instruments Incorporated
DS90UB913Q-Q1, DS90UB914Q-Q1
www.ti.com.cn
ZHCSDZ6D –JULY 2012–REVISED JULY 2015
8 Specifications
8.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1) (2) (3)
MIN
−0.3
−0.3
−0.3
−0.3
−0.3
MAX
2.5
UNIT
V
Supply voltage – VDDn (1.8 V)
Supply voltage – VDDIO
LVCMOS input voltage
4.0
V
VDDIO + 0.3
VDD + 0.3
VDD + 0.3
150
V
CML driver I/O voltage (VDD
)
V
CML receiver I/O voltage (VDD
)
V
Junction temperature
°C
1/θJA above
Maximum package power dissipation capacity package
°C/W
+25°
Air discharge (DOUT+, DOUT–, RIN+, RIN–)
Contact discharge (DOUT+, DOUT–, RIN+, RIN–)
Storage temperature Tstg
−25
−7
25
7
kV
kV
°C
−65
150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) If Military/Aerospace specified devices are required, contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
(3) For soldering specifications: see product folder at www.ti.com and SNOA549.
8.2 ESD Ratings
VALUE
±8000
UNIT
Human body model (HBM), per AEC Q100-002(1)
Charged-device model (CDM), per AEC Q100-011
Machine model (MM)
±1000
±250
Electrostatic
discharge
V(ESD)
Air Discharge (DOUT+, DOUT-, RIN+, RIN-)
≥±25 000
≥±7000
≥±15 000
≥±8000
V
IEC 61000-4-2(2)
ISO10605(3)(4)
Contact Discharge (DOUT+, DOUT-, RIN+, RIN-)
Air Discharge
Contact Discharge
(1) AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
(2) RD = 330 Ω, CS = 150 pF
(3) RD = 330 Ω, CS = 150 / 330 pF
(4) RD = 2 KΩ, CS = 150 / 330 pF
8.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
1.71
1.71
3.0
NOM
1.8
MAX
1.89
1.89
3.6
UNIT
Supply voltage (VDDn
)
V
LVCMOS supply voltage (VDDIO) OR
LVCMOS supply voltage (VDDIO) OR
LVCMOS supply voltage (VDDIO) only serializer
VDDn (1.8 V)
1.8
3.3
V
2.52
2.8
3.08
25
Supply noise(1)
VDDIO (1.8 V)
VDDIO (3.3 V)
25
mVp-p
50
Operating free-air temperature (TA)
PCLK clock frequency
–40
10
25
105
100
°C
MHz
(1) Supply noise testing was done with minimum capacitors (as shown on Figure 49 and Figure 48) on the PCB. A sinusoidal signal is AC
coupled to the VDDn (1.8-V) supply with amplitude = 25 mVp-p measured at the device VDDn pins. Bit error rate testing of input to the
serializer and output of the deserializer with 10 meter cable shows no error when the noise frequency on the serializer is less than
1 MHz. The deserializer on the other hand shows no error when the noise frequency is less than 750 kHz.
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8.4 Thermal Information
DS90UB913Q-Q1
RTV (WQFN)
32 PINS
DS90UB914Q-Q1
RHS (WQFN)
48 PINS
THERMAL METRIC(1)
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
38.4
26.9
°C/W
°C/W
RθJC(top)
6.9
4.4
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
8.5 Electrical Characteristics
over recommended operating supply and temperature ranges unless otherwise specified.(1)
(2) (3)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
LVCMOS DC SPECIFICATIONS 3.3V I/O (SERIALIZER INPUTS, DESERIALIZER OUTPUTS, GPI, GPO, CONTROL INPUTS AND
OUTPUTS)
High level input
voltage
VIH
VIN = 3 V to 3.6 V
2
VIN
V
Low level input
voltage
VIL
IIN
VIN = 3 V to 3.6 V
GND
−20
2.4
0.8
20
V
µA
V
Input current
VIN = 0 V or 3.6 V, VIN = 3 V to 3.6 V
VDDIO = 3 V to 3.6 V, IOH = −4 mA
±1
High level output
voltage
VOH
VDDIO
Low level output
voltage
VOL
IOS
IOZ
VDDIO = 3 V to 3.6 V, IOL = +4 mA
Serializer
GND
0.4
V
–15
–35
GPO outputs
Output short circuit
current
VOUT = 0 V
mA
Deserializer LVCMOS
outputs
TRI-STATE output
current
PDB = 0 V,
VOUT = 0 V or VDD
LVCMOS outputs
–20
20
µA
LVCMOS DC SPECIFICATIONS 1.8V I/O (SERIALIZER INPUTS, DESERIALIZER OUTPUTS, GPI, GPO, CONTROL INPUTS AND
OUTPUTS)
High level input
voltage
VIH
VIN = 1.71 V to 1.89 V
0.65 VIN
VIN
V
Low level input
voltage
VIL
IIN
VIN = 1.71 V to 1.89 V
GND
–20
0.35 VIN
20
Input current
VIN = 0 V or 1.89 V, VIN = 1.71 V to 1.89 V
VDDIO = 1.71 V to 1.89 V, IOH = −4 mA
±1
µA
V
High level output
voltage
VDDIO –
VOH
VDDIO
0.45
VDDIO = 1.71 V to 1.89
Deserializer LVCMOS
V
IOL = 4 mA
Low level output
voltage
VOL
GND
0.45
V
outputs
Serializer
GPO outputs
–11
–17
Output short circuit
current
IOS
VOUT = 0 V
mA
µA
Deserializer LVCMOS
outputs
TRI-STATE output
current
PDB = 0 V,
IOZ
LVCMOS outputs
VOUT = 0 V or VDD
–20
20
(1) The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and
are not ensured.
(2) Current into device pins is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to ground
except VOD, ΔVOD, VTH and VTL which are differential voltages.
(3) Typical values represent most likely parametric norms at 1.8 V or 3.3 V, TA = 25°C, and at the Recommended Operation Conditions at
the time of product characterization and are not specified.
10
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ZHCSDZ6D –JULY 2012–REVISED JULY 2015
Electrical Characteristics (continued)
over recommended operating supply and temperature ranges unless otherwise specified.(1) (2) (3)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
LVCMOS DC SPECIFICATIONS 2.8-V I/O (SERIALIZER INPUTS, GPI, GPO, CONTROL INPUTS AND OUTPUTS)
High level input
voltage
VIH
VIN = 2.52 V to 3.08 V
0.7 VIN
VIN
V
Low level input
voltage
VIL
IIN
VIN = 2.52 V to 3.08 V
GND
−20
0.3 VIN
20
Input current
VIN = 0 V or 3.08 V, VIN = 2.52 V to 3.08 V
VDDIO = 2.52 V to 3.08 V, IOH = −4 mA
±1
µA
V
High level output
voltage
VOH
VDDIO – 0.4
VDDIO
VDDIO =2.52 V to 3.08
Deserializer LVCMOS
V
IOL = 4 mA
Low level output
voltage
VOL
GND
0.4
V
outputs
Serializer
GPO outputs
−11
−20
Output short circuit
current
IOS
VOUT = 0 V
mA
µA
Deserializer LVCMOS
outputs
TRI-STATE output
current
PDB = 0 V,
IOZ
LVCMOS outputs
VOUT = 0 V or VDD
−20
20
CML DRIVER DC SPECIFICATIONS (DOUT+, DOUT–)
Output differential
voltage
|VOD
|
RL = 100 Ω (see Figure 9)
RL = 100 Ω
268
340
412
50
mV
mV
V
Output differential
voltage unbalance
ΔVOD
VOS
1
Output differential
offset voltage
RL = 100 Ω (see Figure 9)
RL = 100 Ω
VDD – VOD/2
Offset voltage
unbalance
ΔVOS
IOS
1
50
mV
mA
Output short
circuit current
DOUT± = 0 V
–26
Differential internal
termination
RT
Differential across DOUT+ and DOUT–
80
100
120
Ω
resistance
CML RECEIVER DC SPECIFICATIONS (RIN0+, RIN0–, RIN1+, RIN1– )
IIN
Input current
VIN = VDD or 0 V, VDD = 1.89 V
−20
1
20
µA
Differential internal
termination
RT
Differential across RIN+ and RIN-
80
100
120
Ω
resistance
CML RECEIVER AC SPECIFICATIONS (RIN0+, RIN0–, RIN1+, RIN1– )
Minimum allowable
|Vswing
|
swing for 1010
Line rate = 1.4 Gbps (see Figure 11)
135
mV
pattern(4)
CML MONITOR OUTPUT DRIVER SPECIFICATIONS (CMLOUTP, CMLOUTN)
Differential output
Ew
0.45
200
UI
eye opening
RL = 100 Ω
Jitter frequency > f / 40 (see Figure 20)
Differential output
eye height
EH
mV
(4) Specification is ensured by characterization and is not tested in production.
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Electrical Characteristics (continued)
over recommended operating supply and temperature ranges unless otherwise specified.(1) (2) (3)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SERIALIZER AND DESERIALIZER SUPPLY CURRENT *DIGITAL, PLL, AND ANALOG VDD
VDDn = 1.89 V
VDDIO = 3.6 V
f = 100 MHz,
10-bit mode
61
80
mA
default registers
VDDn = 1.89 V
VDDIO = 3.6 V
RL = 100 Ω
f = 75 MHz,
61
80
80
WORST CASE pattern 12-bit high-frequency
(see Figure 6)
mode
default registers
mA
VDDn = 1.89 V
VDDIO = 3.6 V
f = 50 MHz,
12-bit low-frequency
mode
61
54
54
Serializer (TX)
VDDn supply current
(includes load
current)
default registers
IDDT
VDDn = 1.89 V
VDDIO = 3.6 V
f = 100 MHz,
10-bit mode
default registers
VDDn = 1.89 V
VDDIO = 3.6 V
f = 75 MHz,
12-bit high-frequency
mode
RL = 100 Ω
RANDOM PRBS-7
pattern
mA
default registers
VDD = 1.89 V
VDDIO = 3.6 V
f = 50 MHz,
12-bit low-frequency
mode
54
default registers
VDDIO = 1.89 V
f = 75 MHz,
12-bit high-freq mode
default registers
1.5
5
3
8
Serializer (TX)
VDDIO supply
current (includes
load current)
RL = 100 Ω
WORST CASE pattern
(see Figure 6)
IDDIOT
mA
VDDIO = 3.6 V
f = 75 MHz,
12-bit high-frequency
mode default registers
VDDIO = 1.89 V
Default registers
300
300
15
900
900
100
100
µA
µA
µA
µA
Serializer (TX)
supply current
power-down
PDB = 0 V; all other
LVCMOS inputs = 0 V
IDDTZ
VDDIO = 3.6 V
Default registers
VDDIO = 1.89 V
Default registers
Serializer (TX)
IDDIOTZ VDDIO supply
current power-down
PDB = 0 V; All other
LVCMOS Inputs = 0 V
VDDIO = 3.6 V
Default registers
15
12
Copyright © 2012–2015, Texas Instruments Incorporated
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ZHCSDZ6D –JULY 2012–REVISED JULY 2015
Electrical Characteristics (continued)
over recommended operating supply and temperature ranges unless otherwise specified.(1) (2) (3)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
f = 100 MHz, 10-bit
mode
22
42
VDDIO = 1.89 V
CL = 8 pF
WORST CASE pattern
f = 75 MHz, 12-bit high-
freq mode
19
21
15
12
14
42
37
25
35
30
18
15
11
16
8
39
32
mA
f = 50 MHz, 12-bit low-
freq mode
f = 100 MHz, 10–bit
mode
VDDIO = 1.89 V
CL=8pF
Random pattern
f = 75 MHz, 12-bit high-
freq mode
mA
mA
mA
mA
mA
mA
mA
f = 50 MHz, 12-bit low-
freq mode
f = 100 MHz, 10-bit
mode
55
50
38
VDDIO = 3.6 V
CL = 8 pF
WORST CASE pattern
f = 75 MHz, 12-bit high-
freq mode
f = 50 MHz, 12-bit low-
freq mode
f = 100 MHz, 10-bit
mode
VDDIO = 3.6 V
CL = 8 pF
Random pattern
f = 75 MHz, 12-bit high-
freq mode
f = 50 MHz, 12-bit low-
freq mode
Deserializer (RX)
total supply current
(includes load
current)
IDDIOR
f = 100 MHz, 10-bit
mode
VDDIO = 1.89 V
CL = 4 pF
WORST CASE pattern
f = 75 MHz, 12-bit high-
freq mode
f = 50 MHz, 12-bit low-
freq mode
f = 100 MHz, 10-bit
mode
VDDIO = 1.89 V
CL = 4 pF
Random pattern
f = 75 MHz, 12-bit high-
freq mode
4
f = 50 MHz, 12-bit low-
freq mode
9
f = 100 MHz, 10-bit
mode
36
29
20
29
22
13
VDDIO = 3.6 V
CL = 4 pF
WORST CASE pattern
f = 75 MHz, 12-bit high-
freq mode
f = 50 MHz, 12-bit low-
freq mode
f = 100 MHz, 10-bit
mode
VDDIO = 3.6 V
CL = 4 pF
Random pattern
f = 75 MHz, 12-bit high-
freq mode
f = 50 MHz, 12-bit low-
freq mode
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Electrical Characteristics (continued)
over recommended operating supply and temperature ranges unless otherwise specified.(1) (2) (3)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
f = 100 MHz,
10-bit mode
64
110
f = 75 MHz,
12-bit high-frequency
mode
VDDn = 1.89 V
CL = 4 pF
WORST CASE pattern
67
63
114
96
f = 50 MHz,
12-bit low-frequency
mode
Deserializer (RX)
VDDn supply current
(includes load
current)
IDDR
mA
f = 100 MHz,
10-bit mode
57
60
56
42
42
VDDn = 1.89 V
CL = 4 pF
Random pattern
f = 75 MHz, 12–bit
high-frequency mode
f = 50 MHz, 12-bit
low-frequency mode
PBB = 0 V, all other
LVCMOS Inputs=0 V
VDDIO = 1.89 V
Default registers
400
400
Deserializer (RX)
supply current
power-down
IDDRZ
µA
µA
PBB = 0 V, all other
LVCMOS Inputs=0 V
VDDIO = 3.6 V
Default registers
Deserializer (RX)
IDDIORZ VDD supply current
power-down
VDDIO = 1.89 V
VDDIO = 3.6 V
8
40
PDB = 0 V, all other
LVCMOS Inputs = 0 V
360
800
8.6 Timing Requirements: Recommended for Serializer PCLK
over recommended operating supply and temperature ranges unless otherwise specified.(1)
TEST CONDITIONS
PIN/FREQ
MIN
NOM
MAX
UNIT
10-bit mode
10
T
50
12-bit high-frequency
mode
13.33
20
T
T
66.66
100
tTCP
Transmit clock period
ns
12-bit low-frequency
mode
Transmit clock
input high time
tTCIH
tTCIL
0.4T
0.4T
0.5T
0.5T
0.5T
0.5T
0.5T
2.5T
2.5T
2.5T
0.6T
0.6T
0.3T
0.3T
0.3T
ns
ns
Transmit clock
input low time
20 MHz–100 MHz,
10-bit mode
PCLK input transition
time (Figure 12)
15 MHz to 75 MHz, 12-bit
high-frequency mode
tCLKT
ns
10 MHz to 50 MHz, 12-bit
low-frequency mode
PCLK input jitter
(PCLK from imager
mode)
tJIT0
Refer to jitter freq > f / 40 f = 10 to 100 MHz
Refer to jitter freq > f / 40 f = 10 to 100 MHz
0.1T
ns
PCLK input jitter (external
oscillator mode)
tJIT1
tJIT2
1T
ns
UI
External oscillator jitter
0.1
(1) Recommended input timing requirements are input specifications and not tested in production.
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ZHCSDZ6D –JULY 2012–REVISED JULY 2015
8.7 AC Timing Specifications (SCL, SDA) - I2C Compliant
over recommended supply and temperature ranges unless otherwise specified. (See Figure 5)
TEST CONDITIONS
RECOMMENDED INPUT TIMING REQUIREMENTS
MIN
NOM
MAX
UNIT
Standard mode
Fast mode
>0
>0
4.7
1.3
4.0
0.6
4
100
400
fSCL
SCL clock frequency
SCL low period
kHz
µs
µs
µs
µs
µs
ns
µs
µs
ns
ns
Standard mode
Fast mode
tLOW
Standard mode
Fast mode
tHIGH
SCL high period
Standard mode
Fast mode
Hold time for a start or a
repeated start condition
tHD:STA
0.6
4.7
0.6
0
Standard mode
Fast mode
Setup time for a start or a
repeated start condition
tSU:STA
Standard mode
Fast mode
3.45
900
tHD:DAT Data hold time
tSU:DAT Data setup time
0
Standard mode
Fast mode
250
100
4
Standard mode
Fast mode
Setup time for STOP
condition
tSU:STO
0.6
4.7
1.3
Standard mode
Fast mode
Bus free time between
stop and start
tBUF
Standard mode
Fast mode
1000
300
300
300
tr
tf
SCL and SDA rise time
SCL and SDA fall time
Standard mode
Fast mode
8.8 Bidirectional Control Bus DC Timing Specifications (SCL, SDA) - I2C Compliant
over recommended supply and temperature ranges unless otherwise specified(1)
TEST CONDITIONS
RECOMMENDED INPUT TIMING REQUIREMENTS
MIN
NOM
MAX
UNIT
VIH
Input high level
Input low level
SDA and SCL
0.7 × VDDIO
GND
VDDIO
V
V
VIL
SDA and SCL
0.3 × VDDIO
VHY
VOL
IIN
Input hysteresis
Output low level
Input current
>50
mV
V
SDA, IOL = 0.5 mA
0
0.4
10
SDA or SCL, VIN = VDDOP OR GND
−10
µA
ns
ns
ns
ns
ns
pF
tR
SDA rise time-READ
SDA fall time-READ
430
20
SDA, RPU = 10 kΩ, Cb ≤ 400 pF (see
Figure 5)
tF
tSU;DAT
tHD;DAT
tSP
See Figure 5
See Figure 5
560
615
50
CIN
SDA or SCL
<5
(1) Specification is ensured by design.
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8.9 Switching Characteristics: Serializer
over recommended operating supply and temperature ranges unless otherwise specified.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
CML low-to-high transition
time
tLHT
RL = 100 Ω (see Figure 7)
150
330
ps
CML high-to-low transition
time
tHLT
tDIS
tDIH
tPLD
RL = 100 Ω (see Figure 7)
150
330
ps
ns
ns
ms
Data input setup to PCLK
2
2
Serializer data inputs (see Figure 13)
Data input hold from
PCLK
Serializer PLL lock time
RL = 100 Ω(1) (2), (see Figure 14)
1
2
RT = 100 Ω, 10-bit mode
Register 0x03h b[0] (TRFB = 1) (see
Figure 15)
32.5T
38T
44T
tSD
Serializer delay(2)
ns
RT = 100 Ω, 12-bit mode
Register 0x03h b[0] (TRFB = 1) (see
Figure 15)
11.75T
13T
15T
Serializer output intrinsic deterministic jitter.
Measured (cycle-cycle) with PRBS-7 test
pattern(3) (4)
Serializer output
deterministic jitter
tJIND
0.13
0.04
UI
UI
Serializer output
random jitter
Serializer output intrinsic random jitter (cycle-
cycle). Alternating-1,0 pattern.(3) (4)
tJINR
Serializer output peak-to-peak jitter includes
deterministic jitter, random jitter, and jitter
transfer from serializer input. Measured
(cycle-cycle) with PRBS-7 test pattern.(3) (4)
Peak-to-peak serializer
output jitter
tJINT
0.396
UI
PCLK = 100 MHz
10-bit mode. Default registers
2.2
2.2
Serializer jitter
PCLK = 75 MHz
12-bit high-frequency mode. Default registers
λSTXBW transfer function –3-dB
MHz
bandwidth(5)
PCLK = 50 MHz
12-bit low-frequency mode. Default registers
2.2
PCLK = 100 MHz
10-bit mode. Default Registers
1.06
1.09
1.16
400
500
600
Serializer jitter
PCLK = 75 MHz
12-bit high-frequency mode. Default registers
δSTX
transfer function
dB
(peaking)(5)
PCLK = 50 MHz
12-bit low-frequency mode. Default registers
PCLK = 100 MHz
10-bit mode. Default registers
Serializer jitter
PCLK = 75 MHz
12-bit high-frequency mode. Default registers
δSTXf
transfer function
kHz
(peaking frequency)(5)
PCLK = 50 MHz
12-bit low-frequency mode. Default registers
(1) tPLD and tDDLT is the time required by the serializer and deserializer to obtain lock when exiting power-down state with an active PCLK
(2) Specification is ensured by design.
(3) Typical values represent most likely parametric norms at 1.8 V or 3.3 V, TA = 25°C, and at the recommended operation conditions at the
time of product characterization and are not specified.
(4) UI – Unit Interval is equivalent to one ideal serialized data bit width. The UI scales with PCLK frequency.
(5) Specification is ensured by characterization and is not tested in production.
16
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ZHCSDZ6D –JULY 2012–REVISED JULY 2015
8.10 Switching Characteristics: Deserializer
over recommended operating supply and temperature ranges unless otherwise specified.
PARAMETER
TEST CONDITIONS
PIN/FREQ
MIN
TYP
MAX
UNIT
10-bit mode
10
50
12-bit high-frequency
mode
Receiver output
clock period
PCLK (see
13.33
66.66
tRCP
ns
Figure 19)
PCLK
12-bit low-frequency
mode
10
45%
40%
100
55%
60%
10-bit mode
50%
50%
12-bit high-frequency
mode
tPDC
PCLK duty cycle
12-bit low-frequency
mode
40%
1.3
50%
2
60%
2.8
LVCMOS low-to-high
transition time
VDDIO: 1.71 V to 1.89 V or
3.0 V to 3.6 V,
tCLH
tCHL
tCLH
tCHL
tROS
tROH
ns
ns
ns
ns
ns
ns
CL = 8 pF (lumped load)
Default registers
PCLK
LVCMOS high-to-low
transition time
1.3
1
2
2.5
2.8
4
(see Figure 17)(1)
LVCMOS low-to-high
transition time
VDDIO: 1.71 V to 1.89 V or
3.0 V to 3.6 V,
ROUT[11:0], HS,
VS
CL = 8 pF (lumped load)
Default registers
LVCMOS high-to-low
transition time
1
2.5
4
(see Figure 17)(1)
ROUT setup data to
PCLK
VDDIO: 1.71 V to 1.89 V or
3.0 V to 3.6 V,
CL = 8 pF (lumped load)
Default registers (see
Figure 19)
0.38T
0.38T
0.5T
0.5T
ROUT[11:0], HS,
VS
ROUT hold data to PCLK
10-bit mode
154T
109T
158T
112T
Default registers
Register 0x03h b[0]
(RRFB = 1)
12-bit low-
frequency mode
tDD
Deserializer delay
ns
(see Figure 18)(1)
12-bit high-
frequency mode
73T
75T
22
10-bit mode
15
15
With Adaptive
Equalization (see
Figure 16)
12-bit low-
frequency mode
Deserializer data lock
time
22
tDDLT
ms
12-bit high-
frequency mode
15
20
22
30
10-bit mode
PCLK = 100 MHz
12-bit low-
PCLK
frequency mode
PCLK = 50 MHz
22
35
tRCJ
Receiver clock jitter
ps
SSCG[3:0] = OFF(1)
12-bit high-
frequency mode
PCLK = 75 MHz
45
170
180
90
815
330
10-bit mode
PCLK = 100 MHz
12-bit low-
frequency mode
PCLK= 50 MHz
PCLK
tDPJ
Deserializer period jitter
ps
SSCG[3:0] = OFF(1) (2)
12-bit high-
frequency mode
PCLK= 75 MHz
300
515
(1) Specification is ensured by characterization and is not tested in production.
(2) tDPJ is the maximum amount the period is allowed to deviate measured over 30,000 samples.
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Switching Characteristics: Deserializer (continued)
over recommended operating supply and temperature ranges unless otherwise specified.
PARAMETER
TEST CONDITIONS
PIN/FREQ
MIN
TYP
MAX
UNIT
10-bit mode
PCLK = 100 MHz
440
1760
12-bit low-
Deserializer cycle-to-
cycle clock jitter
PCLK
frequency mode
PCLK = 50 MHz
460
565
730
tDCCJ
ps
SSCG[3:0] = OFF(1) (3)
12-bit high-
frequency mode
PCLK = 75 MHz
985
Spread spectrum clocking
deviation frequency
±0.5 to
±1.5%
fdev
10 MHz–100 MHz
10 MHz–100 MHz
LVCMOS output bus
SSC[3:0] = ON (see
Figure 24)(1)
Spread spectrum clocking
modulation frequency
fmod
5 to 50
kHz
(3) tDCCJ is the maximum amount of jitter between adjacent clock cycles measured over 30,000 samples.
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8.11 Typical Characteristics
4
2
0.65
0.60
0.55
0.50
0.45
0
- 2
- 4
- 6
- 8
-10
-12
-14
-16
-18
1.0E+05
1.0E+06
1.0E+07
1.0E+04
1E+04
1E+05
1E+06
1E+07
JITTER FREQUENCY (Hz)
MODULATION FREQUENCY ( Hz)
Figure 2. Typical Deserializer Input Jitter Tolerance Curve
at 1.4-Gbps Line Rate
Figure 1. Typical Serializer Jitter Transfer Function
at 100 MHz
18
16
14
12
10
8
25
20
15
10
5
914 Equalizer Gain (dB)
VOD-Vswing Loss
Allowable Interconnect
Loss
6
4
0
100
2
200
300
400
500 600
700
SERIAL LINE FREQUENCY (MHz)
0
100
200
300
400
500
600
700
SERIAL LINE FREQUENCY (MHz)
Figure 3. Maximum Equalizer Gain vs. Line Frequency
Figure 4. Adaptive Equalizer – Interconnect Loss
Compensation
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9 Parameter Measurement Information
9.1 AC Timing Diagrams and Test Circuits
SDA
t
BUF
t
f
t
t
HD;STA
t
r
LOW
t
t
f
r
SCL
t
t
HD;STA
SU;STA
t
SU;STO
t
HIGH
t
t
SU;DAT
HD;DAT
STOP START
START
REPEATED
START
Figure 5. Bidirectional Control Bus Timing
Signal Pattern
Device Pin Name
T
PCLK
(RFB = H)
D
/R
IN OUT
Figure 6. Worst Case Test Pattern
80%
20%
80%
Vdiff
Vdiff = 0V
20%
t
t
HLT
LHT
Vdiff = (D +) - (D -)
OUT OUT
Figure 7. Serializer CML Output Load and Transition Times
100 nF
D
OUT
+
50:
50:
SCOPE
BW 8 4.0 GHz
Z
Diff
= 100:
100:
D
OUT
-
100 nF
Figure 8. Serializer CML Output Load and Transition Times
10/12,
HS,VS
D
D
+
-
OUT
R
L
D
IN
OUT
PCLK
Figure 9. Serializer VOD Diagram
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AC Timing Diagrams and Test Circuits (continued)
Single Ended
V
|
OS
D
OUT
-
V
V
V
OD-
OD
OD+
D
OUT
+
Differential
V
OD+
0V
(D
OUT
+)-(D )
OUT-
V
OD-
Figure 10. Serializer VOD Diagram
R
IN
-
Single Ended
Vswing-
Vswing+
R
IN
+
0V
0V
Differential
Vswing+
Vswing-
(RIN+)-(RIN-)
Figure 11. Differential Vswing Diagram
V
DD
t
TCP
80%
80%
PCLK
20%
20%
0V
PCLK
V
/2
V
DDIO
/2
V
V
/2
DDIO
DDIO
t
t
CLKT
CLKT
t
t
DIH
DIS
DDIO
DINn
Setup
Hold
V
/2
V
/2
DDIO
DDIO
0V
Figure 12. Serializer Input Clock Transition Times
Figure 13. Serializer Set-Up and Hold Times
VDDIO/2
PDB
PCLK
t
PLD
Output Active
TRI-STATE
TRI-STATE
D
±
OUT
Figure 14. Serializer PLL Lock Time
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AC Timing Diagrams and Test Circuits (continued)
SYMBOL N
VDDIO/2
SYMBOL N+1
SYMBOL N+2
SYMBOL N+3
D
IN
t
SD
PCLK
SYMBOL N-4
SYMBOL N-3
SYMBOL N-2
SYMBOL N-1
SYMBOL N
0V
DOUT+-
Figure 15. Serializer Delay
VDDIO/2
PDB
t
DDLT
R
IN±
LOCK
TRI-STATE
VDDIO/2
Figure 16. Deserializer Data Lock Time
80%
20%
80%
20%
Deserializer
8 pF
lumped
t
t
CHL
CLH
Figure 17. Deserializer LVCMOS Output Load and Transition Times
SYMBOL N
SYMBOL N + 1
SYMBOL N + 2
SYMBOL N + 3
SYMBOL N + 3
RIN±
0V
t
DD
PCLK
VDDIO/2
SYMBOL N - 3
SYMBOL N - 2
SYMBOL N - 1
SYMBOL N
SYMBOL N+1
ROUTn
Figure 18. Deserializer Delay
t
RCP
V
DDIO
PCLK
1/2 V
1/2 V
DDIO
DDIO
0V
V
DDIO
ROUT[n],
VS, HS
1/2 V
DDIO
1/2 V
DDIO
0V
t
t
ROH
ROS
Figure 19. Deserializer Output Set-Up and Hold Times
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AC Timing Diagrams and Test Circuits (continued)
Ew
VOD (+)
EH
EH
0V
VOD (-)
t
(1 UI)
BIT
Figure 20. CML Output Driver
PDB= H
VIH
OEN
VIL
VIH
OSS_SEL
VIL
RIN
(Diff.)
'RQ¶Wꢀ&DUH
t
SEH
t
t
SES
ONS
t
ONH
LOCK
PASS
TRI-STATE
LOW
TRI-STATE
LOW
HIGH
ACTIVE
HIGH
HIGH
ROUT[0:11],
HS, VS
LOW
LOW
LOW
LOW
TRI-STATE
TRI-STATE
TRI-STATE
TRI-STATE
ACTIVE
ACTIVE
PCLK
(RFB = L)
Figure 21. Output State (Set-Up and Hold) Times
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AC Timing Diagrams and Test Circuits (continued)
4
2
0.65
0.60
0.55
0.50
0.45
0
- 2
- 4
- 6
- 8
-10
-12
-14
-16
-18
1E+04
1E+05
1E+06
1E+07
1.0E+05
1.0E+06
1.0E+07
1.0E+04
JITTER FREQUENCY (Hz)
MODULATION FREQUENCY ( Hz)
Figure 22. Typical Serializer Jitter Transfer
Function at 100 MHz
Figure 23. Typical Deserializer Input Jitter
Tolerance Curve at 1.4-Gbps Line Rate
Frequency
fdev (max)
F
F
F
PCLK+
PCLK
fdev
fdev (min)
Time
PCLK-
1 / fmod
Figure 24. Spread Spectrum Clock Output Profile
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10 Detailed Description
10.1 Overview
The DS90UB91xQ-Q1 FPD-Link III chipsets are intended to link megapixel camera imagers and video
processors in ECUs. The serializer and deserializer chipset can operate from 10-MHz to 100-MHz pixel clock
frequency. The DS90UB913Q-Q1 device transforms a 10- and 12-bit wide parallel LVCMOS data bus along with
a bidirectional control channel control bus into a single high-speed differential pair. The high-speed serial bit
stream contains an embedded clock and DC-balanced information which enhances signal quality to support AC
coupling. The DS90UB914Q-Q1 device receives the single serial data stream and converts it back into a 10- and
12-bit wide parallel data bus together with the control channel data bus. The DS90UB91xQ-Q1 chipsets can
accept up to:
•
•
•
12 bits of DATA+2 bits SYNC for an input PCLK range of 10 MHz-50 MHz in the 12-bit low-frequency mode
12 bits DATA + 2 SYNC bits for an input PCLK range of 15 MHz to 75 MHz in the 12-bit high-frequency mode
10 bits DATA + 2 SYNC bits for an input PCLK range of 20 MHz to 100 MHz in the 10-bit mode.
The DS90UB914Q-Q1 chipset has a 2:1 multiplexer that allows customers to select between two serializer
inputs. The control channel function of the DS90UB91xQ-Q1 chipset provides bidirectional communication
between the image sensor and ECUs. The integrated bidirectional control channel transfers data bidirectionally
over the same differential pair used for video data interface. This interface offers advantages over other chipsets
by eliminating the need for additional wires for programming and control. The bidirectional control channel bus is
controlled through an I2C port. The bidirectional control channel offers asymmetrical communication and is not
dependent on video blanking intervals.
The DS90UB91xQ-Q1 chipset offer customers the choice to work with different clocking schemes. The
DS90UB91xQ-Q1 chipsets can use an external oscillator as the reference clock source for the PLL or PCLK from
the imager as primary reference clock to the PLL.
10.2 Functional Block Diagram
10
or
12
10 or
12
DIN
HSYNC
ROUT
HSYNC
VSYNC
R
T
R
T
DOUT+
DOUT-
R
T
R
T
RIN0+
VSYNC
4
GPO[3:0]
4
RIN0-
RIN1+
GPIO[3:0]
Clock
Gen
PCLK
LOCK
Clock
Gen
PCLK
PLL
CDR
PASS
RIN1-
PDB
Timing and
Control
Timing and
Control
PDB
BISTEN
OEN
SDA
SCL
SEL
SDA
SCL
IDx[0]
IDx[1]
MODE
ID[x]
MODE
DS90UB914Q - DESERIALIZER
DS90UB913Q - SERIALIZER
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10.3 Feature Description
10.3.1 Serial Frame Format
The high-speed forward channel is composed of 28 bits of data containing video data, sync signals, I2C and
parity bits. This data payload is optimized for signal transmission over an AC-coupled link. Data is randomized,
balanced and scrambled. The 28-bit frame structure changes in the 12-bit low-frequency mode, 12-bit high
frequency mode and the 10-bit mode internally and is seamless to the customer. The bidirectional control
channel data is transferred over the single serial link along with the high-speed forward data. This architecture
provides a full duplex low-speed forward and backward path across the serial link together with a high-speed
forward channel without the dependence on the video blanking phase.
10.3.2 Line Rate Calculations for the DS90UB91xQ
The DS90UB913Q-Q1 device divides the clock internally by divide-by-1 in the 12-bit low-frequency mode, by
divide-by-2 in the 10-bit mode and by divide-by-1.5 in the 12-bit high-frequency mode. Conversely, the
DS90UB914Q-Q1 multiplies the recovered serial clock to generate the proper pixel clock output frequency. Thus
the maximum line rate in the three different modes remains 1.4 Gbps. The following are the formulae used to
calculate the maximum line rate in the different modes.
•
•
•
For 12-bit low-frequency mode, Line rate = fPCLK × 28; that is, fPCLK= 50 MHz, line rate = 50 × 28 = 1.4 Gbps
For 10-bit mode, Line rate = fPCLK / 2 × 28; that is, fPCLK= 100 MHz, line rate = (100 / 2) × 28 = 1.4 Gbps
For the 12-bit high-frequency mode, Line rate = fPCLK × (2 / 3) × 28; that is, fPCLK= 75 MHz, line rate = (75) ×
(2 / 3) × 28 = 1.4 Gbps
10.3.3 Deserializer Multiplexer Input
The DS90UB914Q-Q1 offers a 2:1 multiplexer that can be used to select which camera is used as the input.
Figure 25 shows the operation of the 2:1 multiplexer in the deserializer. The selection of the camera can be pin
controlled as well as register controlled. Both the deserializer inputs cannot be enabled at the same time. If the
Serializer A is selected as the active serializer, the back-channel for Deserializer A turns ON and vice versa. To
switch between the two cameras, first the Serializer B has to be selected using the SEL pin/register on the
deserializer. After that the back channel driver for Deserializer B has to be enabled using the register in the
deserializer.
Serializer A
DS90UB913Q
Camera A
DS90UB914Q
CMOS
Image
Sensor
DATA
PCLK
DATA
PCLK
FSYNC
FSYNC
2
2
I C
I C
Serializer B
DS90UB913Q
ECU
Module
Deserializer A
Camera B
CMOS
Image
Sensor
DATA
PCLK
FSYNC
2
I C
PC
Serializer B
Figure 25. Using the Multiplexer on the Deserializer to Enable a Two-Camera System
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Feature Description (continued)
10.3.4 Error Detection
The chipset provides error detection operations for validating data integrity in long distance transmission and
reception. The data error detection function offers users flexibility and usability of performing bit-by-bit data
transmission error checking. The error detection operating modes support data validation of the following signals:
•
•
Bidirectional control channel data across the serial link
Parallel video/sync data across the serial link
The chipset provides one parity bit on the forward channel and 4 CRC bits on the back channel for error
detection purposes. The DS90UB91xQ-Q1 chipset checks the forward and back channel serial links for errors
and stores the number of detected errors in two 8-bit registers in the serializer and the deserializer respectively.
To check parity errors on the forward-channel, monitor registers 0x1A and 0x1B on the deserializer. If there is a
loss of LOCK, then the counters on registers 0x1A and 0x1B are reset.
NOTE
Whenever there is a parity error on the forward channel, the PASS pin will go low.
To check CRC errors on the back-channel, monitor registers 0x0A and 0x0B on the serializer.
10.3.5 Description of Bidirectional Control Bus and I2C Modes
The I2C-compatible interface allows programming of the DS90UB913Q-Q1, DS90UB914Q-Q1, or an external
remote device (such as image sensor) through the bidirectional control channel. Register programming
transactions to/from the DS90UB913xQ-Q1 chipset are employed through the clock (SCL) and data (SDA) lines.
These two signals have open-drain I/Os and both lines must be pulled up to VDDIO by an external resistor.
Pullup resistors or current sources are required on the SCL and SDA busses to pull them high when they are not
being driven low. A logic LOW is transmitted by driving the output low. Logic HIGH is transmitted by releasing the
output and allowing it to be pulled up externally. The appropriate pullup resistor values will depend upon the total
bus capacitance and operating speed. The DS90UB91xQ-Q1 I2C bus data rate supports up to 400 kbps
according to I2C fast mode specifications.
Bus Activity:
Master
Register
Address
Slave
Address
Data
SDA Line
7-bit Address
P
S
0
A
C
K
A
C
K
A
C
K
Bus Activity:
Slave
Figure 26. Write Byte
N
A
C
K
Bus Activity:
Master
Register
Address
Slave
Address
Slave
Address
S
P
SDA Line
S
7-bit Address
7-bit Address
0
1
A
C
K
A
C
K
A
C
K
Data
Bus Activity:
Slave
Figure 27. Read Byte
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Feature Description (continued)
ACK
MSB
N/ACK
SDA
MSB
LSB
LSB
R/W
Direction
Bit
7-bit Slave Address
Data Byte
Acknowledge
*Acknowledge
or Not-ACK
from the Device
8
9
8
9
1
2
6
7
1
2
SCL
Repeated for the Lower Data Byte
and Additional Data Transfers
START
STOP
Figure 28. Basic Operation
SDA
SCL
S
P
STOP condition
START condition, or
START repeat condition
Figure 29. Start and Stop Conditions
10.3.6 Slave Clock Stretching
The I2C-compatible interface allows programming of the DS90UB913Q-Q1, DS90UB914Q-Q1, or an external
remote device (such as image sensor) through the bidirectional control.
NOTE
To communicate and synchronize with remote devices on the I2C bus through the
bidirectional control channel/MCU, the chipset utilizes bus clock stretching (holding the
SCL line low) during data transmission where the I2C slave pulls the SCL line low on the
9th clock of every I2C transfer (before the ACK signal).
The slave device will not control the clock and only stretches it until the remote peripheral has responded. The
I2C master must support clock stretching to operate with the DS90UB91xQ-Q1 chipset.
10.3.7 I2C Pass-Through
I2C pass-through provides an alternative means to independently address slave devices. The mode enables or
disables I2C bidirectional control channel communication to the remote I2C bus. This option is used to determine
whether or not an I2C instruction is to be transferred over to the remote I2C device. When enabled, the I2C bus
traffic will continue to pass through, I2C commands will be excluded to the remote I2C device. The pass-through
function also provides access and communication to only specific devices on the remote bus.
See Figure 30 for an example of this function.
If master controller transmits I2C transaction for address 0xA0, the SER A with I2C pass-through enabled will
transfer I2C commands to remote Camera A. The SER B with I2C pass-through disabled, any I2C commands will
be bypassed on the I2C bus to Camera B.
28
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Feature Description (continued)
DS90UB913Q
DS90UB914Q
CMOS
Image
Sensor
DIN[11:0]
,HS,VS
PCLK
ROUT[11:0],
HS,VS,
PCLK
2
2
SDA
SCL
SDA
SCL
I C
I C
Camera A
Slave ID: (0xA0)
SER A: I2C _MASTER
DES A: I2C_SLAVE
DS90UB914Q
I2C_PASS_THRU Enabled
ECU
Module
DS90UB913Q
CMOS
Image
Sensor
DIN[11:0]
,HS,VS
PCLK
ROUT[11:0],
HS,VS,
PCLK
2
2
SDA
SCL
I C
I C
PC
Camera B
Slave ID: (0xA0)
SER B: I2C_MASTER
I2C_PASS_THRU Disabled
Master
DES B: I2C_SLAVE
Figure 30. I2C Pass-Through
10.3.8 ID[x] Address Decoder on the Serializer
The ID[x] pin on the serializer is used to decode and set the physical slave address of the serializer (I2C only) to
allow up to five devices on the bus connected to the serializer using only a single pin. The pin sets one of the 5
possible addresses for each serializer device. The pin must be pulled to VDD (1.8 V, not VDDIO) with a 10-kΩ
resistor and a pulldown resistor (RID) of the recommended value to set the physical device address. The
recommended maximum resistor tolerance is 1%.
1.8V
10k
V
DDIO
ID[x]
RPU
RPU
R
ID
HOST
DS90UB913Q
SCL
SDA
SCL
SDA
To other Devices
Figure 31. ID[x] Address Decoder on the Serializer
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Table 1. ID[x] Resistor Value for DS90UB913Q-Q1 Serializer
ID[x] Resistor Value — DS90UB913Q-Q1 Serializer
Resistor RID0 Ω
(1% Tolerance)
Address 8'b 0 appended
Address 7'b
(WRITE)
0 k
2 k
0x58
0x59
0x5A
0x5B
0x5C
0x5D
0xB0
0xB2
4.7 k
8.2 k
14 k
100 k
0xB4
0xB6
0xB8
0xBA
10.3.9 ID[x] Address Decoder on the Deserializer
The IDx[0] and IDx[1] pins on the deserializer are used to decode and set the physical slave address of the
deserializer (I2C only) to allow up to 16 devices on the bus using only two pins. The pins set one of 16 possible
addresses for each deserializer device. As there will be more deserializer devices connected on the same board
than serializers, more I2C device addresses have been defined for the DS90UB914Q-Q1 deserializer than the
DSDS90UB913Q-Q1 serializer. The pins must be pulled to VDD (1.8 V, not VDDIO) with a 10-kΩ resistor and
two pulldown resistors (RID0 and RID1) of the recommended value to set the physical device address. The
recommended maximum resistor tolerance is 1%.
1.8V
1.8V
10k
10k
R
ID1
R
ID0
V
DDIO
IDx[0]
IDx[1]
RPU
RPU
HOST
DS90UB914Q
SCL
SDA
SCL
SDA
To other
Devices
Figure 32. ID[x[ Address Decoder on the Deserializer
Table 2. Resistor Values for IDx[0] and IDx[1] on DS90UB914Q-Q1 Deserializer
ID[X] RESISTOR VALUE — DS90UB913Q SERIALIZER
RESISTOR RID1 Ω
(1%TOLERANCE)
RESISTOR RID0 Ω
(1%TOLERANCE)
ADDRESS 8'b 0 APPENDED
ADDRESS 7'b
(WRITE)
0 k
0 k
0 k
0 k
3 k
0 k
3 k
0x60
0x61
0x62
0x63
0x64
0xC0
0xC2
11 k
100 k
0 k
0xC4
0xC6
0xC8
30
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Table 2. Resistor Values for IDx[0] and IDx[1] on DS90UB914Q-Q1 Deserializer (continued)
ID[X] RESISTOR VALUE — DS90UB913Q SERIALIZER
3 k
3 k
3 k
11 k
100 k
0 k
0x65
0x66
0x67
0x68
0x69
0x6A
0x6B
0x6C
0x6D
0x6E
0x6F
0xCA
0XCC
0XCE
0XD0
0XD2
0XD4
0XD6
0XD8
0XDA
0XDC
0XDE
3 k
11 k
11 k
11 k
11 k
100 k
100 k
100 k
100 k
3 k
11 k
100 k
0 k
3 k
11 k
100 k
10.3.10 Programmable Controller
An integrated I2C slave controller is embedded in the DS90UB913Q-Q1 serializer as well as the DS90UB914Q-
Q1 deserializer. It must be used to configure the extra features embedded within the programmable registers or it
can be used to control the set of programmable GPIOs.
10.3.11 Synchronizing Multiple Cameras
For applications requiring multiple cameras for frame-synchronization, TI recommends to utilize the General-
Purpose Input/Output (GPIO) pins to transmit control signals to synchronize multiple cameras together. To
synchronize the cameras properly, the system controller needs to provide a field sync output (such as a vertical
or frame sync signal) and the cameras must be set to accept an auxiliary sync input. The vertical synchronize
signal corresponds to the start and end of a frame and the start and end of a field.
NOTE
this form of synchronization timing relationship has a non-deterministic latency. After the
control data is reconstructed from the bidirectional control channel, there will be a time
variation of the GPIO signals arriving at the different target devices (between the parallel
links). The maximum latency delta (t1) of the GPIO data transmitted across multiple links
is 25 µs.
NOTE
The user must verify that the timing variations between the different links are within their
system and timing specifications.
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See Figure 33 for an example of synchronizing multiple cameras.
The maximum time (t1) between the rising edge of GPIO (that is, sync signal) arriving at Camera A and Camera
B is 25 µs.
DS90UB913Q
Camera A
DS90UB914Q
CMOS
Image
Sensor
DATA
PCLK
DATA
PCLK
FSYNC
FSYNC
2
2
I C
I C
Serializer A
Deserializer A
ECU
Module
Camera B
DS90UB913Q
DS90UB914Q
CMOS
Image
Sensor
DATA
PCLK
DATA
PCLK
FSYNC
FSYNC
2
2
I C
I C
PC
Serializer B
Deserializer B
Figure 33. Synchronizing Multiple Cameras
DES A
GPIO[n] Input
DES B
GPIO[n] Input
SER A
GPIO[n] Output
SER B
GPIO[n] Output
t1
Figure 34. GPIO Delta Latency
10.3.12 General-Purpose I/O (GPIO) Descriptions
There are 4 GPOs on the serializer and 4 GPIOs on the deserializer when the DS90UB91xQ-Q1 chipsets are run
off the pixel clock from the imager as the reference clock source. The GPOs on the serializer can be configured
as outputs for the input signals that are fed into the deserializer GPIOs. In addition, the GPOs on the serializer
can behave as outputs of the local register on the serializer. The GPIOs on the deserializer can be configured to
be the input signals feeding the output of the GPOs on the serializer. In addition the GPIOs on the deserializer
can be configured to behave as outputs of the local register on the deserializer. If the DS90UB91xQ-Q1 chipsets
are run off the external oscillator source as the reference clock, then GPO3 on the serializer is automatically
configured to be the input for the external clock and GPIO2 on the deserializer is configured to be the output of
the divide-by-2 clock which is fed into the imager as its reference clock. In this case, the GPIO2 and GPIO3 on
the deserializer can only behave as outputs of the local register on the deserializer. The GPIO maximum
switching rate is up to 66 kHz when configured for communication between deserializer GPIO to serializer GPO.
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10.3.13 LVCMOS VDDIO Option
1.8-V, 2.8-V, and 3.3-V serializer inputs and 1.8-V and 3.3-V deserializer outputs are user configurable to provide
compatibility with 1.8-V, 2.8-V and 3.3-V system interfaces.
10.3.14 Deserializer – Adaptive Input Equalization (AEQ)
The receiver inputs provide an adaptive input equalization filter in order to compensate for loss from the media.
The level of equalization can also be manually selected through register controls. The fully-adaptive equalizer
output can be seen using the CMLOUTP/CMLOUTN pins in the deserializer.
18
16
14
12
10
8
6
4
2
0
100
200
300
400
500
600
700
SERIAL LINE FREQUENCY (MHz)
Figure 35. Maximum Equalizer Gain vs. Line Frequency
10.3.15 EMI Reduction
10.3.15.1 Deserializer Staggered Output
The receiver staggers output switching to provide a random distribution of transitions within a defined window.
Outputs transitions are distributed randomly. This minimizes the number of outputs switching simultaneously and
helps to reduce supply noise. In addition it spreads the noise spectrum out reducing overall EMI.
10.3.15.2 Spread Spectrum Clock Generation (SSCG) on the Deserializer
The DS90UB914Q-Q1 parallel data and clock outputs have programmable SSCG ranges from 10 MHz to 100
MHz. The modulation rate and modulation frequency variation of output spread is controlled through the SSC
control registers on the DS90UB914Q-Q1 device. SSC profiles can be generated using bits [3:0] in register 0x02
in the deserializer.
10.4 Device Functional Modes
10.4.1 DS90UB91xQ-Q1 Operation With External Oscillator as Reference Clock
In some applications, the pixel clock that comes from the imager can have jitter which exceeds the tolerance of
the DS90UB91xQ-Q1 chipsets. In this case, the DS90UB913Q-Q1 device should be operated by using an
external clock source as the reference clock for the DS90UB91xQ-Q1 chipsets. This is the recommended
operating mode. The external oscillator clock output goes through a divide-by-2 circuit in the DS90UB913Q-Q1
serializer and this divided clock output is used as the reference clock for the imager. The output data and pixel
clock from the imager are then fed into the DS90UB913Q-Q1 device. Figure 36 shows the operation of the
DS90UB1xQ-Q1 chipsets while using an external automotive grade oscillator.
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Device Functional Modes (continued)
DS90UB913Q
Serializer
DS90UB914Q
Deserializer
FPD Link III-
High Speed
Camera Data
Camera Data
DOUT+
DOUT-
RIN+
RIN-
10 or 12
10 or 12
ROUT[11:0]
or
ROUT[9:0]
HSYNC,
VSYNC
DIN[11:0] or
DATA
Image
Sensor
DATA
DIN[9:0]
HSYNC,
VSYNC
HSYNC
HSYNC
VSYNC
VSYNC
Bi-Directional
PCLK
PCLK
ECU Module
Pixel Clock
Pixel Clock
Control Channel
SDA
SCL
SDA
SCL
2
4
PLL
GPIO[3:0]
GPO[1:0]
GPO[3:0]
Microcontroller
GPO[1:0]
SDA
SCL
SDA
SCL
Camera Unit
GPO3
Reference Clock
(Ext. OSC/2)
÷2
GPO2
External
Oscillator
Figure 36. DS90UB91xQ-Q1 Operation in the External Oscillator Mode
When the DS90UB913Q-Q1 device is operated using an external oscillator, the GPO3 pin on the
DS90UB913Q-Q1 is the input pin for the external oscillator. In applications where the DS90UB913Q-Q1 device is
operated from an external oscillator, the divide-by-2 circuit in the DS90UB913Q-Q1 device feeds back the
divided clock output to the imager device through GPO2 pin. The pixel clock to external oscillator ratios needs to
be fixed for the 12-bit high-frequency mode and the 10-bit mode.
NOTE
In the 10-bit mode, the pixel clock frequency divided by the external oscillator frequency
must be 2. In the 12-bit high-frequency mode, the pixel clock frequency divided by the
external oscillator frequency must be 1.5.
For example, if the external oscillator frequency is 48 MHz in the 10-bit mode, the pixel clock frequency of the
imager needs to be twice of the external oscillator frequency, that is, 96 MHz. If the external oscillator frequency
is 48 MHz in the 12-bit high-frequency mode, the pixel clock frequency of the imager needs to be 1.5 times of the
external oscillator frequency, that is, 72 MHz. In this mode, GPO2 and GPO3 on the serializer cannot act as the
output of the input signal coming from GPIO2 or GPIO3 on the deserializer.
10.4.2 DS90UB91xQ-Q1 Operation With Pixel Clock from Imager as Reference Clock
The DS90UB91xQ-Q1 chipsets can be operated by using the pixel clock from the imager as the reference
clock.Figure 37 shows the operation of the DS90UB91xQ-Q1 chipsets using the pixel clock from the imager. If
the DS90UB913Q-Q1 device is operated using the pixel clock from the imager as the reference clock, then the
imager uses an external oscillator as its reference clock. There are 4 GPIOs on the serializer and 4 GPIOs on
the deserializer in this mode.
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Device Functional Modes (continued)
DS90UB914Q
Deserializer
DS90UB913Q
Camera Data
Camera Data
FPD-Link III
DOUT+
DOUT-
10 or 12
RIN0+
RIN0-
10 or 12
ROUT[11:0]
or
ROUT[9:0]
FV, LV
Image
DIN[11:0] or
YUV
YUV
DIN[9:0]
FV,LV
Sensor
HSYNC
HSYNC
VSYNC
SDA
VSYNC
Bi-Directional
Back Channel
SDA
SCL
PCLK
ECU Module
Pixel Clock
SCL
RIN1+
4
4
GPO[3:0]
PCLK
GPIO[3:0]
GPO
GPIO
Microcontroller
RIN1-
PLL
SDA
SCL
Pixel Clock
SDA
SCL
Camera Unit
Ext.
Oscillator
Figure 37. DS90UB91xQ-Q1 Operation in PCLK mode
10.4.3 MODE Pin on Serializer
The mode pin on the serializer can be configured to select if the DS90UB913Q-Q1 device is to be operated from
the external oscillator or the PCLK from the imager. The pin must be pulled to VDD (1.8 V, not VDDIO) with a
10-kΩ resistor and a pulldown resistor (RMODE) of the recommended value to set the modes shown in Figure 38.
The recommended maximum resistor tolerance is 1%.
1.8V
10k
V
DDIO
MODE
RPU
RPU
R
MODE
DS90UB913Q
HOST
SCL
SDA
SCL
SDA
To other
Devices
Figure 38. MODE Pin Configuration on DS90UB913Q-Q1
Table 3. DS90UB913Q-Q1 Serializer MODE Resistor
Value
MODE SELECT
RMODE RESISTOR VALUE
PCLK from imager mode
External Oscillator mode
100 kΩ
4.7 kΩ
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10.4.4 MODE Pin on Deserializer
The mode pin on the deserializer can be used to configure the device to work in the 12-bit low-frequency mode,
12-bit high frequency mode or the 10-bit mode of operation. Internally, the DS90UB91xQ-Q1 chipset operates in
a divide-by-1 mode in the 12-bit low-frequency mode, divide-by-2 mode in the 10-bit mode and a divide-by-1.5
mode in the 12-bit high-frequency mode. The pin must be pulled to VDD (1.8 V, not VDDIO) with a 10-kΩ resistor
and a pulldown resistor (RMODE) of the recommended value to set the different modes in the deserializer as
mentioned in Table 4. The deserializer automatically configures the serializer to correct mode through the back-
channel. The recommended maximum resistor tolerance is 1%
.
1.8V
10k
V
DDIO
MODE
RPU
RPU
R
MODE
DS90UB914Q
SCL
HOST
SCL
SDA
SDA
To Other
Devices
Figure 39. Mode Pin Configuration on DS90UB914Q-Q1 Deserializer
Table 4. DS90UB914Q-Q1 Deserializer MODE Resistor
Value
DS90UB914Q-Q1 DESERIALIZER MODE RESISTOR VALUE
MODE SELECT
RMODE RESISTOR VALUE
12-bit low-frequency mode
10 to 50 MHz PCLK
0 Ω
10 to 12 bit DATA + 2 SYNC
12-bit low-frequency mode
15 to 75 MHz PCLK
3 kΩ
10 to 12 bit DATA + 2 SYNC
10-bit mode
20 to 100 MHz PCLK
11 kΩ
10 to 10 bit DATA + 2 SYNC
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10.4.5 Clock-Data Recovery Status Flag (LOCK), Output Enable (OEN) and Output State Select
(OSS_SEL)
When PDB is driven HIGH, the CDR PLL of the deserializer begins locking to the serial input and LOCK is TRI-
STATE or LOW (depending on the value of the OEN setting). After the DS90UB914Q-Q1 completes its lock
sequence to the input serial data, the LOCK output is driven HIGH, indicating valid data and clock recovered
from the serial input is available on the parallel bus and PCLK outputs. The states of the outputs are based on
the OEN and OSS_SEL setting (Table 3). See Figure 20.
Table 5. Output States
INPUTS
PDB
OUTPUTS
DATA, GPIO, I2S
SERIAI INPUTS
OEN
OSS
LOCK
Z
PASS
CLK
X
X
X
0
1
1
X
0
0
X
0
1
Z
L
Z
Z
L
Z
Z
L
Z
L or H
L or H
L/Osc (Register
Bit Enable)
Static
1
1
0
L
L
L
Static
Active
Active
1
1
1
1
1
1
1
0
1
H
H
H
Previous State
L
L
L
L
L
Valid
Valid
Valid
10.4.6 Multiple Device Addressing
Some applications require multiple camera devices with the same fixed address to be accessed on the same I2C
bus. The DS90UB91xQ-Q1 provides slave ID matching/aliasing to generate different target slave addresses
when connecting more than two identical devices together on the same bus. This allows the slave devices to be
independently addressed. Each device connected to the bus is addressable through a unique ID by programming
of the SLAVE_ID_MATCH register on deserializer. This will remap the SLAVE_ID_MATCH address to the target
SLAVE_ID_INDEX address; up to 8 ID indexes are supported. The ECU Controller must keep track of the list of
I2C peripherals in order to properly address the target device.
See Figure 40 for an example of multiple device addressing.
•
•
•
•
ECU is the I2C master and has an I2C master interface
The I2C interfaces in DES A and DES B are both slave interfaces
The I2C protocol is bridged from DES A to SER A and from DES B to SER B
The I2C interfaces in SER A and SER B are both master interfaces
If master controller transmits I2C slave 0xA0, the DES A address 0xC0 will forward the transaction to remote
Camera A. If the controller transmits slave address 0xA4, the DES B 0xC2 will recognize that 0xA4 is mapped to
0xA0 and will be transmitted to the remote Camera B. If controller sends command to address 0xA6, the DES B
0xC2 will forward transaction to slave device 0xA2.
The Slave ID index/match is supported only in the camera mode (SER: MODE pin = L; DES: MODE pin = H).
For Multiple device addressing in display mode (SER: MODE pin = H; DES: MODE pin = L), use the I2C pass-
through function.
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Camera A
Slave ID: (0xA0)
DS90UB913Q
DS90UB914Q
ROUT[11:0],
HS, VS,
PCLK
CMOS
Image
Sensor
DIN[11:0]
, HS, VS,
PCLK
2
2
SDA
SCL
SDA
SCL
I C
I C
DES A: ID[x](0xC0)
SER A: ID[x](0xB0)
PC/
SLAVE_ID1_MATCH(0xA0)
SLAVE_ID1_INDEX(0xA0)
SLAVE_ID2_MATCH(0xA2)
SLAVE_ID2_INDEX(0xA2)
DS90UB914Q
EEPROM
ECU
Module
Slave ID: (0xA2)
Camera B
Slave ID: (0xA0)
DS90UB913Q
DIN[11:0]
, HS, VS,
PCLK
ROUT[11:0],
HS, VS,
PCLK
CMOS
Image
Sensor
2
2
SDA
SCL
SDA
SCL
I C
I C
PC
PC/
SER B: ID[x](0xB2)
DES B: ID[x](0xC2)
EEPROM
SLAVE_ID2_MATCH(0xA4)
SLAVE_ID2_INDEX(0xA0)
SLAVE_ID2_MATCH(0xA6)
SLAVE_ID2_INDEX(0xA2)
Master
Slave ID: (0xA2)
Figure 40. Multiple Device Addressing
10.4.7 Powerdown
The SER has a PDB input pin to ENABLE or Powerdown (SLEEP) the device. The modes can be controlled by
the host and is used to disable the Link to save power when the remote device is not operational. In this mode, if
the PDB pin is tied High and the SER will enter SLEEP when the PCLK stops. When the PCLK starts again, the
SER will then lock to the valid input PCLK and transmit the data to the DES. In SLEEP mode, the high-speed
driver outputs are static (High). The DES has a PDB input pin to ENABLE or Powerdown (SLEEP) the device.
This pin can be controlled by the system and is used to disable the DES to save power. An auto mode is also
available. In this mode, the PDB pin is tied High and the DES will enter SLEEP when the serial stream stops.
When the serial stream starts up again, the DES will lock to the input stream and assert the LOCK pin and output
valid data. In SLEEP mode, the Data and PCLK outputs are set by the OSS_SEL configuration.
10.4.8 Pixel Clock Edge Select (TRFB / RRFB)
The TRFB/RRFB selects which edge of the Pixel Clock is used. For the SER, this register determines the edge
that the data is latched on. If TRFB register is 1, data is latched on the Rising edge of the PCLK. If TRFB register
is 0, data is latched on the Falling edge of the PCLK. For the DES, this register determines the edge that the
data is strobed on. If RRFB register is 1, data is strobed on the Rising edge of the PCLK. If RRFB register is 0,
data is strobed on the falling edge of the PCLK.
PCLK
DIN/
ROUT
TRFB/RRFB: 0
TRFB/RRFB: 1
Figure 41. Programmable PCLK Strobe Select
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10.4.9 Power-Up Requirements and PDB Pin
When power is applied, the VDDIO supply needs to reach the expected operating voltage (1.8 V to 3.3 V) before
the other supplies (VDDn) begin to ramp. It is required to delay and release the PDB Signal after VDD (VDDn
and VDDIO) power supplies have settled to the recommended operating voltage. An external RC network can be
connected to the PDB pin to ensure PDB arrives after all the VDD has stabilized.
1.8V OR 3.3V
1.8V
VDDIO
VDD_CORE,
All other 1.8V Supplies
1.8V OR 3.3V
PDB
Figure 42. Power-Up Sequencing
10.4.10 Built-In Self Test
An optional AT-Speed, Built-In Self Test (BIST) feature supports the testing of the high-speed serial link and low-
speed back channel. This is useful in the prototype stage, equipment production, and in-system test and also for
system diagnostics.
10.4.11 BIST Configuration and Status
The chipset can be programmed into BIST mode using either pins or registers. By default BIST configuration is
controlled through pins. BIST can be configured through registers using BIST Control register (0x24). Pin based
configuration is defined as follows:
•
•
BISTEN : Enable the BIST Process
GPIO0 and GPIO1 : Defines the BIST clock source (PCLK vs. various frequencies of internal OSC
Table 6. BIST Configuration
DESERIALIZER GPIO[0:1]
OSCILLATOR SOURCE
External PCLK
Internal
BIST FREQUENCY (MHZ)
00
01
10
11
PCLK or External Oscillator
50
25
Internal
Internal
12.5
The BIST mode provides various options for source PCLK. Using external pins, GPIO0 and GPIO1 or using
registers, customer can program the BIST mode to use external PCLK or various OSC frequencies. The BIST
status can be monitored real time on PASS pin. For every frame with error(s), PASS pin toggles low for half
PCLK period. If two consecutive frames have errors, PCLK will toggle twice to allow counting of frames with
errors. Once the BIST is done, the PASS pin reflects the pass/fail status of the last BIST run. The status can also
be read through I2C for the number of frames in errors. BIST status on PASS pin remains until it is changed by a
new BIST session or a reset. The BIST status on PASS pin is not maintained till RX loses LOCK after BISTEN is
deassserted. To evaluate BIST in the external oscillator mode, both external oscillator and PCLK need to be
present.
The BIST status on PASS pin is not maintained till RX loses LOCK after BISTEN is deassserted. So for all
practical purposes, the BIST status can be monitored from register 0x25, that is, BIST Error Count on the
DS90UB914Q-Q1 deserializer. To evaluate BIST in the external oscillator mode, both external oscillator and
PCLK need to be present.
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10.4.11.1 Sample BIST Sequence
Step 1. For the DS90UB91xQ-Q1 FPD-Link III chipset, BIST Mode is enabled through the BISTEN pin of
DS90UB914Q-Q1 FPD-Link III deserializer. The desired clock source is selected through the GPIO0 and GPIO1
pins as shown in Table 4.
Step 2. The DS90UB913Q-Q1 serializer is woken up through the back channel if it is not already on. The SSO
pattern on the data pins is send through the FPD-Link III to the deserializer. Once the serializer and deserializer
are in the BIST mode and the deserializer acquires Lock, the PASS pin of the deserializer goes high and BIST
starts checking data stream. If an error in the payload is detected the PASS pin will switch low for one half of the
clock period. During the BIST test, the PASS output can be monitored and counted to determine the payload
error rate.
Step 3. To stop the BIST mode, the deserializer BISTEN pin is set low. The deserializer stops checking the data.
The final test result is not maintained on the PASS pin. To monitor the BIST status, check the BIST Error Count
register, 0x25 on the deserializer.
Step 4. The link returns to normal operation after the deserailzer BISTEN pin is low. Figure 44 shows the
waveform diagram of a typical BIST test for two cases. Case 1 is error free, and Case 2 shows one with multiple
errors. In most cases, it is difficult to generate errors due to the robustness of the link (differential data
transmission, and so forth), thus they may be introduced by greatly extending the cable length, faulting the
interconnect, or by reducing signal condition enhancements (RX equalization).
Normal
Step 1: DES in BIST
BIST
Wait
Step 2: Wait, SER in BIST
BIST
start
Step 3: DES in Normal
Mode - check PASS
BIST
stop
Step 4: DES/SER in Normal
Figure 43. AT-Speed BIST System Flow Diagram
BISTEN
(DES)
LOCK
PCLK
(RFB = L)
ROUT[0:11],
SSO
HS, VS
DATA
(internal)
PASS
Prior Result
PASS
X = bit error(s)
DATA
(internal)
X
X
X
PASS
FAIL
Prior Result
Normal
BIST
Result
Held
Normal
BIST Test
BIST Duration
Figure 44. BIST Timing Diagram
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10.5 Register Maps
Table 7. DS90UB913Q-Q1 Control Registers
ADDR
NAME
(HEX)
BITS
FIELD
DEVICE ID
R/W DEFAULT
DESCRIPTION
7-bit address of serializer; 0x58'h
(0101_1000X'b) default
7:1
0x00
I2C Device ID
RW
0x58'h
0: Device ID is from ID[x]
0
7
SER ID SEL
RSVD
1: Register I2C Device ID overrides ID[x]
Reserved
Digital Output Drive Strength
1: High Drive Strength
0: Low Drive Strength
6
5
4
RDS
RW
RW
RW
0
1
1
Auto Voltage Control
1: Enable
0: Disable
VDDIO Control
VDDIO MODE
VDDIOVoltage set
0: 1.8V
1: 3.3V
This register can be set only through local I2C access
1: Analog power-down : Powers Down the analog block
in the serializer
0x01
Power and Reset
3
2
1
ANAPWDN
RSVD
RW
RW
RW
0
0
0
0: No effect
Reserved
1: Resets the digital block except for register values
values. Does not affect device I2C Bus or Device ID.
This bit is self-clearing.
DIGITAL
RESET1
0: Normal Operation
1: Digital Reset, resets the entire digital block including
all register values.This bit is self-clearing.
0: Normal Operation.
0
DIGITAL RESET0
RW
1
RESERVED
1
0x02
Back-channel CRC Checker Enable
1:Enabled
0:Disabled
RX CRC Checker
Enable
7
6
RW
RW
Forward channel Parity Generator Enable
1: Enable
0: Disable
TX Parity Generator
Enable
1
0
Clear CRC Error Counters.
This bit is NOT self-clearing.
1: Clear Counters
5
4
CRC Error Reset
RW
RW
0: Normal Operation
Automatically Acknowledge I2C Remote Write
The mode works when the system is LOCKed.
1: Enable: When enabled, I2C writes to the deserializer
(or any remote I2C Slave, if I2C PASS ALL is enabled)
are immediately acknowledged without waiting for the
deserializer to acknowledge the write. The accesses are
then re-mapped to address specified in 0x06.
0: Disable
I2C Remote Write
Auto Acknowledge
General
Configuration
0x03
0
1: Enable Forward Control Channel pass-through of all
I2C accesses to I2C Slave IDs that do not match the
Serializer I2C Slave ID. The I2C accesses are then
remapped to address specified in register 0x06.
0: Enable Forward Control Channel pass-through only of
I2C accesses to I2C Slave IDs matching either the
remote Deserializer Slave ID or the remote Slave ID.
I2C Pass-Through Mode
0: Pass-Through Disabled
1: Pass-Through Enabled
3
2
I2C Pass All
RW
RW
0
1
I2C PASSTHROUGH
Copyright © 2012–2015, Texas Instruments Incorporated
41
DS90UB913Q-Q1, DS90UB914Q-Q1
ZHCSDZ6D –JULY 2012–REVISED JULY 2015
www.ti.com.cn
Register Maps (continued)
Table 7. DS90UB913Q-Q1 Control Registers (continued)
ADDR
(HEX)
NAME
BITS
FIELD
R/W DEFAULT
DESCRIPTION
1:Enabled : When enabled this registers overrides the
clock to PLL mode (External Oscillator mode or Direct
PCLK mode) defined through MODE pin and allows
selection through register 0x35 in the serializer
0: Disabled : When disabled, Clock to PLL mode
(External Oscillator mode or Direct PCLK mode) is
defined through MODE pin on the serializer.
1
OV_CLK2PLL
RW
RW
0
1
General
Configuration
0x03
0x04
Pixel Clock Edge Select
1: Parallel Interface Data is strobed on the Rising Clock
Edge.
0: Parallel Interface Data is strobed on the Falling Clock
Edge.
0
TRFB
RESERVED
7
6
RSVD
RSVD
RW
RW
0
0
Reserved
Reserved.
Allows overriding mode select bits coming from back-
channel
1: Overrides MODE select bits
0: Does not override MODE select bits
5
MODE_OVERRIDE
RW
0
0x05
Mode Select
Indicates that the status of mode select from deserializer
is up to date
4
3
MODE_UP To DATE
R
R
R
0
0
0
Pin_MODE_12–bit
High Frequency
1: 12-bit high-frequency mode is selected.
0: 12-bit high-frequency mode is not selected.
Pin_MODE_10–bit
mode
1: 10-bit mode is selected.
0: 10-bit mode is not selected.
2
1:0
RSVD
Reserved
7-bit Deserializer Device ID configures the I2C Slave ID
of the remote deserializer. A value of 0 in this field
disables I2C access to the remote deserializer. This field
is automatically configured by the Bidirectional Control
Channel once RX Lock has been detected. Software
may overwrite this value, but should also assert the
FREEZE DEVICE ID bit to prevent overwriting by the
Bidirectional Control Channel.
7:1
Desializer Device ID
RW
0x00
0x06
DES ID
1: Prevents auto-loading of the Deserializer Device ID by
the bidirectional control channel. The ID will be frozen at
the value written.
0
Freeze Device ID
RW
RW
0
0
0: Update
7-bit Remote Deserializer Device Alias ID Configures the
decoder for detecting transactions designated for an I2C
deserializer device. The transaction will be remapped to
the address specified in the DES ID register.
A value of 0 in this field disables access to the remote
I2C Slave.
7:1
0
Deserializer ALIAS ID
RSVD
0x07
0x08
DESAlias
Reserved
7-bit Remote Slave Device ID Configures the physical
I2C address of the remote I2C Slave device attached to
the remote deserializer. If an I2C transaction is
addressed to the Slave Alias ID, the transaction will be
remapped to this address before passing the transaction
across the Bidirectional Control Channel to the
deserializer. A value of 0 in this field disables access to
the remote I2C slave.
7:1
0
SLAVE ID
RSVD
RW
0x00
SlaveID
Reserved
42
Copyright © 2012–2015, Texas Instruments Incorporated
DS90UB913Q-Q1, DS90UB914Q-Q1
www.ti.com.cn
ZHCSDZ6D –JULY 2012–REVISED JULY 2015
Register Maps (continued)
Table 7. DS90UB913Q-Q1 Control Registers (continued)
ADDR
(HEX)
NAME
BITS
FIELD
R/W DEFAULT
DESCRIPTION
7-bit Remote Slave Device Alias ID Configures the
decoder for detecting transactions designated for an I2C
Slave device attached to the remote deserializer. The
transaction will be remapped to the address specified in
the Slave ID register. A value of 0 in this field disables
access to the remote I2C Slave.
7:1
SLAVE ALIAS ID
RW
0x00
0x09
SlaveAlias
0
RSVD
Reserved
Number of back-channel CRC errors during normal
operation. Least Significant byte
0x0A
0x0B
CRC Errors
CRC Errors
7:0
CRC Error Byte 0
R
R
R
R
R
R
0
0
0
0
0
0
Number of back-channel CRC errors during normal
operation. Most Significant byte
7:0
7:5
4
CRC Error Byte 1
Rev-ID
Revision ID
0x00: Production
1: RX LOCKED
0: RX not LOCKED
RX Lock Detect
BIST CRC Error
Status
1: CRC errors in BIST mode
0: No CRC errors in BIST mode
3
1: Valid PCLK detected
0: Valid PCLK not detected
2
PCLK Detect
1: CRC error is detected during communication with
deserializer.
0x0C
General Status
1
0
DES Error
R
R
0
0
This bit is cleared upon loss of link or assertion of CRC
ERROR RESET in register 0x04.
0: No effect
1: Cable link detected
0: Cable link not detected
This includes any of the following faults
— Cable Open
LINK Detect
— + and - shorted
— Short to GND
— Short to battery
Local GPIO Output Value This value is output on the
GPIO pin when the GPIO function is enabled, the local
GPIO direction is Output, and remote GPIO control is
disabled.
7
6
GPO1 Output Value
RW
RW
0
1
Remote GPIO Control
1: Enable GPIO control from remote deserializer. The
GPIO pin needs to be an output, and the value is
received from the remote deserializer.
GPO1 Remote
Enable
0: Disable GPIO control from remote deserializer.
1: Input
0: Output
5
4
GPO1 Direction
GPO0 Enable
RW
RW
0
1
1: GPIO enable
0: Tri-state
GPO[0]
0x0D
and GPO[1]
Configuration
Local GPIO Output Value This value is output on the
GPIO pin when the GPIO function is enabled, the local
GPIO direction is Output, and remote GPIO control is
disabled.
3
2
GPO0 Output Value
RW
RW
0
1
Remote GPIO Control
1: Enable GPIO control from remote deserializer. The
GPIO pin needs to be an output, and the value is
received from the remote deserializer.
GPO0 Remote
Enable
0: Disable GPIO control from remote deserializer.
1: Input
0: Output
1
0
GPO0 Direction
GPO0 Enable
RW
RW
0
1
1: GPIO enable
0: Tri-state
Copyright © 2012–2015, Texas Instruments Incorporated
43
DS90UB913Q-Q1, DS90UB914Q-Q1
ZHCSDZ6D –JULY 2012–REVISED JULY 2015
www.ti.com.cn
Register Maps (continued)
Table 7. DS90UB913Q-Q1 Control Registers (continued)
ADDR
(HEX)
NAME
BITS
FIELD
R/W DEFAULT
DESCRIPTION
Local GPIO Output Value This value is output on the
GPIO pin when the GPIO function is enabled, the local
GPIO direction is Output, and remote GPIO control is
disabled.
7
GPO3 Output Value
RW
RW
0
0
Remote GPIO Control
1: Enable GPIO control from remote deserializer. The
GPIO pin needs to be an output, and the value is
received from the remote deserializer.
GPO3 Remote
Enable
6
0: Disable GPIO control from remote deserializer.
1: Input
0: Output
5
4
GPO3 Direction
GPO3 Enable
RW
RW
1
1
1: GPIO enable
0: Tri-state
GPO[2]
0x0E
and GPO[3]
Configuration
Local GPIO Output Value This value is output on the
GPIO pin when the GPIO function is enabled, the local
GPIO direction is Output, and remote GPIO control is
disabled.
3
GPO2 Output Value
RW
RW
0
1
Remote GPIO Control
1: Enable GPIO control from remote deserializer. The
GPIO pin needs to be an output, and the value is
received from the remote deserializer.
GPO2 Remote
Enable
2
1
0: Disable GPIO control from remote deserializer.
1: Input
0: Output
GPO2 Direction
RW
RW
0
1
1: GPIO enable
0: Tri-state
0
GPO2 Enable
RSVD
7:5
Reserved
SDA Output Delay This field configures output delay on
the SDA output. Setting this value will increase output
delay in units of 50 ns. Nominal output delay values for
SCL to SDA are:
00 : 350 ns
01: 400 ns
10: 450 ns
11: 500 ns
4:3
SDA Output Delay
Local Write Disable
RW
00
Disable Remote Writes to Local Registers Setting this bit
to a 1 will prevent remote writes to local device registers
from across the control channel. This prevents writes to
the serializer registers from an I2C master attached to
the deserializer. Setting this bit does not affect remote
access to I2C slaves at the serializer.
Speed up I2C Bus Watchdog Timer
1: Watchdog Timer expires after approximately 50
microseconds
2
1
RW
RW
0
0
0x0F I2C Master Config
I2C Bus Timer
Speed up
0: Watchdog Timer expires after approximately 1
second.
1. Disable I2C Bus Watchdog Timer When the I2C
Watchdog Timer may be used to detect when the I2C
bus is free or hung up following an invalid termination of
a transaction. If SDA is high and no signaling occurs for
approximately 1 second, the I2C bus will assumed to be
free. If SDA is low and no signaling occurs, the device
will attempt to clear the bus by driving 9 clocks on SCL
0: No effect
I2C Bus Timer
Disable
0
RW
0
44
Copyright © 2012–2015, Texas Instruments Incorporated
DS90UB913Q-Q1, DS90UB914Q-Q1
www.ti.com.cn
ZHCSDZ6D –JULY 2012–REVISED JULY 2015
Register Maps (continued)
Table 7. DS90UB913Q-Q1 Control Registers (continued)
ADDR
(HEX)
NAME
BITS
FIELD
R/W DEFAULT
DESCRIPTION
7
RSVD
Reserved
Internal SDA Hold Time. This field configures the amount
of internal hold time provided for the SDA input relative
to the SCL input. Units are 50 ns.
I2C Glitch Filter Depth This field configures the maximum
width of glitch pulses on the SCL and SDA inputs that
will be rejected. Units are 10 ns.
I2C Master SCL High Time This field configures the high
pulse width of the SCL output when the serializer is the
Master on the local I2C bus. Units are 50 ns for the
nominal oscillator clock frequency. The default value is
set to provide a minimum (4µs + 1µs of rise time for
cases where rise time is very fast) SCL high time with
the internal oscillator clock running at 26MHz rather than
the nominal 20 MHz.
6:4
3:0
SDA Hold Time
I2C Filter Depth
RW
RW
0x1
0x7
0x10
0x11
I2C Control
SCL High Time
7:0
SCL High Time
RW
0x82
I2C SCL Low Time This field configures the low pulse
width of the SCL output when the serializer is the Master
on the local I2C bus. This value is also used as the SDA
setup time by the I2C Slave for providing data prior to
releasing SCL during accesses over the Bidirectional
Control Channel. Units are 50 ns for the nominal
oscillator clock frequency. The default value is set to
provide a minimum (4.7 µs + 0.3 µs of fall time for cases
where fall time is very fast) SCL low time with the
internal oscillator clock running at 26 MHz rather than
the nominal 20 MHz.
0x12
0x13
SCL LOW Time
7:0
SCL Low Time
RW
RW
0x82
General-Purpose
Control
1: High
0: Low
7:0
7:3
GPCR[7:0]
RSVD
0
Reserved
Allows choosing different OSC clock frequencies for
forward channel frame.
OSC Clock Frequency in Functional Mode when OSC
mode is selected or when the selected clock source is
not present, for example, missing PCLK/ External
Oscillator. See Table 9 for oscillator clock frequencies
when PCLK/ External Clock is missing.
2:1
0
Clock Source
BIST Enable
RW
RW
0x0
0x14
BIST Control
BIST Control:
1: Enable BIST mode
0: Disable BIST mode
0
0x15 -
0x1D
RESERVED
The watchdog timer allows termination of a control
channel transaction if it fails to complete within a
programmed amount of time. This field sets the
Bidirectional Control Channel Watchdog Timeout value
in units of 2ms. This field should not be set to 0.
7:1
0
BCC Watchdog Timer RW
0x7F
0
BCC Watchdog
Control
0x1E
Disable Bidirectional Control Channel Watchdog Timer
1: Disables BCC Watchdog Timer operation
0: Enables BCC Watchdog Timer operation
BCC Watchdog Timer
RW
Disable
0x1F-
0x29
RESERVED
BIST Mode CRC
R
Number of CRC Errors in the back channel when in
BIST mode
0x2A
CRC Errors
7:0
0
Errors Count
Copyright © 2012–2015, Texas Instruments Incorporated
45
DS90UB913Q-Q1, DS90UB914Q-Q1
ZHCSDZ6D –JULY 2012–REVISED JULY 2015
www.ti.com.cn
Register Maps (continued)
Table 7. DS90UB913Q-Q1 Control Registers (continued)
ADDR
(HEX)
NAME
BITS
FIELD
R/W DEFAULT
RESERVED
DESCRIPTION
0x2B -
0x34
7:4
3
RSVD
Reserved
Status of mode select pin
1: Indicates External Oscillator mode is selected by
mode-resistor
0: External Oscillator mode is not selected by mode-
resistor
PIN_LOCK to
External Oscillator
RW
0
PLL Clock
Overwrite
Status of mode select pin
1: Indicates PCLK mode is selected by mode-resistor
0: PCLK mode not selected by mode-resistor
0x35
PIN_LOCK to
Oscillator
2
RW
RW
0
0
Affects only when 0x03[1]=1 (OV_CLK2PLL) and
0x35[0]=0.
1: Routes GPO3 directly to PLL
0: Allows PLL to lock to PCLK"
LOCK to External
Oscillator
1
0
RSVD
Reserved
Table 8. DS90UB914Q-Q1 Control Registers
ADDR
(HEX)
NAME
BITS
FIELD
DEVICE ID
R/W
DEFAULT
DESCRIPTION
7-bit address of deserializer;
0x60h
7:1
RW
0x60'h
0x00
I2C Device ID
0: Deserializer Device ID is set using address
coming from CAD
Deserializer ID
Select
0
RW
RW
0
0
1: Register I2C Device ID overrides ID[x]
7:6
RSVD
Reserved
This register can be set only through local I2C
access
1: Analog power-down : Powers down the
analog block in the serializer
0: No effect
5
ANAPWDN
4:2
1
RSVD
Reserved
0x01
Reset
Digital Reset Resets the entire digital block
except registers. This bit is self-clearing.
1: Reset
Digital Reset 1
RW
RW
0
0
0: No effect
Digital Reset Resets the entire digital block
including registers. This bit is self-clearing.
1: Reset
0
Digital Reset 0
0: No effect
46
Copyright © 2012–2015, Texas Instruments Incorporated
DS90UB913Q-Q1, DS90UB914Q-Q1
www.ti.com.cn
ZHCSDZ6D –JULY 2012–REVISED JULY 2015
Table 8. DS90UB914Q-Q1 Control Registers (continued)
ADDR
(HEX)
NAME
BITS
FIELD
R/W
DEFAULT
DESCRIPTION
7
6
RSVD
RSVD
Reserved
Reserved
1: Output PCLK or OSC clock when not
LOCKED
0: Only PCLK
5
4
Auto-Clock
RW
RW
0
0
1: Selects 8x mode for 10-18 MHz frequency
range in SSCG
SSCG LFMODE
0: SSCG running at 4X mode
SSCG Select
0000: Normal Operation, SSCG OFF
0001: fmod (kHz) PCLK/2168, fdev ±0.50%
0010: fmod (kHz) PCLK/2168, fdev ±1.00%
0011: fmod (kHz) PCLK/2168, fdev ±1.50%
0100: fmod (kHz) PCLK/2168, fdev ±2.00%
0101: fmod (kHz) PCLK/1300, fdev ±0.50%
0110: fmod (kHz) PCLK/1300, fdev ±1.00%
0111: fmod (kHz) PCLK/1300, fdev ±1.50%
1000: fmod (kHz) PCLK/1300, fdev ±2.00%
1001: fmod (kHz) PCLK/868, fdev ±0.50%
1010: fmod (kHz) PCLK/868, fdev ±1.00%
1011: fmod (kHz) PCLK/868, fdev ±1.50%
1100: fmod (kHz) PCLK/868, fdev ±2.00%
1101: fmod (kHz) PCLK/650, fdev ±0.50%
1110: fmod (kHz) PCLK/650, fdev ±1.00%
1111: fmod (kHz) PCLK/650, fdev ±1.50%
Note: This register should be changed only
after disabling SSCG.
General
Configuration 0
0x02
3:0
SSCG
RW
0
Forward-Channel Parity Checker Enable
1: Enable
0: Disable
RX Parity Checker
Enable
7
6
5
4
3
RW
RW
RW
RW
RW
1
1
1
0
1
Back-Channel CRC Generator Enable
1: Enable
0: Disable
TX CRC Checker
Enable
General
Configuration 1
0x03
Auto voltage control
1: Enable (auto-detect mode)
0: Disable
VDDIO Control
VDDIO Mode
VDDIO voltage set
1: 3.3 V
0: 1.8 V
I2C Pass-Through Mode
1: Pass-Through Enabled
0: Pass-Through Disabled
I2C Passthrough
Automatically Acknowledge I2C Remote Write
When enabled, I2C writes to the deserializer (or
any remote I2C Slave, if I2C PASS ALL is
enabled) are immediately acknowledged
without waiting for the deserializer to
acknowledge the write. The accesses are then
remapped to address specified in 0x06. This
allows I2C bus without LOCK.
2
AUTO ACK
RW
0
General
Configuration 1
0x03
1: Enable
0: Disable
Parity Error Reset, This bit is self-clearing.
1: Parity Error Reset
0: No effect
1
0
Parity Error Reset
RRFB
RW
RW
0
1
Pixel Clock Edge Select
1: Parallel Interface Data is strobed on the
Rising Clock Edge.
0: Parallel Interface Data is strobed on the
Falling Clock Edge.
Copyright © 2012–2015, Texas Instruments Incorporated
47
DS90UB913Q-Q1, DS90UB914Q-Q1
ZHCSDZ6D –JULY 2012–REVISED JULY 2015
www.ti.com.cn
Table 8. DS90UB914Q-Q1 Control Registers (continued)
ADDR
(HEX)
NAME
BITS
FIELD
R/W
DEFAULT
DESCRIPTION
Equalization gain
0x00 = ~0.0 dB
0x01 = ~4.5 dB
0x03 = ~6.5 dB
0x07 = ~7.5 dB
0x0F = ~8.0 dB
0x1F = ~11.0 dB
0x3F = ~12.5 dB
EQ level - when
AEQ bypass is
enabled EQ setting
is provided by this
register
EQ Feature
Control 1
0x04
7:0
RW
0x00
0x05
0x06
RESERVED
7:1
0
Remote ID
RW
0x0C
Remote Serializer ID
Freeze Serializer Device ID Prevent auto-
loading of the serializer Device ID from the
Forward Channel. The ID will be frozen at the
value written.
SER ID
Freeze Device ID
RW
0
7:1
7-bit Remote Serializer Device Alias ID
Configures the decoder for detecting
transactions designated for an I2C deserializer
device. The transaction will be remapped to the
address specified in the SER ID register. A
value of 0 in this field disables access to the
remote I2C Slave.
Serializer Alias ID
RSVD
RW
0x00
0x07
SER Alias
0
7:1
0
Reserved
7-bit Remote Slave Device ID 0 Configures the
physical I2C address of the remote I2C Slave
device attached to the remote serializer. If an
I2C transaction is addressed to the Slave Alias
ID0, the transaction will be remapped to this
address before passing the transaction across
the Bidirectional Control Channel to the
serializer.
Slave ID0
RSVD
RW
0
0x08
Slave ID[0]
Slave ID[1]
Slave ID[2]
Slave ID[3]
Reserved
7-bit Remote Slave Device ID 1 Configures the
physical I2C address of the remote I2C Slave
device attached to the remote serializer. If an
I2C transaction is addressed to the Slave Alias
ID1, the transaction will be remapped to this
address before passing the transaction across
the Bidirectional Control Channel to the
serializer.
7:1
0
Slave ID1
RSVD
RW
RW
RW
0
0x00
0
0x09
0x0A
0x0B
Reserved
7-bit Remote Slave Device ID 2 Configures the
physical I2C address of the remote I2C Slave
device attached to the remote serializer. If an
I2C transaction is addressed to the Slave Alias
ID2, the transaction will be remapped to this
address before passing the transaction across
the Bidirectional Control Channel to the
serializer.
7:1
0
Slave ID2
RSVD
Reserved
7-bit Remote Slave Device ID 3 Configures the
physical I2C address of the remote I2C Slave
device attached to the remote serializer. If an
I2C transaction is addressed to the Slave Alias
ID3, the transaction will be remapped to this
address before passing the transaction across
the Bidirectional Control Channel to the
serializer.
7:1
0
Slave ID3
RSVD
Reserved
48
Copyright © 2012–2015, Texas Instruments Incorporated
DS90UB913Q-Q1, DS90UB914Q-Q1
www.ti.com.cn
ZHCSDZ6D –JULY 2012–REVISED JULY 2015
Table 8. DS90UB914Q-Q1 Control Registers (continued)
ADDR
(HEX)
NAME
BITS
FIELD
R/W
DEFAULT
DESCRIPTION
7-bit Remote Slave Device ID 4 Configures the
physical I2C address of the remote I2C Slave
device attached to the remote serializer. If an
I2C transaction is addressed to the Slave Alias
ID4, the transaction will be remapped to this
address before passing the transaction across
the Bidirectional Control Channel to the
serializer.
7:1
0
Slave ID4
RW
0
0x0C
0x0D
0x0E
0x0F
Slave ID[4]
RSVD
Reserved
7-bit Remote Slave Device ID 5 Configures the
physical I2C address of the remote I2C Slave
device attached to the remote serializer. If an
I2C transaction is addressed to the Slave Alias
ID5 , the transaction will be remapped to this
address before passing the transaction across
the Bidirectional Control Channel to the
serializer.
7:1
0
Slave ID5
RSVD
RW
RW
RW
RW
RW
0x00
Slave ID[5]
Slave ID[6]
Slave ID[7]
Reserved
7-bit Remote Slave Device ID 6 Configures the
physical I2C address of the remote I2C Slave
device attached to the remote serializer. If an
I2C transaction is addressed to the Slave Alias
ID6, the transaction will be remapped to this
address before passing the transaction across
the Bidirectional Control Channel to the
serializer.
7:1
0
Slave ID6
RSVD
0
Reserved
7-bit Remote Slave Device ID 7 Configures the
physical I2C address of the remote I2C Slave
device attached to the remote serializer. If an
I2C transaction is addressed to the Slave Alias
ID7, the transaction will be remapped to this
address before passing the transaction across
the Bidirectional Control Channel to the
serializer.
7:1
0
Slave ID7
RSVD
0x00
0x00
0x00
Reserved
7-bit Remote Slave Device Alias ID 0
Configures the decoder for detecting
transactions designated for an I2C Slave device
attached to the remote serializer. The
transaction will be remapped to the address
specified in the Slave ID0 register. A value of 0
in this field disables access to the remote I2C
Slave.
7:1
0
Slave Alias ID0
RSVD
0x10
Slave Alias[0]
Reserved
7-bit Remote Slave Device Alias ID 1
Configures the decoder for detecting
transactions designated for an I2C Slave device
attached to the remote serializer. The
transaction will be remapped to the address
specified in the Slave ID1 register. A value of 0
in this field disables access to the remote I2C
Slave.
7:1
0
Slave Alias ID1
RSVD
0x11
Slave Alias[1]
Reserved
Copyright © 2012–2015, Texas Instruments Incorporated
49
DS90UB913Q-Q1, DS90UB914Q-Q1
ZHCSDZ6D –JULY 2012–REVISED JULY 2015
www.ti.com.cn
Table 8. DS90UB914Q-Q1 Control Registers (continued)
ADDR
(HEX)
NAME
BITS
FIELD
R/W
DEFAULT
DESCRIPTION
7-bit Remote Slave Device Alias ID 2
Configures the decoder for detecting
transactions designated for an I2C Slave device
attached to the remote serializer. The
transaction will be remapped to the address
specified in the Slave ID2 register. A value of 0
in this field disables access to the remote I2C
Slave.
7:1
0
Slave Alias ID2
RSVD
RW
0x00
0x12
0x13
0x14
0x15
0x16
Slave Alias[2]
Reserved
7-bit Remote Slave Device Alias ID 3
Configures the decoder for detecting
transactions designated for an I2C Slave device
attached to the remote serializer. The
transaction will be remapped to the address
specified in the Slave ID3 register. A value of 0
in this field disables access to the remote I2C
Slave.
7:1
0
Slave Alias ID3
RSVD
RW
RW
RW
RW
0x00
0x00
0x00
0x00
Slave Alias[3]
Slave Alias[4]
Slave Alias[5]
Slave Alias[6]
Slave Alias[7]
Reserved
7-bit Remote Slave Device Alias ID 4
Configures the decoder for detecting
transactions designated for an I2C Slave device
attached to the remote serializer. The
transaction will be remapped to the address
specified in the Slave ID4 register. A value of 0
in this field disables access to the remote I2C
Slave.
7:1
0
Slave Alias ID4
RSVD
Reserved
7-bit Remote Slave Device Alias ID 5
Configures the decoder for detecting
transactions designated for an I2C Slave device
attached to the remote serializer. The
transaction will be remapped to the address
specified in the Slave ID5 register. A value of 0
in this field disables access to the remote I2C
Slave.
7:1
0
Slave Alias ID5
RSVD
Reserved
7-bit Remote Slave Device Alias ID 6
Configures the decoder for detecting
transactions designated for an I2C Slave device
attached to the remote serializer. The
transaction will be remapped to the address
specified in the Slave ID6 register. A value of 0
in this field disables access to the remote I2C
Slave.
7:1
0
Slave Alias ID6
RSVD
Reserved
7-bit Remote Slave Device Alias ID 7
Configures the decoder for detecting
transactions designated for an I2C Slave device
attached to the remote serializer. The
transaction will be remapped to the address
specified in the Slave ID7 register. A value of 0
in this field disables access to the remote I2C
Slave.
7:1
Slave Alias ID7
RSVD
RW
RW
0x00
0x17
0x18
0
Reserved
Parity errors threshold on the Forward channel
during normal information. This sets the
maximum number of parity errors that can be
counted using register 0x1A.
Parity Errors
Threshold
Parity Error
Threshold Byte 0
7:0
0
Least significant Byte.
50
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www.ti.com.cn
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Table 8. DS90UB914Q-Q1 Control Registers (continued)
ADDR
(HEX)
NAME
BITS
FIELD
R/W
DEFAULT
DESCRIPTION
Parity errors threshold on the Forward channel
during normal operation. This sets the
maximum number of parity errors that can be
counted using register 0x1B.
Parity Errors
Threshold
Parity Error
Threshold Byte 1
0x19
7:0
RW
0
Most significant Byte
Number of parity errors in the Forward channel
during normal operation.
Least significant Byte
0x1A
0x1B
Parity Errors
Parity Errors
7:0
7:0
Parity Error Byte 0
Parity Error Byte 1
RW
0
Number of parity errors in the Forward channel
during normal operation
Most significant Byte
RW
R
0
0
Revision ID
0x0000: Production
7:4
3
Rev-ID
RSVD
Reserved
Parity Error detected
1: Parity Errors detected
0: No Parity Errors
2
1
Parity Error
R
R
0
0
0x1C
General Status
1: Serial input detected
0: Serial input not detected
Signal Detect
Deserializer CDR, PLL's clock to recovered
clock frequency
1: Deserializer locked to recovered clock
0: Deserializer not locked
0
Lock
R
0
0
Local GPIO Output Value This value is the
output on the GPIO pin when the GPIO function
is enabled, the local GPIO direction is Output.
7
6
5
GPIO1 Output Vaue
RW
RSVD
Reserved
GPIO1 Direction
1
Local GPIO Direction
1: Input
0: Output
RW
RW
RW
GPIO[1] and
GPIO[0] Config
0x1D
GPIO Function Enable
1: Enable GPIO operation
0: Enable normal operation
4
GPIO1 Enable
1
0
Local GPIO Output Value This value is output
on the GPIO pin when the GPIO function is
enabled, the local GPIO direction is Output.
3
2
1
GPIO0 Output Value
RSVD
Reserved
Local GPIO Direction
1: Input
0: Output
GPIO0 Direction
RW
RW
1
1
GPIO[1] and
GPIO[0] Config
0x1D
GPIO Function Enable
1: Enable GPIO operation
0: Enable normal operation
0
GPIO0 Enable
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Table 8. DS90UB914Q-Q1 Control Registers (continued)
ADDR
(HEX)
NAME
BITS
FIELD
R/W
DEFAULT
DESCRIPTION
Local GPIO Output Value This value is the
output on the GPIO pin when the GPIO function
is enabled, the local GPIO direction is Output.
7
6
5
GPIO3 Output Vaue
RSVD
RW
0
Reserved
Local GPIO Direction
1: Input
0: Output
GPIO3 Direction
RW
RW
RW
1
1
0
GPIO Function Enable
1: Enable GPIO operation
0: Enable normal operation
4
GPIO3 Enable
GPIO[3] and
GPIO[2] Config
0x1E
Local GPIO Output Value This value is output
on the GPIO pin when the GPIO function is
enabled, the local GPIO direction is Output.
3
2
1
GPIO2 Output Value
RSVD
Reserved
Local GPIO Direction
1: Input
0: Output
GPIO2 Direction
RW
RW
1
1
GPIO Function Enable
1: Enable GPIO operation
0: Enable normal operation
0
7
GPIO2 Enable
Allows overriding OEN and OSS select coming
from Pins
1: Overrides OEN/OSS_SEL selected by pins
0: Does NOT override OEN/OSS_SEL select
by pins
OEN_OSS Override
RW
0
6
5
OEN Select
OSS Select
RW
R
0
0
OEN configuration from register
OSS_SEL configuration from register
Allows overriding mode select bits coming from
back-channel
1: Overrides MODE select bits
0: Does not override MODE select bits
4
MODE_OVERRIDE
RW
0
PIN_MODE_12–bit
HF mode
Status of mode select pin
Mode and OSS
Select
3
2
R
R
0
0
0x1F
PIN_MODE_10-bit
mode
Status of mode select pin
Selects 12-bit high-frequency mode. This bit is
automatically updated by the mode settings
from RX unless MODE_OVERRIDE is SET
1: 12-bit high-frequency mode is selected.
0: 12-bit high-frequency mode is not selected.
MODE_12–bit High
Frequency
1
0
RW
RW
0
0
Selects 10-bit mode. This bit is automatically
updated by the mode settings from RX unless
MODE_OVERRIDE is SET
MODE_10–bit mode
1: Enables 10-bit mode.
0: Disables 10-bit mode.
The watchdog timer allows termination of a
control channel transaction if it fails to complete
within a programmed amount of time. This field
sets the Bidirectional Control Channel
Watchdog Timeout value in units of 2ms. This
field should not be set to 0.
BCC Watchdog
timer
7:1
0
RW
RW
0
0
BCC Watchdog
Control
0x20
Disable Bidirectional Control Channel
Watchdog Timer
1: Disables BCC Watchdog Timer operation
0: Enables BCC Watchdog Timer operation
BCC Watchdog
Timer Disable
52
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ZHCSDZ6D –JULY 2012–REVISED JULY 2015
Table 8. DS90UB914Q-Q1 Control Registers (continued)
ADDR
(HEX)
NAME
BITS
FIELD
R/W
DEFAULT
DESCRIPTION
I2C Pass-Through All Transactions
0: Disabled
7
I2C pass-through all
RW
0
1: Enabled
Internal SDA Hold Time This field configures
the amount of internal hold time provided for
the SDA input relative to the SCL input. Units
are 50ns.
I2C Glitch Filter Depth This field configures the
maximum width of glitch pulses on the SCL and
SDA inputs that will be rejected. Units are 10ns.
0x21
I2C Control 1
6:4
3:0
I2C SDA Hold
RW
RW
0
0
I2C Filter Depth
Control Channel Sequence Error Detected This
bit indicates a sequence error has been
detected in forward control channel.
1: If this bit is set, an error may have occurred
in the control channel operation
Forward Channel
Sequence Error
7
R
0
0
0: No forward channel errors have been
detected on the control channel
Clear Sequence
Error
Clears the Sequence Error Detect bit
6
5
RW
RSVD
Reserved
SDA Output Delay This field configures output
delay on the SDA output. Setting this value will
increase output delay in units of 50 ns. Nominal
output delay values for SCL to SDA are:
00 : 350ns
4:3
SDA Output Delay
RW
0
01: 400ns
10: 450ns
11: 500ns
Disable Remote Writes to local registers
0x22
I2C Control 2
Setting this bit to a 1 will prevent remote writes
to local device registers from across the control
channel. This prevents writes to the deserializer
registers from an I2C master attached to the
serializer. Setting this bit does not affect remote
access to I2C slaves at the deserializer.
Speed up I2C Bus Watchdog Timer
1: Watchdog Timer expires after approximately
50 µs
2
1
Local Write Disable
RW
RW
0
0
I2C Bus Timer
Speed up
0: Watchdog Timer expires after approximately
1 s.
Disable I2C Bus Watchdog Timer When the I2C
Watchdog Timer may be used to detect when
the I2C bus is free or hung up following an
invalid termination of a transaction. If SDA is
high and no signaling occurs for approximately
1 second, the I2C bus will assumed to be free.
If SDA is low and no signaling occurs, the
device will attempt to clear the bus by driving 9
clocks on SCL
I2C Bus Timer
Disable
0
RW
0
General-Purpose
Control
Scratch Register
0x23
0x24
7:0
7:4
GPCR
RSVD
RW
RW
0
1
Reserved
Bist Configured through Pin.
1: Bist configured through pin.
0: Bist configured through register bit
"reg_24[0]"
BIST Pin
Configuration
3
BIST Control
BIST Clock Source
See Table 10
2:1
0
BIST Clock Source
BIST Enable
RW
RW
00
0
BIST Control
1: Enabled
0: Disabled
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Table 8. DS90UB914Q-Q1 Control Registers (continued)
ADDR
(HEX)
NAME
BITS
FIELD
R/W
DEFAULT
DESCRIPTION
Number of Forward channel Parity errors in the
BIST mode.
0x25
Parity Error Count
7:0
BIST Error Count
R
0
0x26 -
0x3B
RESERVED
7:2
1:0
RSVD
Reserved
Selects the divider for the OSC clock out on
PCLK when system is not locked and selected
by OEN/OSSSEL 0x02[5]
00: 50M (± 30%)
Oscillator output
divider select
0x3C
OSC OUT DIVIDER
SEL
RW
0
01: 25M (± 30%)
1X: 12.5M (± 30%)
0x3D -
0x3E
RESERVED
7:5
4
RSVD
Reserved
CML Output
Enable
0: CML Loop-through Driver is powered up
1: CML Loop-through Driver is powered down.
0x3F
CML OUT Enable
RSVD
RW
1
3:0
Reserved
I2C Master SCL High Time This field configures
the high pulse width of the SCL output when
the deserializer is the Master on the local I2C
bus. Units are 50 ns for the nominal oscillator
clock frequency. The default value is set to
provide a minimum (4μs + 0.3μs of rise time for
cases where rise time is very fast) SCL high
time with the internal oscillator clock running at
26MHz rather than the nominal 20MHz.
0x40
SCL High Time
7:0
SCL High Time
RW
0x82
I2C SCL Low Time This field configures the low
pulse width of the SCL output when the
deserializer is the Master on the local I2C bus.
This value is also used as the SDA setup time
by the I2C Slave for providing data prior to
releasing SCL during accesses over the
Bidirectional Control Channel. Units are 50 ns
for the nominal oscillator clock frequency. The
default value is set to provide a minimum
(4.7µs + 0.3µs of fall time for cases where fall
time is very fast) SCL low time with the internal
oscillator clock running at 26MHz rather than
the nominal 20MHz.
0x41
SCL Low Time
7:0
SCL Low Time
RW
0x82
7:2
1
RSVD
Reserved
1: This bit introduces multiple errors into Back
channel frame.
0: No effect
Force Back Channel
Error
RW
RW
0
0
0x42
CRC Force Error
1: This bit introduces ONLY one error into Back
channel frame. Self clearing bit
0: No effect
Force One Back
Channel Error
0
0x43 -
0x4C
RESERVED
7
RSVD
Reserved
AEQ Test Mode
Select
Bypass AEQ and use set manual EQ value
using register 0x04
0x4D
6
AEQ Bypass
RSVD
RW
R
0
0
5:0
7:0
Reserved
AEQ / Manual Eq
Readback
Read back the adaptive and manual
Equalization value
0x4E EQ Value
54
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Table 9. Clock Sources for Forward Channel Frame on the Serializer During Normal Operation
DS90UB913Q
REG 0x14 [2:1]
10-BIT
MODE
12-BIT
12-BIT
HIGH-FREQUENCY MODE
LOW-FREQUENCY MODE
00
01
10
11
50 MHz
100 MHz
50 MHz
25MHz
37.5 MHz
75 MHz
25 MHz
50 MHz
25 MHz
12.5 MHz
37.5 MHz
18.75 MHz
Table 10. BIST Clock Sources
DS90UB914Q
REG 0x24 [2:1]
10-BIT
MODE
12-BIT
12-BIT
HIGH-FREQUENCY MODE
LOW-FREQUENCY MODE
00
01
10
11
PCLK
100 MHz
50 MHz
25MHz
PCLK
PCLK
50 MHz
25 MHz
12.5 MHz
75 MHz
37.5 MHz
18.75 MHz
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11 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
11.1 Applications Information
The serializer and deserializer support only AC-coupled interconnects through an integrated DC-balanced
decoding scheme. External AC-coupling capacitors must be placed in series in the FPD-Link III signal path as
illustrated in Figure 45.
D
+
OUT
R
IN
+
D
R
R
IN
-
D
-
OUT
Figure 45. AC-Coupled Connection
For high-speed FPD-Link III transmissions, the smallest available package should be used for the AC-coupling
capacitor. This will help minimize degradation of signal quality due to package parasitics. The I/Os require a
100-nF AC-coupling capacitors to the line.
11.2 Typical Application
DS90UB913Q
Serializer
DS90UB914Q
Deserializer
FPD-Link III
Camera Data
Camera Data
DOUT+
DOUT-
10 or 12
RIN+
RIN-
10 or 12
ROUT[11:0]
or
ROUT[9:0]
HSYNC,
VSYNC
DIN[11:0] or
DIN[9:0]
HSYNC,
VSYNC
Image
Sensor
DATA
DATA
HSYNC
HSYNC
VSYNC
VSYNC
Bi-Directional
PCLK
PCLK
ECU Module
Pixel Clock
Control Channel
Pixel Clock
4
4
GPO[3:0]
GPIO[3:0]
GPO[3:0]
GPIO[3:0]
Microcontroller
SDA
SCL
SDA
SCL
SDA
SCL
SDA
SCL
Camera Unit
Figure 46. Application Block Diagram
11.2.1 Design Requirements
11.2.1.1 Transmission Media
The DS90UB91xQ-Q1 chipset is intended to be used in a point-to-point configuration through a shielded twisted
pair cable. The serializer and deserializer provide internal termination to minimize impedance discontinuities. The
interconnect (cable and connectors) should have a differential impedance of 100 Ω. The maximum length of
cable that can be used is dependent on the quality of the cable (gauge, impedance), connector, board
(discontinuities, power plane), the electrical environment (for example, power stability, ground noise, input clock
jitter, PCLK frequency, and so forth). The resulting signal quality at the receiving end of the transmission media
may be assessed by monitoring the differential eye opening of the serial data stream. A differential probe should
be used to measure across the termination resistor at the CMLOUTP/N pins. Figure 20 illustrates the minimum
eye width and eye height that is necessary for bit error free operation.
56
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Typical Application (continued)
11.2.1.2 Adaptive Equalizer – Loss Compensation
The adaptive equalizer is designed to compensate for signal degradation due to the differential insertion loss of
the interconnect components. There are limits to the amount of loss that can be compensated – these limits are
defined by the gain curve of the equalizer. In addition, there is an inherent tolerance for loss defined by the delta
between the minimum VDO of the serializer and the input threshold (Vswing) of the deserializer. In order to
determine the maximum cable reach, other factors that affect signal integrity such as jitter, skew, ISI, crosstalk,
and so forth, need to be taken into consideration. Figure 49 illustrates the maximum allowable interconnect loss
with the adaptive equalizer at its maximum gain setting (914 equalizer gain).
11.2.2 Detailed Design Procedure
Figure 47 shows the typical connection of a DS90UB913Q-Q1 serializer.
VDDIO
DS90UB913Q (SER)
1.8V
VDDT
VDDIO
C3
C8
C4
C10
C11
C7
C9
C13
1.8V
DIN0
DIN1
DIN2
DIN3
DIN4
DIN5
DIN6
VDDPLL
VDDCML
VDDD
C14
C5
C6
FB1
FB2
1.8V
C15
C12
1.8V
DIN7
DIN8
DIN9
DIN10
DIN11
HS
LVCMOS
Parallel
Bus
C1
C2
VS
PCLK
1.8V
Serial
FPD-Link III
Interface
DOUT+
DOUT-
10 k:
MODE
1.8V
RID
10 k:
LVCMOS
ID[X]
Control
Interface
RID
PDB
GPO[0]
GPO[1]
GPO[2]
GPO[3]
GPO
Control
Interface
NOTE:
C1 - C2 = 0.1 PF (50 WV)
C3 ± C7 = 0.01 PF
C8 - C12 = 0.1 PF
C13 - C14 = 4.7 PF
VDDIO
C15 = 22 PF
C16 - C17 = >100 pF
RPU = 1 k: to 4.7 k:
RID (see ID[x] Resistor Value Table)
FB1 - FB4: Impedance = 1 k: (@ 100 MHz)
low DC resistance (<1:)
RPU
RPU
C17
I2C
Bus
SCL
SDA
FB3
RES
DAP (GND)
Interface
FB4
C16
The "Optional" components shown are
provisions to provide higher system noise
immunity and will therefore result in higher
performance.
Optional
Optional
Figure 47. DS90UB913Q-Q1 Typical Connection Diagram — Pin Control
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Typical Application (continued)
Figure 48 shows a typical connection of the DS90UB914Q-Q1 deserializer.
DS90UB914Q (Des)
1.8V
VDDIO
VDDD
VDDIO1
VDDIO2
VDDIO3
C3
C11
C8
C16
C18
VDDR
C9
C4
C5
C12
C13
VDDSSCG
VDDPLL
VDDCML
C10
1.8V
1.8V
ROUT0
ROUT1
ROUT2
ROUT3
ROUT4
ROUT5
ROUT6
C14
C17
C19
C6
FB1
FB2
C15
C1
C7
LVCMOS
Parallel
Outputs
ROUT7
ROUT8
ROUT9
ROUT10
ROUT11
HS
RIN1+
RIN1-
Serial
FPD-Link II
Interface
C2
C1
RIN0+
RIN0-
VS
PCLK
C2
LOCK
PASS
1.8V
1.8V
GPIO[0]
GPIO[1]
GPIO[2]
10 k:
10 k:
GPIO[3]
MODE
IDx[0]
RMODE
RID0
PDB
SEL
OEN
1.8V
OSS_SEL
BISTEN
VDDIO
RPU
10 k:
IDx[1]
RPU
C21
RID1
I2C
SCL
SDA
Bus
FB3
NOTE:
Interface
C1 - C2 = 0.1 PF (50 WV)
C3 - C10 = 0.01 PF
FB4
C20
C11 - C16 = 0.1 PF
Optional
C17 - C18 = 4.7 PF
C19 = 22 PF
C20 - C21 = >100 pF
RPU = 1 k: to 4.7 k:
Optional
RES_PIN43
DAP (GND)
RID (see ID[x] Resistor Value Table)
FB1 - FB4: Impedance = 1 k: (@ 100 MHz)
low DC resistance (<1:)
The "Optional" components shown are
provisions to provide higher system noise
immunity and will therefore result in higher
performance.
Figure 48. DS90UB914Q-Q1 Typical Connection Diagram — Pin Control
58
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Typical Application (continued)
11.2.3 Application Curve
25
20
15
10
5
914 Equalizer Gain (dB)
VOD-Vswing Loss
Allowable Interconnect
Loss
0
100
200
300
400
500 600
700
SERIAL LINE FREQUENCY (MHz)
Figure 49. Adaptive Equalizer – Interconnect Loss Compensation
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12 Power Supply Recommendations
This device is designed to operate from an input core voltage supply of 1.8 V. Some devices provide separate
power and ground terminals for different portions of the circuit. This is done to isolate switching noise effects
between different sections of the circuit. Separate planes on the PCB are typically not required. Terminal
description tables typically provide guidance on which circuit blocks are connected to which power terminal pairs.
In some cases, an external filter may be used to provide clean power to sensitive circuits such as PLLs.
13 Layout
13.1 Layout Guidelines
Printed-circuit-board layout and stack-up for the serializer and deserializer devices should be designed to provide
low-noise power feed to the device. Good layout practice will also separate high frequency or high-level inputs
and outputs to minimize unwanted stray noise pickup, feedback and interference. Power system performance
may be greatly improved by using thin dielectrics (2 to 4 mils) for power/ground sandwiches. This arrangement
provides plane capacitance for the PCB power system with low-inductance parasitics, which has proven
especially effective at high frequencies, and makes the value and placement of external bypass capacitors less
critical. External bypass capacitors should include both RF ceramic and tantalum electrolytic types. RF capacitors
may use values in the range of 0.01 µF to 0.1 µF. Tantalum capacitors may be in the 2.2-µF to 10-µF range.
Voltage rating of the tantalum capacitors should be at least 5× the power supply voltage being used.
Surface mount capacitors are recommended due to their smaller parasitics. When using multiple capacitors per
supply pin, locate the smaller value closer to the pin. A large bulk capacitor is recommend at the point of power
entry. This is typically in the 50-µF to 100-µF range and will smooth low frequency switching noise. It is
recommended to connect power and ground pins directly to the power and ground planes with bypass capacitors
connected to the plane with a via on both ends of the capacitor. Connecting power or ground pins to an external
bypass capacitor will increase the inductance of the path.
A small body size X7R chip capacitor, such as 0603, is recommended for external bypass. Its small body size
reduces the parasitic inductance of the capacitor. The user must pay attention to the resonance frequency of
these external bypass capacitors, usually in the range of 20 to 30 MHz. To provide effective bypassing, multiple
capacitors are often used to achieve low impedance between the supply rails over the frequency of interest. At
high frequency, it is also a common practice to use two vias from power and ground pins to the planes, reducing
the impedance at high frequency.
Some devices provide separate power for different portions of the circuit. This is done to isolate switching noise
effects between different sections of the circuit. Separate planes on the PCB are typically not required. Pin
description tables typically provide guidance on which circuit blocks are connected to which power pin pairs. In
some cases, an external filter many be used to provide clean power to sensitive circuits such as PLLs.
Use at least a four-layer board with a power and ground plane. Locate LVCMOS signals away from the
differential lines to prevent coupling from the LVCMOS lines to the differential lines. Closely-coupled differential
lines of 100 Ω are typically recommended for differential interconnect. The closely coupled lines help to ensure
that coupled noise will appear as common-mode and thus is rejected by the receivers. The tightly coupled lines
will also radiate less.
Information on the WQFN style package is provided in Texas Instruments' Application Note: AN-1187
(SNOA401).
See AN-1108 (SNLA008) and AN-905 (SNLA035) for full details.
•
•
Use 100-Ω coupled differential pairs
Use the S, 2S, and 3S rule in spacings
–
–
–
S = space between the pair
2S = space between pairs
3S = space to LVCMOS signal
•
•
•
•
Minimize the number of Vias
Use differential connectors when operating above 500Mbps line speed
Maintain balance of the traces
Minimize skew within the pair
60
Copyright © 2012–2015, Texas Instruments Incorporated
DS90UB913Q-Q1, DS90UB914Q-Q1
www.ti.com.cn
ZHCSDZ6D –JULY 2012–REVISED JULY 2015
Layout Guidelines (continued)
Additional general guidance can be found in the LVDS Owner’s Manual - available in PDF format from the Texas
Instrument web site at: www.ti.com/lvds
13.2 Layout Example
Stencil parameters such as aperture area ratio and the fabrication process have a significant impact on paste
deposition. Inspection of the stencil prior to placement of the WQFN package is highly recommended to improve
board assembly yields. If the via and aperture openings are not carefully monitored, the solder may flow
unevenly through the DAP. Stencil parameters for aperture opening and via locations are shown in Figure 50.
Figure 50. No Pullback WQFN, Single Row Reference Diagram
Figure 50 and Figure 51 PCB layout examples are derived from the layout design of the DS90UB913Q-Q1
Serializer and DS90UB914Q-Q1 Deserializer Evaluation Kit (SNLU110). These graphics and additional layout
description are used to demonstrate both proper routing and proper solder techniques when designing in the
serializer and deserializer.
Table 11. No Pullback WQFN Stencil Aperture Summary for DS90UB913Q-Q1 and DS90UB914Q-Q1
GAP
BETWEEN
DAP
APERTURE
(Dim A mm)
STENCIL
DAP
APERTURE
(mm)
NUMBER OF
DAP
APERTURE
OPENINGS
PCB I/O PAD
SIZE
PCB
PITCH
(mm)
PCB DAP
SIZE
(mm)
STENCIL I/O
APERTURE
(mm)
PIN
COUNT
DEVICE
MKT DWG
(mm)
DS90UB913Q-Q1
DS90UB914Q-Q1
32
48
RTV
RHS
0.25 x 0.6
0.25 x 0.6
0.5
0.5
3.1 x 3.1
5.1 x 5.1
0.25 x 0.7
0.25 x 0.7
1.4 x 1.4
1.1 x 1.1
4
0.2
0.2
16
版权 © 2012–2015, Texas Instruments Incorporated
61
DS90UB913Q-Q1, DS90UB914Q-Q1
ZHCSDZ6D –JULY 2012–REVISED JULY 2015
www.ti.com.cn
Figure 51. 48-Pin WQFN Stencil Example of Via and Opening Placement
62
版权 © 2012–2015, Texas Instruments Incorporated
DS90UB913Q-Q1, DS90UB914Q-Q1
www.ti.com.cn
ZHCSDZ6D –JULY 2012–REVISED JULY 2015
14 器件和文档支持
14.1 文档支持
14.1.1 相关文档
相关文档如下：
•
•
•
•
•
《焊接相关的最大绝对额定值》，SNOA549
AN-1187《无引线框架封装 (LLP)》，SNOA401
AN-1108《通道链路 PCB 和互连设计指南》，SNLA008
《传输线路 RAPIDESIGNER 操作和应用指南》，SNLA035
《DS90UB913Q-Q1 串行器和 DS90UB914Q-Q1 解串器评估套件》，SNLU110
14.2 相关链接
以下表格列出了快速访问链接。 范围包括技术文档、支持与社区资源、工具和软件，并且可以快速访问样片或购买
链接。
表 12. 相关链接
器件
产品文件夹
请单击此处
请单击此处
样片与购买
请单击此处
请单击此处
技术文档
请单击此处
请单击此处
工具与软件
请单击此处
请单击此处
支持与社区
请单击此处
请单击此处
DS90UB913Q-Q1
DS90UB914Q-Q1
14.3 社区资源
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
14.4 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
14.5 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
14.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
15 机械、封装和可订购信息
以下页中包括机械、封装和可订购信息。 这些信息是针对指定器件可提供的最新数据。 这些数据会在无通知且不
对本文档进行修订的情况下发生改变。 欲获得该数据表的浏览器版本，请查阅左侧的导航栏。
版权 © 2012–2015, Texas Instruments Incorporated
63
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
DS90UB913QSQ/NOPB
DS90UB913QSQE/NOPB
DS90UB913QSQX/NOPB
DS90UB914QSQ/NOPB
DS90UB914QSQE/NOPB
DS90UB914QSQX/NOPB
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
WQFN
WQFN
WQFN
WQFN
WQFN
WQFN
RTV
RTV
RTV
RHS
RHS
RHS
32
32
32
48
48
48
1000 RoHS & Green
250 RoHS & Green
SN
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 105
-40 to 105
-40 to 105
-40 to 105
-40 to 105
-40 to 105
UB913SQ
SN
SN
SN
SN
SN
UB913SQ
4500 RoHS & Green
1000 RoHS & Green
UB913SQ
UB914QSQ
UB914QSQ
UB914QSQ
250
RoHS & Green
2500 RoHS & Green
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
DS90UB913QSQ/NOPB WQFN
DS90UB913QSQE/NOPB WQFN
DS90UB913QSQX/NOPB WQFN
DS90UB914QSQ/NOPB WQFN
DS90UB914QSQE/NOPB WQFN
DS90UB914QSQX/NOPB WQFN
RTV
RTV
RTV
RHS
RHS
RHS
32
32
32
48
48
48
1000
250
178.0
178.0
330.0
330.0
178.0
330.0
12.4
12.4
12.4
16.4
16.4
16.4
5.3
5.3
5.3
7.3
7.3
7.3
5.3
5.3
5.3
7.3
7.3
7.3
1.3
1.3
1.3
1.3
1.3
1.3
8.0
8.0
12.0
12.0
12.0
16.0
16.0
16.0
Q1
Q1
Q1
Q1
Q1
Q1
4500
1000
250
8.0
12.0
12.0
12.0
2500
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
DS90UB913QSQ/NOPB
DS90UB913QSQE/NOPB
DS90UB913QSQX/NOPB
DS90UB914QSQ/NOPB
DS90UB914QSQE/NOPB
DS90UB914QSQX/NOPB
WQFN
WQFN
WQFN
WQFN
WQFN
WQFN
RTV
RTV
RTV
RHS
RHS
RHS
32
32
32
48
48
48
1000
250
208.0
208.0
356.0
356.0
208.0
356.0
191.0
191.0
356.0
356.0
191.0
356.0
35.0
35.0
35.0
35.0
35.0
35.0
4500
1000
250
2500
Pack Materials-Page 2
PACKAGE OUTLINE
RTV0032A
WQFN - 0.8 mm max height
S
C
A
L
E
2
.
5
0
0
PLASTIC QUAD FLATPACK - NO LEAD
5.15
4.85
A
B
PIN 1 INDEX AREA
5.15
4.85
0.8
0.7
C
SEATING PLANE
0.08 C
0.05
0.00
2X 3.5
SYMM
EXPOSED
THERMAL PAD
(0.1) TYP
9
16
8
17
SYMM
33
2X 3.5
3.1 0.1
28X 0.5
1
24
0.30
32X
0.18
32
25
PIN 1 ID
0.1
C A B
0.5
0.3
32X
0.05
4224386/B 04/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RTV0032A
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(3.1)
SYMM
SEE SOLDER MASK
DETAIL
32
25
32X (0.6)
1
24
32X (0.24)
28X (0.5)
(3.1)
33
SYMM
(4.8)
(1.3)
8
17
(R0.05) TYP
(
0.2) TYP
VIA
9
16
(1.3)
(4.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 15X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
METAL UNDER
SOLDER MASK
METAL EDGE
EXPOSED METAL
SOLDER MASK
OPENING
EXPOSED
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4224386/B 04/2019
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
RTV0032A
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(0.775) TYP
25
32
32X (0.6)
1
32X (0.24)
28X (0.5)
24
(0.775) TYP
(4.8)
33
SYMM
(R0.05) TYP
4X (1.35)
17
8
9
16
4X (1.35)
SYMM
(4.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 MM THICK STENCIL
SCALE: 20X
EXPOSED PAD 33
76% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
4224386/B 04/2019
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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Copyright © 2023，德州仪器 (TI) 公司
相关型号：
DS90UB914QSQE/NOPB
DS90UB913Q/DS90UB914Q 10-100MHz 10/12- Bit DC-Balanced FPD-Link III Serializer and Deserializer with Bidirectional Control Channel
TAOS
DS90UB914QSQX/NOPB
DS90UB913Q/DS90UB914Q 10-100MHz 10/12- Bit DC-Balanced FPD-Link III Serializer and Deserializer with Bidirectional Control Channel
TAOS
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