LM74500QDDFRQ1 [TI]
反极性保护控制器 | DDF | 8 | -40 to 125;
| 型号： | LM74500QDDFRQ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 反极性保护控制器 | DDF | 8 | -40 to 125 控制器 |
| 文件： | 总27页 (文件大小：1588K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LM74500-Q1
ZHCSN02 –DECEMBER 2020
LM74500-Q1 反极性保护控制器
1 特性
3 说明
• 具有符合AEC-Q100 标准的下列特性
LM74500-Q1 是一款符合汽车 AEC Q100 标准的控制
器，与外部N 沟道MOSFET 配合工作，可作为实现低
损耗反极性保护的解决方案。3.2V 至 65V 的宽电源输
入范围可实现对众多常用直流总线电压（例如：12V、
24V 和 48V 汽车电池系统）的控制。3.2V 输入电压支
持适用于汽车系统中严苛的冷启动要求。该器件可以承
受并保护负载免受低至 -65V 的负电源电压的影响。
LM74500-Q1 没有反向电流阻断功能，适用于对有可
能将能量传输回输入电源的负载（如汽车车身控制模块
电机负载）进行输入反向极性保护。
– 器件温度等级1：
–40°C 至+125°C 环境工作温度范围
– 器件HBM ESD 分类等级2
– 器件CDM ESD 分类等级C4B
• 3.2V 至65V 输入范围（3.9V 启动）
• -65V 输入反向电压额定值
• 适用于外部N 沟道MOSFET 的电荷泵
• 使能引脚特性
• 1µA 关断电流（EN = 低电平）
• 80µA 典型工作静态电流（EN = 高电平）
• 采用额外的TVS 二极管，符合汽车ISO7637 脉冲
1 瞬态要求
LM74500-Q1 控制器可提供适用于外部 N 沟道
MOSFET 的电荷泵栅极驱动器。LM74500-Q1 的高电
压额定值有助于简化满足 ISO7637 汽车保护测试标准
的系统设计。当使能引脚处于低电平时，控制器关闭，
消耗大约 1µA 的电流，从而在进入睡眠模式时提供低
系统电流。
• 采用8 引脚SOT-23 封装2.90mm × 1.60mm
2 应用
• 车身电子装置和照明
• 汽车信息娱乐系统- 数字仪表组、音响主机
• 汽车USB 集线器
器件信息(1)
封装尺寸（标称值）
器件型号
封装
SOT-23 (8)
LM74500-Q1
2.90mm × 1.60mm
• 工业工厂自动化- PLC
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
VBAT
VOUT
Voltage
Regulator
SOURCE
VCAP
GATE
LM74500-Q1
GND
EN
OFF
ON
利用-12V 电源启动LM74500-Q1
LM74500-Q1 典型应用原理图
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SNOSDB7
LM74500-Q1
ZHCSN02 –DECEMBER 2020
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Table of Contents
9 Application and Implementation..................................12
9.1 Reverse Battery Protection for Automotive Body
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings ....................................... 4
6.2 ESD Ratings .............................................................. 4
6.3 Recommended Operating Conditions ........................4
6.4 Thermal Information ...................................................4
6.5 Electrical Characteristics ............................................5
6.6 Switching Characteristics ...........................................6
7 Typical Characteristics................................................... 7
8 Detailed Description........................................................9
8.1 Overview.....................................................................9
8.2 Functional Block Diagram...........................................9
8.3 Feature Description.....................................................9
8.4 Device Functional Modes..........................................11
Control Module Applications........................................12
9.2 Reverse Polarity Protection...................................... 14
9.3 Application Information............................................. 16
10 Power Supply Recommendations..............................20
11 Layout...........................................................................20
11.1 Layout Guidelines................................................... 20
11.2 Layout Example...................................................... 20
12 Device and Documentation Support..........................21
12.1 接收文档更新通知................................................... 21
12.2 支持资源..................................................................21
12.3 Trademarks.............................................................21
12.4 静电放电警告.......................................................... 21
12.5 术语表..................................................................... 21
13 Mechanical, Packaging, and Orderable
Information.................................................................... 22
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
DATE
REVISION
NOTES
December 2020
*
Initial release.
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5 Pin Configuration and Functions
N.C
EN
1
8
7
N.C
2
3
4
GND
N.C
GATE
6
5
SOURCE
VCAP
图5-1. DDF Package 8-Pin SOT-23 LM74500-Q1 Top View
表5-1. LM74500-Q1 Pin Functions
PIN
I/O(1)
DESCRIPTION
NO.
1
NAME
EN
I
G
-
Enable pin. Can be connected to SOURCE for always ON operation
2
GND
Ground pin
3
N.C
No connection
4
5
6
7
VCAP
SOURCE
GATE
O
I
Charge pump output. Connect to external charge pump capacitor
Input supply pin to the controller. Connect to the source of the external N-channel MOSFET
Gate drive output. Connect to gate of the external N-channel MOSFET
No connection
O
-
N.C
8
N.C
-
No connection
(1) I = Input, O = Output, G = GND
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–65
MAX
65
UNIT
V
SOURCE to GND
Input Pins
EN to GND, V(SOURCE) > 0 V
EN to GND, V(SOURCE) ≤0 V
GATE to SOURCE
65
V
–0.3
V(SOURCE)
–0.3
(65 + V(SOURCE)
)
V
15
15
V
Output Pins
VCAP to SOURCE
V
–0.3
Operating junction temperature(2)
Storage temperature, Tstg
150
150
°C
°C
–40
–40
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) High junction temperatures degrade operating lifetimes. Operating lifetime is de-rated for junction temperatures greater than 125°C.
6.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per AEC Q100-002(1)
±2000
Corner pins (EN, VCAP,
SOURCE, NC)
V(ESD)
Electrostatic discharge
±750
±500
V
Charged device model (CDM),
per AEC Q100-011
Other pins
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–60
–60
22
NOM
MAX
60
UNIT
SOURCE to GND
EN to GND
Input Pins
V
60
SOURCE
nF
µF
External
capacitance
VCAP to SOURCE
0.1
External
MOSFET max GATE to SOURCE
VGS rating
15
V
TJ
Operating junction temperature range(2)
150
°C
–40
(1) Recommended Operating Conditions are conditions under which the device is intended to be functional. For specifications and test
conditions, see electrical characteristics
(2) High junction temperatures degrade operating lifetimes. Operating lifetime is de-rated for junction temperatures greater than 125°C.
6.4 Thermal Information
LM74500-Q1
THERMAL METRIC(1)
DDF (SOT)
8 PINS
133.8
72.6
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
Junction-to-top characterization parameter
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
54.5
4.6
ΨJT
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6.4 Thermal Information (continued)
LM74500-Q1
DDF (SOT)
8 PINS
THERMAL METRIC(1)
UNIT
Junction-to-board characterization parameter
54.2
°C/W
ΨJB
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6.5 Electrical Characteristics
TJ = –40°C to +125°C; typical values at TJ = 25°C, V(SOURCE) = 12 V, C(VCAP) = 0.1 µF, V(EN) = 3.3 V, over operating free-air
temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
VSOURCE SUPPLY VOLTAGE
V(SOURCE)
Operating input voltage
4
60
3.9
V
V
VSOURCE POR Rising threshold
VSOURCE POR Falling threshold
V(SOURCE POR)
2.2
2.8
3.1
V
V(SOURCE POR(Hys)) VSOURCE POR Hysteresis
0.44
0.67
1.5
V
I(SHDN)
Shutdown Supply Current
V(EN) = 0 V
0.9
80
µA
µA
I(Q)
Operating Quiescent Current
130
ENABLE INPUT
V(EN_IL)
Enable input low threshold
Enable input high threshold
Enable Hysteresis
0.5
1.06
0.52
0.9
2
1.22
2.6
1.35
5
V
V(EN_IH)
V(EN_Hys)
I(EN)
V
Enable sink current
V(EN) = 12 V
3
µA
GATE DRIVE
Peak source current
Peak sink current
3
11
mA
mA
V
(GATE) –V(SOURCE) = 5 V
EN= High to Low
(GATE) –V(SOURCE) = 5 V
EN = High to Low
I(GATE)
2370
V
RDSON
discharge switch RDSON
0.4
2
Ω
V
(GATE) –V(SOURCE) = 100 mV
CHARGE PUMP
Charge Pump source current (Charge
pump on)
162
300
5
600
10
µA
µA
V
V
V
(VCAP) –V(SOURCE) = 7 V
(VCAP) –V(SOURCE) = 14 V
I(VCAP)
Charge Pump sink current (Charge
pump off)
Charge pump voltage at V(SOURCE)
3.2 V
=
V(VCAP)
V(SOURCE)
–
8
10.3
11
I
(VCAP) ≤30 µA
V(VCAP)
V(SOURCE)
–
Charge pump turn on voltage
Charge pump turn off voltage
11.6
12.4
0.8
13
13.9
1.2
V
V(VCAP)
V(SOURCE)
–
V
Charge Pump Enable comparator
Hysteresis
V(VCAP)
V(SOURCE)
–
0.4
V
V
(VCAP) –V(SOURCE) UV release at
V(VCAP UVLO)
5.7
6.5
7.5
V
rising edge
V
(VCAP) –V(SOURCE) UV threshold at
V(VCAP UVLO)
5.05
5.4
6.2
V
falling edge
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6.6 Switching Characteristics
TJ = –40°C to +125°C; typical values at TJ = 25°C, V(SOURCE) = 12 V, CIN = C(VCAP) = COUT = 0.1 µF, V(EN) = 3.3 V, over
operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
110 µs
Enable (low to high) to Gate Turn On
delay
ENTDLY
V(VCAP) > V(VCAP UVLOR)
75
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7 Typical Characteristics
3.6
3.3
3
700
630
560
490
420
350
280
210
140
70
-40
25
85
125
150
2.7
2.4
2.1
1.8
1.5
1.2
0.9
0.6
0.3
0
-40
25
85
125
150
0
0
5
10 15 20 25 30 35 40 45 50 55 60 65
VSOURCE (V)
0
5
10 15 20 25 30 35 40 45 50 55 60 65
VSOURCE (V)
7450
7450
图7-1. Shutdown Supply Current vs Supply Voltage
325
图7-2. Operating Quiescent Current vs Supply Voltage
500
-40
25
85
125
150
300
275
250
225
200
175
150
125
100
75
450
400
350
300
250
200
150
100
-40
25
85
125
150
3
4
5
6
7
VSOURCE (V)
8
9
10
11
12
0
2
4
6
VCAP (V)
8
10
12
CPI_
VCAP
图7-4. Charge Pump V-I Characteristics at VSOURCE > = 12 V
图7-3. Charge Pump Current vs Supply Voltage at VCAP = 6 V
220
200
2.5
-40
25
Enable Rising Threshold (V)
Enable Falling Threshold (V)
85
125
150
180
2.1
1.7
1.3
0.9
0.5
160
140
120
100
80
60
40
20
0
1
2
3
4
VCAP (V)
5
6
7
8
9
-40
0
40
80
120
160
Free-Air Temperature (èC)
VCAP
EN_R
图7-5. Charge Pump V-I Characteristics at VSOURCE = 3.2 V
图7-6. Enable Rising and Falling threshold vs Temperature
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7 Typical Characteristics (continued)
90
13.4
13.1
12.8
12.5
12.2
11.9
11.6
75
60
45
30
VCAP ON
VCAP OFF
ENTDLY ON
ENTDLY OFF
15
0
-40
0
40
80
120
160
-40
0
40
80
120
160
Free-Air Temperature (èC)
Free-Air Temperature (èC)
ENTD
VCAP
图7-7. Enable to Gate Delay vs Temperature
图7-8. Charge Pump ON/OFF Threshold vs Temperature
7
6.6
6.2
5.8
5.4
5
3.1
3.05
3
2.95
2.9
2.85
2.8
2.75
2.7
2.65
2.6
2.55
2.5
2.45
2.4
VSOURCE PORR
VSOURCE PORF
VCAP UVLOR
VCAP UVLOF
2.35
2.3
-40
0
40
80
120
160
-40 -20
0
20
40
60
80 100 120 140 160
Free-Air Temperature (èC)
Free-Air Temperature (èC)
VCAP
VANO
图7-9. Charge Pump UVLO Threshold vs Temperature
图7-10. VSOURCE POR Threshold vs Temperature
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8 Detailed Description
8.1 Overview
The LM74500-Q1 controller has all the features necessary to implement an efficient and fast reverse polarity
protection circuit. This easy to use reverse polarity protection controller is paired with an external N-channel
MOSFET to replace other reverse polarity schemes such as a P-channel MOSFET. An internal charge pump is
used to drive the external N-Channel MOSFET to a maximum gate drive voltage of approximately 15 V. An
enable pin, EN is available to place the LM74500-Q1 in shutdown mode disabling the N-Channel MOSFET and
minimizing the quiescent current.
8.2 Functional Block Diagram
SOURCE
GATE
VCAP
Bias Rails
VSOURCE
ENGATE
VSOURCE
VCAP_UV
VSOURCE
GATE DRIVER
ENABLE
LOGIC
VCAP_UV
VSOURCE
VSOURCE
Charge Pump
Enable Logic
Charge
Pump
REVERSE
PROTECTION
LOGIC
VCAP
VCAP_UV
ENABLE LOGIC
VCAP
VCAP
EN
GND
8.3 Feature Description
8.3.1 Input Voltage
The SOURCE pin is used to power the LM74500-Q1's internal circuitry, typically drawing 80 µA when enabled
and 1 µA when disabled. If the SOURCE pin voltage is greater than the POR Rising threshold, then LM74500-
Q1 operates in either shutdown mode or conduction mode in accordance with the EN pin voltage. The voltage
from SOURCE to GND is designed to vary from 65 V to –65 V, allowing the LM74500-Q1 to withstand negative
voltage transients.
8.3.2 Charge Pump
The charge pump supplies the voltage necessary to drive the external N-channel MOSFET. An external charge
pump capacitor is placed between VCAP and SOURCE pin to provide energy to turn on the external MOSFET.
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In order for the charge pump to supply current to the external capacitor the EN pin voltage must be above the
specified input high threshold, V(EN_IH). When enabled the charge pump sources a charging current of 300 µA
typically. If EN pins is pulled low, then the charge pump remains disabled. To ensure that the external MOSFET
can be driven above its specified threshold voltage, the VCAP to SOURCE voltage must be above the
undervoltage lockout threshold, typically 6.5 V, before the internal gate driver is enabled. Use 方程式 1 to
calculate the initial gate driver enable delay.
V
(VCAP _UVLOR)
T DRV _EN = 75ms + C(VCAP)
x
(
)
300mA
(1)
where
• C(VCAP) is the charge pump capacitance connected across SOURCE and VCAP pins
• V(VCAP_UVLOR) = 6.5 V (typical)
To remove any chatter on the gate drive approximately 800 mV of hysteresis is added to the VCAP undervoltage
lockout. The charge pump remains enabled until the VCAP to SOURCE voltage reaches 12.4 V, typically, at
which point the charge pump is disabled decreasing the current draw on the SOURCE pin. The charge pump
remains disabled until the VCAP to SOURCE voltage is below to 11.6 V typically at which point the charge pump
is enabled. The voltage between VCAP and SOURCE continue to charge and discharge between 11.6 V and
12.4 V as shown in 图 8-1. By enabling and disabling the charge pump, the operating quiescent current of the
LM74500-Q1 is reduced. When the charge pump is disabled it sinks 5-µA typical.
TDRV_EN
TON
TOFF
VIN
VSOURCE
0V
VEN
12.4 V
11.6 V
VCAP-VSOURCE
6.5 V
V(VCAP UVLOR)
GATE DRIVER
ENABLE
图8-1. Charge Pump Operation
8.3.3 Gate Driver
The gate driver is used to control the external N-Channel MOSFET by setting the appropriate GATE to SOURCE
voltage .
Before the gate driver is enabled following three conditions must be achieved:
• The EN pin voltage must be greater than the specified input high voltage.
• The VCAP to SOURCE voltage must be greater than the undervoltage lockout voltage.
• The SOURCE voltage must be greater than VSOURCE POR Rising threshold.
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If the above conditions are not achieved, then the GATE pin is internally connected to the SOURCE pin, assuring
that the external MOSFET is disabled. Once these conditions are achieved the gate driver operates in the
conduction mode enhancing the external MOSFET completely.
8.3.4 Enable
The LM74500-Q1 has an enable pin, EN. The enable pin allows for the gate driver to be either enabled or
disabled by an external signal. If the EN pin voltage is greater than the rising threshold, the gate driver and
charge pump operates as described in Gate Driver and Charge Pump sections. If the enable pin voltage is less
than the input low threshold, the charge pump and gate driver are disabled placing the LM74500-Q1 in shutdown
mode. The EN pin can withstand a voltage as large as 65 V and as low as –65 V. This allows for the EN pin to
be connected directly to the SOURCE pin if enable functionality is not needed. In conditions where EN is left
floating, the internal sink current of 3 uA pulls EN pin low and disables the device.
8.4 Device Functional Modes
8.4.1 Shutdown Mode
The LM74500-Q1 enters shutdown mode when the EN pin voltage is below the specified input low threshold
V(EN_IL). Both the gate driver and the charge pump are disabled in shutdown mode. During shutdown mode the
LM74500-Q1 enters low IQ operation with the SOURCE pin only sinking 1 µA. When the LM74500-Q1 is in
shutdown mode, forward current flow through the external MOSFET is not interrupted but is conducted through
the MOSFET's body diode.
8.4.2 Conduction Mode
For the LM74500-Q1 to operate in conduction mode the gate driver must be enabled as described in the Gate
Driver section. If these conditions are achieved the GATE pin is internally connected to the VCAP pin resulting in
the GATE to SOURCE voltage being approximately the same as the VCAP to SOURCE voltage. By connecting
VCAP to GATE the external MOSFET's RDS(ON) is minimized reducing the power loss of the external MOSFET
when forward currents are large.
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9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Reverse Battery Protection for Automotive Body Control Module Applications
Reverse-battery protection activates when battery terminals are incorrectly connected during jump start, vehicle
maintenance or service because a connection error can damage the components in ECUs if they are not rated to
handle reverse polarity. An N-channel MOSFET (N-FET) based reverse polarity protection solutions are
becoming obivious choice over discrete reverse-battery protection solutions like Schottky diodes and P-channel
field-effect transistors (P-FETs) due to their better power and thermal efficiency and the comparitively smaller
space they consume on a printed circuit board. Based on the application needs, reverse polarity protection
solutions can be divided into two main categories
• Applications which need both input reverse polarity protection and reverse current blocking
• Applications which need only input reverse polarity protection and does not need reverse current blocking
图9-1 provides an overview of these two reverse polarity protection solution categories. Typically for applications
where output loads are DC/DC converters, voltage regulator followed by MCU/processors (Logic paths), input
reverse polarity protection and reverse current blocking feature is required. For reverse polarity protection
solution of the logic path ideal diode controllers such as LM74700-Q1 is a suitable device.
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For the applications such as Body Control Module (BCM) load driving paths, input reverse polarity protection is
required but reverse current blocking is not a must have feature. For reverse polarity protection solution of the
BCM load driving paths, reverse polarity potection controllers such as LM74500-Q1 is a suitable device.
Load Driving Path
ñ
ñ
Reverse Polarity Protection: Required
Revere Current Blocking: Not Required
Wiper/Washer
Relays
LM74500-Q1
Horn/Alarm
VBAT
Linear
Regulator
DC/DC
Converters
LM74700-Q1
Voltage
Supervisors
Logic Path
ñ
ñ
Reverse Polarity Protection: Required
Revere Current Blocking: Required
图9-1. Typical Block Diagram for Automotive BCM Reverse Battery Protection Solution
For certain applications such as body control module load driving paths where output loads are inductive in
nature such as wiper motor, door control module, it is required that reverse polarity protection device should
provide protection against incorrect input polarity. However, it should not block reverse current from loads back
to the battery. This is mainly required to avoid voltage overshoot which is caused when inductive loads are
turned off. If reverse polarity protection device blocks the reverse current then there could be voltage overshoot
caused due to inductive kick back or motor regenrative action and can damage parallel loads connected on the
output of reverse polarity protection device. For certain specific loads such as wiper motor, a voltage overshoot
is seen due to transformer effect when wiper motor speed is changed from fast speed to slow speed. LM74500-
Q1 is designed to provide protection against input reverse polarity for such applications where reverse current
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blocking is not reuiqred. 图 9-2 shows typical application circuit of reverse polarity protection of body control
module load driving paths.
Reverse current
blocking is not
preferred
Wiper/
Washer
Q1
Door module
Relays
CIN
COUT
GATE
LM74500
GND
VBAT
Input
TVS
EN
SOURCE
VCAP
Lighting
Modules
Input reverse polarity
protection is required
VCAP
图9-2. Typical Block Diagram of Reverse Battery Protection for Body Control Module Load Driving Path
9.2 Reverse Polarity Protection
P-FET based reverse polarity protection is a very commonly used scheme in industrial and automotive
applications to achieve low insertion loss protection solution. A low loss reverse polarity protection solution can
be realised using LM74500-Q1 with an external N-FET to replace P-FET based solution. LM74500-Q1 based
reverse polarity protection solution offers better cold crank performance (low VIN operation) and smaller solution
size compared to P-FET based solution. 图 9-3 compares the performance benefits of LM74500-Q1 +N-FET
over traditional P-FET based reverse polarity protection solution. As shown in 图 9-3, for a given power level
LM74500-Q1+N-FET solution can be three times smaller than a similar power rated P-FET solution. Also as P-
FET is self biased by simply pulling it's gate pin low and thus P-FET shows poorer cold crank performance (low
VIN operation) compared to LM74500-Q1. During severe cold crank where battery voltage falls below 4 V, P-FET
series resistance increase drastically as shown in 图 9-3. This leads to higher voltage drop across the P-FET.
Also with higher gate to source threshold (VT) this can sometimes lead to system reset due to turning off of the
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P-FET. On the other side LM74500-Q1 has excellent severe cold crank performance. LM74500-Q1 keeps
external FET completely enhanced even when input voltage falls to 3.2 V during severe cold crank operation.
Parameter
P-FET
LM74500-Q1 + N-FET
VOUT
COUT
VBATT
VOUT
COUT
VBATT
TVS
CIN
TVS
Typical Application
Diagram
CIN
SOURCE
VCAP
GATE
D1
CVCAP
LM74500-Q1
GND
R1
EN
Solution Size
(Load current >6A)
12mm x 11.7mm
(140mm2)
7mm x 5.3mm
(37.1mm2)
Better cold crank performance compared to PFET
based solution. External N-FET remains fully enhanced
even if input voltage falls to 3.2V.
Low VIN / Cold-Crank
Performance
图9-3. Performance Comparison of P-FET and LM74500-Q1 Based Reverse Polarity Protection Solution
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9.3 Application Information
The LM74500-Q1 is used with N-Channel MOSFET controller in a typical reverse polarity protection application.
The schematic for the 12-V battery protection application is shown in 图 9-4 where the LM74500-Q1 is used to
drive the MOSFET Q1 in series with a battery. The TVS is not required for the LM74500-Q1 to operate, but they
are used to clamp the positive and negative voltage surges. The output capacitor COUT is recommended to
protect the immediate output voltage collapse as a result of line disturbance.
9.3.1 Typical Application
Q1
Voltage
Regulator
COUT
CIN
VBAT
GATE
LM74500
GND
EN
TVS
SOURCE
VCAP
VCAP
图9-4. Typical Application Circuit
9.3.1.1 Design Requirements
A design example, with system design parameters listed in 表9-1 is presented.
表9-1. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
12-V Battery, 12-V Nominal with 3.2-V Cold Crank and 35-V Load
Dump
Input voltage range
Output voltage
Output current range
3.2 V during Cold Crank to 35-V Load Dump
3-A Nominal, 5-A Maximum
Output capacitance
220-µF Typical Output Capacitance
ISO 7637-2 and ISO 16750-2
Automotive EMC Compliance
9.3.1.2 Detailed Design Procedure
9.3.1.2.1 Design Considerations
• Input operating voltage range, including cold crank and load dump conditions
• Nominal load current and maximum load current
9.3.1.2.2 MOSFET Selection
The important MOSFET electrical parameters are the maximum continuous drain current ID, the maximum drain-
to-source voltage VDS(MAX), the maximum source current through body diode and the drain-to-source On
resistance RDSON
.
The maximum continuous drain current, ID, rating must exceed the maximum continuous load current. The
maximum drain-to-source voltage, VDS(MAX), must be high enough to withstand the highest differential voltage
seen in the application. This would include any anticipated fault conditions. It is recommended to use MOSFETs
with voltage rating up to 60-V maximum with the LM74500-Q1 because SOURCE pin maximum voltage rating is
65-V. The maximum VGS LM74500-Q1 can drive is 13 V, so a MOSFET with 15-V minimum VGS rating should be
selected. If a MOSFET with VGS rating < 15 V is selected, a zener diode can be used to clamp VGS to safe level.
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During startup, inrush current flows through the body diode to charge the bulk hold-up capacitors at the output.
The maximum source current through the body diode must be higher than the inrush current that can be seen in
the application.
To reduce the MOSFET conduction losses, lowest possible RDS(ON) is preferred.
Based on the design requirements, preferred MOSFET ratings are:
• 60-V VDS(MAX) and ±20-V VGS(MAX)
DMT6007LFG MOSFET from Diodes Inc. is selected to meet this 12-V reverse battery protection design
requirements and it is rated at:
• 60-V VDS(MAX) and ±20-V VGS(MAX)
• RDS(ON) 6.5-mΩtypical and 8.5-mΩmaximum rated at 4.5-V VGS to ensure lower power dissipationa cross
the FET
Thermal resistance of the MOSFET should be considered against the expected maximum power dissipation in
the MOSFET to ensure that the junction temperature (TJ) is well controlled.
9.3.1.2.3 Charge Pump VCAP, Input and Output Capacitance
Minimum required capacitance for charge pump VCAP and input/output capacitance are:
• VCAP: Minimum 0.1 µF is required; recommended value of VCAP (µF) ≥10 x CISS(MOSFET) (µF)
• CIN: Typical input capacitor of 0.1 µF
• COUT: Typical output capacitor 220 µF
9.3.1.3 Selection of TVS Diodes for 12-V Battery Protection Applications
TVS diodes are used in automotive systems for protection against transients. In the 12-V battery protection
application circuit shown in 图 9-5, a bi-directional TVS diode is used to protect from positive and negative
transient voltages that occur during normal operation of the car and these transient voltage levels and pulses are
specified in ISO 7637-2 and ISO 16750-2 standards.
The two important specifications of the TVS are breakdown voltage and clamping voltage. Breakdown voltage is
the voltage at which the TVS diode goes into avalanche similar to a zener diode and is specified at a low current
value typical 1 mA and the breakdown voltage should be higher than worst case steady state voltages seen in
the system. The breakdown voltage of the TVS+ should be higher than 24-V jump start voltage and 35-V
suppressed load dump voltage and less than the maximum input voltage rating of LM74500-Q1 (65 V). The
breakdown voltage of TVS- should be higher than maximum reverse battery voltage –16 V, so that the TVS- is
not damaged due to long time exposure to reverse connected battery.
Clamping voltage is the voltage the TVS diode clamps in high current pulse situations and this voltage is much
higher than the breakdown voltage. TVS diodes are meant to clamp transient pulses and should not interfere
with steady state operation. In the case of an ISO 7637-2 pulse 1, the input voltage goes up to –150 V with a
generator impedance of 10 Ω. This translates to 15 A flowing through the TVS - and the voltage across the TVS
would be close to its clamping voltage.
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Q1
Voltage
Regulator
CIN
0.1uF
COUT
220uF
VBAT
GATE
LM74500
GND
EN
TVS
SMBJ33CA
SOURCE
VCAP
0.1uF
VCAP
图9-5. Typical 12-V Battery Protection with Single Bi-Directional TVS
The next criterion is that the absolute minimum rating of source voltage of the LM74500-Q1 (–65 V) and the
maximum VDS rating MOSFET are not exceeded. In the design example, 60-V rated MOSFET is chosen.
SMBJ series of TVS' are rated up to 600-W peak pulse power levels. This is sufficient for ISO 7637-2 pulses and
suppressed load dump (ISO-16750-2 pulse B).
9.3.1.4 Selection of TVS Diodes and MOSFET for 24-V Battery Protection Applications
Typical 24-V battery protection application circuit shown in 图 9-6 uses two uni-directional TVS diodes to protect
from positive and negative transient voltages.
Q1
Voltage
Regulator
TVS+
CIN
0.1uF
COUT
220uF
SMBJ58A
VBAT
GATE
LM74500
GND
EN
SOURCE
TVS-
SMBJ26A
VCAP
0.1uF
VCAP
图9-6. Typical 24-V Battery Protection with Two Uni-Directional TVS
The breakdown voltage of the TVS+ should be higher than 48-V jump start voltage, less than the absolute
maximum ratings of source and enable pin of LM74500-Q1 (65 V) and should withstand 65-V suppressed load
dump. The breakdown voltage of TVS- should be lower than maximum reverse battery voltage –32 V, so that
the TVS- is not damaged due to long time exposure to reverse connected battery.
During ISO 7637-2 pulse 1, the input voltage goes up to –600 V with a generator impedance of 50 Ω. Single bi-
directional TVS cannot be used for 24-V battery protection because breakdown voltage for TVS+ ≥ 48V,
maximum negative clamping voltage is ≤ –65 V . Two uni-directional TVS connected back-back needs to be
used at the input. For positive side TVS+, SMBJ58A with the breakdown voltage of 64.4 V (minimum), 67.8
(typical) is recommended. For the negative side TVS-, SMBJ26A with breakdown voltage close to 32 V (to
withstand maximum reverse battery voltage –32 V) and maximum clamping voltage of 42 V is recommended.
For 24-V battery protection, a 75-V rated MOSFET is recommended to be used along with SMBJ26A and
SMBJ58A connected back-back at the input.
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9.3.1.5 Application Curves
图9-7. ISO 7637-2 Pulse 1
Time (2 ms/DIV)
图9-8. Response to ISO 7637-2 Pulse 1
Time (20 ms/DIV)
Time (20ms/DIV)
图9-9. Startup with 3-A Load
图9-10. Startup with 5-A Load
Time (200 ms/DIV)
图9-11. Startup with Input Reverse Voltage (–12 V)
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10 Power Supply Recommendations
The LM74500-Q1 reverse polarity protection controller is designed for the supply voltage range of 3.2 V ≤
SOURCE ≤ 65 V. If the input supply is located more than a few inches from the device, an input ceramic bypass
V
capacitor higher than 22 nF is recommended. To prevent LM74500-Q1 and surrounding components from
damage under the conditions of a direct output short circuit, it is necessary to use a power supply having over
load and short circuit protection.
11 Layout
11.1 Layout Guidelines
• Connect SOURCE and GATE pins of LM74500-Q1 close to the MOSFET's SOURCE and GATE pins.
• The high current path of for this solution is through the MOSFET, therefore it is important to use thick traces
for source and drain of the MOSFET to minimize resistive losses.
• The charge pump capacitor across VCAP and SOURCE pins must be kept away from the MOSFET to lower
the thermal effects on the capacitance value.
• The Gate pin of the LM74500-Q1 must be connected to the MOSFET gate with short trace. Avoid excessively
thin and long running trace to the Gate Drive.
11.2 Layout Example
MOSFET DRAIN
Signal Via
Power Via
Top layer
MOSFET SOURCE
VOUT
VIN
COUT
CIN
CVCAP
GND PLANE
图11-1. Layout Example
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12 Device and Documentation Support
12.1 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
12.2 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
12.3 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
12.4 静电放电警告
静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理
和安装程序，可能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参
数更改都可能会导致器件与其发布的规格不相符。
12.5 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
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13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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7-Feb-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LM74500QDDFRQ1
ACTIVE SOT-23-THIN
DDF
8
3000 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
745F
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OUTLINE
DDF0008A
SOT-23 - 1.1 mm max height
S
C
A
L
E
4
.
0
0
0
PLASTIC SMALL OUTLINE
C
2.95
2.65
SEATING PLANE
TYP
PIN 1 ID
AREA
0.1 C
A
6X 0.65
8
1
2.95
2.85
NOTE 3
2X
1.95
4
5
0.38
0.22
8X
0.1
C A B
1.65
1.55
B
1.1 MAX
0.20
0.08
TYP
SEE DETAIL A
0.25
GAGE PLANE
0.1
0.0
0 - 8
0.6
0.3
DETAIL A
TYPICAL
4222047/C 10/2022
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
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EXAMPLE BOARD LAYOUT
DDF0008A
SOT-23 - 1.1 mm max height
PLASTIC SMALL OUTLINE
8X (1.05)
SYMM
1
8
8X (0.45)
SYMM
6X (0.65)
5
4
(R0.05)
TYP
(2.6)
LAND PATTERN EXAMPLE
SCALE:15X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4222047/C 10/2022
NOTES: (continued)
4. Publication IPC-7351 may have alternate designs.
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
DDF0008A
SOT-23 - 1.1 mm max height
PLASTIC SMALL OUTLINE
8X (1.05)
SYMM
(R0.05) TYP
8
1
8X (0.45)
SYMM
6X (0.65)
5
4
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4222047/C 10/2022
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
7. Board assembly site may have different recommendations for stencil design.
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