LM74501QDDFRQ1 [TI]
具有集成 VDS 钳位的汽车类 3.2V 至 65V 反极性保护控制器 | DDF | 8 | -40 to 125;
| 型号： | LM74501QDDFRQ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有集成 VDS 钳位的汽车类 3.2V 至 65V 反极性保护控制器 | DDF | 8 | -40 to 125 控制器 |
| 文件： | 总24页 (文件大小：1833K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LM74501-Q1
ZHCSOA6A –JULY 2021 –REVISED FEBRUARY 2022
LM74501-Q1 无TVS 汽车电池反向保护控制器
1 特性
3 说明
• 具有符合AEC-Q100 标准的下列特性
LM74501-Q1 与外部 N 沟道 MOSFET 搭配使用，可
实现低损耗反极性保护解决方案。该器件支持 3.2V 至
65V 的宽电源电压输入范围。3.2V 输入电压支持特别
适合对冷启动有严苛要求的汽车系统。该器件可以承受
并保护负载免受低至 -18V 的负电源电压的影响。
LM74501-Q1 没有反向电流阻断功能，适用于对有可
能将能量传输回输入电源的负载（如汽车车身控制模块
电机负载）提供输入反极性保护。
– 器件温度等级1：
–40°C 至+125°C 环境工作温度范围
– 器件HBM ESD 分类等级2
– 器件CDM ESD 分类等级C4B
• 3.2V 至65V 输入范围（3.9V 启动）
• –18V 反向电压额定值
• 适用于外部N 沟道MOSFET 的电荷泵
• 栅极放电计时器：无需额外的TVS 二极管（无
TVS）即可符合汽车ISO7637-2 脉冲1 瞬态要求
• 1µA 关断电流（EN = 低电平）
• 80µA 典型工作静态电流（EN = 高电平）
• 20V VDS 钳位（EN = 低电平）
• 集成电池电压监控开关(SW)
LM74501-Q1 控制器可提供适用于外部 N 沟道
MOSFET 的电荷泵栅极驱动器。LM74501-Q1 具有一
项独特的集成功能，即无需额外的 TVS 二极管（无
TVS）即可使系统符合汽车 ISO7637 脉冲 1 瞬态要
求。LM74501-Q1 具有一个集成开关，可通过外部电
阻分压器来实现电池电压监控。With the enable pin
low, the controller is off and draws only around 1 µA of
current, thus offering low system current when put into
sleep mode.
• 2.90mm × 1.60mm 8 引脚SOT-23 封装
2 应用
• 车身电子装置和照明
– 车身控制模块(BCM)
– 雨刮器模块
• 汽车信息娱乐系统与仪表组
– 数字驾驶舱处理单元
• ADAS 域控制器
器件信息
封装(1)
封装尺寸（标称值）
器件型号
LM74501-Q1
SOT-23 (8)
2.90mm × 1.60mm
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
High Side Switch
To
Load
VBAT
VOUT
COUT
CIN
CT
CVCAP
SOURCE
VCAP
GATE
DRAIN
LM74501-Q1
SW
EN
R1
OFF
ON
BATT_MON
GND
R2
无TVS 条件下的ISO7637-2 脉冲1 运行
提供汽车电池反极性保护的LM74501-Q1 典型应用原
理图
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SNOSD87
LM74501-Q1
ZHCSOA6A –JULY 2021 –REVISED FEBRUARY 2022
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Table of Contents
8.4 Device Functional Modes..........................................14
9 Application and Implementation..................................15
9.1 Application Information............................................. 15
9.2 Typical Application.................................................... 17
10 Power Supply Recommendations..............................21
11 Layout...........................................................................21
11.1 Layout Guidelines................................................... 21
11.2 Layout Example...................................................... 21
12 Device and Documentation Support..........................22
12.1 Device Support....................................................... 22
12.2 接收文档更新通知................................................... 22
12.3 支持资源..................................................................22
12.4 Trademarks.............................................................22
12.5 Electrostatic Discharge Caution..............................22
12.6 术语表..................................................................... 22
13 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings ....................................... 4
6.2 ESD Ratings .............................................................. 4
6.3 Recommended Operating Conditions ........................4
6.4 Thermal Information ...................................................5
6.5 Electrical Characteristics ............................................5
6.6 Switching Characteristics ...........................................6
6.7 Typical Characteristics................................................7
7 Parameter Measurement Information............................9
8 Detailed Description......................................................10
8.1 Overview...................................................................10
8.2 Functional Block Diagram.........................................10
8.3 Feature Description...................................................10
Information.................................................................... 22
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision * (July 2021) to Revision A (February 2022)
Page
• 将状态从“预告信息”更改为“量产数据”....................................................................................................... 1
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5 Pin Configuration and Functions
8
GATE
SOURCE
VCAP
DRAIN
1
2
7
6
N.C
EN
3
4
GND
5
SW
图5-1. DDF Package 8-Pin SOT-23 (LM74501-Q1 Top View)
表5-1. LM74501-Q1 Pin Functions
PIN
I/O(1)
DESCRIPTION
NO.
NAME
1
GATE
O
I
Gate drive output. Connect to the gate of the external N-channel MOSFET.
Connect to the source of the external N-channel MOSFET. This pin also acts as the input
supply for the device.
2
3
SOURCE
VCAP
O
Charge pump output. Connect to an external charge pump capacitor.
Voltage sensing disconnect switch terminal. SOURCE and SW are internally connected
through a switch when EN is high. A resistor ladder from this pin to GND can be used to
monitor battery voltage. When EN is pulled low, the switch is OFF, disconnecting the resistor
ladder from the battery line, thereby cutting off the leakage current.
4
SW
I
5
6
7
8
GND
EN
G
I
Ground pin
Enable pin. Can be connected to SOURCE for always ON operation.
No connect. Keep this pin floating.
N.C
NA
I
DRAIN
Connect to the drain of the external N-channel MOSFET.
(1) I = Input, O = Output, G = GND
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–(VCLAMP –1)
–0.3
MAX
UNIT
V
SOURCE to GND
65
EN, SW to GND, V(SOURCE) > 0 V
65
V
Input pins
V(SOURCE)
V(SOURCE)
–1
65 + V(SOURCE)
V
EN to GND, V(SOURCE) ≤0 V
SW to GND, V(SOURCE) ≤0 V
ISW
0.3 + V(SOURCE)
V
10
15
mA
V
GATE to SOURCE
VCAP to SOURCE
DRAIN to SOURCE
–0.3
Output pins
Output pins
15
V
–0.3
VCLAMP
150
V
–5
Operating junction temperature(2)
Storage temperature, Tstg
°C
°C
–40
150
–40
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If
used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
(2) High junction temperatures degrade operating lifetimes. Operating lifetime is de-rated for junction temperatures greater than 125°C.
6.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per AEC Q100-002(1)
HBM ESD classification level 2
±2000
V(ESD)
Electrostatic discharge
Corner pins (GATE,
SW, GND, DRAIN)
V
±750
±500
Charged device model (CDM), per AEC Q100-011
CDM ESD classification level C4B
Other pins
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–18
–18
NOM
MAX
60
60
60
5
UNIT
SOURCE to GND
EN to GND
Input pins
V
Input pins
DRAIN to GND
SOURCE to DRAIN
SOURCE
V
V
Input to output pins
–VCLAMP
0.1
µF
µF
External capacitance
VCAP to SOURCE
0.1
External MOSFET maximum
VGS rating
GATE to SOURCE
15
V
TJ
Operating junction temperature range(2)
150
°C
–40
(1) Recommended Operating Conditions are conditions under which the device is intended to be functional. For specifications and test
conditions, see Electrical Characteristics.
(2) High junction temperatures degrade operating lifetimes. Operating lifetime is de-rated for junction temperatures greater than 125°C.
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6.4 Thermal Information
DDF (SOT)
UNIT
8 PINS
THERMAL METRIC(1)
RθJA
RθJC(top)
RθJB
ΨJT
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
133.8
72.6
54.5
4.6
°C/W
°C/W
°C/W
°C/W
°C/W
Junction-to-top characterization parameter
Junction-to-board characterization parameter
54.2
ΨJB
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics
TJ = –40°C to +125°C; typical values at TJ = 25°C, V(SOURCE) = 12 V, CIN = C(VCAP) = COUT = 0.1 µF, V(EN) = 3.3 V, over
operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
VSOURCE SUPPLY VOLTAGE
VCLAMP
VDS clamp voltage
V(EN) = 0 V
19
4
24
60
V
V
V(SOURCE)
Operating input voltage
VSOURCE POR rising threshold
VSOURCE POR falling threshold
3.9
V
V(SOURCE POR)
2.2
2.8
3.1
V
V(SOURCE POR(Hys)) VSOURCE POR hysteresis
0.44
0.67
1.5
V
I(SHDN)
Shutdown supply current
V(EN) = 0 V
0.9
80
µA
µA
I(Q)
Operating quiescent current
130
ENABLE INPUT
V(EN_IL)
Enable input low threshold
Enable input high threshold
Enable hysteresis
0.5
1.06
0.52
0.9
2
1.22
2.6
1.35
5
V
V(EN_IH)
V(EN_Hys)
I(EN)
V
Enable sink current
V(EN) = 12 V
3
µA
GATE DRIVE
Enable (low to high)
I(GATE)
Peak source current
3
11
30
mA
V
(GATE) –V(SOURCE) = 5 V
V(EN) = 0 V,
(GATE) –V(SOURCE) = 100 mV
RDSON
discharge switch RDSON
24
36
46
kΩ
V
SW
Battery sensing disconnect switch
resistance
R(SW)
10
19.5
4 V < V(SOURCE) ≤60 V
Ω
CHARGE PUMP
Charge pump source current (charge
pump on)
162
300
5
600
10
µA
µA
V
V
V
(VCAP) –VSOURCE = 7 V
(VCAP) –VSOURCE = 14 V
I(VCAP)
Charge pump sink current (charge
pump off)
Charge pump voltage at V(SOURCE)
3.2 V
=
8
I
(VCAP) ≤30 µA
Charge pump turn-on voltage
Charge pump turn-off voltage
10.3
11
11.6
12.4
13
V
V
V(VCAP)
V(SOURCE)
–
13.9
Charge pump enable comparator
hysteresis
0.4
0.8
1.2
V
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6.5 Electrical Characteristics (continued)
TJ = –40°C to +125°C; typical values at TJ = 25°C, V(SOURCE) = 12 V, CIN = C(VCAP) = COUT = 0.1 µF, V(EN) = 3.3 V, over
operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
V
(VCAP) –V(SOURCE) UV release at
VSOURCE – VDRAIN = 100 mV
5.7
6.5
7.5
6.2
V
V
rising edge
V(VCAP UVLO)
V
(VCAP) –V(SOURCE) UV threshold at
VSOURCE – VDRAIN = 100 mV
5.05
5.4
falling edge
DRAIN
V(SOURCE) = V(EN) = –14 V, V(DRAIN)
0 V
=
I(DRAIN)
DRAIN sink current
4
µA
6.6 Switching Characteristics
TJ = –40°C to +125°C; typical values at TJ = 25°C, V(SOURCE) = 12 V, CIN = C(VCAP) = COUT = 0.1 µF, V(EN) = 3.3 V, over
operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
110 µs
Enable (low to high) to gate turn-on
delay
ENTDLY
V(VCAP) > V(VCAP UVLOR)
75
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6.7 Typical Characteristics
3.9
3.6
3.3
3
750
700
650
600
550
500
450
400
350
300
250
200
150
100
50
–40C
25C
85C
125C
150C
2.7
2.4
2.1
1.8
1.5
1.2
0.9
0.6
0.3
0
–40C
25C
85C
125C
150C
0
0
5
10 15 20 25 30 35 40 45 50 55 60 65
VSOURCE (V)
0
5
10 15 20 25 30 35 40 45 50 55 60 65
VSOURCE (V)
图6-2. Operating Quiescent Current vs Supply Voltage
图6-1. Shutdown Supply Current vs Supply Voltage
325
300
275
250
225
500
–40C
25C
450
400
350
300
250
200
150
100
85C
125C
150C
200
175
150
125
100
75
–40C
25C
85C
125C
150C
3
4
5
6
7
8
9
10
11
12
0
2
4
6
8
10
12
VSOURCE (V)
VCAP (V)
图6-3. Charge Pump Current vs Supply Voltage at VCAP = 6 V
图6-4. Charge Pump V-I Characteristics at VSOURCE > = 12 V
225
2.5
–40C
EN Rising Threshold
EN Falling Threshold
200
25C
85C
2
1.5
1
175
125C
150C
150
125
100
75
50
25
0
0.5
0
-40
0
40
80
120
160
0
1
2
3
4
5
6
7
8
9
Free-Air Temperature (C)
VCAP (V)
图6-6. Enable Threshold vs Temperature
图6-5. Charge Pump V-I Characteristics at VSOURCE = 3.2 V
90
13.5
13.2
12.9
12.6
12.3
12
VCAP ON
VCAP OFF
80
70
60
50
40
11.7
11.4
-40
0
40
80
120
160
-40
0
40
80
120
160
Free-Air Temperature (C)
Free-Air Temperature (C)
图6-8. Charge Pump ON/OFF Threshold vs Temperature
图6-7. Enable to Gate Turn On Delay vs Temperature
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6.7 Typical Characteristics (continued)
3.1
3
VSOURCE PORR
VSOURCE PORF
2.9
2.8
2.7
2.6
2.5
2.4
2.3
-40 -20
0
20
40
60
80 100 120 140 160
Free-Air Temperature (C)
图6-10. VSOURCE POR Threshold vs Temperature
图6-9. Charge Pump UVLO Threshold vs Temperature
24.8
31
24
23.2
22.4
21.6
20.8
20
30
29
28
27
26
-40
0
40
80
120
160
-40
0
40
80
120
160
Free-Air Temperature (C)
Free-Air Temperature (C)
图6-11. VDSCLAMP Threshold vs Temperature
图6-12. Gate Discharge Resistor vs Temperature
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7 Parameter Measurement Information
3.3 V
VEN
0 V
VGATE
90%
VGATE – VSOURCE
0 V
tENTDLY
t
图7-1. Timing Waveforms
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8 Detailed Description
8.1 Overview
The LM74501-Q1 controller has all the features necessary to implement an efficient and fast reverse polarity
protection circuit. This easy-to-use reverse polarity protection controller is paired with an external N-channel
MOSFET to replace other reverse polarity protection schemes such as a P-channel MOSFET. An internal charge
pump is used to drive the external N-Channel MOSFET with a typical gate drive voltage of 12 V. The Gate
Discharge Timer feature of the device enables meeting automotive ISO7637 pulse 1 transient requirements
without an additional TVS Diode (TVS less) under certain load conditions. The LM74501-Q1 has integrated
switch (SW), which enables input battery voltage monitoring by connecting an external resistor divider from the
SW pin to GND. An enable pin, EN, is available to place the LM74501-Q1 in shutdown mode, disabling the N-
Channel MOSFET and minimizing the quiescent current.
8.2 Functional Block Diagram
VOUT
VBATT
DRAIN
GATE
SOURCE
VCAP
CP
VCAP
VS
SW
Internal
Rails
EN
VCAP_UV
R1
R2
Gate Driver and
Gate Discharge
Timer Control
BATT_MON
VCAP
VS
Charge
Pump
Enable
Logic
VDS Clamp
+
–
EN
EN
VS
2 V
0.9 V
VS
Reverse
Protection Logic
LM74501-Q1
GND
8.3 Feature Description
8.3.1 Input Voltage
The SOURCE pin is used to power the internal circuitry of the LM74501-Q1, typically drawing 80 µA when
enabled and 1 µA when disabled. If the SOURCE pin voltage is greater than the POR rising threshold, the
LM74501-Q1 operates in either shutdown mode or conduction mode in accordance with the EN pin voltage. The
LM74501-Q1 can withstand input reverse voltage up to –18 V.
8.3.2 Charge Pump
The charge pump supplies the voltage necessary to drive the external N-channel MOSFET. An external charge
pump capacitor is placed between VCAP and SOURCE pins to provide energy to turn on the external MOSFET.
In order for the charge pump to supply current to the external capacitor, the EN pin voltage must be above the
specified input high threshold, V(EN_IH). When enabled, the charge pump sources a charging current of 300 µA
(typical). If EN pins is pulled low, then the charge pump remains disabled. To ensure that the external MOSFET
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can be driven above its specified threshold voltage, the VCAP-to-SOURCE voltage must be above the
undervoltage lockout threshold, typically 6.5 V, before the internal gate driver is enabled. Use 方程式 1 to
calculate the initial gate driver enable delay.
T
(DRV_EN) = 75 µs + C(VCAP) × V(VCAP_UVLOR)
300 µA
(1)
where
• C(VCAP) is the charge pump capacitance connected across SOURCE and VCAP pins.
• V(VCAP_UVLOR) is 6.5 V (typical).
To remove any chatter on the gate drive, approximately 800 mV of hysteresis is added to the VCAP
undervoltage lockout. The charge pump remains enabled until the VCAP-to-SOURCE voltage reaches 12.4 V
(typical), at which point the charge pump is disabled decreasing the current draw on the SOURCE pin. The
charge pump remains disabled until the VCAP-to-SOURCE voltage is below to 11.6 V (typical), at which point
the charge pump is enabled. The voltage between VCAP and SOURCE continues to charge and discharge
between 11.6 V and 12.4 V as shown in 图 8-1. By enabling and disabling the charge pump, the operating
quiescent current of the LM74501-Q1 is reduced. When the charge pump is disabled, it sinks 5 µA (typical).
TDRV_EN
TON
TOFF
VIN
VSOURCE
0 V
VEN
12.4 V
11.6 V
VCAP-VSOURCE
6.5 V
V(VCAP UVLOR)
GATE DRIVER
ENABLE
图8-1. Charge Pump Operation
8.3.3 Enable
The LM74501-Q1 has an enable pin, EN. The enable pin allows for the gate driver to be either enabled or
disabled by an external signal. If the EN pin voltage is greater than the rising threshold, the gate driver and
charge pump operates as described in Gate Driver and Charge Pump sections. If the enable pin voltage is less
than the input low threshold, the charge pump and gate driver are disabled placing the LM74501-Q1 in shutdown
mode. The EN pin can withstand a voltage as large as 65 V and as low as –18 V. This feature allows for the EN
pin to be connected directly to the SOURCE pin if enable functionality is not needed. In conditions where EN is
left floating, the internal sink current of 1 μA pulls the EN pin low and disables the device.
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8.3.4 Gate Driver
The gate driver is used to control the external N-Channel MOSFET by setting the appropriate GATE-to-SOURCE
voltage.
Before the gate driver is enabled, the following three conditions must be achieved:
• The EN pin voltage must be greater than the specified input high voltage.
• The VCAP to SOURCE voltage must be greater than the undervoltage lockout voltage.
• The SOURCE voltage must be greater than the VSOURCE POR rising threshold.
If the above conditions are not achieved, then the GATE pin is internally connected to the SOURCE pin, assuring
that the external MOSFET is disabled. After these conditions are achieved, the gate driver operates in the full
conduction mode.
8.3.5 SW (Battery Voltage Monitoring)
The LM74501-Q1 has an SW pin to enable battery voltage monitoring in automotive systems. When the device
is enabled, an internal switch connects the SW pin to SOURCE. This connection enables monitoring battery
voltage using an external resistor divider connected from SW pin to GND. When LM74501-Q1 is put in shutdown
mode by pulling down the EN pin to ground, an internal switch between SW and SOURCE pin is disconnected.
This disconnection ensures there is no quiescent current drawn by the resistor ladder when system is put into
low power shutdown mode. When not used, the SW pin can be left floating.
VBAT
SOURCE
SW
EN
R1
BATT_MON
R2
图8-2. LM74501-Q1 SW Functionality
8.3.6 Gate Discharge Timer
The LM74501-Q1 has a unique gate discharge timer feature, which enables TVS less reverse polarity protection
solution in case of ISO7637-2 pulse 1 event. An additional capacitor (CT) across external N-FET's GATE to
SOURCE terminal keeps external N-FET on for specific time window even when input voltage falls below VPORF
threshold of SOURCE pin or when the EN pin is pulled low. This gate discharge feature allows reverse current
back to input source by keeping external MOSFET on for extended time duration set by gate discharge timer
capacitor (CT) and enables automotive systems to meet TVS less ISO 7637-2 pulse 1 operation. Use 方程式2 to
calculate the typical gate discharge time.
tD = –[RD × (CT + Ciss) × ln (VT / VGATE)]
(2)
Where
• RD is the LM74501-Q1 internal GATE discharge resistor (typically 30 kΩ).
• Ciss is the external MOSFET input capacitance.
• CT is the timer capacitor connected between GATE and SOURCE of an external MOSFET.
• VT is the gate-to-source threshold voltage of an external MOSFET.
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• VGATE is the nominal GATE pin voltage of LM74501-Q1 (12.4-V typical).
External FET remains ON
during ISO7637-2 pulse 1
–
ISO7637-2 pulse 1
VOUT
VF
+
13.5 V
VIN
VIN
0 V
CT
CIN
COUT
–VISO
H-Bridge
driving motor load
SOURCE
GATE
DRAIN
–
VCAP
SW
13.5 V
VOUT
VF
+
0 V
LM74501-Q1
GND
–(2 × VF)
EN
R1
R2
OFF
ON
BATT_MON
High Side Switch
Induc ve
Load
Current direction during ISO7637-2 pulse 1
Transient event
图8-3. Typical Application Scenario During ISO7637-2 Pulse 1 Events
图8-3 shows equivalent the LM74501-Q1 circuit operation during an ISO7637-2 pulse 1 event. Note that reverse
current flows back to the input source from output loads such as a high-side switch followed by schottky diode or
MOSFET H-bridge driving motor load. Thus, to achieve TVS less operation during ISO7637-2 pulse 1 events,
output loads must be capable of withstanding the peak reverse current during ISO7637-2 pulse 1 event.
图 8-4 shows the TVS-less ISO7637-2 pulse 1 performance of the LM74501-Q1 with output loads capable of
handling reverse current during an ISO7637-2 pulse 1 event, similar to loads configuration shown in 图8-4.
图8-4. TVS Less Operation During ISO7637-2 Pulse 1
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The other short duration transient events such as ISO7637-2 pulse 2A, 3A, or 3B usually get filtered out by input
and output capacitors and do not affect the system performance.
For the loads that cannot handle peak reverse current during an ISO 7637-2 pulse 1 transient event but can
handle negative voltage for a short duration, a schottky diode capable of handling peak reverse current can be
placed from output to ground to clamp the output voltage to negative forward voltage drop of the Schottky diode
(–VF).
8.4 Device Functional Modes
8.4.1 Shutdown Mode
The LM74501-Q1 enters shutdown mode when the EN pin voltage is below the specified input low threshold
V(EN_IL). Both the gate driver and the charge pump are disabled in shutdown mode. During shutdown mode, the
LM74501-Q1 enters low IQ operation with the SOURCE pin only sinking 1 µA. When the LM74501-Q1 is in
shutdown mode, forward current flowing through the external MOSFET is not interrupted but is conducted
through the body diode of the MOSFET.
8.4.2 Full Conduction Mode
For the LM74501-Q1 to operate in full conduction mode the gate driver must be enabled as described in the
Gate Driver section. If these conditions are achieved, the GATE pin is internally connected to the VCAP pin,
resulting in the GATE to SOURCE voltage being approximately the same as the VCAP to SOURCE voltage. By
connecting VCAP to GATE, the external MOSFET is fully enhanced reducing the power loss of the external
MOSFET.
8.4.3 VDS Clamp
The LM74501-Q1 has an integrated VDS clamp feature that turns on an external MOSFET whenever voltage
difference between DRIAN and SOURCE exceeds VDS clamp threshold (20 V typical) when enable pin is pulled
low. This use case scenario is specially true when the LM74501-Q1 is used to drive inductive loads and
overshoot can happen at the DRAIN pin due to regenerative action of the motor load. Also, if the gate discharge
timer designed to keep external MOSFET on during an ISO7637-2 pulse 1 event expires within stipulated time
window due to component level tolerances, the LM74501-Q1 VDS clamp feature provides second level of
protection to keep maximum voltage across FET to 20 V.
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9 Application and Implementation
备注
以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。
9.1 Application Information
The LM74501-Q1 is used with an N-Channel MOSFET controller in a typical reverse polarity protection
application. The schematic for the 12-V battery protection application is shown in 图 9-2 where the LM74501-Q1
is used to drive a MOSFET Q1 in series with a battery. The LM74501-Q1 enables TVS-less operation with its
integrated gate discharge timer feature.
9.1.1 Reverse Battery Protection
P-FET based reverse polarity protection is a very commonly used scheme in automotive applications to achieve
low insertion loss protection solution. A low loss reverse polarity protection solution can be realized using the
LM74501-Q1 with an external N-FET to replace P-FET based solution. The LM74501-Q1-based reverse polarity
protection solution offers input TVS-less performance during ISO7637-2 pulse 1 event, better cold crank
performance (low VIN operation) and smaller solution size compared to P-FET based solution. 图 9-1 compares
the performance benefits of LM74501-Q1 + N-FET over a traditional P-FET based reverse polarity protection
solution.
• As shown in 图9-1, a given power level LM74501-Q1 + N-FET solution can be 50% smaller than a similar
power rated P-FET solution.
• The second advantage that the LM74501-Q1 offers over a traditional P-FET is TVS-less operation for the
body control module load driving paths where reverse current blocking is not a must-have feature and output
loads are capable of handling negative voltage and reverse current for a short duration of the time.
• As PFET is self biased by simply pulling its gate pin low, P-FET shows poorer cold crank performance (low
VIN operation) compared to the LM74501-Q1. During severe cold crank where battery voltage falls below 4 V,
P-FET series resistance increases drastically as shown in 图9-1. This increase leads to higher voltage drop
across the PFET. Also, with a higher gate-to-source threshold (VT), this can sometimes lead to system reset
due to turning off of the P-FET. On the other side, the LM74501-Q1 has excellent severe cold crank
performance. The LM74501-Q1 keeps the external FET completely enhanced even when input voltage falls
to 3.2 V during severe cold crank operation.
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Parameter
P-channel MOSFET
LM74501-Q1 + N-channel MOSFET
Q1
CT
VOUT
COUT
VBATT
CIN
Q1
VOUT
COUT
VBATT
Typical Application
Diagram
CIN
TVS
D1
SOURCE
VCAP
DRAIN
EN
GATE
D2
CVCAP
LM74501-Q1
GND
R1
SW
LM74501 + NFET (Q1) +
CCVCAP + CT
PFET (Q1) +TVS (D1) +
Zener (D2) + Resistor
(R1)
Solution Size
(Load current > 6 A)
6.3 mm × 8 mm
(50.4 mm2)
12.3 mm × 8.5 mm
(104.5 mm2)
TVS Less solution with
50% reduction in size
Low VIN / Cold-Crank
Performance
Better cold crank performance compared to
PFET based solution. External N-FET
remains fully enhanced even if input voltage
falls to 3.2 V.
VT
图9-1. PFET vs LM74501-Q1 Reverse Polarity Protection Solution Comparison
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9.2 Typical Application
High Side Switch
VBAT
VOUT
To
Load
COUT
47 µF
CIN
CT
0.1 µF
CVCAP
22 nF
220 nF
SOURCE
GATE
DRAIN
VCAP
SW
LM74501-Q1
GND
R1
91 kΩ
EN
OFF
ON
BATT_MON
R2
9.1 kΩ
图9-2. Typical Application Circuit
9.2.1 Design Requirements
A design example, with system design parameters, is presented in 表9-1.
表9-1. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
12-V battery, 12-V nominal with 3.2-V cold crank, and 35-V load
dump
Input voltage range
Output voltage
Output current range
Output capacitance
3.2-V during cold crank to 35-V load dump
3-A nominal, 5-A maximum
47-µF typical holdup capacitance
ISO 7637-2 and ISO 16750-2
Automotive EMC compliance
9.2.2 Detailed Design Procedure
9.2.2.1 Design Considerations
• Input operating voltage range, including cold crank and load dump conditions
• Nominal load current and maximum load current
9.2.2.2 MOSFET Selection
The important MOSFET electrical parameters are the maximum continuous drain current, ID, the maximum
drain-to-source voltage, VDS(MAX), the maximum source current through body diode, and the drain-to-source on
resistance, RDSON
.
The maximum continuous drain current, ID, rating must exceed the maximum continuous load current. The
maximum drain-to-source voltage, VDS(MAX), must be high enough to withstand the highest differential voltage
seen in the application. This would include any anticipated fault conditions. As the LM74501-Q1 has an
integrated VDS clamp control with threshold of 20 V (typical), MOSFETs with voltage rating of 40 V can be used
with the LM74501-Q1. The maximum GATE pin voltage of the LM74501-Q1 can drive is 13.9 V, so a MOSFET
with 15-V minimum VGS must be selected. If a MOSFET with < 15-V VGS rating is selected, a Zener diode can
be used to clamp VGS to safe level. During start-up, inrush current flows through the body diode to charge the
bulk holdup capacitors at the output. The maximum source current through the body diode must be higher than
the inrush current that can be seen in the application.
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To reduce the MOSFET conduction losses, the lowest possible RDS(ON) is preferred. Selecting a MOSFET with
forward voltage drop of < 50 mV is a good starting point and gives good trade off between power dissipation and
cost.
The BUK7Y3R0-40H MOSFET is selected to meet this 12-V reverse battery protection design requirements and
it is rated at:
• 40-V VDS(MAX) and ±20-V VGS(MAX)
• RDS(ON) 2.55 mΩ(typical) and 3-mΩmaximum rated at 10-V VGS
Thermal resistance of the MOSFET must be considered against the expected maximum power dissipation in the
MOSFET to ensure that the junction temperature (TJ) is well controlled.
9.2.2.3 Gate Discharge Timer Capacitor Selection (CT)
A gate discharge timer decides the time duration for which external MOSFET is kept on after the LM74501-Q1
fall below its PoR threshold (VPORF) or when EN pin is pulled low. A ISO7637-2 pulse 1 transient lasts for
typically 2 ms. At the end of 2-ms ISO7637-2 pulse 1, amplitude has already fallen to 10% of its peak value.
Assuming a ISO7637-2 pulse 1 transient with amplitude of –150 V, at the end of 2 ms, the voltage seen by the
LM74501-Q1 is around –15 V. With a VDS rating of external MOSFET of 40 V, the gate discharge timer
capacitor, CT, can be selected such that external FET remains on for less than 2 ms. A CT timer capacitor value
of 22 nF is selected for the given MOSFET as per Equation 2.
9.2.2.4 Charge Pump VCAP, Input and Output Capacitance
Minimum required capacitance for charge pump VCAP and input and output capacitance are:
• VCAP: minimum recommended value of VCAP (µF) ≥10 × (CISS(MOSFET) + CT) µF
• CIN: minimum 100 nF of input capacitance
• COUT: typical 10 µF to 47 µF of output capacitance
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9.2.3 Application Curves
图9-3. ISO 7637-2 Pulse 1
Time (1 ms/DIV)
图9-4. Response to ISO 7637-2 Pulse 1
Time (120 ms/DIV)
Time (40 μs/DIV)
图9-6. Response to ISO7637-2 Pulse 2B
图9-5. Response to ISO7637-2 Pulse 2A
Time (10 ms/DIV)
Time (40 ms/DIV)
图9-8. Start-up with No Load
图9-7. Response to ISO16750-2 Pulse 5B
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Time (20 ms/DIV)
Time (10 ms/DIV)
图9-10. Input Reverse Polarity Hot Plug
图9-9. Start-up with 5-A Load
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10 Power Supply Recommendations
The LM74501-Q1 controller is designed for the supply voltage range of 3.2 V ≤ VSOURCE ≤ 65 V. If the input
supply is located more than a few inches from the device, TI recommends an input ceramic bypass capacitor
higher than 100 nF placed close to SOURCE pin to GND. To prevent Lthe M74501-Q1 and surrounding
components from damage under the conditions of a direct output short circuit, use a power supply having
overload and short-circuit protection.
11 Layout
11.1 Layout Guidelines
• Connect SOURCE, GATE, and DRAIN pins of LM74501-Q1 close to the MOSFET's SOURCE, GATE, and
DRAIN pins.
• Use thick traces for source and drain of the MOSFET to minimize resistive losses because the high current
path of for this solution is through the MOSFET.
• Place the input capacitor close to the SOURCE pin to Ground (GND) to minimize long ground loop.
• Keep the charge pump capacitor across VCAP and SOURCE pins away from the MOSFET to lower the
thermal effects on the capacitance value.
• Avoid excessively thin and long trace for the gate pin connection. The Gate pin of the LM74501-Q1 must be
connected to the MOSFET gate with short trace.
• Use of series gate resistor (typical 10 Ω) can help with better EMI performance.
11.2 Layout Example
Power Via
Top layer
S
S
S
VOUT
G
VIN
CT
8
7
6
DRAIN
N.C
GATE
1
2
SOURCE
CVCAP
3
4
EN
VCAP
SW
COUT
CIN
GND
5
BATT_MON
R1
R2
GND PLANE
图11-1. LM74501-Q1 Layout Example
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12 Device and Documentation Support
12.1 Device Support
12.1.1 第三方产品免责声明
TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此
类产品或服务单独或与任何TI 产品或服务一起的表示或认可。
12.2 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
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TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
12.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.6 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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31-Oct-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LM74501QDDFRQ1
ACTIVE SOT-23-THIN
DDF
8
3000 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
L7501
Samples
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
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