LM74502HDDFR [TI]
具有负载断开、OVP 和高栅极驱动功能的 3.2V 至 65V 工业 RPP 控制器 | DDF | 8 | -40 to 125;
| 型号： | LM74502HDDFR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有负载断开、OVP 和高栅极驱动功能的 3.2V 至 65V 工业 RPP 控制器 | DDF | 8 | -40 to 125 栅极驱动 控制器 |
| 文件： | 总30页 (文件大小：2000K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LM74502, LM74502H
ZHCSO25A –DECEMBER 2021 –REVISED MAY 2022
LM74502，LM74502H 具有反极性保护和过压保护功能的低IQ 高侧开关控制器
1 特性
3 说明
• 3.2V 至65V 输入范围（3.9V 启动）
• -65V 输入反向电压额定值
• 集成电荷泵用于驱动
LM74502/LM74502H 控制器与外部背对背连接的N 沟
道 MOSFET 配合工作，可实现低损耗反极性保护和负
载断开的解决方案。该器件也可以配置为具有过压保护
功能的负载开关，用于驱动高侧 MOSFET。3.2V 至
65V 的宽电源输入范围可实现对众多常用直流总线电
压（例如，12V、24V 和 48V 输入系统）的控制。该
器件可以承受并保护负载免受低至 -65V 的负电源电压
的影响。LM74502/LM74502H 没有反向电流阻断功
能，仅适用于进行输入反极性保护。
– 外部背对背N 沟道MOSFET
– 外部高侧开关MOSFET
– 外部反极性保护MOSFET
• 栅极驱动器型号
– LM74502：60μA 峰值栅极驱动拉电流能力
– LM74502H：11mA 峰值栅极驱动拉电流能力
• 2.3A 峰值栅极灌电流能力
LM74502 控制器为外部 N 沟道 MOSFET 提供电荷泵
栅极驱动。当使能引脚处于低电平时，控制器关闭，消
耗大约 1µA 的电流，从而在进入睡眠模式时提供低系
统电流。LM74502 和LM74502H 还具有可编程的过压
和欠压保护功能，可在发生故障时将负载从输入源切
断。这些器件采用 2.9mm × 1.6mm 8 引脚 DDF 封
装，额定工作温度范围为–40°C 至+125°C。
• 使能引脚特性
• 45µA 典型工作静态电流（EN/UVLO = 高电平）
• 1µA 关断电流（EN/UVLO = 低电平）
• 可调节过压和欠压保护
• –40°C 至+125°C 环境工作温度范围
• 采用8 引脚SOT-23 封装2.90mm × 1.60mm
器件信息(1)
2 应用
封装尺寸（标称值）
器件型号
LM74502
LM74502H
封装
• 工厂自动化和控制–PLC 数字输出模块
• 工业电机驱动
• 工业运输
SOT-23 (8)
2.90mm × 1.60mm
• 电源反极性保护
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
Q1
VIN
CIN
VOUT
VIN
VOUT
COUT
CIN
COUT
SRC
GATE
VS
VS
GATE
SRC
CVCAP
CVCAP
R1
R1
VCAP
OV
LM74502
VCAP
OV
LM74502
EN / UVLO
OFF
EN/UVLO
ON
R2
OFF
ON
R2
GND
GND
LM74502 具有过压保护功能的负载开关控制器
LM74502 典型应用原理图
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SNOSDE5
LM74502, LM74502H
ZHCSO25A –DECEMBER 2021 –REVISED MAY 2022
www.ti.com.cn
Table of Contents
9 Application and Implementation..................................14
9.1 Application Information............................................. 14
9.2 Typical Application.................................................... 14
9.3 Input Surge Stopper Using LM74502, LM74502H....17
9.4 Fast Turn-On and Turn-Off High Side Switch
Driver Using LM74502H..............................................18
10 Power Supply Recommendations..............................19
11 Layout...........................................................................20
11.1 Layout Guidelines................................................... 20
11.2 Layout Example...................................................... 20
12 Device and Documentation Support..........................21
12.1 接收文档更新通知................................................... 21
12.2 支持资源..................................................................21
12.3 Trademarks.............................................................21
12.4 Electrostatic Discharge Caution..............................21
12.5 术语表..................................................................... 21
13 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................4
6.4 Thermal Information....................................................5
6.5 Electrical Characteristics.............................................5
6.6 Switching Characteristics............................................6
6.7 Typical Characteristics................................................7
7 Parameter Measurement Information............................9
8 Detailed Description......................................................10
8.1 Overview...................................................................10
8.2 Functional Block Diagram.........................................10
8.3 Feature Description...................................................10
8.4 Device Functional Modes..........................................13
Information.................................................................... 22
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision * (December 2021) to Revision A (May 2022)
Page
• 通篇删除了LM74502H 的产品预览说明.............................................................................................................1
• 已更新文档标题...................................................................................................................................................1
• Added LM74502H to the Pin Configuration and Functions section.................................................................... 3
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5 Pin Configuration and Functions
EN/UVLO
SRC
OV
8
1
2
GND
7
6
GATE
VS
N.C
3
4
5
VCAP
图5-1. DDF Package 8-Pin SOT-23 LM74502, LM74502H Top View
表5-1. LM74502, LM74502H Pin Functions
PIN
I/O(1)
DESCRIPTION
NO.
NAME
EN/UVLO Input. Connect to VS pin for always ON operation. Can be driven externally from a
micro controller I/O. Pulling the pin low below V(ENF) makes the device enter into low Iq
shutdown mode. For UVLO, connect an external resistor ladder from input supply to EN/
UVLO to ground.
1
EN/UVLO
I
2
3
4
GND
N.C
G
Ground pin
No connection
—
VCAP
O
Charge pump output. Connect to external charge pump capacitor.
Input power supply pin to the controller. Connect a 100-nF capacitor across VS and GND
pins.
5
6
VS
I
GATE
O
Gate drive output. Connect to gate of the external N-channel MOSFET.
Adjustable overvoltage threshold input. Connect a resistor ladder from input supply to OV
pin to ground. When the voltage at OV pin exceeds the overvoltage cutoff threshold then the
GATE is pulled low. GATE turns ON when the OV pin voltage goes below the OVP falling
threshold. Connect OV pin to ground when OV feature is not used.
7
8
OV
I
I
Source pin. Connect to common source point of external back-to-back connected N-channel
MOSFETs or the source pin of the high side switch MOSFET.
SRC
(1) I = Input, O = Output, G = GND
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–65
–0.3
V(VS)
MAX
65
UNIT
V
VS to GND
EN/UVLO, OV to GND, V(VS) > 0 V
65
V
Input Pins
(65 + V(VS))
EN/UVLO, OV, V(VS) ≤0 V
SRC to GND, V(VS) ≤0 V
SRC to GND, V(VS) > 0 V
GATE to SRC
(V(VS) + 0.3)
V
V
V(VS)
15
–(70 –V(VS)
)
0
–0.3
–40
–40
V
Output Pins
VCAP to VS
15
V
Operating junction temperature(2)
Storage temperature, Tstg
150
150
°C
°C
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If
used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
(2) High junction temperatures degrade operating lifetimes. Operating lifetime is de-rated for junction temperatures greater than 125°C.
6.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all
pins(1)
±2000
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per ANSI/ESDA/JEDEC JS-002,
all pins(2)
±750
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–60
–60
22
NOM
MAX
60
UNIT
VS to GND
Input Pins
V
EN/UVLO, OV, SRC to GND
60
VS
nF
µF
External
capacitance
VCAP to VS
0.1
External
MOSFET max GATE to SRC
VGS rating
15
V
TJ
Operating junction temperature range(2)
150
°C
–40
(1) Recommended Operating Conditions are conditions under which the device is intended to be functional. For specifications and test
conditions, see electrical characteristics
(2) High junction temperatures degrade operating lifetimes. Operating lifetime is de-rated for junction temperatures greater than 125°C.
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6.4 Thermal Information
LM74502
LM74502H
THERMAL METRIC(1)
UNIT
DDF (SOT)
8 PINS
RθJA
RθJC(top)
RθJB
ΨJT
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
133.8
72.6
54.5
4.6
°C/W
°C/W
°C/W
°C/W
°C/W
Junction-to-top characterization parameter
Junction-to-board characterization parameter
54.2
ΨJB
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6.5 Electrical Characteristics
TJ = –40°C to +125°C; typical values at TJ = 25°C, V(VS) = 12 V, C(VCAP) = 0.1 µF, V(EN/UVLO) = 3.3 V, over operating free-air
temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
VS SUPPLY VOLTAGE
V(VS)
Operating input voltage
VS POR Rising threshold
VS POR Falling threshold
VS POR Hysteresis
4
60
3.9
3.1
0.67
1.5
65
V
V
V (VS_POR)
2.2
2.8
V
V(VS POR(Hys))
I(SHDN)
0.44
V
Shutdown Supply Current
Operating Quiescent Current
V(EN/UVLO) = 0 V
0.9
45
µA
µA
I(Q)
IGND
VS pin leakage current during input
reverse polarity
I(REV)
100
150
µA
0 V ≤V(VS) ≤–65 V
ENABLE INPUT
V(EN_UVLOF)
Enable/UVLO falling threshold
Enable/UVLO rising threshold
1.027
1.16
1.14
1.24
1.235
1.32
V
V
V(EN_UVLOR)
Enable threshold voltage for low IQ
shutdown
V(ENF)
0.32
38
0.64
0.94
V(EN_Hys)
I(EN/UVLO)
GATE DRIVE
I(GATE)
Enable Hysteresis
Enable sink current
90
3
132
5
mV
µA
V(EN/UVLO) = 12 V
Peak source current
Peak source current
40
3
60
11
77
µA
V
V
(GATE) –V(SRC) = 5 V
mA
(GATE) –V(SRC) = 5 V, LM74502H
I(GATE)
EN= High to Low
(GATE) –V(SRC) = 5 V
Peak sink current
2370
mA
V
EN = High to Low
RDSON
discharge switch RDSON
0.4
2
Ω
V
(GATE) –V(SRC) = 100 mV
CHARGE PUMP
Charge Pump source current (Charge
pump on)
162
300
5
600
10
µA
µA
V
V
(VCAP) –V(VS) = 7 V
(VCAP) –V(VS) = 14 V
I(VCAP)
Charge Pump sink current (Charge
pump off)
Charge pump voltage at V(VS) = 3.2 V
Charge pump turn on voltage
Charge pump turn off voltage
8
10.3
11
V
V
V
V(VCAP) –V(VS)
V(VCAP) –V(VS)
V(VCAP) –V(VS)
I(VCAP) ≤30 µA
11.6
12.4
13
13.9
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6.5 Electrical Characteristics (continued)
TJ = –40°C to +125°C; typical values at TJ = 25°C, V(VS) = 12 V, C(VCAP) = 0.1 µF, V(EN/UVLO) = 3.3 V, over operating free-air
temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
Charge Pump Enable comparator
Hysteresis
0.45
0.8
1.25
7.5
V
V
V
V
(VCAP) –V(VS)
V(VCAP UVLO)
V(VCAP UVLO)
V
(VCAP) –V(S) UV release at rising
5.7
6.5
5.4
edge
V
(VCAP) –V(S) UV threshold at falling
5.05
6.2
edge
OVERVOLTAGE PROTECTION
V(OVR)
V(OVF)
V(OV_Hys)
I(OV)
Overvoltage threshold input, rising
1.165
1.063
1.25
1.143
100
1.333
1.222
V
V
Overvoltage threshold input, falling
OV Hysteresis
mV
nA
OV Input leakage current
0 V < V(OV) < 5 V
12
50
110
6.6 Switching Characteristics
TJ = –40°C to +125°C; typical values at TJ = 25°C, V(VS) = 12 V, CIN = C(VCAP) = COUT = 0.1 µF, V(EN/UVLO) = 3.3 V, over
operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
V(VCAP) > V(VCAP UVLOR), V(EN/UVLO)
>
ENTDLY
EN high to Gate Turn On delay
V(EN_UVLOR) to V(GATE-SRC) > 5 V, C(GATE-
SRC) = 4.7 nF LM74502H
75
110
µs
tUVLO_OFF(deg
V
(EN/UVLO) ↓to V(GATE-SRC) < 1 V,
GATE Turnoff delay during EN/UVLO
GATE Turnoff delay during OV
2
µs
µs
C(GATE-SRC) = 4.7 nF
)_GATE
tOVP_OFF(deg)_
V
(OV) ↑to V(GATE-SRC) < 1 V, C(GATE-
0.6
1
SRC) = 4.7 nF
GATE
V
(OV) ↓to V(GATE-SRC) > 5 V, C(GATE-
tOVP_ON(deg)_G
GATE Turnon delay during OV
5
10
µs
SRC) = 4.7 nF
LM74502H
ATE
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6.7 Typical Characteristics
7
420
390
360
330
300
270
240
210
180
150
120
90
–40C
25C
85C
125C
150C
5.6
4.2
2.8
1.4
0
–40C
25C
85C
125C
150C
60
30
0
0
5
10 15 20 25 30 35 40 45 50 55 60 65
VS (V)
0
5
10 15 20 25 30 35 40 45 50 55 60 65
VS (V)
图6-2. Operating Quiescent Current vs Supply Voltage
图6-1. Shutdown Supply Current vs Supply Voltage
390
360
330
300
270
240
210
550
–40C
500
450
400
350
300
250
200
150
100
25C
85C
125C
150C
–40C
25C
180
150
120
90
85C
125C
150C
60
3
4
5
6
7
8
9
10
11
12
0
2
4
6
8
10
12
VS (V)
VCAP (V)
图6-3. Charge Pump Current vs Supply Voltage at VCAP = 6 V
图6-4. Charge Pump V-I Characteristics at VS > = 12 V
240
1.35
Enable/UVLO rising
Enable/UVLO falling
–40C
220
25C
85C
125C
150C
200
180
160
140
120
100
80
1.28
1.21
1.14
1.07
1
60
40
20
-40
0
40
80
120
160
0
1
2
3
4
5
6
7
8
9
Free-Air Temperature (C)
VCAP (V)
图6-6. EN/UVLO Rising and Falling threshold vs Temperature
图6-5. Charge Pump V-I Characteristics at VS = 3.2 V
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6.7 Typical Characteristics (continued)
85
14
13.4
12.8
12.2
11.6
11
VCAP ON
VCAP OFF
80
75
70
65
60
-40
0
40
80
120
160
-40
0
40
80
120
160
Free-Air Temperature (C)
Free-Air Temperature (C)
图6-8. Charge Pump ON and OFF Threshold vs Temperature
图6-7. Enable to Gate Delay vs Temperature
(LM74502H-Q1)
7.4
3.2
VCAP UVLOR
VCAP UVLOF
VS PORR
VS PORF
7
6.6
6.2
5.8
5.4
5
3
2.8
2.6
2.4
2.2
-40
0
40
80
120
160
-40
0
40
80
120
160
Free-Air Temperature (C)
Free-Air Temperature (C)
图6-9. Charge Pump UVLO Threshold vs Temperature
图6-10. VS POR Threshold vs Temperature
1.4
6
5
4
3
2
1
0
OV Rising
OV Falling
1.32
1.24
1.16
1.08
1
GATE OFF
GATE ON
-40
0
40
80
120
160
-40
0
40
80
120
160
Free-Air Temperature (C)
Free-Air Temperature (C)
图6-11. OV Comparator Threshold vs Temperature
图6-12. OV to GATE Delay vs Temperature (LM74502H-Q1)
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7 Parameter Measurement Information
3.3 V
VEN/UVLOF
–
0.1 V
VENF
0 V
0 V
12.4 V
12.4 V
90%
1 V
0 V
0 V
ttUVLO_OFF(deg)GATE
t
tENTDLY
t
0.1 V
–
VOVF
0.1 V
+
VOVR
0 V
0 V
12.4 V
12.4 V
5 V
1 V
0 V
0 V
ttOVP_OFF(deg)GATE
t
ttOVP_ON(deg)GATEt
图7-1. Timing Waveforms
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8 Detailed Description
8.1 Overview
The LM74502 and LM74502H controller has all the features necessary to implement an efficient and fast reverse
polarity protection circuit with load disconnect feature. This easy to use reverse polarity protection controller is
paired with an external back-to-back connected N-channel MOSFETs to replace other reverse polarity schemes
such as a P-channel MOSFETs. The wide input supply range of 4 V to 65 V allows protection and control of 12-V
and 24-V input supply systems. The device can withstand and protect the loads from negative supply voltages
down to –65 V. An integrated charge pump drives external back-to-back connected N-channel MOSFETs with
gate drive voltage of approximately 13 V. LM74502 with its 60-μA peak gate drive strength is suitable for
applications that needs inherent inrush current control. LM74502H with its fast gate drive strength of 11-mA peak
is suitable for applications which need fast turn-on and turn-off of external MOSFET switch. LM74502 features
an adjustable overvoltage protection using the OV pin. with the enable pin low during the standby mode, both
the external MOSFETs and controller is off and draws a very low shutdown current of 1 μA.
8.2 Functional Block Diagram
VIN
VOUT
GATE
SRC
VS
VCAP
CP
VS
Gate
Driver
VCAP
Internal
Rails
Charge
Pump
Enable
Logic
Gate Drive
Enable
Logic
VS
UVLOb EN
OV
OV
+
EN
1.25 V
1.14 V
EN/UVLO
+
1 V
VS
0.3 V
+
UVLOb
1.25 V
1.14 V
Reverse
Protection Logic
LM74502
LM74502H
GND
8.3 Feature Description
8.3.1 Input Voltage
The VS pin is used to power the LM74502's internal circuitry, typically drawing 45 µA when enabled and 1 µA
when disabled. If the VS pin voltage is greater than the POR Rising threshold, then LM74502 operates in either
shutdown mode or conduction mode in accordance with the EN/UVLO pin voltage. The voltage from VS to GND
is designed to vary from 65 V to –65 V, allowing the LM74502 to withstand negative voltage transients.
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8.3.2 Charge Pump (VCAP)
The charge pump supplies the voltage necessary to drive the external N-channel MOSFET. An external charge
pump capacitor is placed between VCAP and VS pin to provide energy to turn on the external MOSFET. For the
charge pump to supply current to the external capacitor the EN/UVLO pin voltage must be above the specified
input high threshold, V(EN_IH). When enabled the charge pump sources a charging current of 300 µA typically. If
EN/UVLO pins is pulled low, then the charge pump remains disabled. To ensure that the external MOSFET can
be driven above its specified threshold voltage, the VCAP to VS voltage must be above the undervoltage lockout
threshold, typically 6.5 V, before the internal gate driver is enabled. Use 方程式1 to calculate the initial gate
driver enable delay.
T
(DRV_EN) = 75 µs + C(VCAP) × V(VCAP_UVLOR)
300 µA
(1)
where
• C(VCAP) is the charge pump capacitance connected across VS and VCAP pins
• V(VCAP_UVLOR) = 6.5 V (typical)
To remove any chatter on the gate drive approximately 800 mV of hysteresis is added to the VCAP undervoltage
lockout. The charge pump remains enabled until the VCAP to VS voltage reaches 12.4 V, typically, at which
point the charge pump is disabled decreasing the current draw on the VS pin. The charge pump remains
disabled until the VCAP to VS voltage is below to 11.6 V typically at which point the charge pump is enabled.
The voltage between VCAP and VS continue to charge and discharge between 11.6 V and 12.4 V as shown in
图 8-1. By enabling and disabling the charge pump, the operating quiescent current of the LM74502 is reduced.
When the charge pump is disabled it sinks 5-µA typical.
TDRV_EN
TON
TOFF
VIN
VS
0 V
VEN
12.4 V
11.6 V
VCAP-VS
6.5 V
V(VCAP UVLOR)
GATE DRIVER
(GATE to SRC)
ENABLE
图8-1. Charge Pump Operation
8.3.3 Gate Driver (GATE, SRC)
The gate driver is used to control the external N-Channel MOSFET by setting the appropriate GATE to SRC
voltage.
Before the gate driver is enabled, the following three conditions must be achieved:
• The EN/UVLO pin voltage must be greater than the specified input high voltage.
• The VCAP to VS voltage must be greater than the undervoltage lockout voltage.
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• The VS voltage must be greater than VS POR rising threshold.
If the above conditions are not achieved, then the GATE pin is internally connected to the SRC pin, assuring that
the external MOSFET is disabled. After these conditions are achieved, the gate driver operates in the conduction
mode enhancing the external MOSFET completely.
The controller offers two gate drive variants. LM74502 with typical peak gate drive strength of 60 μA is suitable
to achieve smooth start-up with inherent inrush current control due to its lower gate drive strength.
LM74502H with its 11 -mA typical peak gate drive strength is suitable for applications which need faster turn on
such as load switch applications.
LM74502, LM74502H SRC pin is capable of handling negative voltage which also makes it suitable for load
disconnect switch applications with loads which are inductive in nature.
8.3.3.1 Inrush Current Control
An external circuit as shown in 图 8-2 can be added on the GATE pin of the LM74502 to have additional inrush
current control for the applications which have large capacitive loads.
Q1
RG
Cdvdt
GATE
SRC
LM74502
图8-2. Inrush Current Limiting Using LM74502
The CdVdT capacitor is required for slowing down the GATE voltage ramp during power up for inrush current
limiting. Use 方程式2 to calculate CdVdT capacitance value.
C
dvdt = IGATE × COUT
IINRUSH
(2)
where IGATE is 60 μA (typical), IINRUSH is the inrush current and COUT is the output load capacitance. An extra
resistor, RG, in series with the CdVdT capacitor acts as an isolation resistor between Cdvdt and gate of the
MOSFET.
The inrush current control scheme shown in 图 8-2 is not applicable to LM74502H as its gate drive is optimized
for fast turn-on load switch applications.
8.3.4 Enable (EN/UVLO)
The LM74502 has an enable pin, EN/UVLO. The enable pin allows for the gate driver to be either enabled or
disabled by an external signal. If the EN/UVLO pin voltage is greater than the rising threshold, the gate driver
and charge pump operates as described in the Gate Driver (GATE, SRC) and Charge Pump (VCAP) sections. If
the enable pin voltage is less than the input low threshold, the charge pump and gate driver are disabled placing
the LM74502 in shutdown mode. The EN/UVLO pin can withstand a voltage as large as 65 V and as low as –65
V. This feature allows for the EN/UVLO pin to be connected directly to the VS pin if enable functionality is not
needed. In conditions where EN/UVLO is left floating, the internal sink current of 3 uA pulls EN/UVLO pin low
and disables the device.
An external resistor divider connected from input to EN/UVLO to ground can be used to implement the input
Undervoltage Lockout (UVLO) functionality in the system. When EN/UVLO pin voltage is lower than UVLO
comparator falling threshold (VEN/UVLOR) but higher than enable falling threshold (VENF), the device disables gate
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drive voltage, however, charge pump is kept on. This action ensures quick recovery of gate drive when UVLO
condition is removed. If UVLO functionality is not required, connect EN/UVLO pin to VS.
8.3.5 Overvoltage Protection (OV)
LM74502 provides programmable overvoltage protection feature with OV pin. A resistor divider can be
connected from input source to OV pin to ground in order to set overvoltage threshold. An internal comparator
compares the input voltage against fixed reference (1.25 V) and disables the gate drive as soon as OV pin
voltage goes above the OV comparator reference. When the resistor divider is referred from input supply side,
device is configured for overvoltage cutoff functionality. When the resistor divider is referred from output side
(VOUT), the device is configured for overvoltage clamp functionality.
When OV pin voltage goes above OV comparator VOVR threshold (1.25-V typical), the device disables gate
drive, however, charge pump remains active. When OV pin voltage falls below VOVF threshold (1.14-V typical),
the gate is quickly turned on as charge pump is kept on and the device does not go through the device start-up
process. When OV pin is not used, it can be connected to ground.
8.4 Device Functional Modes
8.4.1 Shutdown Mode
The LM74502 enters shutdown mode when the EN/UVLO pin voltage is below the specified input low threshold
V(ENF). Both the gate driver and the charge pump are disabled in shutdown mode. During shutdown mode the
LM74502 enters low IQ operation with the VS pin only sinking 1 µA of current.
8.4.2 Conduction Mode
For the LM74502 to operate in conduction mode the gate driver must be enabled as described in the Gate Driver
(GATE, SRC) section. If these conditions are achieved the GATE pin is
• Internally driven through 60-μA current source in case of LM74502
• Internally connected to the VCAP for fast turn-on of external FET in case of LM74502H
LM74502, LM74502H gate drive is disabled when OV pin voltage is above VOVR threshold or EN/UVLO pin
voltage is lower than VEN/UVLOF threshold.
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9 Application and Implementation
备注
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Application Information
The LM74502 is used with back-to-back connected N-Channel MOSFETs in a typical reverse polarity protection
with load disconnect application. The schematic for the 12-V input supply reverse polarity protection is shown in
图 9-1, where the LM74502 is used to drive the back-to-back connected MOSFETs Q1 and Q2 in series with a
12-V supply.
9.2 Typical Application
Q1
Q2
VOUT
VIN
12 V
CIN
0.1 µF
COUT
220 µF
SRC
GATE
VS
VCAP
220 nF
R1
100 k
VCAP
OV
LM74502
EN / UVLO
OFF
ON
R2
GND
3.5 k
图9-1. Typical Application Circuit
9.2.1 Design Requirements
A design example, with system design parameters listed in 表9-1 is presented.
表9-1. Design Parameters
DESIGN PARAMETER
Input voltage range
Overvoltage protection
Output current
EXAMPLE VALUE
12-V nominal
37 V
5-A full load
Output capacitance
220-µF typical output capacitance
9.2.2 Detailed Design Procedure
9.2.2.1 Design Considerations
• Input operating voltage range (including overvoltage protection)
• Maximum load current
9.2.2.2 MOSFET Selection
The important MOSFET electrical parameters are the maximum continuous drain current ID, the maximum drain-
to-source voltage VDS(MAX), the maximum gate-to-source voltage VGS(MAX) and the drain-to-source On resistance
RDSON
.
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The maximum continuous drain current, ID, rating must exceed the maximum continuous load current. The
maximum drain-to-source voltage, VDS(MAX), must be high enough to withstand the highest differential voltage
seen in the application. This requirement would include any anticipated fault conditions. The maximum VGS
LM74502 can drive is 13.9 V, so a MOSFET with 15-V minimum VGS rating must be selected. If a MOSFET with
VGS rating < 15 V is selected, a zener diode can be used between GATE to SRC pin to clamp VGS to safe level.
To reduce the MOSFET conduction losses, lowest possible RDS(ON) is preferred. Selecting a MOSFET with
RDS(ON) that gives VDS drop 20 mV to 50 mV provides good trade off in terms of power dissipation and cost.
Thermal resistance of the MOSFET must be considered against the expected maximum power dissipation in the
MOSFET to ensure that the junction temperature (TJ) is well controlled.
9.2.2.3 Overvoltage Protection
Resistors R1 and R2 connected in series is used to program the overvoltage threshold. Connecting R1 to VIN
provides overvoltage cutoff and switching the connection to VOUT provides overvoltage clamp response. The
resistor values required for setting the overvoltage threshold VOV to 37 V are calculated by solving 方程式3
R2 × VOV
VOVR
=
R1 + R2
(3)
For minimizing the input current drawn from the supply through resistors R1 and R2, it is recommended to use
higher value of resistance. Using high value resistors adds error in the calculations because the current through
the resistors at higher value becomes comparable to the leakage current into the OV pin. Select (R1 + R2) such
that current through resistors is around 100 times higher than the leakage through OV pin. Based on the device
electrical characteristics, VOVR is 1.25 V , Select (R1) = 100 kΩand R2 = 3.5 kΩas a standard resistor value to
set overvoltage cutoff of 37 V.
9.2.2.4 Charge Pump VCAP, Input and Output Capacitance
Minimum required capacitance for charge pump VCAP and input and output capacitance are:
• CVCAP: minimum recommended value of VCAP (µF) ≥10 × Effective CISS(MOSFET) (µF), 0.22 μF is selected
• CIN: typical input capacitor of 0.1 µF
• COUT: typical output capacitor 220 µF
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9.2.3 Application Curves
Time (4 ms/DIV)
Time (10 ms/DIV)
图9-3. Start-up with No Load
图9-2. Start-up with Reverse Voltage –12 V)
Time (4 ms/DIV)
Time (2 ms/DIV)
图9-4. Start-up with 5-A Load
图9-5. Start-up with EN Control
Time (10 ms/DIV)
Time (4 ms/DIV)
图9-7. Overvoltage Recovery
图9-6. Overvoltage Cutoff Response (37 V)
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9.3 Input Surge Stopper Using LM74502, LM74502H
Many industrial applications need to comply with input overvoltage transients and surge events specified by
standards such as IEC61000-4-x. LM74502, LM74502H can be configured as input surge stopper to provide
overvoltage along with input reverse supply protection.
Q1
200 V
Q2
60 V
VIN
VOUT
24-V Nominal
200-V Transient
R1
10 k
CIN
0.1 µF
COUT
220 µF
VOUT
(OV Clamp)
R2
100 k
VIN
OV cut-off
SRC
VS
GATE
OV
DZ
R3
3.5 k
CVS
1 µF
60 V
VCAP
CVCAP
220 nF
LM74502
GND
EN/UVLO
OFF
ON
图9-8. Typical Surge Stopper Application for 24-V Powered Systems
As shown in 图 9-8 MOSFET Q1 is used to turn off or clamp output voltage to acceptable safe level and protect
the MOSFET Q2 and LM74502 from input transient. Note that only the VS pin is exposed to input transient
through a resistor, R1. A 60-V rated zener diode is used to clamp and protect the VS pin within recommended
operating condition. Rest of the circuit is not exposed to higher voltage as the MOSFET Q1 can either be turned
off completely or output voltage clamped to safe level.
9.3.1 VS Capacitance, Resistor R1 and Zener Clamp (DZ)
Minimum of 1 µF CVS capacitance is required. During input overvoltage transient, resistor R1 and zener diode DZ
are used to protect VS pin from exceeding the maximum ratings by clamping VVS to 60 V. Choosing R1 = 10 kΩ,
the peak power dissipated in zener diode DZ can be calculated using 方程式4.
PDZ = VDZ × (VIN(MAX) – VDZ)
R1
(4)
Where VDZ is the breakdown voltage of zener diode. Select the zener diode which can handle peak power
requirement.
Peak power dissipated in resistor R1 can be calculated using 方程式5.
PR1 = (VIN(MAX) – VDZ)2
R1
(5)
Select a resistor package which can handle peak power and maximum DC voltage.
9.3.2 Overvoltage Protection
For the overvoltage setting, refer to the resistor selection procedure described in Overvoltage Protection. Select
(R2) = 100 kΩand R3 = 3.5 kΩas a standard resistor value to set overvoltage cutoff of 37 V.
9.3.3 MOSFET Selection
The VDS rating of the MOSFET Q1 must be minimum VIN(max) for designs with output overvoltage cutoff where
output can reach 0 V with higher loads. For designs with output overvoltage clamp, MOSFET VDS rating must
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be (VIN(max) – VOUT_CLAMP). The VGS rating is based on GATE-SRC maximum voltage of 15 V. TI recommends
a 20-V VGS rated MOSFET. Power dissipation on MOSFET Q1 on a design where output is clamped is critical
and SOA characteristics of the MOSFET must be considered with sufficient design margin for reliable operation.
An additional zener diode from GATE to SRC can be needed to protect the external FET in case output is
expected to drop to the level where it can exceed external FET VGS(max) rating.
图9-9. 200-V Surge Stopper with Overvoltage Cutoff Using LM74502
9.4 Fast Turn-On and Turn-Off High Side Switch Driver Using LM74502H
In applications such as industrial motor drives and safety power line communication digital output modules, N-
Channel MOSFET based high side switch is very commonly used to disconnect the loads from supply line in
case of faults such as overvoltage event . LM74502, LM74502H can be used to drive external MOSFET to
realize simple high side switch with overvoltage protection. 图 9-10 shows a typical application circuit where
LM74502H is used to drive external MOSFET Q1 as a main power path connect and disconnect switch. A
resistor divider from input to OV pin to ground can be used the set the overvoltage threshold.
If VOUT node (SRC pin) of the device is expected to drop in case of events such as overcurrent or short-circuit
on load side then additional zener diode is required across gate and source pin of external MOSFET to protect it
from exceeding it's maximum VGS rating.
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Q1
VOUT
VIN
High Side
Switch
LOAD3
LOAD2
LOAD3
COUT
CIN
Low Side
Switch
VS
GATE
SRC
CVCAP
VIN
R1
OV pin used for
overvoltage
protection
VCAP
OV
LM74502H
GND
DC/DC
Converter
R2
EN/UVLO
OFF
ON
OFF
ON
OV pin used as logic input for
fast turn ON/OFF of FET Q1
图9-10. Fast Turn-ON and OFF High Side Switch Using LM74502H
Many industrial safety applications require fast switching off of MOSFET to verify proper functioning of the high
side disconnect switch for diagnostic purpose. LM74502H OV pin can be used as control input to realize fast
turn-on and turn-off load switch functionality. with OV pin pulled above VOVR threshold of (1.25-V typical),
LM74502H turns off the external MOSFET (with Ciss = 4.7 nF) within 1 μs typically. When OV pin is pulled low,
LM74502H with its peak gate drive strength of 11 mA turns on external MOSFET with turn on speed of 7-μs
typical. 图 9-11 shows LM74502H GATE to SRC response when OV pin is used as logic input for turning
external MOSFET on and off.
图9-11. Fast Turn-On and Turn-Off High Side Switch Driver Using LM74502H
10 Power Supply Recommendations
The LM74502, LM74502H reverse polarity protection controller is designed for the supply voltage range of 3.2 V
≤ VS ≤ 65 V. If the input supply is located more than a few inches from the device, TI recommends an input
ceramic bypass capacitor higher than 0.1 μF. Based on system requirements, a higher input bypass capacitor
may be needed with LM74502H to avoid supply glitch in case of high inrush current start-up event. To prevent
LM74502 and surrounding components from damage under the conditions of a direct output short circuit, use a
power supply having overload and short-circuit protection.
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11 Layout
11.1 Layout Guidelines
• Place the input capacitor CIN of 0.1-μF minimum close to VS pin to ground. This typically helps with better
EMI performance.
• Connect GATE and SRC pin of LM74502, LM74502H close to the MOSFET's GATE and SOURCE pin.
• Use thick traces for source and drain of the MOSFET to minimize resistive losses because the high current
path of for this solution is through the MOSFET.
• The charge pump capacitor across VCAP and VS pin must be kept away from the MOSFET to lower the
thermal effects on the capacitance value.
• The GATE pin of the LM74502, LM74502H must be connected to the MOSFET gate with short trace. Avoid
excessively thin and long running trace to the Gate Drive.
11.2 Layout Example
Bo om Layer
Signal Via
VOUT
Q2
G
S
S
S
COUT
LM74502
8
SRC
OV
1
EN/UVLO
GND
Q1
VIN
2
7
6
5
D
D
D
D
N.C
3
4
GATE
VS
VCAP
CIN
CVCAP
GND
GND
图11-1. Layout Example
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12 Device and Documentation Support
12.1 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
12.2 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
12.3 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
12.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.5 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
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13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LM74502DDFR
ACTIVE SOT-23-THIN
ACTIVE SOT-23-THIN
DDF
DDF
8
8
3000 RoHS & Green
3000 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
LM502
L502H
Samples
Samples
LM74502HDDFR
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
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15-May-2022
OTHER QUALIFIED VERSIONS OF LM74502, LM74502H :
Automotive : LM74502-Q1, LM74502H-Q1
•
NOTE: Qualified Version Definitions:
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LM74502DDFR
SOT-23-
THIN
DDF
DDF
8
8
3000
3000
180.0
8.4
3.2
3.2
1.4
4.0
8.0
Q3
LM74502HDDFR
SOT-23-
THIN
180.0
8.4
3.2
3.2
1.4
4.0
8.0
Q3
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
LM74502DDFR
SOT-23-THIN
SOT-23-THIN
DDF
DDF
8
8
3000
3000
210.0
210.0
185.0
185.0
35.0
35.0
LM74502HDDFR
Pack Materials-Page 2
PACKAGE OUTLINE
DDF0008A
SOT-23 - 1.1 mm max height
S
C
A
L
E
4
.
0
0
0
PLASTIC SMALL OUTLINE
C
2.95
2.65
SEATING PLANE
TYP
PIN 1 ID
AREA
0.1 C
A
6X 0.65
8
1
2.95
2.85
NOTE 3
2X
1.95
4
5
0.38
0.22
8X
0.1
C A B
1.65
1.55
B
1.1 MAX
0.20
0.08
TYP
SEE DETAIL A
0.25
GAGE PLANE
0.1
0.0
0 - 8
0.6
0.3
DETAIL A
TYPICAL
4222047/C 10/2022
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
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EXAMPLE BOARD LAYOUT
DDF0008A
SOT-23 - 1.1 mm max height
PLASTIC SMALL OUTLINE
8X (1.05)
SYMM
1
8
8X (0.45)
SYMM
6X (0.65)
5
4
(R0.05)
TYP
(2.6)
LAND PATTERN EXAMPLE
SCALE:15X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4222047/C 10/2022
NOTES: (continued)
4. Publication IPC-7351 may have alternate designs.
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
DDF0008A
SOT-23 - 1.1 mm max height
PLASTIC SMALL OUTLINE
8X (1.05)
SYMM
(R0.05) TYP
8
1
8X (0.45)
SYMM
6X (0.65)
5
4
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4222047/C 10/2022
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
7. Board assembly site may have different recommendations for stencil design.
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