ONET2804T [TI]
28Gbps 4 通道限幅跨阻放大器;
| 型号： | ONET2804T |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 28Gbps 4 通道限幅跨阻放大器 放大器 |
| 文件： | 总33页 (文件大小：3948K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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ONET2804T
ZHCSCY8B –JULY 2014–REVISED MARCH 2018
ONET2804T 28Gbps 4 通道限幅 TIA
1 特性
3 说明
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4 通道多速率运行，最高达 28Gbps
ONET2804T 是一款高增益限幅互阻抗放大器，适用于
并行光学互连，数据速率最高可达 28Gbps。该器件与
750μm 间距离光电二极管阵列配合使用，可将光信号
转换为差分输出电压。由内部电路提供光电二极管反向
偏置电压并感测提供给各光电二极管的平均光电流。
10kΩ 差分互阻抗
21GHz 带宽
1.8μArms 输入引入噪声
2.9mAPP 输入过载电流
可编程输出电压
该器件可配合引脚控制或两线制串口使用，从而实现对
输出幅值、增益、带宽和输入阈值的控制。
可调增益和带宽
用于每个通道的接收信号强度指示器 (RSSI)
通道间 40dB 隔离（仅限芯片）
3.3V 单电源
ONET2804T 具有 21GHz 带宽、10kΩ 增益、
1.8µArms 输入引入噪声和每通道的接收信号强度指示
器 (RSSI)。通道间的 40dB 隔离可降低接收器中的串
扰。
每通道 139mW
引脚控制或 2 线控制
片上滤波器电容
该部件需要 3.3V 单电源供电，每个通道的功耗典型值
为 139mW，差分输出幅度为 500mVPP。其工作温度
范围为 –40°C 至 100°C，采用芯片形式，通道间距为
750μm。
工作温度范围 -40°C 至 100°C
芯片尺寸：3250μm × 1450μm，750μm 通道间距
2 应用
要获得完整数据表，请发送邮件至：onet2804t_
request@ti.com。
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100G 以太网光发射器
ITU OTL4.4
器件信息(1)
具有内部重定时功能的 CFP2、CFP4 和 QSFP28
模块
器件型号
ONET2804T
封装
封装尺寸（标称值）
裸片采用叠片封装
3250µm × 1450µm
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
简化原理图
眼图
VCC
330pF
RSSI
RRSSI
GND
GND
Photodiode
FILTER1
IN1
0.1ꢀF
0.1ꢀF
OUT1+
OUT1-
OUT+
OUT-
1 CHANNEL of 4
FILTER1
GND
GND
GND
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SLLSEK1
ONET2804T
ZHCSCY8B –JULY 2014–REVISED MARCH 2018
www.ti.com.cn
目录
7.4 Device Functional Modes........................................ 13
7.5 Register Maps......................................................... 16
Application and Implementation ........................ 24
8.1 Application Information............................................ 24
8.2 Typical Applications ................................................ 24
Power Supply Recommendations...................... 27
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 4
Specifications......................................................... 6
6.1 Absolute Maximum Ratings ...................................... 6
6.2 ESD Ratings ............................................................ 6
6.3 Recommended Operating Conditions....................... 6
6.4 DC Electrical Characteristics .................................... 7
6.5 AC Electrical Characteristics..................................... 7
6.6 Typical Characteristics.............................................. 8
Detailed Description ............................................ 11
7.1 Overview ................................................................. 11
7.2 Functional Block Diagram ....................................... 11
7.3 Feature Description................................................. 12
8
9
10 Layout................................................................... 28
10.1 Layout Guidelines ................................................. 28
10.2 Layout Example .................................................... 28
11 器件和文档支持 ..................................................... 31
11.1 接收文档更新通知 ................................................. 31
11.2 社区资源................................................................ 31
11.3 商标....................................................................... 31
11.4 静电放电警告......................................................... 31
11.5 Glossary................................................................ 31
12 机械、封装和可订购信息....................................... 31
7
4 修订历史记录
Changes from Revision A (April 2015) to Revision B
Page
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首次公开发布的数据表............................................................................................................................................................ 1
已添加 接收文档更新通知和社区资源部分............................................................................................................................ 31
Changes from Original (July 2014) to Revision A
Page
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将说明 中的文字从“差分输出幅度为 450mVPP”更改为“差分输出幅度为 500mVPP”................................................................. 1
Changed PAD 6, AMPL Description From: "VCC: 450 mVpp differential output swing To: "VCC: 500 mVpp
differential output swing" in Bond Pad Functions ................................................................................................................... 4
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Changed From: Handling Ratings To: ESD Ratings ............................................................................................................. 6
Changed the Average Input current MAX value in the Recommended Operating Conditions From: 3 mA to: 2.7 mA ........ 6
Changed From: VOD = 450 mVPP To: VOD = 500 mVPP in the DC Electrical Characteristics condition statement ................. 7
Changed From: VOD = 450 mVPP To: VOD = 500 mVPP in the AC Electrical Characteristics condition statement.................. 7
Changed VOD test conditions in the AC Electrical Characteristics From: 450 mVPP To: VOD = 500 mVPP ............................ 7
Changed VOD values in the AC Electrical Characteristics , TYP From: 450 To: 500, MAX From: 650 To: 700 mVPP .......... 7
Changed From: VOD = 450 mVPP To: VOD = 500 mVPP in the Typical Characteristics condition statement........................... 8
Changed text in Amplitude Adjustment From: "450 mVpp if the pad is tied to VCC" To: "500 mVpp if the pad is tied
to VCC"................................................................................................................................................................................. 12
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Changed From: [reset = 9h] To: [reset = 0h] in Register 1 (0x01) – Amplitude and Rate for Channel 1 (offset = 1h)
[reset = 0h]............................................................................................................................................................................ 17
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Changed Table 3, Reset value 9h To: 0h. Moved (default) From 10010 To: 0000 ............................................................. 17
Changed From: [reset = 9h] To: [reset = 0h] in Register 7 (0x07) – Amplitude and Rate for Channel 2 (offset = 7h)
[reset = 0h]............................................................................................................................................................................ 18
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Changed Table 9, Reset value 9h To: 0h. Moved (default) From 10010 To: 0000 ............................................................. 18
Changed From: [reset = 9h] To: [reset = 0h] in Register 13 (0x0D) – Amplitude and Rate for Channel 3 (offset = Dh)
[reset = 0h]............................................................................................................................................................................ 20
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Changed Table 15, Moved (default) From 10010 To: 0000................................................................................................. 20
Changed From: [reset = 9h] To: [reset = 0h] in Register 19 (0x13) – Amplitude and Rate for Channel 4 (offset =
13h ) [reset = 0h] .................................................................................................................................................................. 22
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Changed Table 21, Moved (default) From 10010 To: 0000................................................................................................. 22
2
Copyright © 2014–2018, Texas Instruments Incorporated
ONET2804T
www.ti.com.cn
ZHCSCY8B –JULY 2014–REVISED MARCH 2018
•
•
Changed the Output voltage From: 450 mVPP to: 500 mvPP in Table 28 ............................................................................. 24
Changed text in Detailed Design Procedure From: "450 mVPP level by bonding AMPL" To: "500 mVPP level by
bonding AMPL"..................................................................................................................................................................... 25
Copyright © 2014–2018, Texas Instruments Incorporated
3
ONET2804T
ZHCSCY8B –JULY 2014–REVISED MARCH 2018
www.ti.com.cn
5 Pin Configuration and Functions
Bond Pad Assignment of ONET2804T
76 75 74 73 72 71 70 69 68 67 66 65 64
59
56
53 52
51 50 49 48
55 54
63 62 61
60
58 57
47
VCCO1
VCCO2
VCCI2
1
2
3
4
5
6
46
45
44
43
42
41
VCCO4
VCCO3
VCCI3
VCC14
NC
VCCI1
I2CENA
AMPL
TRSH
CHANNEL 1
CHANNEL 2
CHANNEL 4
CHANNEL 3
7
8
40
39
SCL
SDA
RATE
GAIN
RSSI1
RSSI2
RSSI4
RSSI3
9
38
37
10
19 20 21
23 24
28 29 30 31 32
36
11 12 13 14 15 16 17 18
22
25 26 27
33 34 35
Bond Pad Functions
PAD
SYMBOL
TYPE
DESCRIPTION
3-state input for amplitude control of all 4 channels.
VCC: 500 mVpp differential output swing
Open: 300 mVpp differential output swing (default)
GND: 250 mVpp differential output swing.
6
AMPL
Digital input
2-wire interface address programming pin. Leave this pad open for a default address of
0001100. Grounding this pad changes the 2nd address bit to a 1 (0001110).
53
54
ADR1
Digital input
Digital input
2-wire interface address programming pin. Leave this pad open for a default address of
0001100. Grounding this pad changes the 1st address bit to a 1 (0001101).
ADR0
12, 14, 19, 21,
26, 28, 33, 35
FILTERx
Analog output Bias voltage for photodiode cathode. These pads are biased to VCC - 100 mV.
3-state input for gain control of all 4 channels.
VCC: Minimum transimpedance
Open: Default transimpedance
8
GAIN
Digital input
GND: Medium transimpedance
11, 15, 18, 22,
25, 29, 32, 36,
47, 48, 51, 52,
55, 56, 59, 60,
63, 64, 67, 68,
71, 72, 75, 76
Circuit ground. All GND pads are connected on die. Bonding all pads is recommended,
except for 11, 15, 18, 22, 25,29,32, and 36.
GND
Supply
2-wire control option. Leave the pad unconnected for pad control of the IC. Two-wire
Digital input
5
I2CENA
control can be enabled by applying a high signal to the pad.
13, 20, 27, 34 INx
Analog input
No Connect
Data input to TIAx (connect to photodiode anode).
16, 17, 23, 24,
30, 31, 42, 61, NC
62, 69
Do not connect
Used to reset the 2-wire state machine and registers. Leave open for normal operation and
set low to reset the 2-wire interface.
70
NRESET
Digital input
49, 57, 65, 73 OUTx–
Analog output Inverted CML data output for channel x. On-chip 50 Ω back-terminated to VCC.
4
Copyright © 2014–2018, Texas Instruments Incorporated
ONET2804T
www.ti.com.cn
PAD
ZHCSCY8B –JULY 2014–REVISED MARCH 2018
Bond Pad Functions (continued)
SYMBOL
TYPE
DESCRIPTION
50, 58, 66, 74 OUTx+
Analog output Non-inverted CML data output for channel x. On-chip 50 Ω back-terminated to VCC.
3-state input for bandwidth control of all 4 channels.
VCC: Increase the bandwidth
Open: 21 GHz bandwidth (default)
GND: reduce the bandwidth
7
RATE
Digital input
Indicates the strength of the received signal (RSSI) for channel x if the photo diode is
biased from FILTERx. The analog output current is proportional to the input data
9, 10, 37, 38 RSSIx
Analog output amplitude. Connect to an external resistor to ground (GND). For proper operation, ensure
that the voltage at the RSSI pad does not exceed VCC - 0.65 V. If the RSSI feature is not
used these pads should be left open.
40
39
SCL
SDA
Digital input
2-wire interface serial clock input. Includes a 10 kΩ pull-up resistor to VCC.
Digital –in/out 2-wire interface serial data input. Includes a 10 kΩ pull-up resistor to VCC
.
3-state input for threshold control.
VCC: Crossing point shifted down
Open: No threshold adjustment (default)
41
TRSH
Digital input
GND: Crossing point shifted up
1, 2, 45, 46
3, 4, 43, 44
VCCOx
VCCIx
Supply
Supply
2.97 V – 3.47 V supply voltage for AGCx and CMLx amplifiers.
2.97 V – 3.47 V supply voltage for input TIAx stage.
Copyright © 2014–2018, Texas Instruments Incorporated
5
ONET2804T
ZHCSCY8B –JULY 2014–REVISED MARCH 2018
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
UNIT
Supply voltage(1)
Voltage(1)
VCCIx, VCCOx
–0.3
4
V
FILTERx, OUTx+, OUTx–, RSSIx, SCL, SDA, I2CENA, AMPL, RATE,
GAIN, TRSH, ADR1, ADR0 and NRESET
–0.3
4
V
INx
–0.7
–8
5
8
mA
mA
mA
°C
Average Input current
FILTERx
Continuous current at outputs OUTx+, OUTx–
Maximum junction temperature, TJ
Storage temperature, Tstg
–8
8
125
150
–65
°C
(1) All voltage values are with respect to network ground terminal.
6.2 ESD Ratings
VALUE
±1000
±500
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC
JS-001
All pins except input INx
Pin INx
Electrostatic
discharge
(1)
V(ESD)
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
TYP
MAX
3.47
2.7
UNIT
V
VCC
Supply voltage
2.97
3.3
I(INx)
Average Input current
mA
°C
nH
pF
V
TA
Operating backside die temperature
Wire-bond inductance at pins FILTERx and INx
Photodiode Capacitance
–40
100
L(FILTER), L(IN)
0.3
0.1
C(PD)
VIH
Digital input high voltage
Digital input low voltage
3-state input high voltage
3-state input low voltage
SDA, SCL
SDA, SCL
2
VIL
0.8
0.4
V
VCC - 0.4
V
V
6
Copyright © 2014–2018, Texas Instruments Incorporated
ONET2804T
www.ti.com.cn
ZHCSCY8B –JULY 2014–REVISED MARCH 2018
6.4 DC Electrical Characteristics
Over recommended operating conditions with VOD = 500 mVPP unless otherwise noted. Typical values are at VCC = 3.3 V and
TA = 25°C
PARAMETER
Supply voltage
TEST CONDITIONS
MIN
TYP
3.3
42
MAX
3.47
57(1)
60(1)
198
UNIT
VCC
ICC
2.97
V
Per channel, 30 μAPP input, maximum 85°C
Per channel, 30 μAPP input, maximum 100°C
Per channel, 30 μAPP input, maximum 85°C
Per channel, 30 μAPP input, maximum 100°C
Supply current
mA
139
P(RX)
Receiver power dissipation
mW
208
VIN
Input bias voltage
0.75
40
0.85
50
0.98
60
V
Ω
ROUT
Output resistance
Single-ended to VCC
V(FILTER)
A(RSSI_IB)
Photodiode bias voltage(2)
2.8
0.49
0
3.2
0.5
V
RSSI gain
Resistive load to GND(3)
0.54
2.5
A/A
µA
RSSI output offset current (no light)
(1) Including RSSI current
(2) Regulated voltage typically 100mV lower than VCC
.
(3) The RSSI output is a current output, which requires a resistive load to ground (GND). The voltage gain can be adjusted for the intended
application by choosing the external resistor; however, for proper operation, ensure that the voltage at RSSI does not exceed
VCC-0.65V.
6.5 AC Electrical Characteristics
Over recommended operating conditions with VOD = 500 mVPP unless otherwise noted. Typical values are at VCC = 3.3 V and
TA = 25°C
PARAMETER
TEST CONDITIONS
MIN
7
TYP
10
MAX
UNIT
kΩ
Z21
Small signal transimpedance
–3dB bandwidth
25 μAPP input signal
25 μAPP input signal(1)
f(3dB-H)
f(3dB-L)
iN(IN)
18.5
21
GHz
kHz
μA
Low frequency –3dB bandwidth
Input referred RMS noise
30
100
2.5
CPD = 0.1 pF, 28 GHz BT4 filter(2)
1.8
35 µApp < iIN < 250 µApp
(27.95 Gbps, PRBS9 pattern)
2
2
4
250 µApp < iIN < 500 µApp
(27.95 Gbps, PRBS9 pattern)
DJ
Deterministic jitter
pspp
500 µApp < iIN < 2900 µApp
(27.95 Gbps, PRBS9 pattern)
VOD
PSRR
Differential output voltage
Crosstalk
500 mVPP setting
Between adjacent channels, up to 20 GHz(3)
250
500
–40
1
700
mVPP
dB
RSSI response time
Power supply rejection ratio
μs
F < 10 MHz(4)
–15
dB
(1) The small signal bandwidth is specified over process corners, temperature, and supply voltage variation. The assumed photodiode
capacitance is 0.1pF and the bond-wire inductance is 0.3nH. The small signal bandwidth strongly depends on environmental parasitics.
Careful attention to layout parasitics and external components is necessary to achieve optimal performance.
(2) Input referred RMS noise is (RMS output noise)/ (gain at 100 MHz).
(3) Die only, no wire bonds
(4) PSRR is the differential output amplitude divided by the voltage ripple on the supply. No input current at IN.
Copyright © 2014–2018, Texas Instruments Incorporated
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ONET2804T
ZHCSCY8B –JULY 2014–REVISED MARCH 2018
www.ti.com.cn
6.6 Typical Characteristics
Typical operating condition is at VCC = 3.3 V, TA = 25°C and VOD = 500 mVpp (unless otherwise noted).
14
12
10
8
12000
10000
8000
6000
4000
2000
0
6
4
2
0
0
200
400
600
800
1000
-40
-20
0
20
40
60
80
100
Input Current (mA)
Ambient Temperature (èC)
D001
D002
Figure 1. Transimpedance vs Input Current
Figure 2. Small Signal Transimpedance vs Ambient
Temperature
6
28
24
20
16
12
8
3
0
-3
-6
-9
-12
-15
-18
-21
4
0
0.01
0.1
1
10
100
-40
-20
0
20
40
60
80
100
Frequency (GHz)
Ambient Temperature (èC)
D004
D003
Figure 3. Gain vs Frequency
(Test Fixture loss De-embedded)
Figure 4. Small Signal Bandwidth vs Ambient Temperature
(Test Fixture loss De-embedded)
500
10
450
400
350
300
250
200
150
100
50
8
6
4
2
0
0
0
100
200
300
400
500
0
400
800
1200
1600
2000
2400
2800
Input Current (mA)
Input Current (mA)
D005
D006
Figure 5. Output Voltage vs Input Current
Figure 6. Deterministic Jitter vs Input Current
8
Copyright © 2014–2018, Texas Instruments Incorporated
ONET2804T
www.ti.com.cn
ZHCSCY8B –JULY 2014–REVISED MARCH 2018
Typical Characteristics (continued)
Typical operating condition is at VCC = 3.3 V, TA = 25°C and VOD = 500 mVpp (unless otherwise noted).
600
500
400
300
200
100
0
2
1.8
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
0
-40
-20
0
20
40
60
80
100
0
500
1000
1500
2000
2500
Ambient Temperature (èC)
Input Current (mA)
D007
D008
Figure 7. Input Referred Noise vs Temperature
Figure 8. Power vs Input Current
1500
1250
1000
750
500
250
0
0
250 500 750 1000 1250 1500 1750 2000 2250 2500
Average Input Current (mA)
D001
Figure 9. RSSI Output Current vs Average Input Current
Copyright © 2014–2018, Texas Instruments Incorporated
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ONET2804T
ZHCSCY8B –JULY 2014–REVISED MARCH 2018
www.ti.com.cn
Typical Characteristics (continued)
Typical operating condition is at VCC = 3.3 V, TA = 25°C and VOD = 500 mVpp (unless otherwise noted).
27.95 GBPS
27.95 GBPS
Figure 10. Output Eye-Diagram, 30 µAP-P Input Current
Figure 11. Output Eye-Diagram, 500 µAP-P Input Current
27.95 GBPS
27.95 GBPS
Figure 12. Output Eye-Diagram, 1.5 mAP-P Input Current
Figure 13. Output Eye-Diagram, 2.5 mAP-P Input Current
10
Copyright © 2014–2018, Texas Instruments Incorporated
ONET2804T
www.ti.com.cn
ZHCSCY8B –JULY 2014–REVISED MARCH 2018
7 Detailed Description
7.1 Overview
A simplified block diagram of one channel of the ONET2804T is shown in Functional Block Diagram.
The ONET2804T consists of the signal path, supply filters, a control block for DC input bias, automatic gain
control (AGC) and received signal strength indication (RSSI), an analog reference block and a 2-wire serial
interface and control logic block.
The signal path consists of a transimpedance amplifier stage, a voltage amplifier, and a CML output buffer. The
on-chip filter circuit provides a filtered VCC for the PIN photodiode and for the transimpedance amplifier. The
RSSI provides the bias for the TIA stage and the control for the AGC.
The DC input bias circuit and automatic gain control use internal low pass filters to cancel the DC current on the
input and to adjust the transimpedance amplifier gain. Furthermore, circuitry is provided to monitor the received
signal strength.
The output amplitude, gain, bandwidth and input threshold can be globally controlled through pin settings or each
channel can be individually controlled through the 2-wire interface.
7.2 Functional Block Diagram
VCCO1
To Output Stages
To TIA Stages
1 Channel of 4
VCCI1
GND
FILTER1
AGC and RSSI
Detection
RSSI1
VCC
RF
Voltage Amplifier
with Selectable
Bandwidth
50ꢀ
50ꢀ
OUT1+
OUT1-
IN1
Gain Stage
CML Output
Buffer
TIA
DC Offset
Cancellation
VCC
10kꢀ
10kꢀ
8 Bit Register
Settings
BW/AMP
Gain/Thres
Settings
Settings
SDA
SCL
SDA
SCL
8 Bit Register
8 Bit Register
8 Bit Register
8 Bit Register
I2CENA
I2CENA
NRESET
ADR0
NRESET
ADR0
2-Wire Control
Individual Channel Control
ADR1
ADR1
AMPL
RATE
GAIN
TRSH
AMPL
RATE
GAIN
TRSH
Pin Control
Global for all 4 Channels
Band-Gap, Analog
References
Power-On
Reset
2-Wire Interface and Control Logic
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ONET2804T
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www.ti.com.cn
7.3 Feature Description
7.3.1 Signal Path
The first stage of the signal path is a transimpedance amplifier which converts the photodiode current into a
voltage. If the input signal current exceeds a certain value, the transimpedance gain is reduced by means of a
nonlinear AGC circuit to limit the signal amplitude.
The second stage is a limiting voltage amplifier that provides additional limiting gain and converts the single
ended input voltage into a differential data signal. The output stage provides CML outputs with an on-chip 50Ω
back-termination to VCC
.
The TIA has adjustable gain, amplitude, bandwidth and input threshold and they can be globally controlled
through pad settings or each channel can be individually controlled through the 2-wire interface. The default
mode of operation is pad control where the state (OPEN, HI or LO) of the AMPL, BW, GAIN and TRSH pads
sets the respective parameter. To enable 2-wire control, the I2CENA pad should be set HIGH and the
functionality of each channel can be controlled individually through the 2-wire interface.
7.3.2 Gain Adjustment
The gain of all TIAs can be adjusted using the GAIN pad (pad 8) in pad control mode. The gain is set to default if
the pad is left open. The gain is reduced approximately 4 dB if the pad is tied to ground, and reduced
approximately 8 dB if the pad is tied to VCC. In 2-wire control mode, the gain of each channel can be adjusted
from minimum to default. The gain is controlled with the GAIN[0..1] bits in registers 2, 8, 14 and 20 respectively
for channels 1, 2, 3 and 4.
7.3.3 Amplitude Adjustment
The output amplifier of all buffers can be adjusted using the AMPL pad (pad 6) in pad control mode. The
amplitude is set to 300 mVpp differential if the pad is left open, 250 mVpp if the pad is tied to ground and 500
mVpp if the pad is tied to VCC (recommended mode of operation). In 2-wire control mode, the amplitude of each
channel can be adjusted from 0mVpp to 600 mVpp. The amplitude is controlled with the AMPL[0..3] bits in
registers 1, 7, 13 and 19 respectively for channels 1, 2, 3 and 4.
7.3.4 Rate Select
The small signal bandwidth can be adjusted using the RATE pad (pad 7) in pad control mode. The bandwidth is
typically 21 GHz if the pad is left open. The bandwidth is reduced approximately 0.4 GHz if the pad is tied to
ground, and increased by approximately 0.4 GHz if the pad is tied to VCC. In 2-wire control mode, the bandwidth
of each channel can be adjusted up or down using the register settings RATE[0..3] in registers 1, 7, 13 and 19
respectively for channels 1, 2, 3 and 4.
7.3.5 Threshold Adjustment
The TIAs have DC offset cancellation to maintain a 50% crossing point; however, the crossing point can be
adjusted using the TRSH pad (pad 41) in pad control mode. No threshold adjustment is applied if the pad is left
open. The crossing point is shifted up approximately 12% if the pad is tied to ground, and it is shifted down
approximately 12% if the pad is tied to VCC. In 2-wire control mode, the crossing point can be adjusted up or
down using register settings TH[0..3] in registers 2, 8, 14 and 20 for channels 1, 2, 3 and 4.
7.3.6 Filter Circuitry
The FILTER pins provide a regulated and filtered VCC for a PIN photodiode bias. The supply voltages for the
transimpedance amplifier have on-chip capacitors but it is recommended to use external filter capacitors as well
for best performance. The input stage has a separate VCC supply (VCCI) which is not connected on chip to the
supply of the limiting and CML stages (VCCO).
7.3.7 AGC and RSSI
The voltage drop across the regulated photodiode FET is monitored by the bias and RSSI control circuit block in
the case where a PIN diode is biased using the FILTER pins.
If the DC input current exceeds a certain level then it is partially cancelled by means of a controlled current
source. This keeps the transimpedance amplifier stage within sufficient operating limits for optimum performance.
12
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Feature Description (continued)
The automatic gain control circuitry adjusts the voltage gain of the AGC amplifier to ensure limiting behavior of
the complete amplifier.
Finally this circuit block senses the current through the FILTER FET and generates a mirrored current that is
proportional to the input signal strength. The mirrored currents are available at the RSSI outputs and can be sunk
to ground (GND) using an external resistor. For proper operation, ensure that the voltage at the RSSI pad does
not exceed VCC - 0.65 V.
7.4 Device Functional Modes
The device has two functional modes of operation: pad control mode and 2-wire interface control mode.
7.4.1 Pad Control
The default mode of operation is pad control and it is recommended that the amplitude be increased to the
500 mVpp setting by bonding AMPL (pad 6) to VCC. If further adjustment is desired as described above, then
the control pads RATE (pad 7), GAIN (pad 8) and TRSH (pad 41) and can be bonded to either ground or VCC.
7.4.2 2-Wire Interface Control
To enable 2-wire interface control I2CENA (pad 5) must be bonded to VCC. In this mode of operation pad control
is not functional and all control is initiated through the 2-wire interface as described in the 2-Wire Interface and
Control Logic section.
7.4.3 2-Wire Interface and Control Logic
The ONET2804T uses a 2-wire serial interface for digital control. For example, the two circuit inputs, SDA and
SCK, are driven by the serial data and serial clock from a microcontroller. Both inputs include 10 kΩ pull-up
resistors to VCC. For driving these inputs, an open drain output is recommended. The 2-wire interface allows
write access to the internal memory map to modify control registers and read access to read out control and
status signals. The ONET2804T is a slave device only which means that it cannot initiate a transmission itself; it
always relies on the availability of the SCK signal for the duration of the transmission. The master device
provides the clock signal as well as the START and STOP commands. It is recommended that the device be
used on a bus with only one master. The protocol for a data transmission is as follows:
1. START command
2. 7 bit slave address (0001100) followed by an eighth bit which is the data direction bit (R/W). A zero indicates
a WRITE and a 1 indicates a READ.
3. 8 bit register address
4. 8 bit register data word
5. STOP command
Regarding timing, the ONET2804T is I2C compatible. The typical timing is shown in Figure 14 and a complete
data transfer is shown in Figure 15. Parameters for Figure 14 are defined in Table 1.
7.4.4 Bus Idle
Both SDA and SCK lines remain HIGH
7.4.5 Start Data Transfer
A change in the state of the SDA line, from HIGH to LOW, while the SCK line is HIGH, defines a START
condition (S). Each data transfer is initiated with a START condition.
7.4.6 Stop Data Transfer
A change in the state of the SDA line from LOW to HIGH while the SCK line is HIGH defines a STOP condition
(P). Each data transfer is terminated with a STOP condition; however, if the master still wishes to communicate
on the bus, it can generate a repeated START condition and address another slave without first generating a
STOP condition.
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Device Functional Modes (continued)
7.4.7 Data Transfer
Only one data byte can be transferred between a START and a STOP condition. The receiver acknowledges the
transfer of data.
7.4.8 Acknowledge
Each receiving device, when addressed, is obliged to generate an acknowledge bit. The transmitter releases the
SDA line and a device that acknowledges must pull down the SDA line during the acknowledge clock pulse in
such a way that the SDA line is stable LOW during the HIGH period of the acknowledge clock pulse. Setup and
hold times must be taken into account. When a slave-receiver does not acknowledge the slave address, the data
line must be left HIGH by the slave. The master can then generate a STOP condition to abort the transfer. If the
slave-receiver does acknowledge the slave address but some time later in the transfer cannot receive any more
data bytes, the master must abort the transfer. This is indicated by the slave generating the not acknowledge on
the first byte to follow. The slave leaves the data line HIGH and the master generates the STOP condition.
SDA
tR
tF
tHDSTA
tBUF
tLOW
tHIGH
SCK
P
S
S
P
tHDSTA
tHDDAT
tSUDAT
tSUSTA
tSUSTO
Figure 14. I2C Timing Diagram
Table 1. Timing Diagram Definitions
MIN
MAX
UNIT
kHz
µs
fSCK
tBUF
SCK clock frequency
400
Bus free time between START and STOP conditions
1.3
0.6
Hold time after repeated START condition. After this period,
the first clock pulse is generated
tHDSTA
µs
tLOW
tHIGH
tSUSTA
tHDDAT
tSUDAT
tR
Low period of the SCK clock
High period of the SCK clock
Setup time for a repeated START condition
Data HOLD time
1.3
0.6
0.6
0
µs
µs
µs
µs
ns
ns
ns
µs
Data setup time
100
Rise time of both SDA and SCK signals
Fall time of both SDA and SCK signals
Setup time for STOP condition
300
300
tF
tSUSTO
0.6
14
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Write Sequence
1
1
1
8
1
8
1
1
7
S
Slave Address
Wr
A
Register Address
A
Data Byte
A
P
Read Sequence
1
1
1
8
1
1
1
1
8
1
1
7
7
S
Slave Address
Wr
A
Register Address
A
S
Slave Address
Rd
A
Data Byte
N
P
Legend
S
Start Condition
Write Bit (bit value = 0)
Read Bit (bit value = 1)
Acknowledge
Wr
Rd
A
Not Acknowledge
Stop Condition
N
P
Figure 15. Data Transfer
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7.5 Register Maps
The register mapping for register addresses 0 (0x00) through 15 (0x0F) are shown in Table 2 through Table 27.
Figure 16 through Figure 41 describes the circuit functionality based on the register settings.
7.5.1 Register 0 (0x00) – Control Settings (offset = 0h) [reset = 0h]
Figure 16. Register 0 (0x00) – Control Settings
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
RESET
PD
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
PWRITE
Table 2. Register 0 (0x00) – Control Settings Field Descriptions
Bit
Field
Type Reset Description
7
RESET
W
0h
Reset registers bit
1 = Resets all registers to default values
0 = Normal operation
6
PD
R/W
0h
Power down bit
1 = Power down all channels (ICC ≈ 4 mA)
0 = Normal operation
5
4
3
2
1
0
Reserved
Reserved
Reserved
Reserved
Reserved
PWRITE
R/W
0h
Parallel write mode bit
1 = Parallel write enabled (write register value to all channels)
0 = Serial write
16
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7.5.2 Register 1 (0x01) – Amplitude and Rate for Channel 1 (offset = 1h) [reset = 0h]
Figure 17. Register 1 (0x01) – Amplitude and Rate for Channel 1
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
RATE3
RATE2
RATE1
RATE0
AMP3
AMP2
AMP1
AMP0
Table 3. Register 1 (0x01) – Amplitude and Rate for Channel 1 Field Descriptions
Bit
Field
Type Reset Description
7
6
5
4
RATE3
RATE2
RATE1
RATE0
R/W
0h
Rate adjustments bits for channel 1
0000 – 21 GHz (default)
0111 – BW decrease of approximately 0.4 GHz
1111 – BW increase of approximately 0.4 GHz
R/W
0h
Amplitude adjustment bits for channel 1
0000 – 0mVpp (default) 1000 – 250mVpp
0001 – 50mVpp
0010 – 100mVpp
0011 – 150mVpp
0100 – 200mVpp
0101 – 250mVpp
0110 – 300mVpp
0111 – 350mVpp
1001 – 300mVpp
1010 – 350mVpp
1011 – 400mVpp
1100 – 450mVpp
1101 – 500mVpp
1110 – 550mVpp
1111 – 600mVpp
3
2
1
0
AMP3
AMP2
AMP1
AMP0
7.5.3 Register 2 (0x02) Mapping – Threshold and Gain for Channel 1 (offset = 2h) [reset = 0h]
Figure 18. Register 2 (0x02) – Threshold and Gain for Channel 1
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
PD
DIS
GAIN1
GAIN0
TH3
TH2
TH1
TH0
Table 4. Register 2 (0x02) – Threshold and Gain for Channel 1
Bit
Field
Type Reset Description
7
PD
R/W
R/W
R/W
0h
0h
0h
Power down bit for channel 1
1 = Power down channel 1
0 = Normal operation
6
DIS
Disable output buffer for channel 1
1 = Disable channel 1 output buffer
0 = Normal operation
Gain adjustment bits for channel 1
5
4
GAIN1
GAIN0
00 – default
01 – NA
10 – medium (–4 dB)
11 – minimum (–8 dB)
R/W
0h
Threshold adjustment bits for channel 1
Minimum positive shift for 0001
Maximum positive shift for 0111
Zero shift for 0000 or 1000
3
2
1
0
TH3
TH2
TH1
TH0
Minimum negative shift for 1001
Maximum negative shift for 1111
7.5.4 Register 3 (0x03) – Reserved
Figure 19. Register 3 (0x03) – Reserved
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
–
–
–
–
–
–
–
–
Table 5. Register 3 (0x03) – Reserved Field Descriptions
Bit
0-7
Field
Type Reset Description
–
Reserved
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7.5.5 Register 4 (0x04) – Reserved
Figure 20. Register 4 (0x04) – Reserved
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
–
–
–
–
–
–
–
–
Table 6. Register 4 (0x04) – Reserved Field Descriptions
Bit
0-7
Field
Type Reset Description
–
Reserved
7.5.6 Register 5 (0x05) – Reserved
Figure 21. Register 5 (0x05) – Reserved
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
–
–
–
–
–
–
–
–
Table 7. Register 5 (0x05) – Reserved Field Descriptions
Bit
0-7
Field
Type Reset Description
–
Reserved
7.5.7 Register 6 (0x06) – Reserved
Figure 22. Register 6 (0x06) – Reserved
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
–
–
–
–
–
–
–
–
Table 8. Register 6 (0x06) – Reserved Field Descriptions
Bit
0-7
Field
Type Reset Description
–
Reserved
7.5.8 Register 7 (0x07) – Amplitude and Rate for Channel 2 (offset = 7h) [reset = 0h]
Figure 23. Register 7 (0x07) – Amplitude and Rate for Channel 2
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
RATE3
RATE2
RATE1
RATE0
AMP3
AMP2
AMP1
AMP0
Table 9. Register 7 (0x07) – Amplitude and Rate for Channel 2 Field Descriptions
Bit
Field
Type Reset Description
7
6
5
4
RATE3
RATE2
RATE1
RATE0
R/W
0h
Rate adjustments bits for channel 2
0000 – 21 GHz (default)
0111 – BW decrease of approximately 0.4 GHz
1111 – BW increase of approximately 0.4 GHz
R/W
0h
Amplitude adjustment bits for channel 2
0000 – 0mVpp (default)
0001 – 50mVpp
1000 – 250mVpp
1001 – 300mVpp
1010 – 350mVpp
1011 – 400mVpp
1100 – 450mVpp
1101 – 500mVpp
1110 – 550mVpp
1111 – 600mVpp
3
2
1
0
AMP3
AMP2
AMP1
AMP0
0010 – 100mVpp
0011 – 150mVpp
0100 – 200mVpp
0101 – 250mVpp
0110 – 300mVpp
0111 – 350mVpp
18
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7.5.9 Register 8 (0x08) Mapping – Threshold and Gain for Channel 1 (offset = 8h) [reset = 0h]
Figure 24. Register 8 (0x08) – Threshold and Gain for Channel 2
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
PD
DIS
GAIN1
GAIN0
TH3
TH2
TH1
TH0
Table 10. Register 8 (0x08) – Threshold and Gain for Channel 2
Bit
Field
Type Reset Description
7
PD
R/W
R/W
R/W
0h
0h
0h
Power down bit for channel 2
1 = Power down channel 2
0 = Normal operation
6
DIS
Disable output buffer for channel 2
1 = Disable channel 2 output buffer
0 = Normal operation
Gain adjustment bits for channel 2
5
4
GAIN1
GAIN0
00 – default
01 – NA
10 – medium (–4 dB)
11 – minimum (–8 dB)
R/W
0h
Threshold adjustment bits for channel 2
Minimum positive shift for 0001
Maximum positive shift for 0111
Zero shift for 0000 or 1000
3
2
1
0
TH3
TH2
TH1
TH0
Minimum negative shift for 1001
Maximum negative shift for 1111
7.5.10 Register 9 (0x09) – Reserved
Figure 25. Register 9 (0x09) – Reserved
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
–
–
–
–
–
–
–
–
Table 11. Register 9 (0x09) – Reserved Field Descriptions
Bit
0-7
Field
Type Reset Description
–
Reserved
7.5.11 Register 10 (0x0A) – Reserved
Figure 26. Register 10 (0x0A) – Reserved
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
–
–
–
–
–
–
–
–
Table 12. Register 10 (0x0A) – Reserved Field Descriptions
Bit
0-7
Field
Type Reset Description
–
Reserved
7.5.12 Register 11 (0x0B) – Reserved
Figure 27. Register 11 (0x0B) – Reserved
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
–
–
–
–
–
–
–
–
Table 13. Register 11 (0x0B) – Reserved Field Descriptions
Bit
0-7
Field
Type Reset Description
–
Reserved
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7.5.13 Register 12 (0x0C) – Reserved
Figure 28. Register 12 (0x0C) – Reserved
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
–
–
–
–
–
–
–
–
Table 14. Register 12 (0x0C) – Reserved Field Descriptions
Bit
0-7
Field
Type Reset Description
–
Reserved
7.5.14 Register 13 (0x0D) – Amplitude and Rate for Channel 3 (offset = Dh) [reset = 0h]
Figure 29. Register 13 (0x0D) – Amplitude and Rate for Channel 3
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
RATE3
RATE2
RATE1
RATE0
AMP3
AMP2
AMP1
AMP0
Table 15. Register 13 (0x0D) – Amplitude and Rate for Channel 3 Field Descriptions
Bit
Field
Type Reset Description
7
6
5
4
RATE3
RATE2
RATE1
RATE0
R/W
0h
Rate adjustments bits for channel 3
0000 – 21 GHz (default)
0111 – BW decrease of approximately 0.4 GHz
1111 – BW increase of approximately 0.4 GHz
R/W
0h
Amplitude adjustment bits for channel 3
0000 – 0mVpp (default)
0001 – 50mVpp
1000 – 250mVpp
1001 – 300mVpp
1010 – 350mVpp
1011 – 400mVpp
1100 – 450mVpp
1101 – 500mVpp
1110 – 550mVpp
1111 – 600mVpp
3
2
1
0
AMP3
AMP2
AMP1
AMP0
0010 – 100mVpp
0011 – 150mVpp
0100 – 200mVpp
0101 – 250mVpp
0110 – 300mVpp
0111 – 350mVpp
7.5.15 Register 14 (0x0E) Mapping – Threshold and Gain for Channel 3 (offset = Eh) [reset = 0h]
Figure 30. Register 14 (0x0E) – Threshold and Gain for Channel 3
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
PD
DIS
GAIN1
GAIN0
TH3
TH2
TH1
TH0
Table 16. Register 14 (0x0E) – Threshold and Gain for Channel 3
Bit
Field
Type Reset Description
7
PD
R/W
R/W
R/W
0h
0h
0h
Power down bit for channel 3
1 = Power down channel 3
0 = Normal operation
6
DIS
Disable output buffer for channel 3
1 = Disable channel 3 output buffer
0 = Normal operation
Gain adjustment bits for channel 3
5
4
GAIN1
GAIN0
00 – default
01 – NA
10 – medium (–4 dB)
11 – minimum (–8 dB)
TH3
TH2
TH1
TH0
R/W
0h
Threshold adjustment bits for channel 3
Minimum positive shift for 0001
Maximum positive shift for 0111
Zero shift for 0000 or 1000
Minimum negative shift for 1001
Maximum negative shift for 1111
3
2
1
0
20
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7.5.16 Register 15 (0x0F) – Reserved
Figure 31. Register 15 (0x0F) – Reserved
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
–
–
–
–
–
–
–
–
Table 17. Register 15 (0x0F) – Reserved Field Descriptions
Bit
0-7
Field
Type Reset Description
–
Reserved
7.5.17 Register 16 (0x10) – Reserved
Figure 32. Register 16 (0x10) – Reserved
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
–
–
–
–
–
–
–
–
Table 18. Register 16 (0x10) – Reserved Field Descriptions
Bit
0-7
Field
Type Reset Description
–
Reserved
7.5.18 Register 17 (0x11) – Reserved
Figure 33. Register 17 (0x11) – Reserved
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
–
–
–
–
–
–
–
–
Table 19. Register 17 (0x11) – Reserved Field Descriptions
Bit
0-7
Field
Type Reset Description
–
Reserved
7.5.19 Register 18 (0x12) – Reserved
Figure 34. Register 18 (0x12) – Reserved
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
–
–
–
–
–
–
–
–
Table 20. Register 18 (0x12) – Reserved Field Descriptions
Bit
0-7
Field
Type Reset Description
–
Reserved
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7.5.20 Register 19 (0x13) – Amplitude and Rate for Channel 4 (offset = 13h ) [reset = 0h]
Figure 35. Register 19 (0x13) – Amplitude and Rate for Channel 4
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
RATE3
RATE2
RATE1
RATE0
AMP3
AMP2
AMP1
AMP0
Table 21. Register 19 (0x13) – Amplitude and Rate for Channel 4 Field Descriptions
Bit
Field
Type Reset Description
7
6
5
4
RATE3
RATE2
RATE1
RATE0
R/W
0h
Rate adjustments bits for channel 4
0000 – 21 GHz (default)
0111 – BW decrease of approximately 0.4 GHz
1111 – BW increase of approximately 0.4 GHz
R/W
0h
Amplitude adjustment bits for channel 4
0000 – 0mVpp (default) 1000 – 250mVpp
0001 – 50mVpp
0010 – 100mVpp
0011 – 150mVpp
0100 – 200mVpp
0101 – 250mVpp
0110 – 300mVpp
0111 – 350mVpp
1001 – 300mVpp
1010 – 350mVpp
1011 – 400mVpp
1100 – 450mVpp
1101 – 500mVpp
1110 – 550mVpp
1111 – 600mVpp
3
2
1
0
AMP3
AMP2
AMP1
AMP0
7.5.21 Register 20 (0x14) Mapping – Threshold and Gain for Channel 4 (offset =14h) [reset = 0h]
Figure 36. Register 20 (0x14) – Threshold and Gain for Channel 4
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
PD
DIS
GAIN1
GAIN0
TH3
TH2
TH1
TH0
Table 22. Register 20 (0x14) – Threshold and Gain for Channel 4
Bit
Field
Type Reset Description
7
PD
R/W
R/W
R/W
0h
0h
0h
Power down bit for channel 4
1 = Power down channel 4
0 = Normal operation
6
DIS
Disable output buffer for channel 4
1 = Disable channel 4 output buffer
0 = Normal operation
Gain adjustment bits for channel 4
5
4
GAIN1
GAIN0
00 – default
01 – NA
10 – medium (–4 dB)
11 – minimum (–8 dB)
TH3
TH2
TH1
TH0
R/W
0h
Threshold adjustment bits for channel 4
Minimum positive shift for 0001
Maximum positive shift for 0111
Zero shift for 0000 or 1000
Minimum negative shift for 1001
Maximum negative shift for 1111
3
2
1
0
7.5.22 Register 21 (0x15) – Reserved
Figure 37. Register 21 (0x15) – Reserved
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
–
–
–
–
–
–
–
–
Table 23. Register 21 (0x15) – Reserved Field Descriptions
Bit
0-7
Field
Type Reset Description
–
Reserved
22
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7.5.23 Register 22 (0x10) – Reserved
Figure 38. Register 21 (0x10) – Reserved
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
–
–
–
–
–
–
–
–
Table 24. Register 21 (0x10) – Reserved Field Descriptions
Bit
0-7
Field
Type Reset Description
–
Reserved
7.5.24 Register 23 (0x17) – Reserved
Figure 39. Register 23 (0x17) – Reserved
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
–
–
–
–
–
–
–
–
Table 25. Register 23 (0x17) – Reserved Field Descriptions
Bit
0-7
Field
Type Reset Description
–
Reserved
7.5.25 Register 24 (0x18) – Reserved
Figure 40. Register 24 (0x18) – Reserved
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
–
–
–
–
–
–
–
–
Table 26. Register 24 (0x18) – Reserved Field Descriptions
Bit
0-7
Field
Type Reset Description
–
Reserved
7.5.26 Register 25 (0x19) – Reserved
Figure 41. Register 25 (0x19) – Reserved
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
–
–
–
–
–
–
–
–
Table 27. Register 25 (0x19) – Reserved Field Descriptions
Bit
0-7
Field
Type Reset Description
–
Reserved
Copyright © 2014–2018, Texas Instruments Incorporated
23
ONET2804T
ZHCSCY8B –JULY 2014–REVISED MARCH 2018
www.ti.com.cn
8 Application and Implementation
8.1 Application Information
Figure 42 shows the ONET2804T being used in a 4 x 25 Gbps fiber optic receiver with pin control and Figure 45
shows the device being used with 2-wire control. The ONET2804T converts the electrical current generated by
the PIN photodiode into a differential output voltage. The FILTER inputs provide a DC bias voltage for the PIN
that is low pass filtered. Because the voltage drop across the photodiode FET is sensed and used by the bias
circuit, the photodiode must be connected to the FILTER pads for the bias to function correctly.
The RSSI outputs are used to mirror the photodiode output current and can be connected via resistors to GND.
The voltage gain can be adjusted for the intended application by choosing the external resistor; however, for
proper operation of the ONET2804T, ensure that the voltage at RSSI never exceeds VCC - 0.65 V. If the RSSI
outputs are not used while operating with internal PD bias they should be left open.
The OUT+ and OUT– pins are internally terminated by 50 Ω pull-up resisters to VCC. The outputs must be AC
coupled, for example by using 0.1 µF capacitors, to the succeeding device.
8.2 Typical Applications
8.2.1 Typical Application, Pad Control
VCC
VCC
AMPL
RATE
TRSH
CHANNEL 1
CHANNEL 2
CHANNEL 4
CHANNEL 3
GAIN
RSSI4
RSSI3
RSSI1
RSSI2
Substrate
750ꢀm Pitch
Photodiode Array
Figure 42. Basic Application Circuit with Pad Control
8.2.1.1 Design Requirements
Table 28. Design Parameters
PARAMETER
Input voltage
Output voltage
VALUE
3.3 V
500 mVPP
24
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ONET2804T
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8.2.1.2 Detailed Design Procedure
The ONET2804T is designed to be used in conjunction with a 750 μm pitch photodiode array or individual
photodiodes and assembled into a receiver optical sub-assembly (ROSA). The TIA will typically be mounted on a
ceramic substrate with etched connections for VCC, RSSI and 100 Ω differential transmission lines for the output
voltage. The photodiode converts the optical input signal into a current that is supplied to the TIA through wire
bonds. The TIA then converts the input current into a voltage and further amplifies the signal. It is recommended
to set the output amplitude to the 500 mVPP level by bonding AMPL (pad 6) to VCC.
The ROSA is typically mounted on a printed circuit board (PCB) with 100 Ω differential transmission lines and RF
connectors such as GPPO or 2.4 mm SMA. When measuring the output from the ROSA mounted on the PCB,
the frequency dependent loss of the transmission lines will impact the frequency response. The loss can be de-
embedded from the measurement to determine the actual frequency response at the output of the ROSA.
Figure 43 shows a typical frequency response without the loss de-embedded and Figure 44 shows a typical
frequency response with the loss de-embedded.
8.2.1.3 Application Curves
6
3
6
3
0
0
-3
-3
-6
-6
-9
-9
-12
-15
-18
-21
-12
-15
-18
-21
0.01
0.1
1
10
100
0.01
0.1
1
10
100
Frequency (GHz)
Frequency (GHz)
C014
C014
Figure 43. Gain vs Frequency (Without De-embedding)
Figure 44. Gain vs Frequency (With De-embedding)
Copyright © 2014–2018, Texas Instruments Incorporated
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ONET2804T
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www.ti.com.cn
8.2.2 Typical Application, 2-Wire Control
VCC
VCC
CHANNEL 1
CHANNEL 2
CHANNEL 4
CHANNEL 3
SCL
SDA
RSSI4
RSSI3
RSSI1
RSSI2
Substrate
750ꢀm Pitch
Photodiode Array
Figure 45. Basic Application Circuit with 2-Wire Control
8.2.2.1 Design Requirements
Refer to Typical Application, Pad Control for the Design Requirements.
8.2.2.2 Detailed Design Procedure
Refer to Typical Application, Pad Control for the Detailed Design Procedure.
8.2.2.3 Application Curves
Refer to Typical Application, Pad Control for the Application Curves.
26
Copyright © 2014–2018, Texas Instruments Incorporated
ONET2804T
www.ti.com.cn
ZHCSCY8B –JULY 2014–REVISED MARCH 2018
9 Power Supply Recommendations
The ONET2804T is designed to operate from an input supply voltage range between 2.97 V and 3.47 V. There
are a total of 8 power supply pads that must be connected for proper operation. VCCI1-4 are used to supply
power to the input transimpedance amplifier stages and VCCO1-4 are used to supply power to the voltage
amplifiers and output buffers. Each amplifier is powered up separately but there are some common internal
connections for support circuitry such as the 2-wire interface. Therefore, if only one channel is being evaluated,
all 8 supply pads must be connected. It is recommended to use two single layer ceramic (SLC) capacitors in the
range of 270 pF to 680 pF for power supply decoupling. VCCI1, VCCI2, VCCO1 and VCCO2 should be bonded
to one capacitor and VCCI3, VCCI4, VCCO3 and VCCO4 should be bonded to the other capacitor. Refer to
Figure 42 and Figure 45 for reference.
Copyright © 2014–2018, Texas Instruments Incorporated
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ONET2804T
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www.ti.com.cn
10 Layout
10.1 Layout Guidelines
Careful attention to assembly parasitics and external components is necessary to achieve optimal performance.
•
Minimize the total capacitance on the IN pad by using a low capacitance photodiode (100fF) and paying
attention to stray capacitances. Place the photodiode close to the ONET2804T die and keep the wire bond
inductance in the range of 300 to 400pH.
•
•
•
Use identical termination and symmetrical transmission lines at the AC coupled differential output pins OUT+
and OUT–.
Use short bond wire connections for the supply terminals VCCIx, VCCOx and GND. Supply voltage filtering is
provided on chip but filtering may be improved by using an additional external capacitor.
The die has backside metal and conductive epoxy must be used to attach the die to ground.
10.2 Layout Example
The IC dimensions are shown in Figure 46, and the pad locations are provided in Table 29. The device is
designed for wire bonding not flip chip.
76 75
74 73 72 71
62 61
59
56
53 52
51 50 49
55 54
48
47
70 69 68 67 66 65 64
63
60
58 57
1
2
3
4
5
6
46
45
44
43
42
41
CHANNEL 1
CHANNEL 2
CHANNEL 4
CHANNEL 3
7
8
40
39
9
38
37
10
19 20
23 24
30 31 32
11 12 13 14 15 16 17 18
21 22
26 27 28 29
33 34 35 36
25
x
3250ꢀm
Figure 46. Chip Dimensions and Pad Locations
Die Thickness: 203 ± 13 μm
Pad Dimensions: 105 μm x 65 μm
Die Size: 3250 μm ±40µm x 1450 μm ±40µm
28
Copyright © 2014–2018, Texas Instruments Incorporated
ONET2804T
www.ti.com.cn
ZHCSCY8B –JULY 2014–REVISED MARCH 2018
Layout Example (continued)
Table 29. Bond Pad Co-ordinates
COORDINATES
PAD
(Referenced to Pad 1)
SYMBOL
VCCO1
TYPE
DESCRIPTION
x (µm)
0
y (µm)
0
1
Supply
3.3V supply voltage
3.3V supply voltage
3.3V supply voltage
3.3V supply voltage
I2C Enable
2
0
–94
VCCO2
VCCI2
VCCI1
I2CENA
AMPL
RATE
GAIN
RSSI1
RSSI2
GND
Supply
3
0
–188
Supply
4
0
–282
Supply
5
0
–376
Digital input
Digital input
Digital input
Digital input
Analog output
Analog output
Supply
6
0
–470
Amplitude control
Rate selection
7
0
–580
8
0
–704
Gain control
9
0
–814
Receive signal strength indicator for channel 1
Receive signal strength indicator for channel 2
Circuit ground
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
0
–908
180
290
400
510
620
720
829
929
1039
1149
1259
1369
1469
1580
1680
1790
1900
2010
2120
2239
2329
2429
2539
2649
2759
2869
3051
3051
3051
3051
3051
3051
3051
3051
–1110
–1110
–1110
–1110
–1110
–1110
–1110
–1110
–1110
–1110
–1110
–1110
–1110
–1110
–1110
–1110
–1110
–1110
–1110
–1110
–1110
–1110
–1110
–1110
–1110
–1110
–908
FILTER1
IN1
Analog output
Analog input
Analog output
Supply
Bias voltage for photodiode 1
TIA input for channel 1
Bias voltage for photodiode 1
Circuit ground
FILTER1
GND
NC
No connect
No connect
Supply
Do not connect
NC
Do not connect
GND
Circuit ground
FILTER2
IN2
Analog output
Analog input
Analog output
Supply
Bias voltage for photodiode 2
TIA input for channel 2
Bias voltage for photodiode 2
Circuit ground
FILTER2
GND
NC
No connect
No connect
Supply
Do not connect
NC
Do not connect
GND
Circuit ground
FILTER3
IN3
Analog output
Analog input
Analog output
Supply
Bias voltage for photodiode 3
TIA input for channel 3
Bias voltage for photodiode 3
Circuit ground
FILTER3
GND
NC
No connect
No connect
Supply
Do not connect
NC
Do not connect
GND
Circuit ground
FILTER4
IN4
Analog output
Analog input
Analog output
Supply
Bias voltage for photodiode 4
TIA input for channel 4
Bias voltage for photodiode 4
Circuit ground
FILTER4
GND
RSSI3
RSSI4
SDA
Analog output
Analog output
Digital in/out
Digital input
Digital input
No connect
Supply
Receive signal strength indicator for channel 3
Receive signal strength indicator for channel 4
2-wire data
–814
–704
–579
SCL
2-wire clock
–470
TRSH
NC
Input threshold control (cross-point)
Do not connect
–376
–282
VCCI4
VCCI3
3.3V supply voltage
–188
Supply
3.3V supply voltage
Copyright © 2014–2018, Texas Instruments Incorporated
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ONET2804T
ZHCSCY8B –JULY 2014–REVISED MARCH 2018
www.ti.com.cn
Layout Example (continued)
Table 29. Bond Pad Co-ordinates (continued)
COORDINATES
(Referenced to Pad 1)
PAD
SYMBOL
TYPE
DESCRIPTION
x (µm)
3051
3051
2888
2799
2699
2599
2499
2410
2322
2228
2139
2050
1950
1850
1750
1661
1572
1477
1388
1299
1199
1099
999
y (µm)
–94
0
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
VCCO3
Supply
Supply
Supply
Supply
3.3V supply voltage
3.3V supply voltage
Circuit ground
VCCO4
GND
140
140
140
140
140
140
140
140
140
140
140
140
140
140
140
140
140
140
140
140
140
140
140
140
140
140
140
140
140
140
GND
Circuit ground
OUT4–
OUT4+
GND
Analog output
Analog output
Supply
Inverted data output for channel 4
Non-inverted data output for channel 4
Circuit ground
GND
Supply
Circuit ground
ADR1
ADR0
GND
Digital input
Digital input
Supply
2-wire address bit 1 control
2-wire address bit 0 control
Circuit ground
GND
Supply
Circuit ground
OUT3-
OUT3+
GND
Analog output
Analog output
Supply
Inverted data output for channel 3
Non-inverted data output for channel 3
Circuit ground
GND
Supply
Circuit ground
NC
No connect
No connect
Supply
Do not connect
NC
Do not connect
GND
Circuit ground
GND
Supply
Circuit ground
OUT2–
OUT2+
GND
Analog output
Analog output
Supply
Inverted data output for channel 2
Non-inverted data output for channel 2
Circuit ground
910
GND
Supply
Circuit ground
821
NC
No connect
Digital input
Supply
Do not connect
728
NRESET
GND
2-wire negative reset
Circuit ground
639
550
GND
Supply
Circuit ground
450
OUT1–
OUT1+
GND
Analog output
Analog output
Supply
Inverted data output for channel 1
Non-inverted data output for channel 1
Circuit ground
350
250
161
GND
Supply
Circuit ground
30
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ONET2804T
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ZHCSCY8B –JULY 2014–REVISED MARCH 2018
11 器件和文档支持
11.1 接收文档更新通知
如需接收文档更新通知，请访问 www.ti.com.cn 网站上的器件产品文件夹。请单击右上角的提醒我 进行注册，即可
每周接收产品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
11.2 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，
并且不一定反映 TI 的观点；请参阅 TI 的 《使用条款》。
TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在
e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。
设计支持
TI 参考设计支持 可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。
11.3 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.4 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
11.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，也
不会对此文档进行修订。如需获取此数据表的浏览器版本，请参阅左侧的导航栏。
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31
PACKAGE OPTION ADDENDUM
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29-Mar-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
ONET2804TY
ACTIVE
DIESALE
Y
0
675
TBD
Call TI
Call TI
-40 to 100
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
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