SN74AXCH1T45DTQR [TI]
单位双电源总线收发器 | DTQ | 6 | -40 to 125;
| 型号： | SN74AXCH1T45DTQR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 单位双电源总线收发器 | DTQ | 6 | -40 to 125 逻辑集成电路 总线收发器 |
| 文件： | 总43页 (文件大小：2588K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN74AXCH1T45
ZHCSJ32C –DECEMBER 2018 –REVISED SEPTEMBER 2020
具有可配置电压转换、三态输出和总线保持输入的
SN74AXCH1T45 1 位双电源总线收发器
DIR 引脚决定信号传播的方向。DIR 引脚配置为高电平
1 特性
时，信号转换由端口 A 流向端口 B。DIR 配置为低电
平时，则由端口B 流向端口A。DIR 引脚以VCCA 为基
准，这意味着它的逻辑高电平和逻辑低电平阈值跟踪
• 完全可配置的双电源轨设计可允许各个端口在
0.65V 至3.6V 的电源电压范围内运行
• 工作温度：–40°C 至+125°C
• 无干扰电源定序
V
CCA 电压。
有源总线保持电路会将未使用或未驱动的输入保持在有
效逻辑状态。不建议在总线保持电路上使用上拉或下拉
电阻器。如果 VCCA 或 VCCB 连上电源，则总线保持电
路分别在 A 端口或 B 端口上始终保持工作状态，与方
向控制引脚的状态无关。
• 总线保持数据输入消除了对外部上拉或下拉电阻的
需求
• 最大静态电流(ICCA + ICCB) 为10µA（最高85°C）
和16µA（最高125°C）
• 从1.8V 转换到3.3 V 时，支持高达500Mbps 的转
换速率
• VCC 隔离特性
该器件完全符合使用 Ioff 电流的部分断电应用的规范要
求。当器件断电时，Ioff 保护电路可确保不从输入、输
出或偏置到特定电压的组合I/O 获取多余电流，也不向
其提供多余电流。
– 如果任何一个VCC 输入低于100mV，则所有
I/O 输出均禁用且处于高阻抗状态
• Ioff 支持局部关断模式运行
• 闩锁性能超过100mA，符合JESD 78 II 类规范的
要求
VCC 隔离特性可确保当 VCCA 或 VCCB 低于 100mV
时，I/O 端口均禁用其输出并进入高阻态。
无干扰电源时序使电源轨能以任何顺序打开或关断，从
而提供强大的电源时序性能。
• ESD 保护性能超过JESD 22 规范要求
– 8000V 人体放电模型
– 1000V 充电器件模型
器件信息
封装(1)
封装尺寸（标称值）
2.90mm × 1.60mm
2.00mm × 1.25mm
1.00mm x 0.80mm
1.40mm x 1.00mm
器件型号
2 应用
SN74AXCH1T45DBV
SN74AXCH1T45DCK
SN74AXCH1T45DTQ
SN74AXCH1T45DRY
SOT-23 (6)
SC70 (6)
X2SON (6)
SON (6)
• 个人电子产品
• 企业与通信
• 无线基础设施
• 楼宇自动化
• 电子销售终端
• 企业级固态硬盘
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
3 说明
VCCA
VCCB
SN74AXCH1T45 是一款采用两个独立可配置电源轨的
单比特位同相总线收发器。VCCA 和 VCCB 电源电压低
至 0.65V 时，该器件可正常工作。A 端口用于跟踪
VCCA，该端口可支持 0.65V 至 3.6V 范围内的任何电
源电压。B 端口用于跟踪 VCCB，该端口也可支持
0.65V 至 3.6V 范围内的任何电源电压。此外，
SN74AXCH1T45 还与单电源系统兼容。
DIR
A
Bus-Hold
B
Bus-Hold
功能方框图
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SCES883
SN74AXCH1T45
ZHCSJ32C –DECEMBER 2018 –REVISED SEPTEMBER 2020
www.ti.com.cn
Table of Contents
8.3 Feature Description...................................................18
8.4 Device Functional Modes..........................................20
9 Application and Implementation..................................21
9.1 Application Information............................................. 21
9.2 Typical Applications.................................................. 21
10 Power Supply Recommendations..............................24
11 Layout...........................................................................24
11.1 Layout Guidelines................................................... 24
11.2 Layout Example...................................................... 24
12 Device and Documentation Support..........................25
12.1 Documentation Support.......................................... 25
12.2 接收文档更新通知................................................... 25
12.3 支持资源..................................................................25
12.4 Trademarks.............................................................25
12.5 静电放电警告.......................................................... 25
12.6 术语表..................................................................... 25
13 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................5
6.4 Thermal Information....................................................5
6.5 Electrical Characteristics.............................................6
6.6 Operating Characteristics: TA = 25°C....................... 13
6.7 Typical Characteristics..............................................14
7 Parameter Measurement Information..........................16
7.1 Load Circuit and Voltage Waveforms........................16
8 Detailed Description......................................................18
8.1 Overview...................................................................18
8.2 Functional Block Diagram.........................................18
Information.................................................................... 26
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision B (June 2020) to Revision C (September 2020)
Page
• Updated ICCA, ICCB, and ICCA + ICCB to reflect updated performance of device..................................................6
Changes from Revision A (January 2019) to Revision B (June 2020)
Page
• 向器件信息表添加了DRY 封装选项...................................................................................................................1
• Added pinout drawing for DRY package.............................................................................................................3
Changes from Revision * (December 2018) to Revision A (January 2019)
Page
• 向器件信息表添加了DBV 和DTQ 封装选项..................................................................................................... 1
• 更新了修订历史记录部分................................................................................................................................... 1
• Added pinout drawings for DBV and DTQ packages .........................................................................................3
• Added DRY package to Pin Configurations........................................................................................................3
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5 Pin Configuration and Functions
VCCA
GND
A
VCCB
DIR
B
1
2
3
6
5
4
VCCA
1
2
3
6
5
4
VCCB
DIR
B
GND
A
图5-2. DCK Package 6-Pin SC70 Top View
图5-1. DBV Package 6-Pin SOT-23 Top View
VCCA
GND
A
1
6
VCCB
DIR
B
1
2
3
6
5
4
VCCA
GND
A
VCCB
DIR
B
2
5
3
4
图5-4. DRY Package 6-Pin SON Transparent Top
图5-3. DTQ Package 6-Pin X2SON Transparent Top
View
View
Pin Functions
PIN
TYPE
DESCRIPTION
NO.
1
NAME
VCCA
GND
A
A-port supply voltage. 0.65 V ≤VCCA ≤3.6 V.
—
2
Ground
—
I/O
I/O
I
3
Input/output A. This pin is referenced to VCCA
Input/output B. This pin is referenced to VCCB
Direction control signal. See for functionality.
.
.
4
B
5
DIR
VCCB
6
B-port supply voltage. 0.65 V ≤VCCB ≤3.6 V.
—
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–50
MAX UNIT
VCCA Supply voltage A
VCCB Supply voltage B
4.2
4.2
V
V
I/O Ports (A Port)
I/O Ports (B Port)
Control Inputs
A Port
4.2
VI
Input Voltage(2)
4.2
V
4.2
4.2
VO
VO
Voltage applied to any output in the high-impedance or power-off state(2)
Voltage applied to any output in the high or low state(2) (3)
V
V
B Port
4.2
A Port
VCCA + 0.2
VCCB + 0.2
B Port
IIK
IOK
IO
Input clamp current
VI < 0
mA
mA
Output clamp current
VO < 0
–50
Continuous output current
Continuous current through VCC or GND
Junction Temperature
50 mA
100 mA
150 °C
150 °C
–50
–100
Tj
Tstg
Storage temperature
–65
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) The input voltage and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
(3) The output positive-voltage rating may be exceeded up to 4.2 V maximum if the output current rating is observed.
6.2 ESD Ratings
VALUE
±8000
±1000
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per JEDEC specification JESD22-C101(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)(1) (2) (3)
MIN
0.65
MAX UNIT
VCCA
VCCB
Supply voltage A
Supply voltage B
3.6
3.6
V
V
0.65
VCCI = 0.65 V - 0.75 V
VCCI = 0.76 V - 1 V
VCCI = 1.1 V - 1.95 V
VCCI = 2.3 V - 2.7 V
VCCI = 3 V - 3.6 V
VCCI x 0.70
VCCI x 0.70
VCCI x 0.65
1.6
Data Inputs
2
VIH
High-level input voltage
V
VCCA = 0.65 V - 0.75 V
VCCA = 0.76 V - 1 V
VCCA = 1.1 V - 1.95 V
VCCA = 2.3 V - 2.7 V
VCCA = 3 V - 3.6 V
VCCI = 0.65 V - 0.75 V
VCCI = 0.76 V - 1 V
VCCI = 1.1 V - 1.95 V
VCCI = 2.3 V - 2.7 V
VCCI = 3 V - 3.6 V
VCCA x 0.70
VCCA x 0.70
VCCA x 0.65
1.6
Control Input (DIR)
Referenced to VCCA
2
VCCI x 0.30
VCCI x 0.30
VCCI x 0.35
0.7
Data Inputs
0.8
VIL
Low-level input voltage
V
VCCA = 0.65 V - 0.75 V
VCCA = 0.76 V - 1 V
VCCA = 1.1 V - 1.95 V
VCCA = 2.3 V - 2.7 V
VCCA = 3 V - 3.6 V
VCCA x 0.30
VCCA x 0.30
VCCA x 0.35
0.7
Control Input (DIR)
Referenced to VCCA
0.8
VI
Input voltage (3)
Output voltage
0
0
0
3.6
V
V
Active State
Tri-State
VCCO
VO
3.6
Input transition rate
100 ns/V
125 °C
Δt/Δv
TA
Operating free-air temperature
–40
(1) VCCI is the VCC associated with the input port.
(2) VCCO is the VCC associated with the output port.
(3) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs.
6.4 Thermal Information
SN74AXCH1T45
DBV
(SOT-23)
DTQ
(X2SON)
THERMAL METRIC(1)
DCK (SC70)
DRY (SON)
UNIT
6 PINS
6 PINS
6 PINS
6 PINS
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
214.0
223.9
327.8
308.3
°C/W
°C/W
Rθ
151.8
150.9
194.9
206.4
JC(top)
RθJB
ψJT
Junction-to-board thermal resistance
93.6
78.1
93.4
75.3
58.2
75.0
248.4
24.1
181.7
42.6
°C/W
°C/W
°C/W
Junction-to-top characterization parameter
Junction-to-board characterization parameter
247.6
180.8
ψJB
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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6.5 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted) (1) (2)
Operating free-air temperature (TA)
UNI
T
PARAMETER
TEST CONDITIONS
VCCA
VCCB
–40°C to 85°C
–40°C to 125°C
MIN TYP(3) MAX
MIN
TYP MAX
VCCO
–0.1
VCCO
–0.1
0.7 V - 3.6 V 0.7 V - 3.6 V
IOH = –100 µA
0.65 V
0.76 V
0.85 V
1.1 V
1.4 V
1.65 V
2.3 V
3 V
0.65 V
0.76 V
0.85 V
1.1 V
1.4 V
1.65 V
2.3 V
3 V
0.55
0.58
0.65
0.85
1.05
1.2
0.55
0.58
0.65
0.85
1.05
1.2
IOH = –50 µA
IOH = –200 µA
IOH = –500 µA
High-level
output voltage
VOH
VI = VIH
V
IOH = –3 mA
IOH = –6 mA
IOH = –8 mA
IOH = –9 mA
IOH = –12 mA
IOL = 100 µA
IOL = 50 µA
IOL = 200 µA
IOL = 500 µA
IOL = 3 mA
1.75
2.3
1.75
2.3
0.7 V - 3.6 V 0.7 V - 3.6 V
0.1
0.1
0.1
0.65 V
0.76 V
0.85 V
1.1 V
1.4 V
1.65 V
2.3 V
3 V
0.65 V
0.76 V
0.85 V
1.1 V
1.4 V
1.65 V
2.3 V
3 V
0.1
0.18
0.2
0.18
0.2
Low-level
output voltage
VOL
VI = VIL
0.25
0.35
0.45
0.55
0.7
0.25
0.35
0.45
0.55
0.7
V
IOL = 6 mA
IOL = 8 mA
IOL = 9 mA
IOL = 12 mA
VI = 0.20 V
VI = 0.23 V
VI = 0.26 V
VI = 0.39 V
VI = 0.49 V
VI = 0.58 V
VI = 0.7 V
VI = 0.8 V
VI = 0.45 V
VI = 0.53 V
VI = 0.59 V
VI = 0.71 V
VI = 0.91 V
VI = 1.07 V
VI = 1.6 V
VI = 2.0 V
0.65 V
0.65 V
4
4
7
0.76 V
0.85 V
1.1 V
1.4 V
1.65 V
2.3 V
3 V
0.76 V
0.85 V
1.1 V
1.4 V
1.65 V
2.3 V
3 V
8
10
10
Bus-hold low
sustaining
current (4)
20
20
IBHL
µA
40
30
55
45
90
80
145
–4
–8
–10
–20
–40
–55
–90
–145
135
–4
–7
–10
–20
–30
–45
–80
–135
0.65 V
0.76 V
0.85 V
1.1 V
1.4 V
1.65 V
2.3 V
3 V
0.65 V
0.76 V
0.85 V
1.1 V
1.4 V
1.65 V
2.3 V
3 V
Bus-hold high
sustaining
IBHH
µA
current (5)
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6.5 Electrical Characteristics (continued)
over operating free-air temperature range (unless otherwise noted) (1) (2)
Operating free-air temperature (TA)
UNI
PARAMETER
TEST CONDITIONS
VCCA
VCCB
–40°C to 85°C
–40°C to 125°C
T
MIN TYP(3) MAX
MIN
40
TYP MAX
0.75 V
0.84 V
0.95 V
1.3 V
0.75 V
0.84 V
0.95 V
1.3 V
40
50
50
65
65
Bus-hold low
IBHLO overdrive
current (6)
105
105
VI = 0 to VCC
µA
1.6 V
1.6 V
150
150
1.95 V
2.7 V
1.95 V
2.7 V
205
205
335
335
3.6 V
3.6 V
480
480
0.75 V
0.84 V
0.95 V
1.3 V
0.75 V
0.84 V
0.95 V
1.3 V
–40
–50
–65
–105
–150
–205
–335
–480
–40
–50
–65
–105
–150
–205
–335
–480
Bus-hold high
IBHHO overdrive
current (7)
VI = 0 to VCC
µA
1.6 V
1.6 V
1.95 V
2.7 V
1.95 V
2.7 V
3.6 V
3.6 V
Control input (DIR): VI =
VCCA or GND
0.65 V - 3.6 V 0.65 V - 3.6 V
0.65 V - 3.6 V 0.65 V - 3.6 V
0.5
4
1
8
–0.5
–4
–1
–8
Input leakage
current
II
µA
A or B Port: Vi = VCCI or
GND
0 V
0 V - 3.6 V
0 V
8
8
8
12
12
12
–8
–8
–12
–12
Partial power A or B Port: Vi or Vo = 0 V -
down current 3.6 V
Ioff
µA
µA
0 V - 3.6 V
0.65 V - 3.6 V 0.65 V - 3.6 V
VCCA supply
current
VI = VCCI
or GND
ICCA
IO = 0
0 V
3.6 V
0 V
–2
–8
3.6 V
2
8
2
8
12
8
0.65 V - 3.6 V 0.65 V - 3.6 V
VCCB supply
current
VI = VCCI
or GND
0 V
3.6 V
0 V
ICCB
IO = 0
IO = 0
µA
3.6 V
–2
–8
ICCA
ICCB
+
Combined
supply current or GND
VI = VCCI
0.65 V - 3.6 V 0.65 V - 3.6 V
10
16 µA
pF
Control input
capacitance
Ci
VI = 3.3 V or GND
3.3 V
3.3 V
3.3 V
0 V
4.3
7.4
4.3
7.4
Data I/O
capacitance,
A Port
VO = 1.65 V DC +1 MHz -16
dBm sine wave
Cio
pF
pF
Data I/O
capacitance,
B Port
VO = 1.65 V DC +1 MHz -16
dBm sine wave
Cio
0 V
3.3 V
7.4
7.4
(1) VCCI is the VCC associated with the input port.
(2) VCCO is the VCC associated with the output port.
(3) All typical data is taken at 25°C.
(4) The bus-hold circuit can sink at least the minimum low sustaining current at VIL(MAX). IBHL should be measured after lowering VI to
GND and then raising it to VIL(MAX).
(5) The bus-hold circuit can source at least the minimum high sustaining current at VIH(MIN). IBHH should be measured after raising VI to
VCC and then lowering it to VIH(MIN).
(6) An external driver must source at least IBHLO to switch this node from low to high.
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(7) An external driver must sink at least IBHHO to switch this node from high to low.
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表6-1. Switching Characteristics, VCCA = 0.7 V
–40°C to
85°C
0.5 181
0.5 181
0.5 181
0.5 181
0.5 152
0.5 152
0.5 170
0.5 170
0.5 343
0.5 343
0.5 326
0.5 326
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
119
119
162
162
152
152
127
127
278
278
257
257
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
85
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
51
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
49
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
52
52
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
65
65
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
152
152
88
A
B
A
A
B
A
B
–40°C to
125°C
85
51
49
Propagation
delay
tpd
ns
ns
ns
–40°C to
85°C
136
136
152
152
102
102
231
231
222
222
96
91
89
88
B
–40°C to
125°C
96
91
89
88
88
–40°C to
85°C
152
152
48
152
152
42
152
152
46
152
152
58
152
152
108
108
193
193
277
277
DIR
DIR
DIR
DIR
–40°C to
125°C
tdis Disable time
–40°C to
85°C
–40°C to
125°C
48
42
46
58
–40°C to
85°C
141
141
194
194
132
132
191
191
134
134
191
191
144
144
197
197
–40°C to
125°C
ten Enable time
–40°C to
85°C
–40°C to
125°C
表6-2. Switching Characteristics, VCCA = 0.8 V
–40°C to
85°C
0.5 162
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
98
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
65
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
33
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
28
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
26
26
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
27
27
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
37
37
A
B
A
A
B
A
B
–40°C to
125°C
0.5 162
98
65
33
28
Propagation
delay
tpd
ns
ns
ns
–40°C to
85°C
0.5
0.5
119
119
98
81
54
45
44
43
42
B
–40°C to
125°C
98
81
54
45
44
43
42
–40°C to
85°C
0.5 107
0.5 107
0.5 160
0.5 160
0.5 268
0.5 268
0.5 257
0.5 257
107
107
117
117
205
205
194
194
107
107
90
107
107
39
107
107
31
107
107
29
107
107
29
107
107
37
DIR
DIR
DIR
DIR
–40°C to
125°C
tdis Disable time
–40°C to
85°C
–40°C to
125°C
90
39
31
29
29
37
–40°C to
85°C
165
165
161
161
90
74
71
70
77
–40°C to
125°C
90
74
71
70
77
ten Enable time
–40°C to
85°C
130
130
125
125
126
126
125
125
132
132
–40°C to
125°C
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表6-3. Switching Characteristics, VCCA = 0.9 V
–40°C to
85°C
0.5 135
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
81
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
54
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
24
24
41
41
79
79
34
34
71
71
96
96
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
18
18
30
30
79
79
27
27
53
53
91
91
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
17
17
26
26
79
79
25
25
48
48
89
89
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
15
15
23
23
79
79
21
21
42
42
89
89
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
18
18
23
23
79
79
23
23
44
44
92
92
A
B
A
A
B
A
B
–40°C to
125°C
0.5 135
81
54
Propagation
delay
tpd
ns
ns
ns
–40°C to
85°C
0.5
0.5
0.5
0.5
86
86
79
79
65
54
B
–40°C to
125°C
65
54
–40°C to
85°C
79
79
DIR
DIR
DIR
DIR
–40°C to
125°C
79
79
tdis Disable time
–40°C to
85°C
0.5 154
0.5 154
0.5 227
0.5 227
0.5 206
0.5 206
111
111
166
166
152
152
85
–40°C to
125°C
85
–40°C to
85°C
131
131
125
125
–40°C to
125°C
ten Enable time
–40°C to
85°C
–40°C to
125°C
表6-4. Switching Characteristics, VCCA = 1.2 V
–40°C to
85°C
0.5
0.5
0.5
0.5
0.5
0.5
95
95
51
51
28
28
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
54
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
41
41
24
24
28
28
78
78
96
96
61
61
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
16
16
16
16
28
28
30
30
43
43
41
41
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
11
11
13
13
28
28
23
23
34
34
37
37
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
9
9
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
8
8
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
8
8
A
B
A
A
B
A
B
–40°C to
125°C
54
Propagation
delay
tpd
ns
ns
ns
–40°C to
85°C
33
11
11
28
28
20
20
30
30
36
36
8
8
B
–40°C to
125°C
33
8
8
–40°C to
85°C
28
28
28
16
16
23
23
35
35
28
28
16
16
22
22
35
35
DIR
DIR
DIR
DIR
–40°C to
125°C
28
tdis Disable time
–40°C to
85°C
0.5 148
0.5 148
0.5 191
0.5 191
105
105
129
129
75
–40°C to
125°C
–40°C to
85°C
–40°C to
125°C
ten Enable time
–40°C to
85°C
0.5
0.5
116
116
–40°C to
125°C
75
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表6-5. Switching Characteristics, VCCA = 1.5 V
–40°C to
85°C
0.5
0.5
0.5
0.5
0.5
0.5
91
91
49
49
20
20
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
45
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
30
30
18
18
20
20
76
76
89
89
43
43
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
13
13
11
11
20
20
28
28
38
38
31
31
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
9
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
8
8
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
6
6
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
6
6
A
B
A
A
B
A
B
–40°C to
125°C
45
9
Propagation
delay
tpd
ns
ns
ns
–40°C to
85°C
28
9
8
6
5
B
–40°C to
125°C
28
9
8
6
5
–40°C to
85°C
20
20
20
21
21
29
29
28
28
20
20
19
19
26
26
27
27
20
20
15
15
20
20
25
25
20
20
14
14
18
18
25
25
DIR
DIR
DIR
DIR
–40°C to
125°C
20
tdis Disable time
–40°C to
85°C
0.5 146
0.5 146
0.5 186
0.5 186
0.5 104
0.5 104
103
103
124
124
58
–40°C to
125°C
–40°C to
85°C
–40°C to
125°C
ten Enable time
–40°C to
85°C
–40°C to
125°C
58
表6-6. Switching Characteristics, VCCA = 1.8 V
–40°C to
85°C
0.5
0.5
0.5
0.5
0.5
0.5
89
89
52
52
17
17
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
44
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
26
26
17
17
17
17
76
76
86
86
37
37
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
11
11
9
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
8
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
7
7
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
6
6
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
5
5
A
B
A
A
B
A
B
–40°C to
125°C
44
8
Propagation
delay
tpd
ns
ns
ns
–40°C to
85°C
26
8
7
6
5
B
–40°C to
125°C
26
9
8
7
6
5
–40°C to
85°C
17
17
17
27
27
35
35
27
27
17
17
20
20
27
27
25
25
17
17
18
18
24
24
24
24
17
17
14
14
19
19
22
22
17
17
13
13
17
17
22
22
DIR
DIR
DIR
DIR
–40°C to
125°C
17
tdis Disable time
–40°C to
85°C
0.5 147
0.5 147
0.5 185
0.5 185
0.5 100
0.5 100
103
103
122
122
54
–40°C to
125°C
–40°C to
85°C
–40°C to
125°C
ten Enable time
–40°C to
85°C
–40°C to
125°C
54
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表6-7. Switching Characteristics, VCCA = 2.5 V
–40°C to
85°C
0.5
0.5
0.5
0.5
0.5
0.5
88
88
65
65
13
13
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
42
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
23
23
15
15
13
13
75
75
85
85
31
31
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
8
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
6
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
6
6
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
5
5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
5
5
A
B
A
A
B
A
B
–40°C to
125°C
42
8
6
Propagation
delay
tpd
ns
ns
ns
–40°C to
85°C
27
8
6
6
5
4
B
–40°C to
125°C
27
8
6
6
5
4
–40°C to
85°C
13
13
13
27
27
33
33
20
20
13
13
19
19
25
25
18
18
13
13
17
17
22
22
17
17
13
13
13
13
17
17
17
17
13
13
12
12
16
16
17
17
DIR
DIR
DIR
DIR
–40°C to
125°C
13
tdis Disable time
–40°C to
85°C
0.5 146
0.5 146
0.5 191
0.5 191
102
102
122
122
50
–40°C to
125°C
–40°C to
85°C
–40°C to
125°C
ten Enable time
–40°C to
85°C
0.5
0.5
95
95
–40°C to
125°C
50
表6-8. Switching Characteristics, VCCA = 3.3 V
–40°C to
85°C
0.5
87
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
42
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
23
23
18
18
12
12
75
75
88
88
30
30
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
8
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
5
5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
4
4
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
4
4
A
B
A
A
B
A
B
–40°C to
125°C
0.5
87
42
8
5
Propagation
delay
tpd
ns
ns
ns
–40°C to
85°C
0.5 154
0.5 154
37
8
6
5
5
4
B
–40°C to
125°C
37
8
6
5
5
4
–40°C to
85°C
0.5
0.5
12
12
12
12
12
26
26
34
34
18
18
12
12
19
19
24
24
16
16
12
12
17
17
21
21
16
16
12
12
13
13
17
17
15
15
12
12
12
12
16
16
15
15
DIR
DIR
DIR
DIR
–40°C to
125°C
12
tdis Disable time
–40°C to
85°C
0.5 147
0.5 147
0.5 275
0.5 275
102
102
129
129
49
–40°C to
125°C
–40°C to
85°C
–40°C to
125°C
ten Enable time
–40°C to
85°C
0.5
0.5
94
94
–40°C to
125°C
49
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6.6 Operating Characteristics: TA = 25°C
PARAMETER
TEST CONDITIONS
VCCA
0.7 V
VCCB
0.7 V
MIN
TYP
2.0
2.0
2.0
2.0
1.9
2.0
2.4
3.0
12
MAX UNIT
0.8 V
0.9 V
1.2 V
1.5 V
1.8 V
2.5 V
3.3 V
0.7 V
0.8 V
0.9 V
1.2 V
1.5 V
1.8 V
2.5 V
3.3 V
0.7 V
0.8 V
0.9 V
1.2 V
1.5 V
1.8 V
2.5 V
3.3 V
0.7 V
0.8 V
0.9 V
1.2 V
1.5 V
1.8 V
2.5 V
3.3 V
0.8 V
0.9 V
1.2 V
1.5 V
1.8 V
2.5 V
3.3 V
0.7 V
0.8 V
0.9 V
1.2 V
1.5 V
1.8 V
2.5 V
3.3 V
0.7 V
0.8 V
0.9 V
1.2 V
1.5 V
1.8 V
2.5 V
3.3 V
0.7 V
0.8 V
0.9 V
1.2 V
1.5 V
1.8 V
2.5 V
3.3 V
Power Dissipation Capacitance
per transceiver (A to B: outputs
enabled)
CL = 0, RL = Open f = 1
MHz, tr = tf = 1 ns
pF
CpdA
12
12
Power Dissipation Capacitance
per transceiver (B to A: outputs
enabled)
12
CL = 0, RL = Open f = 1
MHz, tr = tf = 1 ns
pF
pF
pF
13
13
17
21
12
12
12
Power Dissipation Capacitance
per transceiver (A to B: outputs
enabled)
12
CL = 0, RL = Open f = 1
MHz, tr = tf = 1 ns
13
13
17
21
CpdB
2.1
2.2
2.2
2.2
2.3
2.3
2.6
3.3
Power Dissipation Capacitance
per transceiver (B to A: outputs
enabled)
CL = 0, RL = Open f = 1
MHz, tr = tf = 1 ns
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6.7 Typical Characteristics
50
45
40
35
30
25
20
15
10
CL = 45 pF
CL = 62 pF
CL = 79 pF
CL = 105 pF
CL = 123 pF
CL = 45 pF
CL = 62 pF
CL = 79 pF
CL = 105 pF
CL = 123 pF
45
40
35
30
25
20
15
0.6
0.9
1.2
1.5
1.8 2.1
Supply B (V)
2.4
2.7
3
3.3
0.6
0.9
1.2
1.5
1.8 2.1
Supply B (V)
2.4
2.7
3
3.3
D016
D001
TA = 25°C VCCA = 0.7 V
TA = 25°C VCCA = 0.8 V
图6-1. Typical Propagation Delay of Low-to-High
图6-2. Typical Propagation Delay of Low-to-High
(A to B) vs Load Capacitance
(A to B) vs Load Capacitance
40
30
CL = 45 pF
CL = 62 pF
CL = 79 pF
CL = 105 pF
CL = 123 pF
CL = 45 pF
CL = 62 pF
CL = 79 pF
CL = 105 pF
CL = 123 pF
27
24
21
18
15
12
9
35
30
25
20
15
10
5
6
0.6
0.9
1.2
1.5
1.8 2.1
Supply B (V)
2.4
2.7
3
3.3
0.6
0.9
1.2
1.5
1.8 2.1
Supply B (V)
2.4
2.7
3
3.3
D002
D003
TA = 25°C VCCA = 0.9 V
TA = 25°C VCCA = 1.2 V
图6-3. Typical Propagation Delay of Low-to-High
图6-4. Typical Propagation Delay of Low-to-High
(A to B) vs Load Capacitance
(A to B) vs Load Capacitance
30
27
CL = 45 pF
CL = 45 pF
CL = 62 pF
CL = 79 pF
CL = 105 pF
CL = 123 pF
CL = 62 pF
CL = 79 pF
CL = 105 pF
CL = 123 pF
27
24
21
18
15
12
9
24
21
18
15
12
9
6
6
3
0.6
0.9
1.2
1.5
1.8 2.1
Supply B (V)
2.4
2.7
3
3.3
0.6
0.9
1.2
1.5
1.8 2.1
Supply B (V)
2.4
2.7
3
3.3
D004
D005
TA = 25°C VCCA = 1.5 V
TA = 25°C VCCA = 1.8 V
图6-5. Typical Propagation Delay of Low-to-High
图6-6. Typical Propagation Delay of Low-to-High
(A to B) vs Load Capacitance
(A to B) vs Load Capacitance
27
27
CL = 45 pF
CL = 45 pF
CL = 62 pF
CL = 79 pF
CL = 105 pF
CL = 123 pF
CL = 62 pF
CL = 79 pF
CL = 105 pF
CL = 123 pF
24
21
18
15
12
9
24
21
18
15
12
9
6
6
3
3
0.6
0.9
1.2
1.5
1.8 2.1
Supply B (V)
2.4
2.7
3
3.3
0.6
0.9
1.2
1.5
1.8 2.1
Supply B (V)
2.4
2.7
3
3.3
D007
D006
TA = 25°C VCCA = 3.3 V
TA = 25°C VCCA = 2.5 V
图6-7. Typical Propagation Delay of Low-to-High
图6-8. Typical Propagation Delay of Low-to-High
(A to B) vs Load Capacitance
(A to B) vs Load Capacitance
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50
45
40
35
30
25
20
15
40
CL = 45 pF
CL = 62 pF
CL = 79 pF
CL = 105 pF
CL = 123 pF
CL = 45 pF
CL = 62 pF
CL = 79 pF
CL = 105 pF
CL = 123 pF
35
30
25
20
15
10
0.6
0.9
1.2
1.5
1.8 2.1
Supply A (V)
2.4
2.7
3
3.3
0.6
0.9
1.2
1.5
1.8 2.1
Supply A (V)
2.4
2.7
3
3.3
D008
D009
TA = 25°C VCCA = 0.7 V
TA = 25°C VCCA = 0.8 V
图6-9. Typical Propagation Delay of Low-to-High 图6-10. Typical Propagation Delay of Low-to-High
(B to A) vs Load Capacitance
(B to A) vs Load Capacitance
36
27.5
CL = 45 pF
CL = 45 pF
33
30
27
24
21
18
15
12
9
CL = 62 pF
CL = 79 pF
CL = 105 pF
CL = 123 pF
CL = 62 pF
CL = 79 pF
CL = 105 pF
CL = 123 pF
25
22.5
20
17.5
15
12.5
10
7.5
0.6
0.9
1.2
1.5
1.8 2.1
Supply A (V)
2.4
2.7
3
3.3
0.6
0.9
1.2
1.5
1.8 2.1
Supply A (V)
2.4
2.7
3
3.3
D010
D011
TA = 25°C VCCA = 0.9 V
TA = 25°C VCCA = 1.2 V
图6-11. Typical Propagation Delay of Low-to-High 图6-12. Typical Propagation Delay of Low-to-High
(B to A) vs Load Capacitance
(B to A) vs Load Capacitance
30
25
CL = 45 pF
CL = 45 pF
CL = 62 pF
CL = 79 pF
CL = 105 pF
CL = 123 pF
CL = 62 pF
CL = 79 pF
CL = 105 pF
CL = 123 pF
27
24
21
18
15
12
9
22.5
20
17.5
15
12.5
10
7.5
5
6
0.6
0.9
1.2
1.5
1.8 2.1
Supply A (V)
2.4
2.7
3
3.3
0.6
0.9
1.2
1.5
1.8 2.1
Supply A (V)
2.4
2.7
3
3.3
D012
D013
TA = 25°C VCCA = 1.5 V
TA = 25°C
VCCA = 1.8 V
图6-13. Typical Propagation Delay of Low-to-High 图6-14. Typical Propagation Delay of Low-to-High
(B to A) vs Load Capacitance
(B to A) vs Load Capacitance
30
30
CL = 45 pF
CL = 62 pF
CL = 79 pF
CL = 105 pF
CL = 123 pF
CL = 45 pF
27
24
21
18
15
12
9
CL = 62 pF
CL = 79 pF
CL = 105 pF
CL = 123 pF
25
20
15
10
5
6
3
0.6
0.9
1.2
1.5
1.8 2.1
Supply A (V)
2.4
2.7
3
3.3
0.6
0.9
1.2
1.5
1.8 2.1
Supply A (V)
2.4
2.7
3
3.3
D014
D015
TA = 25°C VCCA = 2.5 V
TA = 25°C VCCA = 3.3 V
图6-15. Typical Propagation Delay of Low-to-High 图6-16. Typical Propagation Delay of Low-to-High
(B to A) vs Load Capacitance (B to A) vs Load Capacitance
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7 Parameter Measurement Information
7.1 Load Circuit and Voltage Waveforms
Unless otherwise noted, all input pulses are supplied by generators having the following characteristics:
• f = 1 MHz
• ZO = 50 Ω
• dv/dt ≤1 ns/V
Measurement Point
2 x VCCO
Open
GND
S1
RL
Output Pin
Under Test
(1)
CL
RL
A. CL includes probe and jig capacitance.
图7-1. Load Circuit
表7-1. Load Circuit Conditions
Parameter
VCCO
RL
CL
S1
VTP
N/A
N/A
N/A
Δt/
Δv
Input transition rise or fall rate
15 pF
15 pF
15 pF
Open
Open
Open
0.65 V –3.6 V
1.1 V –3.6 V
1 MΩ
2 kΩ
20 kΩ
tpd
Propagation (delay) time
0.65 V –0.95
V
15 pF
15 pF
15 pF
2 × VCCO
2 × VCCO
2 × VCCO
0.3 V
0.15 V
0.1 V
3 V –3.6 V
1.65 V –2.7 V
1.1 V –1.6 V
2 kΩ
2 kΩ
2 kΩ
ten, tdis Enable time, disable time
0.65 V –0.95
15 pF
2 × VCCO
0.1 V
20 kΩ
V
15 pF
15 pF
15 pF
GND
GND
GND
0.3 V
0.15 V
0.1 V
3 V –3.6 V
1.65 V –2.7 V
1.1 V –1.6 V
2 kΩ
2 kΩ
2 kΩ
ten, tdis Enable time, disable time
0.65 V –0.95
15 pF
GND
0.1 V
20 kΩ
V
(1)
VCCI
(1)
VCCI
Input A, B
100 kHz
VCCI / 2
VCCI / 2
Input A, B
500 ps/V œ 100 ns/V
0 V
VOH
0 V
VOH
(2)
tpd
tpd
(2)
Output B, A
Ensure Monotonic
Rising and Falling Edge
(2)
VOL
Output B, A
VCCI / 2
VCCI / 2
(2)
VOL
1. VCCI is the supply pin associated with the input port.
2. VOH and VOL are typical output voltage levels that occur
with specified RL, CL, and S1
1. VCCI is the supply pin associated with the input port.
2. VOH and VOL are typical output voltage levels that occur
with specified RL, CL, and S1
图7-3. Input Transition Rise or Fall Rate
图7-2. Propagation Delay
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VCCA
VCCA / 2
DIR
VCCA / 2
GND
(1)
ten
(5)
VCCO
Output A(2)
Output A(3)
VCCO / 2
VOL + VTP
(6)
VOL
tdis
(6)
VOH
VOH - VTP
VCCO / 2
GND
(1)
ten
(5)
VCCO
Output B(2)
Output B(3)
VCCO / 2
VOL + VTP
(6)
VOL
tdis
(6)
VOH
VOH - VTP
VCCO / 2
GND
1. Illustrative purposes only. Enable Time is a calculation as described in the data sheet.
2. Output waveform on the condition that input is driven to a valid Logic Low.
3. Output waveform on the condition that input is driven to a valid Logic High.
4. VCCI is the supply pin associated with the input port
5. VCCO is the supply pin associated with the output port.
6. VOH and VOL are typical output voltage levels that occur with specified RL, CL, and S1
图7-4. Disable and Enable Time
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8 Detailed Description
8.1 Overview
The SN74AXCH1T45 is single-bit, dual-supply, noninverting voltage level translator. Pin A and the direction
control pin are referenced to VCCA logic levels and pin B is referenced to VCCB logic levels, as depicted in . The A
port can accept I/O voltages ranging from 0.65 V to 3.6 V, and the B port can accept I/O voltages from 0.65 V to
3.6 V. A logic high on the DIR pin enables data transmission from A to B and a logic low on the DIR pin enables
data transmission from B to A.
8.2 Functional Block Diagram
VCCA
VCCB
DIR
A
Bus-Hold
B
Bus-Hold
图8-1. Functional Block Diagram
8.3 Feature Description
8.3.1 Standard CMOS Inputs
Standard CMOS inputs are high impedance and are typically modeled as a resistor in parallel with the input
capacitance given in the Electrical Characteristics. The worst case resistance is calculated with the maximum
input voltage, given in the Absolute Maximum Ratings, and the maximum input leakage current, given in the
Electrical Characteristics, using ohm's law (R = V ÷ I).
Signals applied to the inputs need to have fast edge rates, as defined by Δt/Δv in Recommended Operating
Conditions to avoid excessive current consumption and oscillations. If a slow or noisy input signal is required, a
device with a Schmitt-trigger input should be used to condition the input signal prior to the standard CMOS input.
8.3.2 Balanced High-Drive CMOS Push-Pull Outputs
A balanced output allows the device to sink and source similar currents. The high drive capability of this device
creates fast edges into light loads so routing and load conditions should be considered to prevent ringing.
Additionally, the outputs of this device are capable of driving larger currents than the device can sustain without
being damaged. The electrical and thermal limits defined in the Absolute Maximum Ratings must be followed at
all times.
8.3.3 Partial Power Down (Ioff
)
The inputs and outputs for this device enter a high-impedance state when the device is powered down, inhibiting
current backflow into the device. The maximum leakage into or out of any input or output pin on the device is
specified by Ioff in the Electrical Characteristics.
8.3.4 VCC Isolation
The inputs and outputs for this device enter a high-impedance state when either supply is <100mV.
8.3.5 Over-voltage Tolerant Inputs
Input signals to this device can be driven above the supply voltage so long as they remain below the maximum
input voltage value specified in the Recommended Operating Conditions.
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8.3.6 Negative Clamping Diodes
The inputs and outputs to this device have negative clamping diodes as depicted in 图8-2.
CAUTION
Voltages beyond the values specified in the Absolute Maximum Ratings table can cause damage to
the device. The input negative-voltage and output voltage ratings may be exceeded if the input and
output clamp-current ratings are observed.
VCC
Device
Input
Output
Logic
GND
-IIK
-IOK
图8-2. Electrical Placement of Clamping Diodes for Each Input and Output
8.3.7 Fully Configurable Dual-Rail Design
Both the VCCA and VCCB pins can be supplied at any voltage from 0.65 V to 3.6 V, making the device suitable for
translating between any of the voltage nodes (0.7 V, 0.8 V, 0.9 V, 1.2 V, 1.8 V, 2.5 V and 3.3 V).
8.3.8 Supports High-Speed Translation
The SN74AXCH1T45 device can support high data-rate applications. The translated signal data rate can be up
to 500 Mbps when the signal is translated from 1.8 V to 3.3 V.
8.3.9 Bus-Hold Data Inputs
Each data input on this device includes a weak latch that maintains a valid logic level on the input. The state of
these latches is unknown at startup and remains unknown until the input has been forced to a valid high or low
state. After data has been sent through a channel, the latch then maintains the previous state on the input if the
line is left floating. It is not recommended to use pull-up or pull-down resistors together with a bus-hold input, as
it may cause undefined inputs to occur which leads to excessive current consumption.
Bus-hold data inputs prevent floating inputs on this device. The Implications of Slow or Floating CMOS Inputs
application report explains the problems associated with leaving CMOS inputs floating.
These latches remain active at all times, independent of all control signals such as direction control or output
enable.
The Bus-Hold Circuit application report has additional details regarding bus-hold inputs.
Input
Logic
Output
Bus-Hold Latch
图8-3. Simplified Schematic For Device With Bus-Hold Data Inputs
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8.4 Device Functional Modes
表8-1 lists the device functions for the DIR input.
表8-1. Function Table
INPUT(1)
DIR
OPERATION
L
B data to A bus
A data to B bus
H
(1) Input circuits of the data I/Os always are active.
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9 Application and Implementation
Note
以下应用部分的信息不属于TI 组件规范，TI 不担保其准确性和完整性。客户应负责确定 TI 组件是否适
用于其应用。客户应验证并测试其设计，以确保系统功能。
9.1 Application Information
The SN74AXCH1T45 device can be used in level-translation applications for interfacing devices or systems with
one another when they are operating at different interface voltages. The maximum data rate can be up to 500
Mbps when the device translate signals from 1.8 V to 3.3 V.
9.1.1 Enable Times
Calculate the enable times for the SN74AXC1T45 using the following formulas:
tA_en (DIR to A) = tdis (DIR to B) + tpd (B to A)
tB_en (DIR to B) = tdis (DIR to A) + tpd (A to B)
(1)
(2)
In a bidirectional application, these enable times provide the maximum delay time from the time the DIR bit is
switched until an output is expected. For example, if the SN74AXCH1T45 initially is transmitting from A to B,
then the DIR bit is switched; the B port of the device must be disabled (tdis) before presenting it with an input.
After the B port has been disabled, an input signal applied to it appears on the corresponding A port after the
specified propagation delay (tpd). To avoid bus contention care should be taken to not apply an input signal prior
to the output port being disabled (tdis max).
9.2 Typical Applications
9.2.1 Interrupt Request Application
图 9-1 shows an example of the SN74AXCH1T45 being used in an application where a system controller flags
an interrupt request (IRQ) to the CPU. The system controller determines the direction of the IRQ line to either
flag an interrupt to the CPU or allow the CPU to drive data on the line. In this application the controller is
operating at 3.3 V while the CPU can be operating as low as 0.65 V.
The SN74AXCH1T45 device is used to ensure that these devices can communicate at the appropriate voltage
levels. Because the SN74AXCH1T45 does not have an output-enable ( OE) pin, the system designer should
take precautions to avoid bus contention between the CPU and controller when changing directions.
0.7 V
3.3 V
0.1 µF
0.1 µF
VCCA
VCCB
IRQ
Data
IRQ
Data
CPU
Controller
B
SN74AXCH1T45
GND
A
IRQ
Direction
DIR
图9-1. Interrupt Request Application
9.2.1.1 Design Requirements
For this design example, use the parameters listed in 表9-1.
表9-1. Design Parameters
DESIGN PARAMETERS
EXAMPLE VALUES
Input voltage range
0.65 V to 3.6 V
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表9-1. Design Parameters (continued)
DESIGN PARAMETERS
EXAMPLE VALUES
Output voltage range
0.65 V to 3.6 V
9.2.1.2 Detailed Design Procedure
To begin the design process, determine the following:
• Input voltage range
– Use the supply voltage of the device that is driving the SN74AXCH1T45 device to determine the input
voltage range. For a valid logic-high, the value must exceed the high-level input voltage (VIH) of the input
port. For a valid logic low the value must be less than the low-level input voltage (VIL) of the input port.
• Output voltage range
– Use the supply voltage of the device that the SN74AXCH1T45 device is driving to determine the output
voltage range.
9.2.1.3 Application Curve
图9-2. Up Translation at 2.5 MHz (0.7 V to 3.3 V)
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9.2.2 Universal Asynchronous Receiver-Transmitter (UART) Interface Application
图 9-3 shows the SN74AXCH1T45 being used for the two-bit UART interface application. One SN74AXCH1T45
device is used to level shift the voltage and drive the TX from the processor to the GPS Module while a second
SN74AXCH1T45 device is used to drive the TX Data line from the GPS Module to the Processor. Devices with
bus-hold inputs remove the requirement for external pullup resistors to maintain a valid logic level at the input.
0.7 V
3.3 V
0.1 µF
0.1 µF
VCCA
VCCB
RX
TX
B
SN74AXCH1T45
GND
A
DIR
0.1 µF
0.1 µF
Processor
GPS Module
VCCA
VCCB
TX
RX
B
SN74AXCH1T45
GND
A
DIR
图9-3. UART Interface Application
9.2.2.1 Design Requirements
Refer to Design Requirements.
9.2.2.2 Detailed Design Procedure
Refer to Detailed Design Procedure.
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10 Power Supply Recommendations
Always apply a ground reference to the GND pins first. This device is designed for glitch free power sequencing
without any supply sequencing requirements such as ramp order or ramp rate.
This device was designed with various power supply sequencing methods in mind to help prevent unintended
triggering of downstream devices. For more information regarding the power up glitch performance of the AXC
family of level translators, see the Power Sequencing for AXC Family of Devices application report
11 Layout
11.1 Layout Guidelines
To ensure reliability of the device, following common printed-circuit board layout guidelines are recommended:
• Use bypass capacitors on the power supply pins and place them as close to the device as possible.
• Use short trace lengths to avoid excessive loading.
11.2 Layout Example
LEGEND
Polygonal Copper Pour
VIA to Power Plane
VIA to GND Plane (Inner Layer)
VCCB
VCCA
6
5
4
1
2
3
VCCA
GND
A
VCCB
DIR
B
VCCA
From Controller
To System
图11-1. PCB Layout Example
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12 Device and Documentation Support
12.1 Documentation Support
For related documentation see the following:
• Texas Instruments, Evaluate SN74AXC1T45DRL Using a Generic EVM application report
• Texas Instruments, System Considerations For Using Bus-hold Circuits To Avoid Floating Inputsapplication
report
• Texas Instruments, Power Sequencing for the AXC Family of Devices application report
• Texas Instruments, Implications of Slow or Floating CMOS Inputs application report
12.2 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
12.3 支持资源
TI E2E™ 中文支持论坛是工程师的重要参考资料，可直接从专家处获得快速、经过验证的解答和设计帮助。搜索
现有解答或提出自己的问题，获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的使用条款。
12.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
12.5 静电放电警告
静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理
和安装程序，可能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参
数更改都可能会导致器件与其发布的规格不相符。
12.6 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
Copyright © 2021 Texas Instruments Incorporated
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Product Folder Links: SN74AXCH1T45
SN74AXCH1T45
ZHCSJ32C –DECEMBER 2018 –REVISED SEPTEMBER 2020
www.ti.com.cn
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2021 Texas Instruments Incorporated
26
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Product Folder Links: SN74AXCH1T45
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
SN74AXCH1T45DBVR
SN74AXCH1T45DCKR
SN74AXCH1T45DRY2
SN74AXCH1T45DRYR
SN74AXCH1T45DTQR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOT-23
SC70
SON
DBV
DCK
DRY
DRY
DTQ
6
6
6
6
6
3000 RoHS & Green
3000 RoHS & Green
5000 RoHS & Green
5000 RoHS & Green
3000 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
1PNL
1CC
IR
SN
NIPDAU
NIPDAU
NIPDAU
SON
II
X2SON
DM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Jun-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN74AXCH1T45DBVR SOT-23
DBV
DCK
DRY
DRY
DTQ
6
6
6
6
6
3000
3000
5000
5000
3000
180.0
178.0
180.0
180.0
180.0
8.4
9.0
9.5
9.5
9.5
3.2
2.4
3.2
2.5
1.4
1.2
4.0
4.0
4.0
4.0
2.0
8.0
8.0
8.0
8.0
8.0
Q3
Q3
Q3
Q1
Q2
SN74AXCH1T45DCKR
SN74AXCH1T45DRY2
SN74AXCH1T45DRYR
SC70
SON
SON
1.6
1.15
1.65
1.13
0.68
0.7
1.2
SN74AXCH1T45DTQR X2SON
0.94
0.5
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Jun-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
SN74AXCH1T45DBVR
SN74AXCH1T45DCKR
SN74AXCH1T45DRY2
SN74AXCH1T45DRYR
SN74AXCH1T45DTQR
SOT-23
SC70
SON
DBV
DCK
DRY
DRY
DTQ
6
6
6
6
6
3000
3000
5000
5000
3000
210.0
180.0
189.0
189.0
189.0
185.0
180.0
185.0
185.0
185.0
35.0
18.0
36.0
36.0
36.0
SON
X2SON
Pack Materials-Page 2
PACKAGE OUTLINE
DTQ0006A
X2SON - 0.4 mm max height
S
C
A
L
E
1
2
.
0
0
0
PLASTIC SMALL OUTLINE - NO LEAD
1.05
0.95
A
B
PIN 1 INDEX AREA
0.85
0.75
0.40 MAX
(0.1) TYP
C
SEATING PLANE
0.05 C
(0.1)
2X 0.6
0.4
0.05
0.00
(0.027) TYP
3
4
PKG
+0.05
-0.03
0.25
TYP
2
5
(0.08)
0.25
4X
0.17
1
6
PIN 1 ID
(OPTIONAL)
NOTE 5
PKG
0.30
4X
0.22
0.1
0.05
C A B
C
4224056/A 11/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pads must be soldered to the printed circuit board for optimal thermal and mechanical performance.
4. The size and shape of this feature may vary.
5. Features may not exist. Recommend use of pin 1 marking on top of package for orientation purposes.
www.ti.com
EXAMPLE BOARD LAYOUT
DTQ0006A
X2SON - 0.4 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
0.05 MIN
ALL AROUND
TYP
SOLDER MASK OPEING
TYP
SYMM
4X (0.25)
6
(0.25)
TYP
1
4X (0.4)
SYMM
(0.8)
2
5
(0.2) TYP
EXPOSED METAL
CLEARANCE
METAL UNDER
SOLDER MASK
TYP
3
4
(0.2)
TYP
(0.027) TYP
(R0.05) TYP
(0.4)
(0.6)
LAND PATTERN EXAMPLE
SOLDER MASK DEFINED
SCALE:50X
4224056/A 11/2017
NOTES: (continued)
6. This package is designed to be soldered to a thermal pads on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
7. Vias are optional depending on application, refer to device data sheet. If some or all are implemented, recommended via locations are shown.
www.ti.com
EXAMPLE STENCIL DESIGN
DTQ0006A
X2SON - 0.4 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
4X (0.25)
SYMM
(0.027) TYP
(0.279)
TYP
6
1
4X (0.4)
SYMM
(0.8)
5
2
(0.2) TYP
SOLDER MASK
EDGE, 2X
3
METAL UNDER
SOLDER MASK
TYP
4
(0.2)
TYP
(R0.05) TYP
(0.21)
(0.367)
4X (0.6)
SOLDER PASTE EXAMPLE
BASED ON 0.07 mm THICK STENCIL
PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:50X
4224056/A 11/2017
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
PACKAGE OUTLINE
DBV0006A
SOT-23 - 1.45 mm max height
S
C
A
L
E
4
.
0
0
0
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
0.1 C
1.75
1.45
B
1.45 MAX
A
PIN 1
INDEX AREA
1
2
6
5
2X 0.95
1.9
3.05
2.75
4
3
0.50
6X
0.25
C A B
0.15
0.00
0.2
(1.1)
TYP
0.25
GAGE PLANE
0.22
0.08
TYP
8
TYP
0
0.6
0.3
TYP
SEATING PLANE
4214840/C 06/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Body dimensions do not include mold flash or protrusion. Mold flash and protrusion shall not exceed 0.25 per side.
4. Leads 1,2,3 may be wider than leads 4,5,6 for package orientation.
5. Refernce JEDEC MO-178.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0006A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
6X (1.1)
1
6X (0.6)
6
SYMM
5
2
3
2X (0.95)
4
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214840/C 06/2021
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0006A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
6X (1.1)
1
6X (0.6)
6
SYMM
5
2
3
2X(0.95)
4
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214840/C 06/2021
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
GENERIC PACKAGE VIEW
DRY 6
USON - 0.6 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4207181/G
PACKAGE OUTLINE
DRY0006A
USON - 0.6 mm max height
S
C
A
L
E
8
.
5
0
0
PLASTIC SMALL OUTLINE - NO LEAD
1.05
0.95
A
B
PIN 1 INDEX AREA
1.5
1.4
C
0.6 MAX
SEATING PLANE
0.08 C
0.05
0.00
3X 0.6
SYMM
(0.127) TYP
(0.05) TYP
3
4
4X
0.5
SYMM
2X
1
6
1
0.25
6X
0.15
0.4
0.3
0.1
C A B
C
0.05
PIN 1 ID
(OPTIONAL)
0.35
0.25
5X
4222894/A 01/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
DRY0006A
USON - 0.6 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
SYMM
(0.35)
5X (0.3)
6
1
6X (0.2)
SYMM
4X (0.5)
4
3
(R0.05) TYP
(0.6)
LAND PATTERN EXAMPLE
1:1 RATIO WITH PKG SOLDER PADS
EXPOSED METAL SHOWN
SCALE:40X
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
EXPOSED
EXPOSED
METAL
METAL
METAL
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4222894/A 01/2018
NOTES: (continued)
3. For more information, see QFN/SON PCB application report in literature No. SLUA271 (www.ti.com/lit/slua271).
www.ti.com
EXAMPLE STENCIL DESIGN
DRY0006A
USON - 0.6 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
SYMM
(0.35)
5X (0.3)
1
6
6X (0.2)
SYMM
4X (0.5)
4
3
(R0.05) TYP
(0.6)
SOLDER PASTE EXAMPLE
BASED ON 0.075 - 0.1 mm THICK STENCIL
SCALE:40X
4222894/A 01/2018
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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