TFP6422PAP_技术文档

TFP6422, TFP6424

PanelBus DIGITAL TRANSMITTER/VIDEO ENCODER COMBO

SLDS118 – MARCH 2000

Supports UXGA Resolution (Output Pixel

Rates up to 165 MHz)

Simultaneous Composite and S-Video(Y/C

Component) or YPrPb Component Output

Digital Visual Interface (DVI 1.0)

SCART Interface (Simultaneous Composite

and Interlaced RGB Output)

Specification and Video Specifications

1

Compliant

2

Programmable Functionality and I C Serial

2

Seamlessly Interfaces With Intel DVO Port

on Whitney and Future Intel Chipsets

Interface

Four 10-Bit DACs

Supports 24-bit RGB and YCrCb Input

Formats on a 12-Bit Pixel Port

2X Over-Sampling and Optimized Filters for

Luma and Chroma Channels

Supports CCIR-656 YCbCr 4:2:2 Input

Format on an 8-Bit Port

Reduced Power Consumption – 1.8 V

Digital Core and 3.3 V Analog Circuit

Analog Composite Video Out Formats:

Lowest Noise and Best Power Dissipation

Using PowerPAD Packaging

– NTSC-M

– PAL-B,D,G,H,I

– PAL-M

– PAL-N

– PAL-Nc

Advanced Technology Using TIs 0.18 µm

EPIC-5 CMOS Process

TFP6424 Incorporates Macrovision 7.11

Support

description

The Texas Instruments TFP6422 and TFP6424 are PanelBus flat panel display products, part of a

comprehensive family of end-to-end DVI 1.0 compliant solutions. Targeted primarily at digital entertainment /

set-top-box applications, Internet PCs/appliances, PC-to-TV, and connectivity to DVD players and digital

camcorders/cameras, the TFP6422/6424 finds applications in any design requiring a high-speed digital

interface combined with TV-out support.

The scalable (1.1 V to 1.8 V) low-swing digital pixel interface provides a low-EMI and high-speed bus that

connects seamlessly with Intels Digital Video Out (DVO) port, perfectly linking the graphics controller and the

DVI transmitter. The DVI interface supports display resolutions up to UXGA at 165 MHz in 24-bit true color pixel

format.

The TFP6422/6424 combines a high performance DVI transmitter and a high performance NTSC/PAL video

encoder into a single chip in a compact 64-pin TQFP package, providing a cost–effective video output solution

for the most demanding multimedia applications. The video encoder provides advanced horizontal and vertical

scaling for overscan compensation and features a 5-tap adaptive anti–flicker filter. These features combine to

produce high quality display of noninterlaced data on traditional interlaced TV.

The TFP6422/6424 combines PanelBus circuit innovation with TIs advanced 0.18 µm EPIC-5 CMOS

process technology along with TI PowerPAD ultra-low ground inductance package technology to provide a

reliable, low-powered, low noise solution with integrated high-speed digital interface and highest quality TV

output.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

EPIC-5, PowerPAD, and PanelBus are trademarks of Texas Instruments.

Intel is a trademark of Intel Corporation.

Other trademarkes are property of their respective owners.

1. The Digital Visual Interface (DVI) specification is an industry standard developed by the Digital Display Working Group (DDWG) for

high–speed digital connection to digital displays. The TFP6422 and TFP6424 are compliant to the DVI Specification Rev. 1.0. Both are also

compliant to the SMPTE 170M NTSC composite video, and CCIR624/CCIR601 PAL composite video specifications.

2. Programmable functionality includes: arbitrary horizontal and vertical downscaling ratio, sync, black and blank levels, color burst amplitude,

luminance and chrominance gains, luminance delay, subcarrier frequency, overscan compensation, flicker removal and SCH.

PRODUCT PREVIEW information concerns products in the formative or

design phase of development. Characteristic data and other

specifications are design goals. Texas Instruments reserves the right to

change or discontinue these products without notice.

1

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PanelBus DIGITAL TRANSMITTER/VIDEO ENCODER COMBO

SLDS118 – MARCH 2000

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49

DV

DVSS

1

2

3

4

5

6

7

8

9

10

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

DD

BLANK

AV

CC

V

VS/FID

HS/CS/GPIO1

B/Pb

REF

HSYNC

VSYNC

DVSS

C/R/Pr

AVSS

INT1/CLKOUT

DVDDQ

Y/G

INT0/CBARE

A0

CVBS

AFADJ

COMP

HTPLG 11

DV 12

RST 13

AV

CC

PVSS

PV

14

15

16

SDA

SCL

DD

XTALO

XTALI

DVSS

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

2

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TFP6422, TFP6424

PanelBus DIGITAL TRANSMITTER/VIDEO ENCODER COMBO

SLDS118 – MARCH 2000

functional block diagram

BLANK

LTVDATA(11:0)

CLKOUT(1:0)

Video Input

T.M.D.S. Transmit

Serializer

Digital Input I/F

Encoder

TX2±

TX1±

TX0±

TXC±

Serializer

Control

DVO

I/F

Vertical

Scaler

and

Deflicker

Filter

RGB-YUV

Conversion

Resync

FIFO

SCL

SDA

I2C

I/F

Timing and Sync

Encoder Data

XTAL1

XTAL2

Closed

Caption

Macro

Vision

PLL

Generation

Data

Select

Luma Stage

CVBS

B/Pb

C/R/Pr

Y/G

10-Bit

DAC

Luma

Interpolation

Filter

Y

Luma

Color

Bar

Luma

Delay

Luma

Gain/Shape

DAC

Mux

10-Bit

DAC

Gain U

Gain V

CCIR656

Decode

Cross

Color

Filter

Sin/Cos

LUT

YUV-

RGB

10-Bit

DAC

Chroma Stage

Composite

Chroma

Low Pass

Filter

(1.3 MHz)

(1x)

Chroma

Interpol

Filter #2

(2x)

Chroma

Gain/Shape

(1x, 2x)

UV

Color

Bar

Interpol

Filter #1

(1x, 2x)

U

V

10-Bit

DAC

Quadrature

Modulation

TVCLKIN/INT

TVHSYNC

TVVSYNC

3

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TFP6422, TFP6424

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SLDS118 – MARCH 2000

digital video out (DVO) interface diagram

TFP6422/6424

DVI

Graphic

TV-Out

Intel-Based

DVO I/F

Terminal Functions

TERMINAL

I/O

DESCRIPTION

POWER

RAIL

NAME

NO.

Digital Video Input Port

INT0/CBARE DV

9

I/O Interrupt for hot plug support (Output)

DD

INT0 is an open drain signal and an assertion low interrupt request informing the graphics

controller of Flat Panel/TV/secondary monitor hot–plug or hot unplug event. For normal

applications, a 10K pull-up resistor must be connected between this pin and DV

.

CC

Color bar display enable at reset (Input)

Fordiagnosticspurpose,thispincanbepulleddownviaapulldownresistortoenablethevideo

encoder to output the color bar test signal upon the completion of reset. The state of this pin

is sensed immediately after the low-to-high transition of RST. If the state of this pin is LOW,

the video encoder will be enabled and output the color bar test signal. If the state of this pin

is HIGH, DVI transmitter will be enabled and analog video will be disabled.

CLKIN[1:0]

DV

57, 56

I

TFP6422/6424 uses CLKIN [1:0] to clock in video data and timing control signals. When used

as a differential pair, CLKIN0 connects to the positive end and CLKIN1 connects to the

negativeend. For single–ended clock input, the clock is connected to CLKIN0 and a reference

voltage of VDDQ/2 must be connected to CLKIN1.

DD

During TV mode, CLKIN [1:0] must be connected to CLKOUT or a clock signal derived from

the graphics controller.

During LCD mode, the graphics controller should use internal DOT clock to generate

CLKIN[1:0].

4

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SLDS118 – MARCH 2000

Terminal Functions (Continued)

TERMINAL

POWER

RAIL

I/O

DESCRIPTION

NAME

NO.

INT1/CLKOUT

DV

7

O

This pin can be programmed as clock or interrupt output.

DD

Clock out – The internal TV encoder PLL drives CLKOUT. The frequency of CLKOUT is

programmable and depends on TV standards, and the desired horizontal and vertical

overscan compensation ratios. An external graphic controller may use CLKOUT directly to

source video pixel data to DATA[11:0] bus and to clock out timing control signals HSYNC,

VSYNC and BLANK, or alternatively, use CLKOUT as a reference signal to generate a clock

internally to clock out the video pixel data and timing control. In the first case, the CLKOUT

should be connected directly to CLKIN. In the second case, the clock signal generated by the

graphics controller should be connected to CLKIN[1:0] if the clock is a differential pair, or

CLKIN[0] if the clock is single-ended with CLKIN1 connected to VDDQ/2.

Interrupt for hot plug support

INT1 is an open drain signal and an assertion low interrupt request informing the graphics

controller of Flat Panel/secondary monitor hot–plug or hot unplug event. When this pin is

programmed as CLKOUT, INT0# is used for hot plug support.

HSYNC

VSYNC

DV

4

5

2

I

Horizontal sync input

DD

Vertical sync input

BLANK

Blanking signal – BLANK is low during blanking interval and high during active video.

DATA[11:0] is the pixel port

DATA[11:0]

49–54,

59–64

Reference Crystal

XTALO

PVDD

34

33

I

Terminal for reference crystal for the internal video encoder PLL or external reference

oscillator input.

XTALI

Terminal for reference crystal for the internal video encoder PLL. Leave unconnected if an

external oscillator is connected to XTAL0.

DVI Output

TX2+

TVDD

28

A

Red channel positive transmitter output – positive side of red channel T.M.D.S. low voltage

signal differential output pair. Red channel transmits red pixel data in active display and 00

control bits in blank.

TX2–

TX1+

TVDD

27

25

A

Red channel negative transmitter output – Negative side of red channel T.M.D.S. low voltage

signal differential output pair.

Green channel positive transmitter output – Positive side of green channel T.M.D.S. low

voltage signal differential output pair. Green channel transmits green pixel data in active

display and 00 control bits in blank.

TX1–

TX0+

TVDD

24

22

A

Green channel negative transmitter output – Negative side of green channel T.M.D.S. low

voltage signal differential output pair.

Blue channel positive transmitter output – Positive side of blue channel T.M.D.S. low voltage

signal differential output pair. Blue channel transmits blue pixel data in active display and

HSYNC, VSYNC control signals in blank.

TX0–

TVDD

21

30

31

19

A

Bluechannel negative transmitter output – Negative side of blue channel T.M.D.S. low voltage

signal differential output pair.

TXC+

TXC–

TFADJ

Clock positive transmitter output – Positive side of reference clock T.M.D.S. low voltage signal

differential output pair.

Clock negative transmitter output – Negative side of reference clock T.M.D.S. low voltage

signal differential output pair.

T.M.D.S. drivers full scale adjust control

A 2 kΩ resistor must be connected between this pin and TVSS.

5

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SLDS118 – MARCH 2000

Terminal Functions (Continued)

TERMINAL

I/O

DESCRIPTION

POWER

RAIL

NAME

NO.

Analog Video Out

CVBS

Y/G

AVCC

40

41

A

Analog composite video output

Analog luminance video output

Analog green output

C/R/Pr

AVCC

43

A

Analog chrominance output

Analog red output

Analog Pr output

B/Pb

AVCC

44

38

39

A

Analog blue output

Component Pb output

COMP

AFADJ

Compensation for the internal reference amplifier A 0.1 µF capacitor should be connected

between this pin and AVCC.

Full scale adjust control. A 920-Ω resistor should be connected between this pin and AVSS to

control the full-scale output current on the analog outputs.

2

I C Interface and Miscellaneous

2

I/O I C serial clock input maximum. Clock rate of 400 kHz. Open drained I/O.

SCL

DV

15

CC

2

I/O I C Serial data line open drained I/O.

SDA

DV

14

13

11

10

45

CC

RST

I

Reset signal active low.

HTPLG

A0

DVI/P&D/DFP hot plug detect input

2

I C slave address select

HS/CS/GPIO1

AVCC

I/O This signal is only active when RGB analog output is enabled.

Digital horizontal sync output – This is the HSYNC signal that connects to the VGA connector.

Digital composite sync output – Composite HSYNC and VSYNC. The polarity of this signal is

programmable when used for HS/CS.

General-purpose I/O #1 – Second general–purpose I/O. This pin has an internal weak

pull–down of 1 MΩ (TBD). With GPIO1 as an input, use an external 10 kΩ resistor to pull up or

down to set the state of this pin.

VS/FID

AVCC

46

O

Digital vertical sync output

When the analog RGB video output is enabled this signal is the VSYNC that connects to the

VGA connector.

Digital field ID

When the analog video output is interlaced (composite video, S–video, or interlaced

component video), this signal indicates if the current field is ODD (first field) or EVEN (second

field).

The polarity of this signal is programmable.

GPIO0

TEST

DV

18

17

I/O General-purpose I/O #0

CC

First general–purpose I/O. This pin has an internal weak pull-down of 1 MΩ (TBD). With

GPIO0 as an input, use an external 10 kΩ resistor to pull up or down to set the state of this pin.

I

Test Mode Enable

This pin must be tied to LOW for normal mode of operation. Connecting this pin to HIGH puts

TFP6422/6424 in test mode.

Digital Video Input Port Voltage Reference

DVDDQ/2

V

3

A

Digitalvideoinputportvoltagereference. –Setstheswitchingthresholdofallthesignalslisted

in Digital Video Input Port section of this table. VREF must be set to DVDDQ/2, where DVDDQ

is the swing of the signals. DVDDQ ranges from 1.1 V to 1.8 V.

REF

6

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TFP6422, TFP6424

PanelBus DIGITAL TRANSMITTER/VIDEO ENCODER COMBO

SLDS118 – MARCH 2000

Terminal Functions (Continued)

TERMINAL

POWER

I/O

DESCRIPTION

NAME

NO.

RAIL

Power and Ground

DV

DD

DVSS

1.8 V

0.0 V

1, 55

P

Digital Power

Digital ground

6, 16,

G

48, 58

DV

3.3 V

1.8 V

0.0 V

12

P

G

Digital power

CC

TVDD

TVSS

23, 29

Analog power for the DVI output drivers

Analog ground for the DVI output drivers

20, 26,

32

AVCC

AVSS

PVDD

PVSS

3.3 V

0.0 V

1.8 V

0.0 V

37, 47

42

P

G

P

Analog power for the video DACs

Analog ground for the video DACs

Power for PLLs

35

36

G

Ground for PLLs

†

absolute maximum ratings over operating free-air temperature (unless otherwise noted)

External DACs load resistance, RLdac . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 Ω to open circuit

External T.M.D.S. termination resistance, RLtmds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 Ω to open circuit

External AFADJ resistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 Ω to open circuit

External TFADJ resistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 kΩ to open circuit

Operating free-air temperature range, T

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C

A

Storage temperature range, T

Maximum total power dissipation, P . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 W

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C

stg

D

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

recommended operating conditions (ALL DATA PRELIMINARY)

MIN

1.7

NOM

1.8

3.3

1.8

3.3

1.8

MAX

1.9

UNIT

V

Digital supply voltage, DV

DD

3.13

1.0

3.47

1.9

V

CC

Digital supply voltage, DVDDQ

Analog supply voltage, AVCC

Analog supply voltage, TVDD

Analog supply voltage, PVDD

V

3.13

1.7

3.47

1.9

V

1.7

1.9

V

VREF–

100 mv

Digital low–level input voltage, DV

V

(Scalable with VREF)

V

DD IL

VREF+

100 mv

V

DD IH

Digital low–level input voltage, DV

V

0.8

V

CC IL

V

CC IH

Digital supply current, DVDD

Digital supply current, DVDDQ

Analog supply current, TVDD

Analog supply current, AVCC

Analog supply voltage, PVDD

80

0

DVI 1280x1024 Resolution 60 Hz Refresh Rate

120

6

mA

100

7

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TFP6422, TFP6424

PanelBus DIGITAL TRANSMITTER/VIDEO ENCODER COMBO

SLDS118 – MARCH 2000

recommended operating conditions (ALL DATA PRELIMINARY) (continued)

MIN

NOM

MAX

150

20

UNIT

Digital supply current, DV

DD

Digital supply current, DVDDQ

Analog supply current, TVDD

Analog supply current, AVCC

Analog supply voltage, PVDD

Simultaneous composite and S–video

mA

0

135

100

150

20

Digital supply current, DV

DD

Digital supply current, DVDDQ

Analog supply current, TVDD

Analog supply current, AVCC

Analog supply voltage, PVDD

Composite video

mA

0

45

100

150

20

Digital supply current, DV

DD

Digital supply current, DVDDQ

Analog supply current, TVDD

Analog supply current, AVCC

Analog supply voltage, PVDD

S–video

0

90

100

150

20

Digital supply current, DV

DD

Digital supply current, DVDDQ

Analog supply current, TVDD

Analog supply current, AVCC

Analog supply voltage, PVDD

Interlaced YPrPb component video

SCART (simultaneous composite and interlaced RGB)

Progressive RGB

0

135

100

150

20

Digital supply current, DV

DD

Digital supply current, DVDDQ

Analog supply current, TVDD

Analog supply current, AVCC

Analog supply voltage, PVDD

0

180

100

80

Digital supply current, DV

DD

Digital supply current, DVDDQ

Analog supply current, TVDD

Analog supply current, AVCC

Analog supply voltage, PVDD

0

135

10

Digital supply current, DV

150

20

DD

Digital supply current, DVDDQ

Analog supply current, TVDD

Analog supply current, AVCC

Analog supply voltage, PVDD

Simultaneous composite and interlaced YPrPb component

Video

0

180

100

10

Digital supply current, DV

DD

Digital supply current, DVDDQ

Analog supply current, TVDD

Analog supply current, AVCC

Analog supply voltage, PVDD

0

Power Down

0

10

Reference voltage, V

REF

0.52

45

0.9

37.5

50

0.95

V

Ω

External DAC load resistor, Rldac, double termination

External T.M.D.S. termination resistor

External AFADJ resistor

55

2.6

70

Ω

TBD

2

Ω

External TFADJ resistor

1.4

0

kΩ

pF

°C

Output load resistance, DAC, C

25

L

Operating free-air temperature, T

A

8

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TFP6422, TFP6424

PanelBus DIGITAL TRANSMITTER/VIDEO ENCODER COMBO

SLDS118 – MARCH 2000

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)

dc digital I/O specifications

PARAMETER

TEST CONDITIONS

MIN

2

TYP

MAX

UNIT

V

†

‡

V

High level digital input voltage

DV

IH

DD

0.8

†

Low level digital input voltage

0

V

IL

ST = High,

ST = Low,

ST = High,

ST = Low,

V

OH

V

OH

V

OL

V

OL

= 2.4 V

= 0.8 V

TBD

-10

18

9

TBD

10

I

mA

High level output drive current

OH

18

9

‡

I

mA

Low level output drive current

Hi-Z output current

OL

PD = Low or PDO = Low

µA

OZ

V

I

= –18 mA

= 18 mA

= –18 mA

= 18 mA

DGND-0.8

DGND+0.8

DGND-0.8

DGND+0.8

IK(–)

CL

Input clamp voltage

IK(+)

V

OK(_)

OK(+)

Output clamp voltage

†

‡

Digital inputs are labeled DI in I/O column of Terminal Functions Table.

Digital outputs are labeled DO in I/O column of Terminal Functions Table.

dc specifications

PARAMETER

TEST CONDITIONS

MIN

150

AV –300

TYP

MAX

1200

AV –37

UNIT

mv

V

ID

V

IC

V

I

Input differential voltage (see Note 1)

Input common mode voltage (see Note 1)

Open circuit analog input voltage

mv

DD

AV –10

DD

AV +10

DD

mv

Pixel Rate = 56 MHz

2-pix/clock

I

Normal 2-pix/clock power supply current (see Note 2)

TBD

mA

DD(2PIX)

I

Power down current (see Note 3)

PD = Low

µA

PD

NOTES: 1. Specified as dc characteristic with no overshoot or undershoot.

2. Alternating 2-pixel black/2-pixel white pattern. ST = high, STAG = high, QE[23:0] and QO[23:0] C = 10 pF.

L

3. Analog inputs are open circuit (transmitter is disconnected from TFP201).

9

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SLDS118 – MARCH 2000

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted) (continued)

ac specifications

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

†

V

Differential input sensitivity

150

1560 mV

ID

(1)

(2)

p-p

‡

t

Analog input intra-pair (+ to -) differential skew time

Analog Input inter-pair or channel-to-channel skew time

0.4

1

t

bit

§

t

pix

¶

t

Worse case differential input clock jitter tolerance

TBD

ns

(3)

ST = Low,

ST = High, C =10 pF

C =5 pF

2.9

3.1

L

#, ||

Rise time of data and control signals

t

r(1)

L

ST = Low,

ST = High, C =10 pF

C =5 pF

2.84

3.2

L

#, ||

Fall time of data and control signals

t

ns

f(1)

L

ST = Low,

ST = High, C =10 pF

C =5 pF

L

#

Rise time of ODCK clock

TBD

r(2)

ST = Low,

ST = High, C =10 pF

C =5 pF

L

#

Fall time of ODCK clock

f(2)

Setup time, data and control signal to falling edge of ODCK ST = Low,

||

C =5 pF

L

TBD

su(1)

h(1)

su(2)

h(2)

(OCK_INV = low)

ST = High, C =10 pF

Hold time, data and control signal to falling edge of ODCK

ST = Low,

ST = High, C =10 pF

C =5 pF

L

||

(OCK_INV = low)

Setup time, data and control signal to rising edge of ODCK

||

ST = Low,

ST = High, C =10 pF

C =5 pF

L

(OCK_INV = high)

Hold time, data and control signal to rising edge of ODCK

ST = Low,

ST = High, C =10 pF

L

C =5 pF

L

||

(OCK_INV = high)

ODCK frequency

ODCK duty-cycle

PIX = Low (1-PIX/CLK)

PIX = High (2-PIX/CLK)

25

12.5

40%

112

56

f

MHz

(ODCK)

50%

60%

9

t

Propagation delay time from PD low to Hi-Z outputs

Propagation delay time from PDO low to Hi-Z outputs

Delay time from PD rising edge to inputs active

Pulse duration, minimum time PD low

ns

d(1)

d(2)

d(3)

d(4)

t(1)

9

Transition time between DE transition to SCDT low

Transition time between DE transition to SCDT high

1e6

t

pix

1280

t

t(2)

STAG = Low,

Pixs = High

t

Delay time, ODCK latching edge to QE[23:0] data output

0.25

t

s(1)

pix

†

‡

§

Specified as ac parameter to include sensitivity to overshoot, undershoot and reflection.

t

is 1/10 the pixel time, tpix

is the pixel time defined as the period of the RxC input clock. The period of ODCK is equal to t

bit

pix

in 1-pixel/clock mode or 2t

when in

pix

2-pixel/clock mode.

¶

#

||

Measured differentially at 50% crossing using ODCK output clock as trigger.

Rise and fall times measured as time between 20% and 80% of signal amplitude.

Data and control signals are : QE[23:0], QO[23:0], DE, HSYNC, VSYNC and CTL[3:1]

Link active or inactive is determined by amount of time detected between DE transitions. SCDT indicates link activity.

10

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TFP6422, TFP6424

PanelBus DIGITAL TRANSMITTER/VIDEO ENCODER COMBO

SLDS118 – MARCH 2000

functional description

overview

TFP6422 and TFP6424 integrates multiple video output interfaces in a single device in a compact 64-pin TQFP

package. It supports all the most commonly used PC and consumer video standards as follows:

DVI

Composite video

–

NTSC–M

PAL–B,D,G,H,I

PAL–M

PAL–N

PAL–Nc

S–Video

SCART interface

YPrPb Component video

Analog RGB output

TFP6422 and TFP6424 integrates video encoder, color space converter, horizontal and vertical scaler,

flicker-reduction filter, two PLLs, four DACs, DVI encoder, and three differential pairs of T.M.D.S. drivers. A

dedicated high-speed low-pin count video pixel port transfers high-bandwidth digital video data from a graphics

controller or other digital video source to the TFP6422 and TFP6424. All video modes share the same video

pixel port.

The TFP6422 and TFP6424 is versatile and highly programmable to provide maximum flexibility for the users.

2

An I C host interface is provided to program and configure the TFP6422 and TFP6424.

The TFP6424 also conforms to the Macrovision 7.11 copy protection scheme.

default modes after reset

Depending on the state of the INT0/CBARE pin, TFP6422 and TFP6424 is reset to one of two default modes.

If INT0/CBAREis pullup, TFP6422 and TFP6424 will be initialized to be in DVI transmitter mode. If INT0/CBARE

pin is pull-down, TFP6422 and TFP6424 will be initialized to be in simultaneous composite and S-video out

mode, and will display an internally generated color bar.

2

I C interface

2

The I C interface is used to access the internal TFP6422 and TFP6424 registers. This two–pin interface

2

consists of one clock line, SCL, and one serial data line, SDA. The basic I C access cycles are shown in

Figures 1 and 2.

SDA

SCL

Start Condition (S)

Stop Condition (P)

2

Figure 1. I C Stop and Stop Conditions

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2

I C interface (continued)

The basic access cycle consists of the following:

A start condition

A slave address cycle

A subaddress cycle

Any number of data cycles

A stop condition

The start and stop conditions are shown in Figure 2. The high to low transition of SDA while SCL is high defines

the start condition. The low to high transition of SDA while SCL is high defines the stop condition. Each cycle,

data or address, consists of 8 bits of serial data followed by one acknowledge bit generated by the receiving

device. Thus, each data/address cycle contains 9 bits as shown in Figure 2.

1

2

3

4

5

6

7

8

9

1

2

3

4

5

6

7

8

9

1

2

3

4

5

6

7

SCL

SDA

Stop

MSB

Slave Address

Sub Address

2

Data

Figure 2. I C Access Cycles

2

Following a start condition, each I C device decodes the slave address. The TFP6422 and TFP6424 responds

with an acknowledge by pulling the SDA line low during the ninth clock cycle if it decodes the address as its

address. During subsequent subaddress and data cycles the TFP6422 and TFP6424 responds with

acknowledge as shown in Figure 3. The subaddress is auto-incremented after each data cycle.

The transmitting device must not drive the SDA signal during the acknowledge cycle so that the receiving device

may drive the SDA signal low. The not acknowledge, A, condition is indicated by the master by keeping the SDA

signal high just before it asserts the stop, P, condition. This sequence terminates a read cycle as shown in

Figure 4.

The slave address consists of 7 bits of address along with 1 bit of read/write information as shown below in

Figures 3 and 4. For the TFP6422 and TFP6424, the possible slave addresses (including the r/w bit) are 0x40,

0x42 for write cycles and 0x41 and 0x43 for read cycles. Refer to register description, for additional base

address information.

S

Slave Address

W

A

Sub Address

A

Data

A

Data

A

P

From Transmitter

From Receiver

A

S

P

/

Acknowledge

Start Condition

Stop Condition

Not Acknowledge (SDA A High)

2

Figure 3. I C Write Cycle

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functional description (continued)

S

Slave Address

W

R

A

Sub Address

A

P

Data

A

Data

/A

P

A

S

P

/

Acknowledge

Start Condition

Stop Condition

From Transmitter

From Receiver

Not Acknowledge (SDA A High)

2

Figure 4. I C Read Cycle

video port

The TFP6422/6424 Video Port is a low pin count, high-speed digital interface for a variety of digital video

formats. The video port consists of a 12-bit data bus (DATA[11:0]), horizontal timing signal (HSYNC), vertical

timing signal (VSYNC), blanking control (BLANK), clock signals (CLKOUT, CLKIN0 and CLKIN) and interrupt

request signals (INT0 and INT1). To reduce the pin count and the board space, a compact 12-bit pixel bus is

used. The bus operates in either single-pump or double-pump mode depending on the selection of the input

pixel format (FMT[2:0]). In single pump mode only the first edge of the CLKIN0/CLKIN1 differential clock pair

is used to sample the data, timing and blanking control signals. In double-pump mode, both edges of the clock

are used. With the double-pump mode high pixel transfer rates, up to 165 Mpixels/sec, can be achieved.

To ease the timing and EMI issues associated with a high pixel transfer rate, the signaling level of the signals

in Video Port is scalable. The input signals in video port are scalable by adjusting the voltage on the V

REF

to VDDQ/2. Similarly, the output signals are scalable by adjusting the voltage on the VDDQ pin to VDDQ, where

VDDQis the desirable full-swing voltage for the video port I/O signals. The differential CLKIN pair provides more

robust and reliable sampling for the pixel data and control signals, alleviating tight setup and hold time

requirements for high pixel transfer rates. Although differential clocking is the recommended clocking scheme,

it is possible to use single-end clocking with reduced timing margin, which may be significant with high clock

rates. When single-end clocking is used, CLKIN0 must be connected to the clock and CLKIN1 must be

connected to VDDQ/2.

INT1 and CLKOUT share the same pin. The function of the pin is defaulted to INT1 immediately after reset.

Reprogramming this may be done by writing to INTCKO bit. INT1 generates an interrupt to inform the host CPU

of events related to hot plug and power management. INT1# is open-drained and must be pulled up to VDDQ

with a 10K resistor. When programmed for CLKOUT function, CLKOUT pin outputs the clock generated by the

on-chip PLL. CLKOUT provides a reference clock which an external device, such as a graphics controller, may

to generate the CLKIN0 and CLKIN1 signals. CLKOUT signal is also tightly coupled to the progressive to

interlace conversion and overscan compensation functions. Refer to clock generation section for details for

clock generation and overscan compensation.

INT0 provides a dedicated interrupt for applications that need both CLKOUT signal and the interrupt signal.

Similar to INT1, INT0 is open–drained and normally a 10K pull-up resistor is needed to pull the signal to VDDQ.

TFP6422 and TFP6424 enters a special mode when INT0 is forced to low just before the deassertion of RST.

In this special mode, TFP6422 and TFP6424 is in simultaneous composite and S-video output mode, and

2

outputs an internally generated 100% color bar signal. No I C programming is required to enable this feature.

This feature is very useful for initial system diagnostics during product development, but is not recommended

in the final product.

13

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functional description (continued)

digital input video formats

Utilizing its multiple digital input video formats, TFP6422 and TFP6424 provides a flexible interface to the

external digital video sources such as compressed video from DVD, streaming video content from the Web,

cable or any broadband media, graphics and text images typical for PCs. The digital input video formats are

characterized by the following properties:

Color space:

Pixel format:

RGB or YCbCr

4:4:4 or 4:2:2

Color component order: Normal (Cb first) or reverse (Cr first)

Scan format:

Progressive or interlaced

Synchronization:

External sync or embedded sync

Although it is not cost effective to support all possible permutations of formats, TFP6422 and TFP6424 does

support the most commonly used formats required by most of the applications. Refer to the video output section

for the details of the supported digital input video formats.

The digital input video formats supported for a particular configuration are related to the video output formats.

When TFP6422 and TFP6424 is programmed for one of TV video output modes, all digital input video formats

listed in Table 3 are supported. When TFP6422 and TFP6424 is in either DVI or progressive RGB output mode,

only RGB input formats are supported.

data manager

Data Manager resides at the very beginning of the processing pipeline. Data manager is responsible for

receiving pixel data from the video port, and based on the selected input pixel format and output video format,

performs format conversions and dispatches the converted pixel data to the proper video processing unit to

create the required video output. The input pixel formats supported by TFP6422/6424 are described in detail

in the F_CONTROL register, sub address 3A.

When TV video output mode is enabled (VIDOUT[3:0] = 0001, 0010, 0011, 0100 or 0101), data manager

receives the pixel data in various formats from the video port and converts them to internal YUV representation

required by the TV encoder for further TV video encoding process. When DVI output mode is enabled, the input

pixel format must be set for 24-bit RGB mode (FMT[3:2] = 00) for correct operation and data manager passes

the RGB data to the DVI encoder without processing. When RGB output mode is enabled, similar to DVI output

mode, Data manager passes the RGB data to the video output DACs, converting the digital RGB pixel data to

analog RGB video output.

Data manager consists of two functional units: RGB-to-YCbCr color space converter and chrominance

decimator. The RGB-to-YCbCr color space converter converts the 24-bit RGB pixel data to 24-bit YCbCr

representation with 8 bits in each of Y, Cb and Cr components. If the input pixel data is already in 24–bit YCrCb

format, the data is bypasses the color space converter. The remaining Cb and Cr color components enter the

2-to-1 chrominance decimator which reduces the chrominance bandwidth and the amount of chrominance data

by half. The reduction of chrominance data decreases the amount of buffering required for vertical scaling

processbythescalingprocessor. Iftheinputpixeldataisalreadyin4:2:2YCbCrformat, boththeRGB-to-YCrCb

color space converter and chrominance decimator are bypassed.

14

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functional description (continued)

Table 1. 100/100 Color Bar Table in 2’s Complement

COLOR

White

Yellow

Cyan

Y (Hex)

6B

Cr (Hex)

00

Cb (Hex)

00

52

12

90

2A

90

26

Green

Magenta

Red

11

A2

B6

EA

D1

5E

4A

70

DA

70

Blue

A9

EE

Black

90

00

For diagnostic purposes, data manager can be forced to output 100/100 color bar YCbCr data by setting CBAR

2

bit to 1. CBAR bit can be set to 1 through I C interface or can be defaulted to 1 after reset by pulling down

INT0/CBARE Pin (Pin 9). For normal operations, INT0 pin should be pulled up.

DVI encoder

TheDVIencoderreceivesRGBpixeldatafromDataManagerandencodesthepixeldatabasedontheT.M.D.S.

(Transition Minimized Differential Signaling) encoding algorithm. The DVI Encoder consists of three

independent identical channels, each of which is responsible for encoding one color component. The encoding

algorithmminimizesthesignaltransitionwhilemaintainingagoodDCbalancetoreduceEMI. Theencodeddata

is then serially shifted to the DVI output drivers for transmission. The low–voltage swing differential output

further reduces EMI.

Each channel is encoded independently. Each channel receives 2 bits of control data and 8 bits of color

component data. Depending on the state of BLANK#, the DVI encoder either encodes control data or color

components. In either case, the data is encoded to 10–bit character and serially shifted out with the LSB

transmitted first. Blue channel (Channel 0) receives HSYNC and VSYNC as the control data and the blue color

component as the pixel data. If BLANK# is low, indicating valid blue component data is not transmitting, the

DVI encoder of the blue channel encodes the HSYNC and VSYNC signals based on Table TBD. If BLANK# is

high, indicating valid blue component data is transmitting, the DVI encoder encodes the blue component data

based on the table in Appendix A. The Green channel (Channel1) and Red channel (Channel 2) operate in a

way similar to Blue channel with the exception that the control bits are hardwired to ‘0’.

There are two possible encoded characters for each pixel data. The DVI encoder keeps tracks of the difference

between the number of ones and zeros that have been sent and selects the character that minimizes the

difference in order to maintain the best DC balance. Appendix A of this product datasheet contains a table

mapping of the 256 8–bit RGB pixel data to one of two possible 10 bit T.M.D.S. characters.

A serializer serializes the 10–bit character in each channel. An on–chip PLL locks to the CLKIN0 and CLKIN1

and generates the 10X clock to drive the serializer. The 10X clock is also sent to the T.M.D.S. drivers for output.

scaling processor

The Scaling Processor scales down the input image in both horizontal and vertical directions. In addition to

scaling, the Scaling Processor filters the image in the vertical direction and removes annoying flickers, which

are common when computer–generated graphics or text, especially static images, are displayed on the TV.

Scaling Processor uses a 5–tap adaptive filter for vertical scaling and filtering, whose coefficients are

dynamically adjusted on a line–by–line basis to maintain optimal performance. To preserve maximum

horizontal details, Scaling Processor scales internal encoding clock to process horizontal scaling.

15

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TFP6422, TFP6424

PanelBus DIGITAL TRANSMITTER/VIDEO ENCODER COMBO

SLDS118 – MARCH 2000

scaling processor (continued)

The Scaling Processor is enabled when the video output mode is one of the TV output modes (VIDOUT[3:0]

= 0001 through 0101) and the video input is progressive (FMT[[3:0] = any value other than 1000, 1001, 1100

and 1101).

Vertical scaling ratio registers VRATIOQ, VRATIOR, VRATIOQ2 and VRATIOR2 control the vertical scaling

ratio. The proper values of the vertical scaling ratio registers are computed as a function of the number of lines

from the input frame (defined in FLENS registers) and the number of the lines in the desired output frame

(defined in FLEN registers). Arbitrary scaling ratio from 0.5 to 1.0 is supported. Refer to the description of the

vertical scaling ratio registers for details.

VFLTR_CTRL register controls the filter characteristics of the vertical filter. The vertical filter performs both the

vertical interpolation and deflicker filtering. INPT bit determines whether the nearest neighboring interpolated

pixel (zero phase) or the interpolated dynamically adjusted pixel is to be used. The bandwidth of the vertical

filter is also programmable. DEFLKR[2:0] defines the filter bandwidth, which ranges from near all–pass to a very

narrow band. When selecting the bandwidth for an application, users must consider the trade–off between the

sharpness of the image and the amount of flickers present in the image. Refer to the description of

VFLTR_CTRL for details.

Horizontal scaling process is determined by the desired number of pixels in an input scan line and the nominal

number of pixels in a scan line in the output frame. The desired number of pixels in a scan line is defined by

the LLEN registers, while the nominal number of pixels in a scan line is determined by the SQP bit and FFRQ

bit. See the description of BSTAMP register for details. The nominal number of pixels in a scan line determines

the default video encoding timing when horizontal scaling is disabled. When horizontal scaling is enabled, an

internal horizontal scaling ratio is computed and the internal video encoding time base is adjusted to account

for the scaling ratio. The horizontal scaling also affects the subcarrier frequency and the close caption carrier

frequency due to the change of the video encoding clock frequency. Both frequencies must be scaled

proportionally in order to maintain the correct frequencies. Please refer to S_CARR and CC_CARR registers

for details.

Scaling process is also tightly coupled to the video encoding clock and the clock of the video port. The clocks

must be scaled precisely to guarantee correct operations. See Clock Generation for details.

clock generation

There are five clock signals in TFP6422/6424. XTALI/XTALO, CLKOUT, CLKIN0/CLKIN1, CLKENC and

TXC–/TXC+.

XTALI and XTALO are terminals for the 14.31818 MHz crystal. When TFP6422/6424 is in TV video output

modes, the on–chip PLL uses the 14.31818 MHz clock as a reference to generate CLKOUT and CLKENC.

CLKOUT is output to an external device such as a graphics controller. The external device then uses CLKOUT

as a reference and generates and outputs a clock signal back to the CLKIN0 and CLKIN1 pins on

TFP6422/6424. CLKIN0 and CLKIN1 clock out the video pixel and control to the TFP6422/6424 Video Port. The

clock connected to CLKIN0 and CLKIN1 can be differential or single–ended. When the clock is differential,

CLKIN0 is the positive side of the clock and CLKIN1 is the negative side. In the case of single–ended, the clock

connects to CLKIN0 and CLKIN1 is tied to VDDQ/2. CLKENC is an internal clock, thus not accessible externally.

It is used by the internal video encoder core to encode the TV video output signal. Depending on the

applications, it is also possible to connect CLKOUT directly to CLKIN0 signal.

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clock generation (continued)

ThefrequenciesofCLKENCandCLKOUTarecontrolledbyPLL_XregistersandPLL_Yregisters, respectively.

They must be related to each other, to other parameters and register values, in a precise manner for correct

video encoding operations. The following equations describe their relationship.

CLKENC = 2*LLEN * Fh

CLKOUT = S*((FLENS+1)/(FLEN+1))*CLKENC

Where

LLEN

= Number of pixels in a scan line

FLENS+1 = Number of lines in the input frame

FLEN+1 = Number of lines in the output frame

Fh

= Line Frequency

S is an integer scaling factor that relates the frequencies between CLKIN and CLKOUT by CLKIN =

CLKOUT/S. S accounts for the frequency divider used by the external device to divide CLKOUT to generate

CLKIN. S takes on the value of 1 or 2.

Refer to the description of PLL_X registers and PLL_Y registers for the procedure to compute the values of

PLL_X registers and PLL_Y registers to satisfy the relationship described above.

When TFP6422/6424 is in DVI or progressive RGB video output mode, similar to the case of TV video output

modes, differential or single–ended CLKIN is used to clock the pixel data and control signals to TFP6422/6424.

However, as opposed to TV video output modes, which use the clock signal on XTALI and XTAL0 as the

reference, TFP6422/6424 uses CLKIN signal to generate the required clock for DVI and progressive RGB video

output. The on–chip PLL takes CLKIN as the reference and generates the 10X clock. This clock is used

internally by the DVI encoder to encode and clock out the DVI bit stream as well as to output TXC+ and TXC–

differential clock along with the DVI data signals.

CLK_CTRL register provides additional control over the clock signals. CLKENCSE bit allows the internal video

encoding clock CLKENC to bypass the PLL and connect directly to CLKIN. DKEN and CLKINDSK[2:0] allow

the user to compensate the skew between CLKIN and the pixel data and control signals. Refer to the description

of CLK_CTRL for details.

timing synchronization

When TFP6422/6424 is in TV video output modes, Video Encoder maintains a set of counters as an internal

timereferencetoschedulevariousvideoencodingprocessestotakeplace, whichincludeactivevideoinsertion,

color burst insertion, horizontal sync and vertical sync pulse generation. The horizontal counters keep track of

the current horizontal time base in terms of half pixels. The vertical counters maintain vertical time based in

terms of half line. The field counters manage the field sequence. All the counters must be synchronized to the

input video data and control signals for correct operation.

The synchronization is achieved by resetting the counters at the periodical synchronization events. Use

HTRIGGER registers and VTRIGGER registers to program the values that the counters are reset to. These

registers can be used to define the horizontal phase and vertical phase relationship between the input image

and the output image.

When the input digital video is in interlace mode with embedded synchronization (FMT[3:0] = 1100 or 1101),

the ‘F’ bit in the SAV and EAV codes is used to synchronize the vertical counter and the field counter, and the

‘H’ bit is used to synchronize the horizontal counter. At the ‘0’ to ‘1’ transition of ‘F’ bit, the field counter is reset

to indicate EVEN field (second field) and the vertical counter is reset to the value defined in the VTRIGGER

registers. At the ‘0’ to ‘1’ transition of ‘H’ bit, the horizontal counter is reset to the values defined in the

HTRIGGER registers.

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timing synchronization (continued)

When the input digital video is in interlace mode with external synchronization (FMT[3:0] = 1000 or 1001), the

risingedgeoftheVSYNCresetstheverticalcounterandtherisingedgeofHSYNCresetsthehorizontalcounter.

The field counter in this case is free–running and does not reset. However, the FID pin outputs the current field

ID(EVEN or ODD).

When the input digital video is in progressive mode with external sync, the Scaling Processor performs the

scaling and the video port clock (CLKIN0 and CLKIN1) runs at a different frequency than the internal video

encoding clock (CLKENC). As a result, the digital video input timing is somewhat decoupled from the internal

video encoder timing. In this case, VSYNC (in the CLKIN domain) resets both the vertical counter and the

horizontal counter (in CLKENC domain). Special precaution is taken in the synchronization logic to handle the

potential metastability caused by a signal travelling across two different clock domains. The field counter does

not reset and runs freely. The FID pin outputs the current field ID (EVEN or ODD).

When the input digital video is in progressive mode with embedded sync, the ‘0’ to ‘1’ transition of ‘V’ bit resets

the vertical counter and the ‘0’ to ‘1’ transition of ‘H’ bit resets the horizontal counter. The field counter does not

reset and runs freely. The FID pin outputs the current filed ID (EVEN or ODD).

The timing synchronization described above is not applicable when TFP6422/6424 is in DVI output or

progressive RGB output mode.

As mentioned previously, when the Scaling Processor is enabled (TV video output mode and progressive digital

video input), the time base of Video Encoder core is decoupled from the timing of the Video Port. A FIFO is

placed between two domains to transfer the pixels across two domains. Video Encoder in this case acts as a

master that sources the pixel data from the FIFO. The point of time at each output scan line when Video Encoder

begins to request data is critical. It must be properly chosen not to overflow the FIFO. The point of time when

each output scan line starts to request pixel data is controlled by BPIX registers. To avoid overflowing the FIFO,

the HTRIGGER registers must be adjusted based on the value in BPIX.

See the descriptions of HTRIGGER, VTRIGGER and BPIX for details.

hot plug/unplug (auto connect/disconnect detection)

TFP6422/6424 supports Hot Plug/Unplug (auto connect/disconnect detection) for DVI link as well as the analog

video connections. The connection status of DVI link, HOTPLUG sense pin and DACs output, is provided by

the CON_STATUS register. RXCON bit indicates if a DVI receiver is connected to the TXC+ and TXC–. HPCON

bit reflects the current state of the HTPLUG pin connected to the monitor via DVI connector. HTPLUG pin is 5V

tolerant with an internal digital debouncing circuit to allow for direct connection to the DVI connector.

DACCON[0:3] bits reflect the connection status on the output of the DACs on CVBS, Y/G, C/R/Pr and B/Pr pins.

Whenever one or more connection status bits change states, the corresponding bit in the IN_STATUS bit is to

‘1’ to record the changes. An interrupt can also be generated as an option. The interrupt for each type of

connect/disconnect event can be individually enabled or disabled by writing a ‘1’ or ‘0’ to the corresponding bit

in the INT_ENABLE register. Notice that INT_ENABLE register does not affect the state of the INT_STATUS

bits. A host can either poll the INT_STATUS bits or rely on the interrupt to learn about the states or the change

of states of the connections. The interrupt continues to be asserted until ‘1’ is written to the corresponding

interrupt bit in the INT_STATUS register to reset the bit back to ‘0’. Writing ‘0’ to an interrupt status bit has no

effect.

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hot plug/unplug (auto connect/disconnect detection) (continued)

The hot plug/unplug detection indicated by HTPLUG bit is always enabled regardless of whether or not

TFP6422 is in DVI video output mode. The DVI receiver detection indicated by RXCON is only enabled when

DVI is not in fully off state. In other words, even if TFP6422 is not in DVI video output mode, it is still capable

of detecting Hot Plug/Unplug. However it can detect only DVI receiver connect/disconnect events if DVI is not

in fully off state. When TFP6422 is in one of the analog video output modes, the DAC connect/disconnect

detection is automatically enabled for the DACs that are currently used to output analog video. In all video output

modes, for the DACs that are inactive (in power-down mode), the connect/disconnect detection is normally

disabled unless AVCDEN bit is set to 0. During the period that a particular type of connect/disconnect detection

is disabled, the corresponding status bit in CON_STATUS register maintains its state just prior to disabling the

detection.

power management

When TFP6422 and TFP6424 is in a particular video output mode, it shuts down the unused circuit(s) to save

power. For example, when TV6422 and TV6424 is in DVI output mode, video encoder and all of four DACs are

shut down. Only the PLLs and DVI encoder are active. When TFP6422 and TFP6424 is composite video output

mode, both the DVI encoder and DVI drivers are powered down and only one DAC is active to output the

composite video. The rest of the DACs are powered down. Refer to VIDOUT_CTRL for details.

video output

Table 2. Color Bar Test Pattern Values

†

B

R

255

0

G

255

0

B

255

0

R

G

Y

Cb

128

16

Cr

128

146

16

White

Yellow

Cyan

235

0

235

0

235

0

235

210

170

145

106

81

255

0

235

0

166

54

Green

Magenta

Red

0

34

255

0

255

0

235

0

235

0

202

90

222

240

110

128

0

Blue

0

255

0

235

16

41

240

128

Black

0

16

†

These figures are only valid for non-switching lines. For switching lines, change the sign of the figures.

Table 3. 100/0/100/0 PAL (mV)

DACs

DVI DRIVERS PINS 21,

22, 24, 25, 27, 28, 30, 31

VIDOUT[3:0]

VIDEO OUTPUT TYPE

PIN 40

PD

PIN 41

PD

Y

PIN 43

PD

C

PIN 44

PD

Pb

0000

0001

0010

0011

0100

0101

0110

0111

1000

1111

DVI

Simultaneous composite and S-video

Composite video

DVI signals

PD

CVBS

PD

Y

PD

C

S-video

PD

Interlaced YPrPb

PD

Y

Pr

SCART

PD

CVBS

PD

G

R

B

Progressive RGB

PD

G

R

B

Simultaneous composite and interlaced YPrPb

DACs connection detection

Powerdown

PD

CVBS

HC

Y

Pr

Pb

PD

HC

PD

HC

PD

HC

PD

Legend: PD = powerdown,

CVBS = composite video,

Y = luminance,

B = blue,

C = chrominance,

HC = half of the full-scale current = 17.4 mA

Pr = red color difference,

Pb = blue color difference,

R = red, G = green,

19

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DVI

composite video

Table 4. 100/7.5/100/7.5 NTSC Composts (IRE)

CHROMI-

NANCE

LEVEL

(IRE)

MINIMUM

CHROMINANCE CHROMINANCE

EXCURSION

(IRE)6

MAXIMUM

LUMINANCE

LEVEL

CHROMINANCE

PHASE

U LEVEL V LEVEL

(IRE)

EXCURSION

(IRE)

(DEGREE)

White

Yellow

Cyan

Green

Magenta

Red

100.0

89.5

72.3

61.8

45.7

35.2

18.0

7.5

0.0

–40.3

13.6

–26.7

26.7

–13.6

40.3

0.0

9.2

0.0

82.7

116.9

109.2

116.9

82.7

0.0

100.0

48.1

13.9

7.2

100.0

130.8

116.4

100.3

93.6

59.4

7.5

–

167.1

283.5

240.7

60.7

103.5

347.1

–

–56.9

–47.6

47.6

56.9

–9.2

0.0

–8.9

–23.3

7.5

Blue

Black

Blank

Sync

0.0

–

–40.0

0.0

–

Burst

–20.0

0.0

40.0

–20.0

20.0

180.0

Table 5. 100/7.5/100/7.5 NTSC Composts (mV)

MINIMUM

CHROMINANCE CHROMINANCE

EXCURSION

(mV)

MAXIMUM

LUMINANCE

LEVEL

CHROMINANCE

PHASE

U LEVEL V LEVEL

LEVEL

(mV)

EXCURSION

(mV)

(DEGREE)

White

Yellow

Cyan

Green

Magenta

Red

1020

945

823

748

633

557

435

360

306

20

0

–288

97

0

66

0

591

835

780

835

591

0

1020

650

405

358

243

140

360

0.0

1020

1241

1138

1023

975

–

167.1

283.5

240.7

60.7

103.5

347.1

–

–406

–340

340

406

–66

0

–191

191

–97

288

0

Blue

731

Black

Blank

Sync

360

0.0

0

0.0

0

0.0

–

0

20

–

Burst

306

–143

0

286

163

449

180.0

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Table 6. 100/0/100/0 NTSC (IRE)

MINIMUM

CHROMINANCE CHROMINANCE

EXCURSION

(IRE)

MAXIMUM

LUMINANCE

LEVEL

CHROMINANCE

LEVEL

CHROMINANCE

PHASE

U LEVEL V LEVEL

(IRE)

EXCURSION

(IRE)

(DEGREE)

White

Yellow

Cyan

Green

Magenta

Red

100.0

88.6

70.1

58.7

41.3

29.9

11.4

0.0

–43.6

14.7

–28.9

28.9

–14.7

43.6

0.0

10.0

–61.5

–51.5

51.5

61.5

–10.0

0.0

89.4

126.4

118.1

126.4

89.4

0.0

100.0

43.9

6.9

100.0

133.3

117.7

100.3

93.1

56.1

0.0

–

167.1

283.5

240.7

60.7

103.5

347.1

–

–0.3

–17.7

–33.3

0.0

Blue

Black

Blank

Sync

0.0

–

–40.0

0.0

–

Burst

–20.0

0.0

40.0

–20.0

20.0

180.0

Table 7. 100/0/100/0 NTSC (mV)

MINIMUM

CHROMINANCE CHROMINANCE

EXCURSION

(mV)

MAXIMUM

LUMINANCE

LEVEL

CHROMINANCE

LEVEL

CHROMINANCE

PHASE

U LEVEL V LEVEL

(mV)

EXCURSION

(mV)

(DEGREE)

White

Yellow

Cyan

Green

Magenta

Red

1020

939

807

725

601

520

388

306

20

0

–311

105

–206

206

–105

311

0

71

0

639

903

843

903

639

0

1020

620

355

304

179

68

1020

1258

1147

1023

971

707

306

–

167.1

283.5

240.7

60.7

103.5

347.1

–

–439

–368

368

439

–71

0

Blue

68

Black

Blank

Sync

306

–

0

–

0

–

Burst

306

–143

0

286

163

449

180.0

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Table 8. 100/0/100/0 PAL (IRE)

MINIMUM

CHROMINANCE CHROMINANCE

EXCURSION

(IRE)

MAXIMUM

LUMINANCE

LEVEL

CHROMINANCE

LEVEL

CHROMINANCE

U LEVEL V LEVEL

†

PHASE

(DEGREE)

(IRE)

EXCURSION

(IRE)

White

Yellow

Cyan

Green

Magenta

Red

100.0

88.6

70.1

58.7

41.3

29.9

11.4

0.0

–43.6

14.7

–28.9

28.9

–14.7

43.6

0.0

10.0

–61.5

–51.5

51.5

61.5

–10.0

0.0

89.4

126.4

118.1

126.4

89.4

0.0

100.0

43.9

6.9

100.0

133.3

117.7

100.3

93.1

56.1

0.0

–

167.1

283.5

240.7

60.7

103.5

347.1

–

–0.3

–17.7

–33.3

0.0

Blue

Black

Blank

Sync

0.0

–

–43.0

0.0

–

Burst

–15.2

15.2

43.0

–25.5

21.5

135.0

†

These figures are only valid for non-switching lines. For switching lines, subtract the figures from 360.

Table 9. 100/0/100/0 PAL (mV)

MINIMUM

CHROMINANCE CHROMINANCE

EXCURSION

(mV)

MAXIMUM

LUMINANCE

LEVEL

CHROMINANCE

LEVEL

CHROMINANCE

U LEVEL V LEVEL

†

PHASE

(DEGREE)

(mV)

EXCURSION

(mV)

White

1020

941

811

732

610

530

401

321

20

0

–305

103

–202

202

–103

305

0

70

0

625

884

826

884

625

0

1020

628

369

319

197

88

1020

1253

1144

1023

972

714

321

–

167.1

283.5

240.7

60.7

103.5

347.1

–

Yellow

Cyan

Green

Magenta

Red

–430

–360

360

430

–70

0

Blue

88

Black

Blank

Sync

321

–

Burst

321

–106

106

301

171

471

135.0

†

These figures are only valid for non-switching lines. For switching lines, subtract the figures from 360.

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S-video

Table 10. 100/7.5/100/7.5 NTSC S-Video C Channel (mV)

MINIMUM

CHROMINANCE CHROMINANCE

EXCURSION

(mV)

MAXIMUM

DC OFFSET

LEVEL

CHROMINANCE

LEVEL

CHROMINANCE

PHASE

U LEVEL V LEVEL

(mV)

EXCURSION

(mV)

(DEGREE)

White

Yellow

Cyan

Green

Magenta

Red

652

0

591

835

780

835

591

0

652

357

235

262

235

357

652

–

652

948

1070

1042

1070

948

652

–

167.1

283.5

240.7

60.7

103.5

347.1

–

–288

66

97

–191

191

–97

288

0

–406

–340

340

406

–66

0

Blue

Black

Blank

Burst

–

–143

0

307

499

806

180.0

Table 11. 100/0/100/0 NTSC S-Video C Channel (mV)

MINIMUM

CHROMINANCE CHROMINANCE

EXCURSION

(mV)

MAXIMUM

DC OFFSET

LEVEL

CHROMINANCE

PHASE

U LEVEL V LEVEL

LEVEL

(mV)

EXCURSION

(mV)

(DEGREE)

White

Yellow

Cyan

Green

Magenta

Red

652

0

–288

97

0

66

0

639

903

842

843

903

639

0

652

333

201

231

201

333

652

–

652

972

1104

1074

1104

972

652

–

167.1

283.5

240.7

60.7

103.5

347.1

–

–406

–340

340

406

–66

0

–191

191

–97

288

0

Blue

Black

Blank

Burst

–

–143

0

307

499

806

180.0

Table 12. 100/0/100/0 PAL S-Video C Channel (mV)

MINIMUM

CHROMINANCE CHROMINANCE

EXCURSION

(mV)

MAXIMUM

DC OFFSET

LEVEL

CHROMINANCE

†

U LEVEL V LEVEL

‡

LEVEL

(mV)

PHASE

(DEGREE)

(mV)

EXCURSION

(mV)

White

Yellow

Cyan

Green

Magenta

Red

652

0

–305

103

–202

202

103

305

0

625

884

826

884

625

0

652

340

210

240

210

340

652

–

652

965

1094

1065

1094

965

652

–

167.1

283.5

240.7

60.7

103.5

347.1

–

70

–430

–360

360

430

–70

–

Blue

Black

Blank

Burst

–

–106

106

301

502

803

180.0

†

‡

These figures are only valid for non-switching lines. For switching lines, change the sign of the figures.

These figures are only valid for non-switching lines. For switching lines, subtract the figures from 360.

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YPbPr

Table 13. 100/7.5/100/7.5 NTSC YPbPr (mV)

LUMINANCE

LEVEL

DC OFFSET

Level

U LEVEL V LEVEL

Pb LEVEL

(mV)

Pr LEVEL

(mV)

White

Yellow

Cyan

Green

Magenta

Red

1020

945

823

748

633

557

435

360

306

20

0

–350

118

–232

232

–118

350

0

57

652

–

652

303

770

421

884

534

1002

652

–

652

709

303

359

945

1002

596

652

–

–350

–293

293

350

–57

0

Blue

Black

Blank

Sync

–

Table 14. 100/0/100/0 NTSC YPbPr (mV)

LUMINANCE

LEVEL

DC OFFSET

U LEVEL V LEVEL

Pb LEVEL

Pr LEVEL

(mV)

Level

(mV)

White

Yellow

Cyan

Green

Magenta

Red

1020

939

807

725

601

520

388

306

20

0

–350

118

–232

232

–118

350

0

57

652

–

652

303

770

421

884

534

1002

652

–

652

709

303

359

945

1002

596

652

–

–350

–293

293

350

–57

0

Blue

Black

Blank

Sync

–

Table 15. 100/0/100/0 PAL YPbPr (mV)

LUMINANCE

LEVEL

DC OFFSET

U LEVEL V LEVEL

Pb LEVEL

(mV)

Pr LEVEL

(mV)

Level

(mV)

White

Yellow

Cyan

Green

Magenta

Red

1020

941

811

732

610

530

401

321

20

0

–350

118

–232

232

–118

350

0

57

652

–

652

303

770

421

884

534

1002

652

–

652

709

303

359

945

1002

596

652

–

–350

–293

293

350

–57

0

Blue

Black

Blank

Sync

–

24

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SCART

Table 16. SCART RGB (mV)

RED

LEVEL

(mV)

GREEN

LEVEL

(mV)

BLUE

LEVEL

(mV)

White

Yellow

Cyan

Green

Magenta

Red

1020

320

1020

320

–

1020

320

20

1020

320

1020

320

1020

320

1020

320

–

Blue

Black

Blank

Sync

Table 17. Progressive RGB (mV)

RED

LEVEL

(mV)

GREEN

LEVEL

(mV)

BLUE

LEVEL

(mV)

White

Yellow

Cyan

Green

Magenta

Red

1020

320

1020

320

–

1020

320

20

1020

320

1020

320

1020

320

1020

320

–

Blue

Black

Blank

Sync

luminance encoding

A programmable gain is first applied to the luminance data output from Data Manager or Scaling Processor

dependingonwhethertheScalingProcessorisbypassedorenabled. TheluminancegainisdefinedbyGAIN_Y

register at subaddresses 5F and 60. The horizontal sync, vertical sync and setup insertion are then performed.

Both black level and blank level are programmable through BLACK_LEVEL and BLANK_LEVEL registers at

subaddresses 5D and 5E, respectively.

Allthetransitionedgesoftheluminancesignal, suchassyncedgesandactivevideoedges, areproperlyshaped

and filtered to limit the bandwidth within the standards.

luminance low-pass and interpolation filter

After all the necessary components of luminance signal have been added, the resultant signal is low–passed

and interpolated to 2X–pixel rate. This 2X interpolation simplifies the external analog reconstruction filter design

and improves the signal–to–noise ratio. Refer to Figures 8 and 9 for the filter frequency responses.

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GAIN

vs

GAIN

vs

FREQUENCY

5.00

0.00

0.50

0.00

NTSC_SQP

–5.00

PAL_SQP

–0.50

–1.00

–1.50

–2.00

–2.50

–3.00

–10.00

–15.00

–20.00

–25.00

–30.00

–35.00

–40.00

NTSC_SQP

NTSC_CCIR

PAL_CCIR

NTSC_CCIR

0.00 1.00 2.00 3.00 4.00 5.00 6.00 7.00 8.00 9.0010.00

f – Frequency – MHz

Figure 5. Luma Filter Frequency Response

cross color reduction filter

Figure 6. Luma Interpolation Filter Frequency

Response

An optional cross color reduction filter can be applied to the luminance signal before the luminance signal

combines with the chrominance signal to form the composite signal. The cross color reduction filter reduces the

interference between luminance and chrominance in the composite signal. This filter does not apply to S-video.

chrominance encoding

A pair of programmable gains adjusts the time-multiplexed U/V signal. The gain for U and the gain for V are

independently controlled by GAIN_U and GAIN_V register bits respectively at subaddresses 5B, 5C, 5D and

5E. The gain-adjusted signal then passes through a chrominance lowpass filter to limit the bandwidth of the U/V

signal. See Figure 7 for the filter frequency response. The chrominance lowpass filter can be bypassed by

setting CBW bit of M_CONTROL register at subaddress 61 to 0. This setting enlarges the bandwidth on U/V

for S-video output.

The lowpass U/V signal is then subjected to a 1-to-4 interpolation through a two-stage interpolation filter. The

data rate for both U and V is now at 2X-pixel rate.

The U and V signals are then quadrature-modulated by the internally generated subcarrier signal to form the

chrominance (C) signal. The subcarrier reference signal color burst is inserted right before the active video.

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chrominance encoding (continued)

The frequency, the phase of the modulating subcarrier and the amplitude of the color burst are all

programmable. The S_CARR registers at subaddresses 63,64,65 and 66 control the subcarrier frequency. The

values of the registers are computed based on the desired subcarrier frequency and the internal video encoding

clock CLKENC using the equation in the register description. C_PHASE register at subaddress 5A controls the

phase of the subcarrier. The phase of the color subcarrier is reset to C_PHASE. Four modes of color subcarrier

reset are provided: reset every two lines, every two fields or every eight fields. Users can use C_PHASE register

to adjust SCH (subcarrier to horizontal sync phase). BSTAP[6:0] of BSTAMP register at subaddress 62 sets the

amplitude of the color burst. PAL bit of M_CONTROL register enables Phase Alternation Line encoding. A

sweeping subcarrier is generated to encode the chrominance signal, when PAL bit is set to 1. Otherwise a

normal subcarrier is generated. Phase Alternation Line refers to the encoding scheme in which subcarrier

alternate between two phases every scan line. There are two possible alternation sequences and PALPHS bit

of M_CONTROL register selects one of the sequences.

GAIN

vs

FREQUENCY

0.00

PAL_SQP

–10.00

–20.00

–30.00

–40.00

–50.00

–60.00

NTSC_CCIR

PAL_CCIR

NTSC_SQP

0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00 4.50 5.00

f – Frequency – MHz

Figure 7. Chroma Filter Frequency Response

closed caption encoding

TFP6422 and TFP6424 can be programmed to encode closed caption data and extended data in the selected

2

line. The closed caption data are sent to TFP6422 and TFP6424 through I C. The data stream consists of

seven-bit US-ASCII code and one odd parity bit as shown in Figure 8.

MSB

US-ASCII

Bit 5

LSB

Bit 1

Odd-Parity

Bit 6

Bit 4

Bit 3

Bit 2

Bit 0

Figure 8. Closed Caption Data Format

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closed caption encoding (continued)

The standard service encodes closed caption only in the ODD field, while the extended service encodes closed

caption in both fields. L21ENA, when set to 1, enables closed caption encoding in ODD field and L21ENB, when

set to 1, enables closed caption encoding in EVEN field.

Use SLINE register at subaddress 6B to program the scan line where closed caption is to be encoded.

Four closed caption data registers contain the data to be encoded. Registers LINE21_O0 and LINE21_O1

contain the first byte and the second byte of close caption data to be encoded in the ODD field. Registers

LINE21_E0 and LINE21_E1 contain the first byte and the second byte of data to be encoded in the EVEN field.

Immediately after the closed caption data is written to the registers either in the ODD field or EVEN field, the

corresponding closed caption status bit, CCE or CCO in STATUS register at subaddress 02, is reset to 0 to

indicate that the closed caption data is available in the closed caption data registers and yet to be encoded.

Immediately after the closed caption is encoded, CCE or CCO bit is set to 1 to indicate that the closed caption

data has been encoded and is ready to accept new data. Null character is automatically inserted if the closed

caption data is not written to the closed caption data registers in time for encoding.

Therun–inclockfrequencyis5034960.5Hz(32xf

ofNTSC).Theclosedcaptiondataisencodedintheformat

line

of NRZ (Nonreturn to Zero). Additionally, the data translates to IRE scale in the following manner:

0 = 0 IRE; 1 = 50 IRE.

The following four diagrams present the parameters of closed caption line data implemented in different

standards.

59.65 µS

27.4 µS

2 Null Characters

(7 Cycles)

13.9 µS

Transition Time: 220 nS

10 µS

Figure 9. NTSC CCIR601 Rate Closed Caption Line

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closed caption encoding (continued)

59.65 µS

27.4 µS

2 Null Characters

(7 Cycles)

13.9 µS

Transition Time: 220 nS

10 µS

Figure 10. PAL CCIR601 Pixel Rate Closed Caption Line

59.67 µS

27.4 µS

2 Null Characters

(7 Cycles)

13.9 µS

Transition Time: 240 nS

10.02 µS

Figure 11. NTSC Square Pixel Rate Closed Caption Line

59.67 µS

27.4 µS

2 Null Characters

(7 Cycles)

13.9 µS

Transition Time: 200 nS

10 µS

Figure 12. PAL Square Pixel Rate Closed Caption Line

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closed caption encoding (continued)

1 µH

2.7 µH

0.7 µH

CVBS/Y/C

To 75 Ω Cable

TFP6422

TFP6424

470 pF

330 pF

56 pF

75 Ω

Figure 13. Output Filtering

register map

2

TFP6422 and TFP6424 is a standard I C slave device. All the registers can be written and read through the I C

2

interface. The I C base address of TFP6422 and TFP6424 is dependent on pin 10 (A0) as shown in Table 18

below.

2

Table 18. Base I C Address

PIN 10

WRITE ADDRESS (HEX)

READ ADDRESS (HEX)

0

1

40

42

41

43

REGISTER

VEN_ID

RW SUBADDRESS

BIT7

BIT6

BIT5

BIT4

BIT3

BIT2

BIT1

BIT0

R

00

01

Ven_id[7:0]

Ven_id[15:8]

Dev_Id[7:0]

Dev_id[15:8]

Rev_Id[7:0]

02

DEV_ID

03

REV_ID

04

STATUS

05

Cce

Cco

Fsq[2:0]

RESERVED

F_CONTROL

CLK_CTRL

VIDOUT_CTRL

SYNC_CTRL0

CON_STATUS

INT_STATUS

INT_ENABLE

GP_CTRL

05–39

3A

3B

3C

3D

3E

3F

40

RESERVED

RW

R

Cbar

Intcko

RGBF

Vs_fid

Fmt[3:0]

Ckindsk[3:0]

Ckencse

Vidout[3:0]

Syn_g

Fid_pol

Hs_com

Vsen

Hsen

Tvsen

Hpcon

Hpevnt

Hpen

Thsen

Rxcon

Rxevnt

Rxen

Daccon3 Daccon2 Daccon1 Daccon0

RW

41

Gio1_en

Gp1_in

Gp0_in

Gp1_oe

Gp0_oe

Gp1_out Gp0_out

42

Llen[7:0]

LLEN

Flens

43

Llen[10:8]

44

Flens[7:0]

45

Flens[10:8]

46

Pll_x[7:0]

Pll_x[15:8]

Pll_x[23:16]

47

PLL_X

48

49

Pll_x_sf[1:0]

Pll_x[29:24]

30

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TFP6422, TFP6424

PanelBus DIGITAL TRANSMITTER/VIDEO ENCODER COMBO

SLDS118 – MARCH 2000

REGISTER

RW SUBADDRESS

BIT7

BIT6

BIT5

BIT4

BIT3

BIT2

BIT1

BIT0

RW

R

4A

4B

4C

4D

4E

4F

50

51

52

53

54

55

56

57

58

59

5A

5B

5C

5D

5E

5F

60

61

62

63

64

65

66

67

68

69

6A

6B

6C

6D

6E

6F

70

71

72–76

77

78

79

7A

Pll_y[7:0]

Pll_y[15:8]

PLL_Y

Pll_y[23:16]

Pll_y_sf[1:0]

Pll_bw[1:0]

Pll_y[29:24]

Pll_hi[1:0]

PLL_BWRNG

PLL_STATUS

Pll_adj

Pll_sel

Pll_lo[1:0]

Pll_status[7:0]

Fifo_dly[7:0]

Fifo_dly[15:8]

Vratior2[7:0]

RW

FIFO_DLY

VRATIOR2

VRATIOQ2

VRATIOR

Vratioq2[4:0]

Vratior [7:0]

Vratioq[4:0]

Vratior2[29:8]

Vratior[9:8]

VRATIOQ

VFLTR_CTRL

HFLTR_CTRL

Sc_load

Deflkr

Intp

Yintp

Cintp[1:0]

Fcc[7:0]

Fcc[15:8]

Cphs[7:0]

Gu[7:0]

CC_CARR

C_PHASE

GAIN_U

GAIN_V

Gv[7:0]

BLACK_LEVEL

BLANK_LEVEL

GAIN_Y

Gu[8]

Gv[8]

Black[6:0]

Blank[6:0]

Gy[7:0]

Xcbw[1:0]

Cbw[2:0]

Bstap[6:0]

Fsc[7:0]

X_COLOR

M_CONTROL

BSTAMP

RW

Xce

Gy[8]

Lcd[2:0]

Pal

Ffrq

Palphs

Sqp

S_CARR1

S_CARR2

S_CARR3

S_CARR4

LINE21_O0

LINE21_O1

LINE21_E0

LINE21_E1

LN_SEL

Fsc[15:8]

Fsc[23:16]

Fsc[31:24]

L21o[7:0]

L21o[15:8]

L21e[7:0]

L21e[15:8]

Sline[4:0]

RESERVED

L21

RESERVED

Htrig[7:0]

L21ena

L21enb

HTRIGGER

VTRIGGER

Htrig]10:8]

Vtrig[7:0]

Presa

Presb

Sblank

Vtrig[9:8]

RESERVED

BAVID

RESERVED

Bavid7:0]

RW

EAVID

Eavid[7:0]

BEAVID

FLEN

Eavid[10:8]

Bavid[10:8]

Flen[7:0]

31

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TFP6422, TFP6424

PanelBus DIGITAL TRANSMITTER/VIDEO ENCODER COMBO

SLDS118 – MARCH 2000

REGISTER

RW SUBADDRESS

BIT7

BIT6

BIT5

BIT4

Fal[7:0]

Lal[7:0]

Fal[8]

Nblkns

Border_y[7:0]

BIT3

BIT2

BIT1

BIT0

FAL

LAL

RW

7B

7C

FLAL

7D

Lal[8]

Ignp

Flen[9:8]

Hblkm[1:0]

SYN_CTRL1

BORDER_Y

BORDER_CR

BORDER_CB

7E

Free

Esav

Vblkm[1:0]

7F

80

Border_cr[7:0]

Border_cb[7:0]

BPIX[7:0]

81

82

BPIX

83

BPIX[10:8]

A_vtrig

VTRIG_CTRL

RESERVED

PLL_TST0

84

F_vtrig

85–8F

90–A1

A2–AF

B0

RESERVED

RW

PLL_TST1

B1

PLL test registers

Fuse test registers

PLL_TST2

B2

PLL_TST3

B3

FUSE_TST0

FUSE_TST1

FUSE_TST2

FUSE_TST3

TMDS_TST0

TMDS_TST1

TMDS_TST2

TMDS_TST3

TMDS_TST4

TMDS_TST5

TMDS_TST6

TMDS_TST7

TMDS_TST8

TMDS_TST9

TMDS_TST10

TMDS_TST11

TMDS_TST12

TMDS_TST13

TMDS_TST14

TMDS_TST15

DAC_TST

B4

B5

B6

B7

C0

C1

C2

C3

C4

C5

C6

C7

T.M.D.S. test registers

C8

C9

CA

CB

CC

CD

CE

CF

D0

DAC test register

Reserved

RESERVED

D1–FF

32

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TFP6422, TFP6424

PanelBus DIGITAL TRANSMITTER/VIDEO ENCODER COMBO

SLDS118 – MARCH 2000

register description

The default register settings are indicated with (*). If two defaults are indicated, the state of INT0 / CBARE at

reset will determine which default is used.

VEN_ID

Subaddress = 00

Read Only

Default = 0x4C

7

6

5

4

3

2

1

0

VEN_ID[7:0]

Subaddress = 01

Read Only

Default = 0x01

7

6

5

4

3

2

1

0

VEN_ID[15:8]

This read-only register contains the 16–bit Texas Instruments vendor ID for the TFP6422/6424. VEN_ID[15:0]

is hardwired to 0x014C.

DEV_ID

Subaddress = 02

Read Only

Default = 0x22/23

7

6

5

4

3

2

1

0

DEV_ID[7:0]

Subaddress = 03

Read Only

Default = 0x64

7

6

5

4

3

2

1

0

DEV_ID[15:8]

This read-only register contains the 16-bit device ID for the TFP6422 and TFP6424. The revision ID will identify

different revisions of the device. For TFP6422, DEV_ID[15:0] is hardwired to 0x6422. For TFP6424,

DEV_ID[15:0] is hardwired to 0x6424.

REV_ID

Subaddress = 03

Read Only

Default = 0x01

7

6

5

4

3

2

1

0

REV_ID[7:0]

This read-only register contains the revision ID for the TFP6422 and TFP6424. The revision ID will identify

different revisions of the device. REV_ID[7:0] is hardwired to 0x01.

STATUS

Subaddress = 05

Read Only

7

6

5

4

3

2

1

0

CCE

CCO

FSQ[2:0]

CCE

CCO

Closed caption status for even field. This bit is set immediately after the data in registers LINE21_E0 and

LINE21_E1havebeenencodedtoclosedcaption. Thisbitisresetwhenbothoftheseregistersarewritten.

Closed caption status for odd field. This bit is set immediately after the data in registers LINE21_O0 and

LINE21_O1havebeenencodedtoclosedcaption. Thisbitisresetwhenbothoftheseregistersarewritten.

FSQ[2:0] Field sequence ID. For PAL, all three FSQ[2:0] are used whereas for NTSC only FSQ[1:0] is meaningful.

Furthermore, FSQ[0] represents ODD field when it is 0 and EVEN field when it is 1.

33

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TFP6422, TFP6424

PanelBus DIGITAL TRANSMITTER/VIDEO ENCODER COMBO

SLDS118 – MARCH 2000

F_CONTROL

Subaddress = 3A

Default = 0x8D

7

6

5

4

3

2

1

0

CBAR

INTCKO

RGBF

FMT[3:0]

Format Control Register. This register specifies the input video source and format.

CBAR Select Video Data Source.

0(*)

1(*)

Use external video source

Use internal color bars

INTCKO INT1/CLKOUT pin function select

0(*)

1

INT1

CLKOUT

RGBF

RGB /YCrCb input coding range

0(*)

The input RGB data are in binary format with coding range 0–255

The input YCrCb data are in binary format with coding range 0–255

The input RGB data are in binary format with coding range 16–235

1

The input YCrCb data are in binary format conforming to ITU–601 standard

FMT[3:0] These four bits specify the video input data stream format and timing as shown in the table below.

H indicates the sampling point at the crossover of the rising edge of CLKIN0 and the falling edge of

CLKIN1

L indicates the sampling point at the crossover of the falling edge of CLKIN0 and the rising edge of

CLKIN1

34

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TFP6422, TFP6424

PanelBus DIGITAL TRANSMITTER/VIDEO ENCODER COMBO

SLDS118 – MARCH 2000

Digital Input Video Data and Sync Format

FMT[3:2] = 00(*)

RGB

Color space

Pixel format

Scan

(8,8,8)

Progressive

Sync

HSYNC, VSYNC and BLANK

FMT[1:0]

00(*)

01

10

11

DATA[11:0]

H

L

H

L

H

L

H

L

DATA[11]

DATA[10]

DATA[9]

DATA[8]

DATA[7]

DATA[6]

DATA[5]

DATA[4]

DATA[3]

DATA[2]

DATA[1]

DATA[0]

R[7]

R[6]

R[5]

R[4]

R[3]

R[2]

R[1]

R[0]

G[7]

G[6]

G[5]

G[4]

G[3]

G[2]

G[1]

G[0]

B[7]

B[6]

B[5]

B[4]

B[3]

B[2]

B[1]

B[0]

G[3]

G[2]

G[1]

G[0]

B[7]

B[6]

B[5]

B[4]

B[3]

B[2]

B[1]

B[0]

R[7]

R[6]

R[5]

R[4]

R[3]

R[2]

R[1]

R[0]

G[7]

G[6]

G[5]

G[4]

R[7]

R[6]

R[5]

R[4]

R[3]

G[7]

G[6]

G[5]

R[2]

R[1]

R[0]

G[1]

G[4]

G[3]

G[2]

B[7]

B[6]

B[5]

B[4]

B[3]

G[0]

B[2]

B[1]

B[0]

G[4]

G[3]

G[2]

B[7]

B[6]

B[5]

B[4]

B[3]

G[0]

B[2]

B[1]

B[0]

R[7]

R[6]

R[5]

R[4]

R[3]

G[7]

G[6]

G[5]

R[2]

R[1]

R[0]

G[1]

FMT[3:2] = 01

YCrCb

Color space

Pixel format

Scan

4:4:4

Progressive

Sync

HSYNC, VSYNC and BLANK

FMT[1:0]

00

01

10

11

DATA[11:0]

H

L

H

L

H

L

H

L

DATA[11]

DATA[10]

DATA[9]

DATA[8]

DATA[7]

DATA[6]

DATA[5]

DATA[4]

DATA[3]

DATA[2]

DATA[1]

DATA[0]

Cr[7]

Cr[6]

Cr[5]

Cr[4]

Cr[3]

Cr[2]

Cr[1]

Cr[0]

Y[7]

Y[3]

Cr[7]

Cr[6]

Cr[5]

Cr[4]

Cr[3]

Cr[2]

Cr[1]

Cr[0]

Y[7]

Cr[7]

Cr[6]

Cr[5]

Cr[4]

Cr[3]

Y[7]

Y[4]

Cr[7]

Cr[6]

Cr[5]

Cr[4]

Cr[3]

Y[7]

Y[2]

Y[3]

Y[1]

Y[2]

Y[0]

Cb[7]

Cb[6]

Cb[5]

Cb[4]

Cb[3]

Y[0]

Cb[7]

Cb[6]

Cb[5]

Cb[4]

Cb[3]

Y[0]

Cb[7]

Cb[6]

Cb[5]

Cb[4]

Cb[3]

Cb[2]

Cb[1]

Cb[0]

Cb[7]

Cb[6]

Cb[5]

Cb[4]

Cb[3]

Cb[2]

Cb[1]

Cb[0]

Y[6]

Y[5]

Cr[2]

Cr[1]

Cr[0]

Y[1]

Cr[2]

Cr[1]

Cr[0]

Y[1]

Y[6]

Cb[2]

Cb[1]

Cb[0]

Cb[2]

Cb[1]

Cb[0]

Y[5]

Y[4]

35

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TFP6422, TFP6424

PanelBus DIGITAL TRANSMITTER/VIDEO ENCODER COMBO

SLDS118 – MARCH 2000

FMT[3:2] = 10

Color space

Pixel format

YCrCb

4:2:2

FMT[1:0] = 00

Scan

Interlaced

Sync

HSYNC, VSYNC and BLANK

DATA[11:0]

DATA[11]

DATA[10]

DATA[9]

DATA[8]

DATA[7]

DATA[6]

DATA[5]

DATA[4]

DATA[3]

DATA[2]

DATA[1]

DATA[0]

0H

0L

1H

1L

2H

2L

3H

3L

Cb0[7]

Cb0[6]

Cb0[5]

Cb0[4]

Cb0[3]

Cb0[2]

Cb0[1]

Cb0[0]

Y0[7]

Y0[6]

Y0[5]

Y0[4]

Y0[3]

Y0[2]

Y0[1]

Y0[0]

Cr0[7]

Cr0[6]

Cr0[5]

Cr0[4]

Cr0[3]

Cr0[2]

Cr0[1]

Cr0[0]

Y1[7]

Y1[6]

Y1[5]

Y1[4]

Y1[3]

Y1[2]

Y1[1]

Y1[0]

FMT[1:0] = 01

Scan

Sync

Interlaced

HSYNC, VSYNC and BLANK

0H

0L

1H

1L

2H

2L

3H

3L

DATA[11]

DATA[10]

DATA[9]

DATA[8]

DATA[7]

DATA[6]

DATA[5]

DATA[4]

DATA[3]

DATA[2]

DATA[1]

DATA[0]

Cr0[7]

Cr0[6]

Cr0[5]

Cr0[4]

Cr0[3]

Cr0[2]

Cr0[1]

Cr0[0]

Y0[7]

Y0[6]

Y0[5]

Y0[4]

Y0[3]

Y0[2]

Y0[1]

Y0[0]

Cb0[7]

Cb0[6]

Cb0[5]

Cb0[4]

Cb0[3]

Cb0[2]

Cb0[1]

Cb0[0]

Y1[7]

Y1[6]

Y1[5]

Y1[4]

Y1[3]

Y1[2]

Y1[1]

Y1[0]

36

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TFP6422, TFP6424

PanelBus DIGITAL TRANSMITTER/VIDEO ENCODER COMBO

SLDS118 – MARCH 2000

FMT[3:2] = 10

YCrCb

Color space

Pixel format

4:2:2

FMT[1:0] = 10

Progressive

Scan

Sync

HSYNC, VSYNC and BLANK

DATA[11:0]

DATA[11]

DATA[10]

DATA[9]

DATA[8]

DATA[7]

DATA[6]

DATA[5]

DATA[4]

DATA[3]

DATA[2]

DATA[1]

DATA[0]

0H

0L

1H

1L

2H

2L

3H

3L

Cb0[7]

Cb0[6]

Cb0[5]

Cb0[4]

Cb0[3]

Cb0[2]

Cb0[1]

Cb0[0]

Y0[7]

Y0[6]

Y0[5]

Y0[4]

Y0[3]

Y0[2]

Y0[1]

Y0[0]

Cr0[7]

Cr0[6]

Cr0[5]

Cr0[4]

Cr0[3]

Cr0[2]

Cr0[1]

Cr0[0]

Y1[7]

Y1[6]

Cb2[7]

Cb2[6]

Cb2[5]

Cb2[4]

Cb2[3]

Cb2[2]

Cb2[1]

Cb2[0]

Y2[7]

Y2[6]

Y2[5]

Y2[4]

Y2[3]

Y2[2]

Y2[1]

Y2[0]

Cr2[7]

Cr2[6]

Cr2[5]

Cr2[4]

Cr2[3]

Cr2[2]

Cr2[1]

Cr2[0]

Y3[7]

Y3[6]

Y3[5]

Y3[4]

Y3[3]

Y3[2]

Y3[1]

Y3[0]

Y1[5]

Y1[4]

Y1[3]

Y1[2]

Y1[1]

Y1[0]

FMT[1:0] = 11

Scan

Progressive

HSYNC, VSYNC and BLANK

Sync

DATA[11:0]

DATA[11]

DATA[10]

DATA[9]

DATA[8]

DATA[7]

DATA[6]

DATA[5]

DATA[4]

DATA[3]

DATA[2]

DATA[1]

DATA[0]

0H

0L

1H

1L

2H

2L

3H

3L

Cr0[7]

Cr0[6]

Cr0[5]

Cr0[4]

Cr0[3]

Cr0[2]

Cr0[1]

Cr0[0]

Y0[7]

Y0[6]

Y0[5]

Y0[4]

Y0[3]

Y0[2]

Y0[1]

Y0[0]

Cb0[7]

Cb0[6]

Cb0[5]

Cb0[4]

Cb0[3]

Cb0[2]

Cb0[1]

Cb0[0]

Y1[7]

Y1[6]

Y1[5]

Y1[4]

Y1[3]

Y1[2]

Y1[1]

Y1[0]

Cr2[7]

Cr2[6]

Cr2[5]

Cr2[4]

Cr2[3]

Cr2[2]

Cr2[1]

Cr2[0]

Y2[7]

Y2[6]

Y2[5]

Y2[4]

Y2[3]

Y2[2]

Y2[1]

Y2[0]

Cb2[7]

Cb2[6]

Cb2[5]

Cb2[4]

Cb2[3]

Cb2[2]

Cb2[1]

Cb2[0]

Y3[7]

Y3[6]

Y3[5]

Y3[4]

Y3[3]

Y3[2]

Y3[1]

Y3[0]

37

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TFP6422, TFP6424

PanelBus DIGITAL TRANSMITTER/VIDEO ENCODER COMBO

SLDS118 – MARCH 2000

FMT[3:2] = 11

Color space

Pixel format

YCrCb

4:2:2

FMT[1:0] = 00

Scan

Interlaced

Sync

F, V and H bits in the SAV and EAV codes are embedded in the video stream

DATA[11:0]

DATA[11]

DATA[10]

DATA[9]

DATA[8]

DATA[7]

DATA[6]

DATA[5]

DATA[4]

DATA[3]

DATA[2]

DATA[1]

DATA[0]

0H

0L

1H

1L

2H

2L

3H

3L

Cb0[7]

Cb0[6]

Cb0[5]

Cb0[4]

Cb0[3]

Cb0[2]

Cb0[1]

Cb0[0]

Y0[7]

Y0[6]

Y0[5]

Y0[4]

Y0[3]

Y0[2]

Y0[1]

Y0[0]

Cr0[7]

Cr0[6]

Cr0[5]

Cr0[4]

Cr0[3]

Cr0[2]

Cr0[1]

Cr0[0]

Y1[7]

Y1[6]

Y1[5]

Y1[4]

Y1[3]

Y1[2]

Y1[1]

Y1[0]

FMT[1:0] = 01

Scan

Interlaced

F, V and H bits in the SAV and EAV codes are embedded in the video stream

Sync

DATA[11:0]

DATA[11]

DATA[10]

DATA[9]

DATA[8]

DATA[7]

DATA[6]

DATA[5]

DATA[4]

DATA[3]

DATA[2]

DATA[1]

DATA[0]

0H

0L

1H

1L

2H

2L

3H

3L

Cr0[7]

Cr0[6]

Cr0[5]

Cr0[4]

Cr0[3]

Cr0[2]

Cr0[1]

Cr0[0]

Y0[7]

Y0[6]

Y0[5]

Y0[4]

Y0[3]

Y0[2]

Y0[1]

Y0[0]

Cb0[7]

Cb0[6]

Cb0[5]

Cb0[4]

Cb0[3]

Cb0[2]

Cb0[1]

Cb0[0]

Y1[7]

Y1[6]

Y1[5]

Y1[4]

Y1[3]

Y1[2]

Y1[1]

Y1[0]

FMT[1:0] = 10 Reserved

FMT[1:0] = 11 Reserved

38

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TFP6422, TFP6424

PanelBus DIGITAL TRANSMITTER/VIDEO ENCODER COMBO

SLDS118 – MARCH 2000

CLK_CTRL

Subaddress = 3B

Default = 0xAA

7

6

5

4

3

2

1

0

CKINDSK[3:0]

CKENCSE

CKINDSK

Video encoder core clock select

0

The clock signal generated by the on-chip clock generator PLL_Y is selected

to encode the video

1(*) CLKIN is selected to encode the video

[3:0] CLKIN deskew control

0000 –8 T

0001 –7 T

0010 –6 T

0011 –5 T

0100 –4 T

0101 –3 T

0110 –2 T

0111 –T

1000(*) No Skew

1001 T

1010 2 T

1011 3 T

1100 4 T

1101 5 T

1110 6 T

1111 7 T

Where T = approximately 100 ps.

VIDOUT_CTRL

Subaddress = 3C

Default = 0x00/01

7

6

5

4

3

2

1

0

VIDOUT[3:0]

VIDOUT[3:0] Video output mode

0000(*)

0001(*)

0010

0011

0100

0101

0110

DVI

Simultaneous composite and S–video

Composite video

S–video

Interlaced YPrPb component video (525 or 625 lines)

SCART (Simultaneous composite and interlaced RGB)

Progressive RGB

0111

1000

Simultaneous composite and interlaced YPrPb component video

DACs connection testWrite 1000 to test the connection of four DACs. Read the

connection status for each DAC from DACCON[3:0] bits in CON_STATUS

register. See CON_STATUS for details.

1001–1110 Reserved

1111 Power down

VIDOUT[2:0] defaults to 0000 after reset if INT0# pin is pulled high or defaults to 0001 if INT0 pin

is pulled low during reset.

2

I C interface continues to be active in power down modes.

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SYNC_CTRL0

Subaddress = 3D

Default = 0x03

7

6

5

4

3

2

1

0

SYNC_G

FID_POL

VS_FID

HS_COM

VSEN

HSEN

TYSEN

THSEN

THSEN DVI HSYNC enable

0

1(*)

HSYNC is transmitted as 0

HSYNC is transmitted as received from the video port

TVSEN DVI VSYNC enable

0

VSYNC is transmitted as 0

1(*)

VSYNC is transmitted as received from the video port

HSEN

VSEN

HS enable

0(*)

1

HS is in inactive state (LOW)

HS outputs digital horizontal / composite sync

VS enable

0(*)

1

VS is in inactive state (LOW)

VS outputs digital vertical sync

HS_COM HS function select

0(*)

1

HS outputs horizontal sync

HS outputs composite sync

VS_FID VS function select

0(*)

1

VS outputs vertical sync

VS outputs field ID

FID_POL FID polarity

0(*)

1

ODD field = 0 EVEN field = 1

ODD field = 1 EVEN field = 0

SYNC_G RGB sync on green

0(*)

No Sync on Green

1

Sync on Green

CON_STATUS

Subaddress = 3E

Read Only

7

6

5

4

3

2

1

0

DACCON3

DACCON2

DACCON1

DACCON0

HPCON

RXCON

0

1

DVI receiver is not connected

DVI receiver is connected

HPCON

0

1

Hot plug is not connected

Hot plug is connected

DACCON0

DACCON1

DACCON2

DACCON3

0

1

DAC0 output is not connected

DAC0 output is connected

0

1

DAC1 output is not connected

DAC1 is connected

0

1

DAC2 output is not connected

DAC2 output is connected

0

1

DAC3 output is not connected

DAC3 output is connected

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INT_STATUS

Subaddress = 3F

Read Only

7

6

5

4

3

2

1

0

HPEVNT

RXEVNT

HPEVNT

0

1

RXCON bit has not changed

RXCON bit has changed

0

1

HPCON bit has not changed

HPCON bit has changed

To clear a bit, write 1 to the bit to clear. Writing 0 will not change the bit status.

INT_ENABLE

Subaddress = 40

Default = 0x00

7

6

5

4

3

2

1

0

hpen

rxen

RXEN

HPEN

0(*)

1

RXEVNT interrupt disabled

RXEVNT interrupt enabled

0(*)

1

HPEVNT interrupt disabled

HPEVNT interrupt enabled

GP_CTRL

Subaddress = 41

Default = 0x80

7

6

5

4

3

2

1

0

GIO1_EN

Reserved

GP1_IN

GP0_IN

GP1_OE

GP0_OE

GP1_OUT

GP0_OUT

GP0_OUTGeneral-purpose output bit. The state of this bit shows on GPIO0 pin if GP0_OE is set to 1. Otherwise,

GPIO0 pin is 3-stated.

0(*)

1

GPIO0 pin outputs LOW

GPIO0 pin outputs HIGH

GP1_OUTGeneral-purpose output bit. The state of this bit shows on GPIO1 pin if GP1_OE is set to 1. Otherwise,

GPIO1 pin is 3-stated.

0(*)

1

GPIO1 pin outputs LOW

GPIO1 pin outputs HIGH

GP0_OE General-purpose bit output enable.

0(*)

1

GPIO0 output is disabled and 3-stated

GPIO0 output is enabled

GP1_OE General-purpose bit output enable.

0(*)

1

GPIO1 output is disabled and 3-stated.

GPIO1 output is enabled

GP0_IN General-purpose input bit. This bit shows the state of GPIO0 pin.

0(*)

1

GPIO0 pin is LOW

GPIO0 pin is HIGH

GP0_IN General-purpose input bit. This bit shows the state of GPIO1 pin.

0(*)

1

GPIO1 pin is LOW

GPIO1 pin is HIGH

GIO1_EN .GPIO1 pin enable

0(*)

1

HC/CS/GPIO1 outputs Horizontal or composite sync

HC/CS/GPIO1 is used as the second general-purpose I/O pin.

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GIO1_EN

GP1_OUT

GP1_OE

HS_COM

HSEN

VSEN

Pin 45

LOW

HS

0

1

X

0

X

0

1

X

0

1

0

1

X

0

LOW

VS

1

0

HS

1

CS

X

3-state

LOW

3-state

HIGH

0

1

0

1

LLEN

Subaddress = 42

Default = 0x59

7

6

5

4

3

2

1

0

LLEN[7:0]

Subaddress = 43

Default = 0x03

7

6

5

3

0

LLEN[10:8]

LLEN[10:0] Line length or total number of pixels in a scan line including active video and blanking. Total

number of pixels in a scan line = LLEN

FLENS

Subaddress = 44

Default = 0x0C

7

6

5

4

3

2

1

0

FLENS[7:0]

Subaddress = 45

Default = 0x02

7

6

5

4

3

2

1

0

FLENS[10:8]

FLENS[10:0] The frame length or total number of lines in a frame including active video and blanking from

the source image. Total number of lines in a frame from the source image = FLENS + 1

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PLL_X

Subaddress = 46

Default = 0xC9

7

6

5

4

3

2

1

0

PLL_X[7:0]

Subaddress = 47

Default = 0x35

7

6

5

3

PLL_X[15:8]

Subaddress = 48

Default = 0xD9

6

5

3

PLL_X[23:16]

Subaddress = 49

Default = 0x94

6

5

3

PLL_X_SF

PLL_X[29:24]

PLL_X[29:0]

30-bit frequency control for the PLL that generates the internal video encoding clock.

PLL scaling factor

PLL_X_SF[1:0]

Use the following equations to calculate PLL_X:

X = Round (5 × 2^(30 – PLL_X_SF) × Fref/(Fh × LLEN) × (FLENS+1)))

X1 = X × (FLENS+1)

Adjust PLL_X_SF such that 2^30 < X1 <= 2^31

PLL_X = X1–2^30

Where

Fref

Fh

LLEN

= Reference clock = 14.31818 MHz

= Line frequency of the output video

= Length of a scan line in pixels

FLENS+1 = Length of a frame of source image in lines

The reset default values generate an internal 27 MHz video encoding clock.

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PLL_Y

Subaddress = 4A

Default = 0xC9

7

6

5

4

3

2

1

0

PLL_Y[7:0]

Subaddress = 4B

Default = 0x35

7

6

5

3

PLL_Y[15:8]

Subaddress = 4C

Default = 0xD9

6

5

3

PLL_Y[23:16]

Subaddress = 4D

Default = 0x94

6

5

3

PLL_Y_SF

PLL_Y[29:24]

PLL_Y[29:0]

30-bit frequency control for the PLL that generates the video PORT CLKOUT.

PLL_Y_SF scaling factor

PLL_Y_SF[1:0]

Use the following equations to calculate PLL_Y:

For 1X output clock,

Y1 = X × (FLEN+1) × 2^(PLL_X_SF–PLL_Y_SF)

Adjust PLL_F_SF such that 2^30 < Y1 <= 2^31

PLL_Y = Y1–2^30

A clock derived from the CLKOUT with the same frequency must be connected to CLKIN for the

correct operation.

For 2X output clock,

Y1 = X × (FLEN+1) × 2^(PLL_X_SF–PLL_Y_SF–1)

Adjust PLL_F_SF such that 2^31 < Y1 <= 2^30

PLL_Y = Y1–2^30

A clock derived from the CLKOUT with half the frequency must be connected to CLKIN for the

correct operation.

Where:

FLEN +1 = Total number of lines per frame in the output video including active lines and vertical blanking

FLENS+1 = Total number of lines per frame in the input video including active lines and vertical blanking

The reset default values generate a 27 MHz clock on CLKOUT pin.

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PLL_BWRNG

Subaddress = 4E

Default = 0x00

7

6

5

4

3

2

1

0

PLL_BW[1:0]

PLL_ADJ

PLL_SEL

PLL_HI[1:0]

PLL_LO[1:0]

PLL_BW[1:0] PLL filter bandwidth control. PLL_BW[1:0] selects the bandwidth of the PLL loop filter when

TFP6422/6424 is in DVI output mode (VIDOUT[2:0] = 000). The default value is 00 after reset. Users

should always use the default value except when the signal conditions on the reference clock

(CLKIN0 and CLKIN1) are too noisy. The narrower bandwidth results in better noise and jitter

immunity of the reference clock at the expense of longer lock time.

00(*) Normal bandwidth

01

10

11

Wide bandwidth

Narrow bandwidth

Reserved

In nonDVI output modes, PLL_BW[1:0] is ignored and the loop filter bandwidth is fixed internally and

cannot be changed.

PLL_ADJ

PLL range adjustment select

0(*)

1

PLL range adjustment is automatic

PLL range is manually adjusted by programming PLL_SEL, PLL_LO[1:0] and

PLL_HI[1:0]

PLL_SEL

PLL select

0(*)

1

Low–range PLL is selected

High–range PLL is selected

PLL_HI[1:0]

High–range PLL range select

00(*) Highest Frequency

01

10

11

Lowest frequency

PLL_LO[1:0]

Low–range PLL range select

00(*) Highest frequency

01

10

11

Lowest frequency

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PLL_STATUS

Subaddress = 4F

Read Only

7

6

5

4

3

2

1

0

STATUS_HI[2:0]

STATUS_LO[2:0]

STATUS_LO[2:0] Low-range PLL lock status

001

The low-range PLL is not locked due to the selected frequency range being

too low. PLL_LO[1:0] needs to be adjusted to move to a higher frequency

range.

110

The low-range PLL is not locked due to the selected frequency range being too

high. PLL_LO[1:0] needs to be adjusted to move to a lower frequency range.

Other Low-range PLL is locked. Do not adjust PLL_LO[1:0]

STATUS_HI[2:0] High-range PLL lock status

001

110

The high-range PLL is not locked due to the selected frequency range being

toolow. PLL_HI[1:0]needstobeadjustedtomovetoahigherfrequencyrange.

The high-range PLL is not locked due to the selected frequency range being

too high. PLL_HI[1:0] needs to be adjusted to move to a lower frequency

range.

Other Low-range PLL is locked. Do not adjust PLL_HI[1:0]

FIFO_DLY

Subaddress = 50

Default = 0xBC

7

6

5

4

3

2

1

0

FIFO_DLY[7:0]

Subaddress = 51

Default = 0x02

7

6

5

3

FIFO_DLY[15:8]

FIFO_DLY[15:0]

FIFO delay control1

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VRATIOQ2

VRATIOR2

Subaddress = 52

Default = 0x00

7

6

5

4

3

2

1

0

VRATIOR2[7:0]

Subaddress = 53

Default = 0x00

7

6

5

4

3

2

VRATIQR2[4:0]

VRATIOR2[9:8]

VRATIOQ2[4:0]

VRATIOR2[9:0]

Quotient part of the second vertical scaling ratio control

Remainder part of the second vertical scaling ratio control

Internal vertical scaling ratio control = VRATIOQ2 + VRATIOR2/(FLEN+1)

Use the following equations to calculate VRATIOQ2 and VRATIOR2:

VRATIOQ2 = FLOOR (((FLENS+1)/(FLEN+1) –1) * 64)

VRATIOR2 = 64* (FLENS–FLEN) – VRATIOQ * (FLEN+1)

Where

FLEN +1 = Total number of lines per frame in the output video including active lines and vertical

blanking

FLENS+1 = Total number of lines per frame in the input video including active lines and vertical

blanking

FLOOR(X)

returns the greatest integer that is less then X.

VRATIOQ

VRATIOR

Subaddress = 54

Default = 0x00

7

6

5

4

3

2

1

0

VRATIOR[7:0]

Subaddress = 53

Default = 0x00

7

6

5

4

3

VRATIQ[4:0]

VRATIOR[9:8]

VRATIOQ[4:0]

VRATIOR[9:0]

Quotient part of the second vertical scaling ratio control

Remainder part of the second vertical scaling ratio control

Internal vertical scaling ratio control = VRATIOQ + VRATIOR/(FLEN+1)

Use the following equations to calculate VRATIOQ and VRATIOR:

VRATIOQ = FLOOR (((FLENS+1)/(FLEN+1) –1) * 32)

VRATIOR = 32* (FLENS–FLEN) – VRATIOQ * (FLEN+1)

Where

FLEN +1 = Total number of lines per frame in the output video including active lines and vertical

blanking

FLENS+1 = Total number of lines per frame in the input video including active lines and vertical

blanking

FLOOR(X)

returns the greatest integer that is less then X.

47

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VFLTR_CTRL

Subaddress = 56

Default = 0x00

7

6

5

4

3

2

1

0

SC_LOAD

SCBYPS

DEFLKR

INTP

Vertical interpolation control for 5-tap interpolation filter

0(*)

1

Single-phase nearest neighbor

Adaptive 32-phase interpolation

DEFLKR

Vertical deflicker filter cut-off frequency control

000(*) Near all-pass

001

010

011

100

–6dB at 3/8 cycle per line

–6dB at 5/16 cycle per line

–6dB at 1/4 cycle per line

–6dB at 3/16 cycle per line

101–111 Reserved

SCBYPS

Scaler Bypass

0(*)

1

Scaler is enabled

Scaler is bypassed

SC_LOAD

Load bit for scaling related registers to perform overscan compensation

0(*)

1

No effects.

2

Enables the content of the I C registers for overscan compensation to be loaded into the

internal hardware registers. A 0 to 1 transition at SC_LOAD bit will trigger the loading.

SC_LOAD affects the following register bits:

CKENCSE

CKOUTSE

PLL_X [27:0]

PLL_X_SF[1:0]

PLL_Y[27:0]

PLL_Y_SF[1:0]

LLEN[10:0]

LLEN_EN

FLENS[10:0]

VRATIOR[9:0]

VRATIOQ[4:0]

VRATIOR2[9:0]

VRATIOQ2[4:0]

HFLTR_CTRL

Subaddress = 57

Default = 0x00

7

6

5

4

3

2

1

0

CINTP

YINTP

CINTP

Luminance interpolation filter control

0(*)

1

The luminance interpolation filter is enabled

The luminance interpolation filter is bypassed

Chrominance interpolation filter control

00(*) The chrominance interpolation filter is enabled

01

10

11

The first section of the chrominance interpolation filter is bypassed

The second section of the chrominance interpolation filter is bypassed

Both sections of the filter are bypassed

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CC_CARR1,2

Subaddress = 58

Default = 0x31

7

6

5

4

3

2

1

0

FCC[7:0]

Subaddress = 59

Default = 0x26

7

6

5

3

FCC[15:8]

FCC[15:0]

Close caption carrier frequency control

For 60 Hz system,

FCC = 2^18* 0.5035*10^6/(LLEN*Fh)

For 50 Hz systems,

FCC = 2^18* 0.500*10^6/(LLEN*Fh)

Where

LLEN = Total number of pixels in a scan line

Fh = Line frequency

C_PHASE

Subaddress = 5A

Default = 0x00

7

6

5

4

3

2

1

0

CPHS[7:0]

Phase of the encoded video color subcarrier (including the color burst) relative to H–sync. The

adjustable step is 360/256 degrees.

GAIN_U

Subaddress = 5B

Default = 0x02

7

6

5

4

3

2

1

0

GU[7:0]

Gain control for Cb signal. The MSB, GU[8], is located at subaddress 5D, bit 7. Following are typical

programming examples for NTSC and PAL standards.

NTSC with 7.5 IRE pedestal:

NTSC with no pedestal:

PAL with no pedestal:

WHITE – BLACK = 92.5 IRE

WHITE – BLACK = 100 IRE

GAIN_U = 0x102

GAIN_U = 0x117

GAIN_U = 0x111

GAIN_V

Subaddress = 5C

Default = 0x6C

7

6

5

4

3

2

1

0

GV[7:0]

GU[7:0]

Gain control for Cr signal. The MSB, GV[8], is located at subaddress 5E, bit 7. Following are typical

programming examples for NTSC and PAL standards.

NTSC with 7.5 IRE pedestal:

NTSC with no pedestal:

PAL with no pedestal:

WHITE – BLACK = 92.5 IRE

WHITE – BLACK = 100 IRE

GAIN_V = 0x16C

GAIN_V = 0x189

GAIN_V = 0x181

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BLACK_LEVEL

Subaddress = 5D

Default = 0xC3

7

6

5

4

3

2

1

0

GU[8]

BLACK[6:0]

GU[8]

The most significant bit of Gain_U register. See Gain_U register for more details.

BLACK[6:0]

Black level setting. Following are typical programming examples for NTSC/PAL standards.

NTSC with 7.5 IRE pedestal:

NTSC with no pedestal:

PAL with no pedestal:

WHITE – BLACK = 92.5 IRE

WHITE – BLACK = 100 IRE

BLACK_LEVEL = 0x43

BLACK_LEVEL = 0x38

BLACK_LEVEL = 0x3B

BLANK_LEVEL

Subaddress = 5E

Default = 0xB8

7

6

5

4

3

2

1

0

GV[8]

BLANK[6:0]

GV[8]

The most significant bit of Gain_V register. See Gain_V register for more details.

BLANK[6:0]

Blank level setting. Following are typical programming examples for NTSC/PAL standards.

NTSC with 7.5 IRE pedestal:

NTSC with no pedestal:

PAL with no pedestal:

WHITE – BLACK = 92.5 IRE

WHITE – BLACK = 100 IRE

BLANK_LEVEL = 0x38

BLANK_LEVEL = 0x3B

GAIN_Y

Subaddress = 5F

Default = 0x2F

7

6

5

4

3

2

1

0

GY[7:0]

GU[7:0]

Gain control for Y signal. The MSB, bit 8, is located at address 60, bit 5. Following are typical

programming examples for NTSC and PAL standards.

NTSC with 7.5 IRE pedestal:

NTSC with no pedestal:

PAL with no pedestal:

WHITE – BLACK = 92.5 IRE

WHITE – BLACK = 100 IRE

GAIN_Y = 0x12F

GAIN_Y = 0x147

GAIN_Y = 0x140

ANALOG

VIDEO

OUTPUT

TYPE

PEAK

WHITE

IRE/mV

UV

SYNC

IRE/mV

SETUP

IRE/mV

EXCURSION Y_GAIN U_GAIN V_GAIN BLACK_LEVEL BLANK_LEVEL

(mV)

–40(286)

–43(300)

–40(286)

–43(300)

–40(286)

–43(300)

7.5(54)

0(0)

100

–

0x12F

0x147

0x140

0x12F

0x147

0x140

0x12F

0x147

0x140

0x102

0x117

0x111

0x102

0x117

0x111

0x16C

0x189

0x181

0x16C

0x189

0x181

0x43

0x38

0x3B

0x43

0x38

0x3B

0x43

0x38

0x3B

0x38

0x3B

0x38

0x3B

0x38

0x3B

Composite

or

S-video

–

0(0)

–

7.5(54)

0(0)

±330

±357

±350

0(0)

YPrPb

7.5(54)

0(0)

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X_COLOR

Subaddress = 4D

Default = 0x94

7

6

5

4

3

2

1

0

XCE

GU[8]

XCBW[1:0]

LCD[2:0]

Cross Color and Chroma delay compensation register.

XCE Cross color reduction enable for composite video output. Cross color does not affect S-video output

0(*)

1

Cross color reduction is disabled

Cross color is enabled

XCBW[1:0] Cross color reduction filter selection

00

01

10

11

The notch is at 32.8 % of the frequency of the encoding pixel clock

The notch is at 26.5 % of the frequency of the encoding pixel clock

The notch is at 30.0 % of the frequency of the encoding pixel clock

The notch is at 29.2 % of the frequency of the encoding pixel clock

LCD[2:0]

These three bits can be used for chroma channel delay compensation. Table below shows the delay

corresponding to LCD[2:0] settings.

LCD[2:0]

DELAY ON LUMA CHANNEL

0

1

0

1

X

0

1

0

1

X

0.5 pixel clock period

1.0 pixel clock period

1.5 pixel clock period

2.0 pixel clock period

M_CONTROL

Subaddress = 61

Default = 0x05

7

6

5

4

3

2

1

0

PALPHS

CBW[2:0]

PAL

FFRQ

Mode control register. This register provides various operating mode controls including DAC power management.

PALPHS

PAL switch phase setting

0(*)

1

PAL switch phase is nominal

PAL switch phase is inverted compared to nominal

CBW[2:0]

Chrominance lowpass filter bandwidth control

000(*)–6db at 21.8 % of encoding pixel clock frequency

001

010

011

100

101

110

111

–6db at 19.8 % of encoding pixel clock frequency

–6db at 18.0 % of encoding pixel clock frequency

Reserved

–6db at 23.7 % of encoding pixel clock frequency

–6db at 26.8 % of encoding pixel clock frequency

Chrominance lowpass filter bypass

PAL

Phase alternation line encoding selection

0(*)

1

Phase alternation line encoding disabled

Phase alternation line encoding enabled

FFRQ

Field rate selection.

0

1(*)

50 Hz

60 Hz

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BSTAMP

Subaddress = 62

Default = 0x38

7

6

5

4

3

2

1

0

SQP

BSTAP[6:0]

Color burst amplitude.

SQP Square-pixel sampling rate.

0(*)

1

CCIR601 sampling rate

Square-pixel sampling rate

BSTAP[6:0]

Setting of amplitude of color burst.

The SQP and FFRQ bits determine the total number of horizontal pixels displayed per scan line as shown in the

following register.

MODE

SQP

FFRQ

NO. OF PIXEL PER LINE

CCIR601 PAL

0

1

0

1

0

1

864

858

944

780

CCIR601 NTSC

Square pixel PAL

Square pixel NTSC

S_CARR1,2,3,4

Subaddress = 63.64.65,66

Default = 0x1F, 0x7C, 0xF0, 0x21

7

6

5

4

3

2

1

0

FCS[7:0]

FSC[15:8]

FSC[23:16]

FSC[31:24]

Color Subcarrier Frequency Registers.

FSC[31:0] These four bytes’ data are used to program color subcarrier frequency. These four bytes are

determined by the following formula.

32

S_CARR = ROUND((Fsc/Fclkenc) * 2

)

Where Fsc

= Frequency of the subcarrier

Fclkenc= Frequency of the internal video encoding clock

= 2*LLEN *Fh

LLEN = Number of pixels in a scan line

Fh

= Line frequency

Refer to the description of LLEN registers (subaddresses 0x42 and 0x43).

The following register lists some common values for S_Carr.

SUBCARRIER FREQUENCY

STANDARD

PIXEL TYPE

Fclkin

S_Carr (Dec) S_Carr (Hex)

(Fsc)

M/NTSC

Rectangular

Square

3.579545 MHz

27 MHz 569408543(*)

21F07C1F

2A098ACB

21F69446

21E6EFE3

25555555

26798C0C

1F15C01E

254AD4AD

B,D,G,H,I,N/PAL

N/PAL; Argentina

4.43361875 MHz

3.58205625 MHz

3.5756083125 MHz

3.579545 MHz

27 MHz

705268427

569807942

568782819

626349397

645499916

521519134

625661101

27 MHz

M/NTSC

24.5454 MHz

29.50 MHz

24.5454 MHz

B,D,G,H,I,N/PAL

N/PAL; Argentina

Square

4.43361875 MHz

3.58205625 MHz

3.5756083125 MHz

Square

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SUBCARRIER FREQUENCY

(Fsc)

CLOCK

(Fclock)

S_Carr

(Dec)

S_Carr

(Hex)

PIXEL TYPE

Rectangular

Square

3.5795452 MHz

4.43361875 MHz

3.58205625 MHz

3.5756083125 MHz

3.579545 MHz

27 MHz

569408543(*)

705268427

569807942

568782819

626349397

645499916

521519134

625661101

21F07C1F

2A098ACB

21F69446

21E6EFE3

25555555

26798C0C

1F15C01E

254AD4AD

27 MHz

24.5454 MHz

29.50 MHz

24.5454 MHz

Square

4.43361875 MHz

3.58205625 MHz

3.5756083125 MHz

Square

LINE21_O0

Subaddress = 67

Default = 0x00

7

6

5

4

3

2

1

0

L21O[7:0]

The least significant byte of the closed caption data in the odd field.

LINE21_O1

Subaddress = 68

Default = 0x00

7

6

5

4

3

2

L21O[15:8]

The most significant byte of the closed caption data in the odd field.

LINE21_E0

Subaddress = 69

Default = 0x00

7

6

5

4

3

2

1

0

L21E[15:8]

L21E[7:0]

The least significant byte of the extended service data in the even field.

LINE21_E1

Subaddress = 6A

Default = 0x00

7

6

5

4

3

2

1

0

L21E[15:8]

The least significant byte of the extended service data in the even field.

LN_SEL

Subaddress = 6B

Default = 0x0B

7

6

5

4

3

2

SLINE[4:0]

Selects the line where closed caption or extended service data are encoded.

L21

Subaddress = 6D

Default = 0x00

7

6

5

4

3

2

1

L21ENA

L21ENB

L21ENA

L21ENB

This bit controls the closed caption encoding. See following register for programming information.

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L21ENA

L21ENB

Line21 ENCODING MODE

Line21 encoding OFF

0(*)

0

0(*)

1

st

Enables encoding in 1 field (odd field)

nd

1

0

Enables encoding in 2 field (even field)

1

Enables encoding in both fields

HTRIGGER0

Subaddress = 6E

Default = 0x00

7

6

5

4

3

2

1

0

HTRIG[7:0]

LSB of horizontal trigger phase, which sets HSYNC. HTRIG is expressed in half-pixels or clk2x

periods.

HTRIGGER1

Subaddress = 6F

Default = 0x00

7

6

5

4

3

2

1

0

HTRIG[10:8]

HTRIG[11:8]

MSB of horizontal trigger phase, which sets HSYNC. HTRIG is expressed in half-pixels or clk2x

periods.

VTRIGGER0

Subaddress = 70

Default = 0x00

7

6

5

4

3

2

1

0

VTRIG[7:0]

Subaddress = 71

Default = 0xC0

7

6

5

PRESA

PRESB

SBLANK

VTRIG[9:8]

PRESA

PRESB

Phase reset A. Used as shown in the register below.

Phase reset B. Used as shown in the register below. Color subcarrier phase is reset to C_Phase

(subaddress 5A) upon reset.

SBLANK

Vertical blanking setting

0(*)

1

Vertical blanking is defined by the setting of FAL and LAL registers.

Vertical blanking is forced automatically during field synchronization and equalization.

VTRIG[9:0]

Vertical trigger reference for VSYNC. These bits specify the phase between VSYNC input and the

lines in a field. The VTRIG field is expressed in units of half-line.

PRESA

PRESB

PHASE RESET MODE

0

1

No resest

Reset every two lines

Reset every eight fields

Reset every four fields

1

0

1(*)

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BAVID

Subaddress = 77

Default = 0x00

7

6

5

4

3

2

1

0

BAVID[7:0]

Beginning of active video.

BAVID[7:0]

EAVID

Subaddress = 78

5

Default = 0x00

7

6

4

3

2

1

0

EAVID[7:0]

End of active video.

EAVID[7:0]

BEAVID

Subaddress = 79

Default = 0x00

7

6

5

EAVID[10:8]

4

3

2

1

BAVID[10:8]

0

Overflow register for BAVID and EAVID fields.

FLEN

Subaddress = 7A

Default = 0x0C

7

6

5

3

1

FLEN[7:0]

Field Length

FLEN[7:0] These bits define the number of half_lines in each field. The upper 2 bits of this register are located in

FLAL register.

Length of field = (FLEN + 1) half_lines

FAL

Subaddress = 7B

Default = 0x12

7

6

5

4

3

2

1

0

FAL[7:0]

First Active Line of Field

FAL[7:0]

These bits define the first active line of a field. The MSB is located in register FLAL.

LAL

Subaddress = 7C

Default = 0x03

7

6

5

4

3

2

1

0

LAL[7:0]

Last Active Line of Field

LAL[7:0]

These bits define the last active line of a field. The MSB is located in register FLAL.

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flal

Subaddress = 7d

Default = 0x22

7

6

5

4

3

2

1

0

LAL[8]

FAL[8]

FLEM[9:8]

Overflow bits from FLEN, FAL and LAL Registers.

LAL[8]

FAL[8]

These bits define the last active line of a field. The LSB is located in register LAL.

These bits define the first active line of a field. The LSB is located in register FAL.

FLEN[9:8] These bits define the number of half_lines in each field. The lower 8 bits of this register are located in

FLEN register.

SYN_CTRL1

Subaddress = 7E

Default = 0x00 or 0x80

7

6

5

4

3

2

1

0

FREE

ESAV

IGNP

NBLNKS

VBLKM[1:0]

HBLKM[1:0]

FREE

Free running

0(*)

1(*)

Free running disabled.

Free running enabled. HSYNC and VSYNC are ignored.

Reset to 0 if the CBAR pin is high upon reset otherwise reset to 1.

ESAV

Enable to detect F and V bits only on EAV in CCIR656 input mode

0(*)

1

Detection of F and V bits on both EAV and SAV

Detection of F and V bits only on EAV.

IGNP

Ignore protection bits in CCIR656 input mode

0(*)

1

Protection bits are not ignored.

Protection bits are ignored

NBLNKS

Blank shaping

0(*)

1

Blank shaping enabled

Blank shaping disabled

VBLKM[1:0] Vertical blanking mode

00(*) Internal default blanking

01

10

11

Internal default blanking AND internal programmable blanking defined by FAL and LAL

Internal blanking and external blanking defined by BLANK

Internal blanking AND internal programmable blanking defined by FAL

and LAL AND external blanking defined by BLANK

HBLKM[1:0] Horizontal blanking mode

00(*) Internal default blanking

01

10

11

Internal programmable blanking defined by SAVID and EAVID

External blanking defined by BLANK

Internal programmable blanking defined by SAVID and EAVID

AND external blanking defined by BLANK

BORDER_Y

Subaddress = 7F

Default = 0x10

7

6

5

4

3

2

1

0

BORDER_Y[7:0]

BORDER_Y[7:0] Y component of the border color

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BORDER_CR

Subaddress = 80

Default = 0x80

7

6

5

4

3

2

1

0

BORDER_CR[7:0]

BORDER_CR[7:0] CR component of the border color

BORDER_CB

Subaddress = 81

Default = 0x80

7

6

5

4

3

BORDER_CB[7:0]

BORDER_CB[7:0] CB component of the border color

BPIX

Subaddress = 82

Default = 0x4A

7

6

5

4

3

BPIX[7:0]

BPIX[10:0] Begin of pixels. Defines the location in a line where the first pixel appears. Only applicable when the

inputpixelsareinprogressivemode. BAPIX[10:0]isignoredwhentheinputpixelsareininterlacemode.

MV_REG0~MV_REG31

Subaddress = 90:A1

Default = 0x00

7

6

5

4

3

2

1

0

MV_REG[0:17]

In TFP6422, registers to control the Macrovision 7.11 copy protection process.

In TFP6424, any access, read or write to these registers will shut down all four outputs of the

DACs.

PLL_TST0

Subaddress = B0

7

6

5

4

3

2

1

0

PLL_FTR[7:0]

PLL_FTR[7:0] PLL Filter control

PLL_TST1

Subaddress = B1

7

6

5

0

PLL_TST1 Subaddress = B2

PLL_TST3 Subaddress = B3

Macrovision is a trademark of Macrovision Corporation

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FUS_TST0–3

Subaddress = B4–B7

7

6

5

4

3

2

1

0

FUSEA[7:0]

7

6

5

FUSEA[15:8]

7

6

5

4

3

2

1

0

FUSEB[7:0]

FUSEB[15:8]

TMDS_TST0

TMDS_TST1

TMDS_TST2

TMDS_TST3

TMDS_TST4

TMDS_TST5

TMDS_TST6

TMDS_TST7

TMDS_TST8

TMDS_TST9

TMDS_TST10

TMDS_TST11

TMDS_TST12

TMDS_TST13

TMDS_TST14

TMDS_TST15

Subaddress = C0

Subaddress = C1

Subaddress = C2

Subaddress = C3

Subaddress = C4

Subaddress = C5

Subaddress = C6

Subaddress = C7

Subaddress = C8

Subaddress = C9

Subaddress = CA

Subaddress = CB

Subaddress = CC

Subaddress = CD

Subaddress = CE

Subaddress = CF

DAC_TST

Subaddress = D0

Default = 0x00

7

6

5

4

3

2

1

0

DAC_DX

DACX3

DACX2

DACX1

DACX0

DAC_DX

Direct DAC output

0*

1

DACs are in normal operation

Video port DATA[9:0] is directly connected to DACs for testing output. DACX[3:0] will select

which DACs to output.

DACX3

DACX2

DACX1

DACX0

0

1

DAC3 at pin 40 is shut down

DAC3 outputs DATA [9:0]

0

1

DAC2 at pin 41 is shut down

DAC2 outputs DATA [9:0]

0

1

DAC1 at pin 43 is shut down

DAC1 outputs DATA [9:0]

0

1

DAC0 at pin 44 is shut down

DAC0 outputs DATA [9:0]

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PowerPAD 64TQFP package

The TFP6422/6424 is packaged in TIs thermally enhanced PowerPAD 64TQFP packaging. The PowerPAD

package is a 10 mm x 10 mm x 1.4mm TQFP outline with 0.5mm lead-pitch. The PowerPAD package has a

specially designed die mount pad that offers improved thermal capability over typical TQFP packages of the

same outline. The TI 64TQFP PowerPAD package offers a backside solder plane that connects directly to the

die mount pad for enhanced thermal conduction. The system designer has the option to solder this backside

plane to a thermal/ ground plane on the PCB. Since the die pad is electrically connected to the TFP6422/6424

chip substrate and hence ground, the backside PowerPAD connection to a PCB ground plane can improve

ground bounce and power supply noise.

The connection of the PowerPAD to a PCB thermal/ground plane is purely optional.

The following table outlines the thermal properties of the TI 64-TQFP PowerPAD package. The 64-TQFP

non-PowerPAD package is included only for reference.

TI 64-TQFP (10 × 10 × 1.4 mm)/0.5 mm lead-pitch

POWERPAD

NOT CONNECTED TO PCB

THERMAL PLANE

PowerPAD

CONNECTED TO PCB

PARAMETER

WITHOUT PowerPAD

†

THERMAL PLANE

17.3°C/W

0.12°C/W

4.3 W

†‡

Theta–JA

45°C/W

3.11°C/W

1.6 W

27.3°C/W

0.12°C/W

2.7 W

†‡

Theta–JC

†‡§

Maximum power dissipation

Maximum TFP6422 pixel rate

TBD

†

‡

§

Specified with 2 oz. Cu PCB plating.

Airflow is at 0 LFM (no airflow)

Measured at ambient temperature, T = 70°C.

A

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MECHANICAL DATA

PAP (S-PQFP-G64)

PowerPAD PLASTIC QUAD FLATPACK

0,27

0,17

M

0,50

48

0,08

33

49

32

Thermal Pad

(See Note D)

64

17

0,13 NOM

1

16

7,50 TYP

Gage Plane

10,20

SQ

9,80

12,20

SQ

0,25

11,80

0,15

0,05

0°–7°

1,05

0,95

0,75

0,45

Seating Plane

0,08

1,20 MAX

4147702/A 01/98

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Body dimensions do not include mold flash or protrusion.

D. The package thermal performance may be enhanced by bonding the thermal pad to an external thermal plane.

This pad is electrically and thermally connected to the backside of the die and possibly selected leads.

E. Falls within JEDEC MS-026

PowerPAD is a trademark of Texas Instruments.

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APPENDIX A

T.M.D.S. encoding for control characteris and 8-bit pixel data

For each input code, 2 output codes are possible. The DVI transmitter keeps track of the number of ones and

zeros sent and transmits the character that best approximates a dc balance.

2–BIT CONTROL TO T.M.D.S. CHARACTER ENCODING.

(DE= Low)

HSYNC

CTL0

VSYNC

CTL1

T.M.D.S. 10–bit character

(LSB – MSB)

CTL2

CTL3

0

1

0

1

0

1

0010101011

1101010100

0010101010

1101010101

8–BIT PIXEL DATA TO T.M.D.S. CHARACTER ENCODING (DE = High)

T.M.D.S. CHARACTER PIXEL

Binary

PIXEL

Binary

T.M.D.S. CHARACTER

Char1

Char2

Char1

Char2

Dec.

msb–lsb

00000000

00000001

00000010

00000011

00000100

00000101

00000110

00000111

00001000

00001001

00001010

00001011

00001100

00001101

00001110

00001111

00010000

00010001

00010010

00010011

00010100

00010101

00010110

00010111

00011000

lsb – msb

0100000000

0111111111

0111111110

0100000001

0111111100

0100000011

0100000010

0111111101

0111111000

0100000111

0100000110

0111111001

0100000100

0111111011

0111111010

0100000101

0111110000

0100001111

0100001110

0111110001

0100001100

0111110011

0111110010

0100001101

0100001000

lsb – msb

msb–lsb

10000000

10000001

10000010

10000011

10000100

10000101

10000110

10000111

10001000

10001001

10001010

10001011

10001100

10001101

10001110

10001111

10010000

10010001

10010010

10010011

10010100

10010101

10010110

10010111

10011000

lsb – msb

1101111111

1110000000

1110000001

1101111110

1110000011

1101111100

1101111101

1110000010

1110000111

1101111000

1101111001

1110000110

1101111011

1110000100

1000101111

1011010000

1110001111

1101110000

1101110001

1110001110

1101110011

1110001100

1000100111

1011011000

1101110111

0

1

1111111111

1100000000

1100000001

1111111110

1100000011

1111111100

1111111101

1100000010

1100000111

1111111000

1111111001

1100000110

1111111011

1100000100

1100000101

1111111010

1100001111

1111110000

1111110001

1100001110

1111110011

1100001100

1100001101

1111110010

1111110111

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

145

146

147

148

149

150

151

152

0110000000

0101111111

0101111110

0110000001

0101111100

0110000011

0110000010

0101111101

0101111000

0110000111

0110000110

0101111001

0110000100

0101111011

0011010000

0000101111

0101110000

0110001111

0110001110

0101110001

0110001100

0101110011

0011011000

0000100111

0110001000

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

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8–BIT PIXEL DATA TO T.M.D.S. CHARACTER ENCODING (DE = High)

PIXEL

Binary

T.M.D.S. CHARACTER

PIXEL

T.M.D.S. CHARACTER

Char1

Char2

Binary

Char1

Char2

Dec.

msb–lsb

00011001

00011010

00011011

00011100

00011101

00011110

00011111

00100000

00100001

00100010

00100011

00100100

00100101

00100110

00100111

00101000

00101001

00101010

00101011

00101100

00101101

00101110

00101111

00110000

00110001

00110010

00110011

00110100

00110101

00110110

00110111

00111000

00111001

00111010

00111011

00111100

00111101

00111110

00111111

lsb – msb

0111110111

0111110110

0100001001

0111110100

0100001011

0010100000

0001011111

0111100000

0100011111

0100011110

0111100001

0100011100

0111100011

0111100010

0100011101

0100011000

0111100111

0111100110

0100011001

0111100100

0100011011

0010110000

0001001111

0100010000

0111101111

0111101110

0100010001

0111101100

0100010011

0010111000

0001000111

0111101000

0100010111

0010111100

0001000011

0010111110

0001000001

0001000000

0010111111

lsb – msb

msb–lsb

10011001

10011010

10011011

10011100

10011101

10011110

10011111

10100000

10100001

10100010

10100011

10100100

10100101

10100110

10100111

10101000

10101001

10101010

10101011

10101100

10101101

10101110

10101111

10110000

10110001

10110010

10110011

10110100

10110101

10110110

10110111

10111000

10111001

10111010

10111011

10111100

10111101

10111110

10111111

lsb – msb

1110001000

1000100011

1011011100

1000100001

1011011110

1011011111

1000100000

1110011111

1101100000

1101100001

1110011110

1101100011

1110011100

1000110111

1011001000

1101100111

1110011000

1000110011

1011001100

1000110001

1011001110

1011001111

1000110000

1101101111

1110010000

1000111011

1011000100

1000111001

1011000110

1011000111

1000111000

1000111101

1011000010

1011000011

1000111100

1011000001

1000111110

1000111111

1011000000

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

1100001000

1100001001

1111110110

1100001011

1111110100

1001011111

1010100000

1100011111

1111100000

1111100001

1100011110

1111100011

1100011100

1100011101

1111100010

1111100111

1100011000

1100011001

1111100110

1100011011

1111100100

1001001111

1010110000

1111101111

1100010000

1100010001

1111101110

1100010011

1111101100

1001000111

1010111000

1100010111

1111101000

1001000011

1010111100

1001000001

1010111110

1010111111

1001000000

153

154

155

156

157

158

159

160

161

162

163

164

165

166

167

168

169

170

171

172

173

174

175

176

177

178

179

180

181

182

183

184

185

186

187

188

189

190

191

0101110111

0011011100

0000100011

0011011110

0000100001

0000100000

0011011111

0101100000

0110011111

0110011110

0101100001

0110011100

0101100011

0011001000

0000110111

0110011000

0101100111

0011001100

0000110011

0011001110

0000110001

0000110000

0011001111

0110010000

0101101111

0011000100

0000111011

0011000110

0000111001

0000111000

0011000111

0011000010

0000111101

0000111100

0011000011

0000111110

0011000001

0011000000

0000111111

62

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TFP6422, TFP6424

PanelBus DIGITAL TRANSMITTER/VIDEO ENCODER COMBO

SLDS118 – MARCH 2000

8–BIT PIXEL DATA TO T.M.D.S. CHARACTER ENCODING (DE = High)

PIXEL

Binary

T.M.D.S. CHARACTER

PIXEL

T.M.D.S. CHARACTER

Char1

Char2

Binary

Char1

Char2

Dec.

msb–lsb

01000000

01000001

01000010

01000011

01000100

01000101

01000110

01000111

01001000

01001001

01001010

01001011

01001100

01001101

01001110

01001111

01010000

01010001

01010010

01010011

01010100

01010101

01010110

01010111

01011000

01011001

01011010

01011011

01011100

01011101

01011110

01011111

01100000

01100001

01100010

01100011

01100100

01100101

01100110

lsb – msb

0111000000

0100111111

0100111110

0111000001

0100111100

0111000011

0111000010

0100111101

0100111000

0111000111

0111000110

0100111001

0111000100

0100111011

0010010000

0001101111

0100110000

0111001111

0111001110

0100110001

0111001100

0100110011

0010011000

0001100111

0111001000

0100110111

0010011100

0001100011

0010011110

0001100001

0001100000

0010011111

0100100000

0111011111

0111011110

0100100001

0111011100

0100100011

0010001000

lsb – msb

msb–lsb

11000000

11000001

11000010

11000011

11000100

11000101

11000110

11000111

11001000

11001001

11001010

11001011

11001100

11001101

11001110

11001111

11010000

11010001

11010010

11010011

11010100

11010101

11010110

11010111

11011000

11011001

11011010

11011011

11011100

11011101

11011110

11011111

11100000

11100001

11100010

11100011

11100100

11100101

11100110

lsb – msb

1110111111

1101000000

1101000001

1110111110

1101000011

1110111100

1000010111

1011101000

1101000111

1110111000

1000010011

1011101100

1000010001

1011101110

1011101111

1000010000

1101001111

1110110000

1000011011

1011100100

1000011001

1011100110

1011100111

1000011000

1000011101

1011100010

1011100011

1000011100

1011100001

1000011110

1000011111

1011100000

1101011111

1110100000

1000001011

1011110100

1000001001

1011110110

1011110111

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

100

101

102

1100111111

1111000000

1111000001

1100111110

1111000011

1100111100

1100111101

1111000010

1111000111

1100111000

1100111001

1111000110

1100111011

1111000100

1001101111

1010010000

1111001111

1100110000

1100110001

1111001110

1100110011

1111001100

1001100111

1010011000

1100110111

1111001000

1001100011

1010011100

1001100001

1010011110

1010011111

1001100000

1111011111

1100100000

1100100001

1111011110

1100100011

1111011100

1001110111

192

193

194

195

196

197

198

199

200

201

202

203

204

205

206

207

208

209

210

211

212

213

214

215

216

217

218

219

220

221

222

223

224

225

226

227

228

229

230

0101000000

0110111111

0110111110

0101000001

0110111100

0101000011

0011101000

0000010111

0110111000

0101000111

0011101100

0000010011

0011101110

0000010001

0000010000

0011101111

0110110000

0101001111

0011100100

0000011011

0011100110

0000011001

0000011000

0011100111

0011100010

0000011101

0000011100

0011100011

0000011110

0011100001

0011100000

0000011111

0110100000

0101011111

0011110100

0000001011

0011110110

0000001001

0000001000

63

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TFP6422, TFP6424

PanelBus DIGITAL TRANSMITTER/VIDEO ENCODER COMBO

SLDS118 – MARCH 2000

8–BIT PIXEL DATA TO T.M.D.S. CHARACTER ENCODING (DE = High)

PIXEL

Binary

T.M.D.S. CHARACTER

PIXEL

T.M.D.S. CHARACTER

Char1

Char2

Binary

Char1

Char2

Dec.

msb–lsb

01100111

01101000

01101001

01101010

01101011

01101100

01101101

01101110

01101111

01110000

01110001

01110010

01110011

01110100

01110101

01110110

01110111

01111000

01111001

01111010

01111011

01111100

01111101

01111110

01111111

lsb – msb

0001110111

0111011000

0100100111

0010001100

0001110011

0010001110

0001110001

0001110000

0010001111

0111010000

0100101111

0010000100

0001111011

0010000110

0001111001

0001111000

0010000111

0010000010

0001111101

0001111100

0010000011

0001111110

0010000001

0010000000

0001111111

lsb – msb

msb–lsb

11100111

11101000

11101001

11101010

11101011

11101100

11101101

11101110

11101111

11110000

11110001

11110010

11110011

11110100

11110101

11110110

11110111

11111000

11111001

11111010

11111011

11111100

11111101

11111110

11111111

lsb – msb

1000001000

1000001101

1011110010

1011110011

1000001100

1011110001

1000001110

1000001111

1011110000

1000000101

1011111010

1011111011

1000000100

1011111001

1000000110

1000000111

1011111000

1011111101

1000000010

1000000011

1011111100

1000000001

1011111110

1011111111

1000000000

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

1010001000

1100100111

1111011000

1001110011

1010001100

1001110001

1010001110

1010001111

1001110000

1100101111

1111010000

1001111011

1010000100

1001111001

1010000110

1010000111

1001111000

1001111101

1010000010

1010000011

1001111100

1010000001

1001111110

1001111111

1010000000

231

232

233

234

235

236

237

238

239

240

241

242

243

244

245

246

247

248

249

250

251

252

253

254

255

0011110111

0011110010

0000001101

0000001100

0011110011

0000001110

0011110001

0011110000

0000001111

0011111010

0000000101

0000000100

0011111011

0000000110

0011111001

0011111000

0000000111

0000000010

0011111101

0011111100

0000000011

0011111110

0000000001

0000000000

0011111111

64

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

IMPORTANT NOTICE

Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue

any product or service without notice, and advise customers to obtain the latest version of relevant information

to verify, before placing orders, that information being relied on is current and complete. All products are sold

subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those

pertaining to warranty, patent infringement, and limitation of liability.

TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in

accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent

TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily

performed, except those mandated by government requirements.

Of course, customers are responsible for their applications using TI components.

In order to minimize risks associated with the customer’s applications, adequate design and operating

safeguards must be provided by the customer to minimize inherent or procedural hazards.

TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent

that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other

intellectual property right of TI covering or relating to any combination, machine, or process in which such

semiconductor products or services might be or are used. TI’s publication of information regarding any third

party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.


型号：	TFP6422PAP
厂家：	TEXAS INSTRUMENTS
描述：	SPECIALTY CONSUMER CIRCUIT, PQFP64, 10 X 10 MM, 1.40 MM HEIGHT, 0.50 MM PITCH, THERMALLY ENHANCED, POWER, PLASTIC, TQFP-64 商用集成电路
文件：	总65页 (文件大小：813K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TFP6422PAP [TI]

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