TLC6A598_技术文档

TLC6A598

ZHCSNT5C –JUNE 2021 –REVISED MARCH 2022

TLC6A598 电源逻辑8 位移位寄存器

1 特性

3 说明

• 具有高可靠性和稳健性，适合航空电子设备应用

• 宽工作环境温度范围：-55°C 至+125ºC

• 3V 至5.5V 的宽V_CC范围

TLC6A598 器件是一款单片、高压、高电流功率 8 位

移位寄存器，专为负载功率要求相对较高的系统（例

如，LED）而设计。

• 八个电源DMOS 晶体管输出通道

该器件包含内置的输出钳位电压，用于提供电感瞬态保

护。电源驱动器应用包括继电器、螺线管和其他高电流

或高电压负载。每个开漏 DMOS 晶体管都具有独立的

斩波限流电路，以防止在短路情况下损坏。

– 350 mA 持续电流

– 1.1A 电流限制能力

– 输出钳位电压，50V

– 低R_ds(on)，1Ω（典型值）

– 雪崩能量，90mJ（最大值）

• 保护

此器件包含一个 8 位串入、并出移位寄存器，此寄存

器为一个 8 位 D 类存储寄存器提供数据。输出为低

侧、漏极开路 DMOS 晶体管，额定输出为 50V，连续

灌电流能力为 350mA。内置负载开路和负载短路诊断

机制提供增强的安全保护。器件提供循环冗余校验，以

验证移位寄存器中的寄存器值。在读回模式中，该器件

提供 6 位 CRC 提醒。MCU 可以读回 CRC 提醒并检

查该提醒是否正确，以确定 MCU 与该器件之间的通信

环路是否良好。

– 过流保护

– 开路和短路负载检测

– 串行接口通信误差检测

– 热关断保护

• 针对多级的增强型级联

• 所有寄存器通过单个输入清零

• 循环冗余校验(CRC)

• 低功耗

TLC6A598 的额定工作环境温度范围为 -55°C 至

125°C。

• 24 引脚SOIC DW 封装

2 应用

器件信息⁽¹⁾

• 飞行控制系统

• PLC 控制和功能指示器

• 仪表组

封装尺寸（标称值）

器件型号

TLC6A598

封装

SOIC (24)

15.70 mm x 7.50 mm

(1) 如需了解所有可用封装，请参阅产品说明书末尾的可订购产品

附录。

• 继电器或螺线管驱动器

• 电器显示面板

• LED 指示和照明

Power

5

V

Injectors or

Solenoids

0.1 μF

LEDs

VCC

G

DRAIN0

DRAIN1

DRAIN2

DRAIN3

DRAIN4

DRAIN5

DRAIN6

DRAIN7

SER OUT

RCK

SRCK

SER IN

SRCLR

MCU

Relays

PGND

LGND

典型应用原理图

本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问

www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SLIS187

TLC6A598

ZHCSNT5C –JUNE 2021 –REVISED MARCH 2022

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Table of Contents

8.4 Device Functional Modes..........................................18

8.5 Register Maps...........................................................18

9 Application and Implementation..................................22

9.1 Application Information............................................. 22

9.2 Typical Application 1................................................. 22

9.3 Typical Application 2................................................. 24

9.4 Typical Application 3................................................. 25

10 Power Supply Recommendations..............................27

11 Layout...........................................................................27

11.1 Layout Guidelines................................................... 27

11.2 Layout Example...................................................... 27

12 Device and Documentation Support..........................28

12.1 接收文档更新通知................................................... 28

12.2 支持资源..................................................................28

12.3 Trademarks.............................................................28

12.4 Electrostatic Discharge Caution..............................28

12.5 术语表..................................................................... 28

13 Mechanical, Packaging, and Orderable

1 特性................................................................................... 1

2 应用................................................................................... 1

3 说明................................................................................... 1

4 Revision History.............................................................. 2

5 Pin Configuration and Functions...................................3

6 Specifications.................................................................. 4

6.1 Absolute Maximum Ratings........................................ 4

6.2 ESD Ratings............................................................... 4

6.3 Recommended Operating Conditions.........................4

6.4 Thermal Information....................................................5

6.5 Electrical Characteristics.............................................5

6.6 Timing Requirements..................................................6

6.7 Timing Waveforms...................................................... 7

6.8 Typical Characteristics................................................9

7 Parameter Measurement Information..........................10

8 Detailed Description......................................................12

8.1 Overview...................................................................12

8.2 Functional Block Diagram.........................................13

8.3 Feature Description...................................................14

Information.................................................................... 28

4 Revision History

注：以前版本的页码可能与当前版本的页码不同

Changes from Revision B (December 2021) to Revision C (March 2022)

Page

• Updated the ESD level in the ESD Ratings, Overview, and Application Information sections........................... 4

Changes from Revision A (October 2021) to Revision B (December 2021)

Page

• 从数据表中删除了所有与汽车相关的信息...........................................................................................................1

Changes from Revision * (June 2021) to Revision A (October 2021)

Page

• 将状态从“预告信息”更改为“量产数据”....................................................................................................... 1

2

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5 Pin Configuration and Functions

(TOP VIEW)

24

23

22

21

20

19

18

17

16

15

14

13

1

2

DRAIN1

DRAIN2

DRAIN3

SRCLR

G

DRAIN0

SER IN

VCC

3

4

5

PGND

RCK

6

PGND

7

PGND

8

PGND

9

LGND

SRCK

DRAIN4

DRAIN5

10

11

12

SER OUT

DRAIN7

DRAIN6

图5-1. DW Package 24-Pin SOIC Top View

表5-1. Pin Functions

I/O

DESCRIPTION

NAME

NO.

Shift register clear, active-low. The storage register transfers data to the output buffer when SRCLR is

high. Driving SRCLR low clears all the registers in the device.

SRCLR

3

I

DRAIN0

DRAIN1

DRAIN2

DRAIN3

DRAIN4

DRAIN5

DRAIN6

DRAIN7

23

24

1

O

Open-drain output

2

11

12

13

14

Output enable, active-low. Channel enable and disable input pin. Having G low enables all drain

channels according to the output-latch register content. When high, all channels are off.

G

4

I

5, 6, 7, 8, 17,

18, 19, 20

Power ground, the ground reference pin for the device. This pin must connect to the ground plane on

the PCB.

PGND

LGND

—

Signal ground, the ground reference pin for the device. This pin must connect to the ground plane on

the PCB.

16

Register clock. The data in each shift register stage transfers to the storage register at the rising edge

of RCK.

RCK

9

I

SER IN

22

15

Serial data input. Data on SER IN loads into the internal register on each rising edge of SRCK.

Serial data output of the 8-bit serial shift register. The purpose of this pin is to cascade several devices

on the serial bus.

SER OUT

O

Serial clock input. On each rising SRCK edge, data transfers from SER IN to the internal serial shift

registers.

SRCK

V_CC

10

21

I

Power supply pin for the device. TI recommends adding a 0.1-μF ceramic capacitor close to the pin.

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6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

MAX

UNIT

VCC

V_I

Supply voltage

7

V

–0.3

logic input voltage, CLR, EN, G1, G2, RCK, SER IN,

SRCK

7

V

–0.3

V_DS

I_SD

Power DMOS Drain-source voltage

65

1

V

A

Continuous source-to-drain diode anode current

Pulsed source-to-drain diode anode current

2

Pulsed drain current, each output, all outputs on, T_A

= 25°C

I_D

1.1

A

Continuous drain current, each output, all outputs

on, T_A= 25°C

350

mA

I_D

Peak drain current single output, T_A= 25°C

Single-pulse avalanche energy, T_A= 25°C

Avalanche current, T_A= 25°C

1.1

90

A

E_AS

I_AS

mJ

mA

°C

500

150

Operating junction temperature, T_J

Storage temperature, T_stg

–55

–65

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under

Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device

reliability.

6.2 ESD Ratings

VALUE

UNIT

Human body model (HBM), per ANSI/ESDA/

JEDEC JS-001⁽¹⁾

±7000

V_(ESD)

Electrostatic discharge

V

Charged device model (CDM), per ANSI/ESDA/

JEDEC JS-002⁽²⁾

±1500

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP155 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

NOM

MAX

5.5

UNIT

V

V_CC

I_(nom)

V_IH

Supply voltage

3

Nominal output current

High-level input voltage

Low-level input voltage

350

mA

V

2.4

V_IL

0.7

0.6

V

Pulsed drain output current, T_A= 25°C, V_CC

5 V

=

I_D

A

–1.8

–55

T_A

Operating ambient temperature

125

°C

4

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6.4 Thermal Information

TLC6A598

THERMAL METRIC⁽¹⁾

DW (SOIC-24)

24 PINS

55.5

UNIT

R_θJA

R_θJC(top)

R_θJB

Ψ_JT

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

°C/W

29.5

30.3

Junction-to-top characterization parameter

Junction-to-board characterization parameter

7.3

30.0

Ψ_JB

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report, SPRA953.

6.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

DRAIN0 to DRAIN7 Drain-to-source

voltage

V_(BR)DSX

V_SD

I_D= 1 mA

50

65

V

Source-to-drain forward

voltage

IF = 350 mA

0.9

1.1

V

High-level output voltage

SER OUT

4.9

4.5

4.99

4.69

I_OH= –20 µA

I_OH= –4 mA

I_OH= 20 µA

I_OH= 4 mA

V_I= 5 V

V_OH

Low-level output voltage

SER OUT

0.02

0.4

1

V_OL

V

I_IH

I_IL

High-level input current

Low-level input current

µA

V_I= 0 V

–1

Output current at which chopping

starts

I_O(chop)

T_A= 25°C

0.6

0.8

180

300

1.1

300

500

600

A

V_CC= 5 V, All outputs off, no clock

signal

I_CC

Logic supply current

µA

V_CC= 5 V, All outputs on, no clock

signal

f_SRCK= 5 MHz, C_L= 30 pF, all outputs

on

I_CC(FRQ)

I_(nom)

Logic supply current at frequency

Nominal current

360

350

µA

V_DS(on)= 0.5 V, T_C= 85°C

V_DS= 40 V, T_A= 25°C

V_DS= 40 V, T_A= 125°C

mA

1

I_DSX

Off-state drain current

µA

V_CC= 5 V, I_D= 350 mA

Single channel on, T_A= 25°C

R_ds(on)

Static drain-source on-state resistance

1

1.1

1.5

1.6

15

1.5

1.6

2.2

2.3

25

Ω

V_CC= 3.3 V, I_D=350 mA

Single channel on, T_A= 25°C

V_CC= 5 V, I_D= 150 mA

Single channel on, T_A= 125°C

Ω

V_CC= 3.3 V, I_D= 150 mA

Single channel on, T_A= 125°C

Ω

Load open and short detection

threshold

8.5

mA

I(O_S_th)

Load open and short detection

threshold hysteresis

5.7

mA

°C

I(O_S_hys)

T_SHUTDOWN

Thermal shutdown threshold

150

175

200

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6.5 Electrical Characteristics (continued)

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

T_HYS

Thermal shutdown hysteresis

18

°C

6.6 Timing Requirements

MIN

NOM

MAX

UNIT

Propagation delay time from G to output, low-to-high

level

t_PLH

t_PHL

30

ns

Propagation delay time from G to output, high-to-low

level

22

ns

t_r

t_f

Rise time, drain output

Fall time, drain output

25

35

ns

Propagation delay time, SRCK falling edge to

SEROUT change

t_pd

10

ns

t_or

SEROUT rise time (10% to 90%)

SEROUT fall time (90% to 10%)

Serial clock frequency

3

2

ns

t_of

f_SRCK

10

MHz

ns

t_{SRCK_WH}

SRCK pulse duration, high

30

10

20

t_{SRCK_WL}

SRCK pulse duration, low

ns

t_su

t_h

Setup time, SER IN high before SRCK rise

Hold time, SER IN high after SRCK rise

SER IN pulse duration

ns

t_w

t_a

ns

Reverse-recovery-current rise time

Reverse-recovery time

80

ns

t_rr

t_d

100

ns

Last SRCK rise to RCK rise

200

ns

6

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6.7 Timing Waveforms

图6-1 shows the resistive-load test circuit and voltage waveforms. One can see from 图6-1 that with G held low

and SRCLR held high, the status of each drain changes on the rising edge of the register clock, indicating the

transfer of data to the output buffers at that time.

7

4

3

0

6

5

2

1

5 V

SRCK

G

0 V

5 V

24 V

0 V

5 V

VCC

DUT

SER IN

ID

SRCLR

SRCK

SER IN

RCK

0 V

RL = 68 Ω

5 V

Output

RCK

MCU

0 V

DRAIN

PGND

5 V

SRCLR

CL = 30 pF

(see Note A)

G

0 V

LGND

24 V

0.5 V

24 V

0.5 V

DRAIN1,2,5,6

DRAIN0,3,4,7

TEST CIRCUIT

VOLTAGE WAVEFORMs

A. C_Lincludes probe and jig capacitance.

图6-1. Resistive Load Operation

图 6-2 shows the SER IN to SER OUT waveform. The output signal appears on the falling edge of the shift

register clock (SRCK) because there is a phase inverter at SER OUT (see the Functional Block Diagram). As a

result, it takes seven and a half periods of SRCK for data to transfer from SER IN to SER OUT.

8

3

7

6

5

4

2

1

SRCK

SER IN

1

0

CLR

SER OUT

图6-2. SER IN to SER OUT Waveform

图6-3 shows the test circuit, switching times, and voltage waveforms.

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5 V

24 V

G

50%

0 V

t_PLH

t_PHL

VCC

24 V

ID

SRCLR

SRCK

SER IN

RCK

RL = 68 Ω

90%

t_r

SWITCHING TIMES

90%

t_f

DUT

Output

10%

0.5 V

Output

MCU

DRAIN

PGND

CL = 30 pF

(see Note A)

5 V

0 V

G

50%

SRCK

LGND

t_su

t_h

50%

5 V

0 V

TEST CIRCUIT

SER IN

50%

t_w

INPUT SETUP AND HOLD WAVEFORMS

5 V

0 V

50%

t_pd

50%

t_pd

SRCK

5 V

0 V

SER OUT

50%

SER OUT PROPAGATION DELAY WAVEFORM

A. C_Lincludes probe and jig capacitance.

图6-3. Switching Times and Voltage Waveforms

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6.8 Typical Characteristics

0.4

0.75

0.72

0.69

0.66

0.63

0.6

0.57

0.54

0.51

0.48

0.45

0.42

0.39

0.36

0.33

0.3

V_CC= 3.3 V, T_A= –55°C

V_CC= 3.3 V, T_A= 25 °C

V_CC= 3.3 V, T_A= 125 °C

V_CC= 5 V, T_A= –55°C

V_CC= 5 V, T_A= 25 °C

V_CC= 5 V, T_A= 125 °C

0.375

0.35

0.325

0.3

V_CC= 3.3 V, T_A= 25°C

V_CC= 3.3 V, T_A= 100°C

V_CC= 3.3 V, T_A= 125°C

V_CC= 5 V, T_A= 25°C

V_CC= 5 V, T_A= 100°C

V_CC= 5 V, T_A= 125°C

0.275

0.25

0.225

0.1

0.2 0.3

0.5 0.7

1

2

3

4

5 6 7 8 10

1

1.5

2 2.5 3 3.5 4 4.5 5 5.5 6 6.5 7 7.5 8

f - Frequency - MHz

N - Number of Outputs Conducting Simultaneously

D1 - SLIS187.grf

D2 - SLIS187.grf

图6-4. Supply Current vs Frequency

图6-5. Maximum Continuous Drain Current of

Each Output vs Number of Outputs Conducting

Simultaneously

DRAIN-SOURCE ON-STATE RESISTANCE vs DRAIN CURRENT

1.9

1.8

T_A= –55°C

T_A= –40°C

T_A= –55°C

T_A= –40°C

1.8

1.7

1.6

1.5

1.4

1.3

1.2

1.1

1

1.6

1.4

1.2

1

T_A= 25°C

T_A= 125°C

Current limit

T_A= 25°C

T_A= 125°C

Current limit

0.9

0.8

0.7

0.8

0.6

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

1

1.1

0

0.2

0.4

0.6

0.8

1

1.2

I_D- Drain Current - A

D3 - SLIS187.grf

D4 - SLIS187.grf

V_CC= 3.3 V, T_A= 25 °C

V_CC= 5 V, T_A= 25 °C

图6-6. Static Drain-to-Source On-State Resistance 图6-7. Static Drain-to-Source On-State Resistance

vs Drain Current vs Drain Current

1.8

1.6

1.4

1.2

1

T_A= –55°C

T_A= –40°C

T_A= 25°C

T_A= 125°C

0.8

0.6

3

3.5

4

4.5

5

5.5

6

6.5

7

V_CC- Logic Supply Voltage - V

D5 - SLIS187.grf

All channels on, I_DS= 350 mA

图6-8. Static Drain-to-Source On-State Resistance vs Supply Voltage

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7 Parameter Measurement Information

图7-1 shows the resistive-load test circuit and voltage waveforms. One can see from 图 7-1 that with G held low

and SRCLR held high, the status of each drain changes on the rising edge of the register clock, indicating the

transfer of data to the output buffers at that time.

7

4

3

0

6

5

2

1

5 V

SRCK

G

0 V

5 V

24 V

0 V

5 V

VCC

DUT

SER IN

ID

SRCLR

SRCK

SER IN

RCK

0 V

RL = 68 Ω

5 V

Output

RCK

MCU

0 V

DRAIN

PGND

5 V

SRCLR

CL = 30 pF

(see Note A)

G

0 V

LGND

24 V

0.5 V

24 V

0.5 V

DRAIN1,2,5,6

DRAIN0,3,4,7

TEST CIRCUIT

VOLTAGE WAVEFORMs

A. C_Lincludes probe and jig capacitance.

图7-1. Resistive-Load Test Circuit and Voltage Waveforms

图7-2 shows the reverse recovery current test circuit and waveforms of source to drain diode.

TP K

Circuit

Under

Test

2500 μF

250 V

0.35 A

(di/dt = 14 A/us)

24 V

L = 1 mH

IF

0

IF

(see note B)

TP A

25% of IRM

t₃

t₂

t₁

RG

IRM

(see note C)

VGG

(see note A)

50

t_a

t_rr

TEST CIRCUIT

VOLTAGE WAVEFORMs

图7-2. Reverse Recovery Current Test Circuit and Waveforms of Source to Drain Diode

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备注

A. The V_GGamplitude and R_Gare adjusted for di/dt = 14 A/μs. A V_GGdouble-pulse train is used to

set I_F= 0.35 A, where t₁= 10 μs, t₂= 7 μs, and t₃= 3 μs.

备注

B. The DRAIN terminal under test is connected to the TP K test point. All other terminals are

connected together and connected to the TP A test point.

备注

C. I_RM= maximum recovery current.

图7-3 shows the single pulse avalanche energy test circuit and waveforms.

t_w

t_av

5 V

36 V

Input

VCC

DUT

6

0 V

SRCLR

SRCK

SER IN

RCK

ID

IAS = 500 mA

300 mH

ID

MCU

DRAIN

PGND

VDS

V(BR)DSX = 50 V

MIN

G

VDS

LGND

TEST CIRCUIT

VOLTAGE AND CURRENT WAVEFORMS

图7-3. Single Pulse Avalanche Energy Test Circuit and Waveforms

备注

A. The MCU has the following characteristics: t_r≤10 ns, t_f≤10 ns, Z_O= 50 Ω.

备注

B. Input pulse duration, tw, is increased until peak current I_AS= 500 mA.

Energy test level is defined as E_AS= (I_AS× V_(BR)DSX× t_av) / 2 = 90 mJ.

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8 Detailed Description

8.1 Overview

The TLC6A598 device is a monolithic, high-voltage, high-current 8-bit shift register designed to drive relatively

high load power such as LEDs. The device contains a built-in voltage clamp on the outputs for inductive

transient protection, so it can also drive relays, solenoids, and other low-current or high-voltage loads.

This device contains an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. Data

transfers through both the shift and storage registers on the rising edge of the shift register clock (SRCK) and the

register clock (RCK) respectively. The storage register transfers data to the output buffer when shift register clear

(CLR) is high. When CLR is low, all registers in the device are cleared. When output enable (G) is held high, all

data in the output buffers is held low and all drain outputs are off. When G is held low, data from the storage

register transfers to the output buffers. When data in the output buffers is low, the DMOS transistor outputs are

off. When data is high, the DMOS transistor outputs have sink-current capability.

The serial output (SER OUT) is clocked out of the device on the falling edge of SRCK to provide additional hold

time for cascaded applications. This action provides improved performance for applications where clock signals

can be skewed, devices are not located near one another, or the system must tolerate electromagnetic

interference.

Outputs are low-side, open-drain DMOS transistors with output ratings of 50-V and 350-mA continuous sink-

current capability. The current limit decreases as the junction temperature increases for additional device

protection. The device also provides up to 7000 V of ESD protection when tested using the human body model

and the 1500 V machine model.

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8.2 Functional Block Diagram

G

RCK

DRAIN0

DRAIN1

DRAIN2

DRAIN3

DRAIN4

DRAIN5

DRAIN6

DRAIN7

D

SER IN

SRCK

SRCLR

C1

CLR

D

C1

CLR

C1

CLR

D

C1

CLR

C1

CLR

D

C1

CLR

C1

CLR

D

C1

CLR

C1

CLR

D

C1

CLR

C1

CLR

D

C1

CLR

C1

CLR

D

C1

CLR

C1

CLR

PGND

D

C1

CLR

SER OUT

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8.3 Feature Description

8.3.1 Serial-In Interface

The TLC6A598 device contains an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage

register. Data transfer through the shift and storage registers is on the rising edge of the shift register clock

(SRCK) and the register clock (RCK), respectively. The storage register transfers data to the output buffer when

shift-register clear (SRCLR) is high.

8.3.2 Clear Registers

A logic low on the SRCLR pin clears all registers in the device. TI suggests clearing the device during power up

or initialization.

8.3.3 Output Channels

DRAIN0–DRAIN7. These pins can survive up to 50-V LED supply voltage.

8.3.4 Register Clock

RCK is the storage-register clock. Data in the storage register appears at the output whenever the output enable

(G) input signal is high.

8.3.5 Cascade Through SER OUT

By connecting the SER OUT pin to the SER IN input of the next device on the serial bus in cascade, the data

transfers to the next device on the falling edge of SRCK. This connection can improve the cascade application

reliability, as it can avoid the issue that the second device receives SRCK and data input on the same rising

edge of SRCK.

8.3.6 Output Control

Holding the output enable (pin G) high holds all data in the output buffers low, and all drain outputs are off.

Holding G low makes data from the storage register transferred to the output buffers. When data in the output

buffers is low, the DMOS transistor outputs are off. When data is high, the DMOS transistor outputs are capable

of sinking current. This pin also can be used for global PWM dimming.

8.3.7 Clamping Structure

When switching off inductive loads, the potential at pin OUT rises to VDS(CL) potential, because the inductance

intends to continue driving the current. The clamping voltage is necessary to prevent destruction of the device.

See 图8-1 for the clamping circuit principle. Nevertheless, the maximum allowed load inductance is limited.

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L

RL

DRAINx

IL

VDScl

Rpulldown

RSENSE

PGND

LGND

图8-1. Output Clamp Implementation

During demagnetization of inductive loads, energy has to be dissipated in the TLC6A598. This energy can be

calculated with 方程式1:

V

− V

R

× I

bat

DS CL

L

E = V

×

× ln 1 −

+ I

×

(1)

(2)

DS CL

L

V

− V

I

L

bat

DS CL

L

The 方程式2 simplifies under the assumption of R_L= 0:

V

1

2

bat

E = × L × I × 1 −

L

V

− V

bat

DS CL

The thermal design of the component limits the maximum energy, which is converted into heat.

8.3.8 Protection Functions

8.3.8.1 Overcurrent Protection

When any output is in on status (the corresponding Data Register bit is set to ‘1’), if the output current

through the MOS is sensed to be larger than I_OK, it enters chopping mode as below.

图 8-2 illustrates the output current characteristics of the device energizing a load having initially low, increasing

resistance, For example, an incandescent lamp. In region 1, chopping occurs and the peak current is limited to

I_O(chop). In region 2, output current is continuous. The same characteristics occur in reverse order when the

device energizes a load having an initially high, decreasing resistance.

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OUTPUT CURRENT

vs

REGION 1 CURRENT

WAVEFORM

TIME FOR INCREASING LOAD

RESISTANCE

1.5

1.25

1

Iok

0.75

0.5

0.25

0

t₁

t₂

t₁

t₂

t₁: 40 us

t₂: 2.5 ms

Region1

Region2

Time

图8-2. Chopping-Mode Characteristics

备注

Region 1 duty cycle is approximately 2%.

8.3.8.2 Output Detection

When any output is in on status (the corresponding Data Register bit is set to ‘1’), if the current goes through

any output is sensed to be lower than I_{OS_th}mA, then an open load condition or short to ground fault is reported

to the fault register while the output does not close automatically.

For the inductive load, during the on status of any output, TI recommends to read the fault regs two times.

Because the inductive load leads to error detection results and it needs ignore the first time readout results

during the set up process of the output current, TI recommends to read the fault regs again after the current

through the load is stable.

8.3.8.3 Serial Communication Error

The device provides a cyclic redundancy check to verify register values in the shift registers. In read back mode,

the device provides 6 bits of the CRC remainder. The MCU can read back the CRC remainder and check if the

remainder is correct to determine whether the communication loop between MCU and device is good. Shift-

Register Communication-Fault Detection gives a detailed description of the CRC check.

8.3.8.4 Thermal Shutdown

The device implements an internal thermal shutdown to protect itself if the junction temperature exceeds 175°C

(typical). The thermal shutdown forces the device to have an open state when the junction temperature exceeds

the thermal trip threshold. After the junction temperature decreases below 160°C (typical), the device begins to

operate again.

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8.3.9 Interface

8.3.9.1 Register Write

The TLC6A598 device has a 8-bit configuration register. Data transfers through the shift registers on the rising

edge of SRCK and latches into the storage registers on the rising edge of RCK. The data bits control 8 open-

drain outputs independently.

RCK

SRCK

1

2

3

4

5

6

7

8

SER IN

SER OUT

OUTPUT

D7

D6

D5

D4

D3

D2

D1

D0

D7

OLD

OUTPUTS

NEW

OUTPUTS

Register Writes Timing Diagram

图8-3. Register Write Timing Diagram

8.3.9.2 Register Read

The fault information loads to shift registers on the rising edge of RCK and can be read out on SER OUT. 图 8-4

shows on the rising edge of the RCK signal, the MSB data "DRAIN7_OCP" appears on the SER OUT pin. On

each falling edge of SRCK signal, there is 1 bit of data shifted out on the SER OUT pin. There is a total of 24 bits

in the fault information registers. REgister Maps describes the details.

RCK

SRCK

D23_N-1

D23_N

SER IN

D22_N-1

D0_N-1

D0_N

D23_N-2

D23_N-1

D0_N-2

D0_N-1

D0_N-3

D0_N-2

D0_0

D0_1

D23_N-3

D23_N-2

D23_0

D23_1

SER OUT

D22_N

D23_0

D0_0

Device N Fault Info

Device N-1 Fault Info

Device N-2 Fault Info

Fault Read back Timing Diagram

Device 1 Fault Info

Device 0 Fault Info

图8-4. Register Read Timing Diagram

8.3.9.3 Shift-Register Communication-Fault Detection

The TLC6A598 device provides a cyclic redundancy check to verify register values in the shift registers. In read

back mode, the TLC6A598 device provides 6 bits of the CRC remainder. The MCU can read back the CRC

remainder and check if the remainder is correct. The CRC checksum provides a read back method to verify shift

register values without altering them.

Input

CRC

Bit3

CRC

Bit2

CRC

Bit1

CRC

Bit0

CRC

Bit5

CRC

Bit4

图8-5. CRC Check Block Diagram

The TLC6A598 device also checks the configuration register for faulty commands. The TLC6A598 configuration

register consists of 8 bits. To generate the CRC checksum, the device first shifts left 6 bits and appends 0s, then

bit-wise exclusive-ORs the 14 data bits with the polynomial to get the checksum.

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For example, if the configuration data is 0xFF and the polynomial is 0x43 (7’b1000011), the CRC checksum is

0x0D (6’b00 1101).

The MCU can read back the CRC checksum and append it to the LSB of 8 bits, and then the 14 bits of data

becomes 0x3FCD. Performing the bit-wise exclusive-OR operation with the polynomial must lead to a residual of

0.

8.4 Device Functional Modes

8.4.1 Operation With V_CC< 3 V

This device works normally within the range 3 V ≤ V_CC≤ 5.5 V. When the operating voltage is lower than 3 V,

correct behavior of the device, including communication interface and current capability, is not assured.

8.4.2 Operation With 5.5 V ≤V_CC≤7 V

The device works normally in this voltage range, but reliability issues can occur if the device works for a long

time in this voltage range.

8.5 Register Maps

表8-1. Register Map

CONFIGURATION REGISTER

Field name

Default value

Bit

DRAIN7

DRAIN6

DRAIN5

DRAIN4

DRAIN3

DRAIN2

DRAIN1

DRAIN0

0h

7

0h

6

0h

5

0h

4

0h

3

0h

2

0h

1

0h

0

FAULT READBACK REGISTER

21 20 19

Bit

23

22

18

17

16

Field name

DRAIN7_OC DRAIN6_OC DRAIN5_OC DRAIN4_OC DRAIN3_OC DRAIN2_OC DRAIN1_OC DRAIN0_OC

P

Default value

0h

Bit

15

14

13

12

11

10

9

8

Field name

DRAIN7_Oor DRAIN6_Oor DRAIN5_Oor DRAIN4_Oor DRAIN3_Oor DRAIN2_Oor DRAIN1_Oor DRAIN0_Oor

S

Default value

0h

Bit

7

6

5

4

3

2

1

0

Field name

Default value

TBD

0h

TSD

0h

CRC

0h

表8-2 lists the memory-mapped registers for the interface.

表8-2. Interface Registers

OFFSET

0h

ACRONYM

Config

REGISTER NAME

SECTION

Configuration Register

1h

Fault_Readback

Fault Readback Register

表8-3. Interface Access Type Codes

CODE

DESCRIPTION

Read type

R

Read-only

Read to clear

Write

RC

W

Read to clear the fault

Write-only

Reset or Default Value

-n

Value after reset or the default value

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8.5.1 Configuration Register(Offset=0h)[reset=0h]

Configuration register is shown in 表8-4and described in 表8-5.

表8-4. Configuration Register

7

6

5

4

3

2

1

0

DRAIN7

W-0h

DRAIN6

W-0h

DRAIN5

W-0h

DRAIN4

W-0h

DRAIN3

W-0h

DRAIN2

W-0h

DRAIN1

W-0h

DRAIN0

W-0h

表8-5. Configuration Register Field Descriptions

Bit

Field

Type

Reset

Description

7

DRAIN7

DRAIN6

DRAIN5

DRAIN4

DRAIN3

DRAIN2

DRAIN1

DRAIN0

W

0h

•

Open-drain output bit for DRAIN7

HIGH=Output power switch enabled

LOW=Output power switch disabled

6

5

4

3

2

1

0

W

0h

•

Open-drain output bit for DRAIN6

HIGH=Output power switch enabled

LOW=Output power switch disabled

•

Open-drain output bit for DRAIN5

HIGH=Output power switch enabled

LOW=Output power switch disabled

•

Open-drain output bit for DRAIN4

HIGH=Output power switch enabled

LOW=Output power switch disabled

•

Open-drain output bit for DRAIN3

HIGH=Output power switch enabled

LOW=Output power switch disabled

•

Open-drain output bit for DRAIN2

HIGH=Output power switch enabled

LOW=Output power switch disabled

•

Open-drain output bit for DRAIN1

HIGH=Output power switch enabled

LOW=Output power switch disabled

•

Open-drain output bit for DRAIN0

HIGH=Output power switch enabled

LOW=Output power switch disabled

8.5.2 Fault Readback Register(Offset=1h)[reset=0h]

Fault readback is shown in 表8-6 and described in 表8-7.

表8-6. Fault Readback Register

23

22

21

20

19

18

17

16

DRAIN7_OCP DRAIN6_OCP DRAIN5_OCP DRAIN4_OCP DRAIN3_OCP DRAIN2_OCP DRAIN1_OCP DRAIN0_OCP

RC-0h

15

RC-0h

14

RC-0h

13

RC-0h

12

RC-0h

11

RC-0h

10

RC-0h

9

RC-0h

8

DRAIN7_OorS DRAIN6_OorS DRAIN5_OorS DRAIN4_OorS DRAIN3_OorS DRAIN2_OorS DRAIN1_OorS DRAIN0_OorS

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表8-6. Fault Readback Register (continued)

23

22

21

20

19

18

17

16

RC-0h

7

6

5

4

3

2

1

0

TBD

TSD

CRC

RC-0h

表8-7. Configuration Register Field Descriptions

Bit

Field

Type

Reset

Description

23

DRAIN7_OCP

DRAIN6_OCP

DRAIN5_OCP

DRAIN4_OCP

DRAIN3_OCP

DRAIN2_OCP

DRAIN1_OCP

DRAIN0_OCP

DRAIN7_OorS

RC

0h

•

Over current fault flag for DRAIN7, read to clear the fault

HIGH=Over current fault detected

LOW=Over current fault not detected

22

21

20

19

18

17

16

15

RC

0h

•

Over current fault flag for DRAIN6, read to clear the fault

HIGH=Over current fault detected

LOW=Over current fault not detected

•

Over current fault flag for DRAIN5, read to clear the fault

HIGH=Over current fault detected

LOW=Over current fault not detected

•

Over current fault flag for DRAIN4, read to clear the fault

HIGH=Over current fault detected

LOW=Over current fault not detected

•

Over current fault flag for DRAIN3, read to clear the fault

HIGH=Over current fault detected

LOW=Over current fault not detected

•

Over current fault flag for DRAIN2, read to clear the fault

HIGH=Over current fault detected

LOW=Over current fault not detected

•

Over current fault flag for DRAIN1, read to clear the fault

HIGH=Over current fault detected

LOW=Over current fault not detected

•

Over current fault flag for DRAIN0, read to clear the fault

HIGH=Over current fault detected

LOW=Over current fault not detected

•

Open or short to ground fault flag for DRAIN7, read to clear

the fault

•

HIGH=Open or short to ground fault detected

LOW=Open or short to ground fault not detected

14

DRAIN6_OorS

RC

0h

•

Open or short to ground fault flag for DRAIN6, read to clear

the fault

•

HIGH=Open or short to ground fault detected

LOW=Open or short to ground fault not detected

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表8-7. Configuration Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

13

DRAIN5_OorS

RC

0h

•

Open or short to ground fault flag for DRAIN5, read to clear

the fault

•

HIGH=Open or short to ground fault detected

LOW=Open or short to ground fault not detected

12

11

10

9

DRAIN4_OorS

DRAIN3_OorS

DRAIN2_OorS

DRAIN1_OorS

DRAIN0_OorS

RC

0h

•

Open or short to ground fault flag for DRAIN4, read to clear

the fault

•

HIGH=Open or short to ground fault detected

LOW=Open or short to ground fault not detected

•

Open or short to ground fault flag for DRAIN3, read to clear

the fault

•

HIGH=Open or short to ground fault detected

LOW=Open or short to ground fault not detected

•

Open or short to ground fault flag for DRAIN2, read to clear

the fault

•

HIGH=Open or short to ground fault detected

LOW=Open or short to ground fault not detected

•

Open or short to ground fault flag for DRAIN1, read to clear

the fault

•

HIGH=Open or short to ground fault detected

LOW=Open or short to ground fault not detected

8

•

Open or short to ground fault flag for DRAIN0, read to clear

the fault

•

HIGH=Open or short to ground fault detected

LOW=Open or short to ground fault not detected

7

6

TBD

TSD

RC

0h

TBD

•

Thermal-shutdown detection flag, read to clear the fault

HIGH = Thermal shutdown detected

LOW = Thermal shutdown not detected

5

4

3

2

1

0

CRC

R

0h

CRC checksum of configuration registers

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9 Application and Implementation

备注

以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客户应负责确定

器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。

9.1 Application Information

The TLC6A598 device is a serial-in, parallel-out, power and logic, 8-bit shift register with low-side open-drain

DMOS output ratings of 50-V and 350-mA continuous sink-current capabilities when VCC = 5 V. The device is

designed to drive resistive loads and is particularly well-suited as an interface between a microcontroller and

LEDs or lamps. The device also provides up to 7000 V of ESD protection when tested using the human body

model and 1500 V when using the machine model.

The serial output (SEROUT) clocks out of the device on the falling edge of SRCK to provide additional hold time

for cascaded applications. Connect the device (SEROUT) pin to the next device (SERIN) for daisy chain. This

connection provides improved performance for applications where clock signals can be skewed, devices are not

located near one another, or the system must tolerate electromagnetic interference.

9.2 Typical Application 1

图9-1 shows a typical application circuit with TLC6A598 to drive LEDs. The MCU generates all the input signals.

Vsupply

5 V - 50 V

VCC

3 V - 5.5 V

Rx

0.1 μF

LEDx

VCC

G

DRAIN0

DRAIN1

DRAIN2

DRAIN3

DRAIN4

DRAIN5

DRAIN6

DRAIN7

SER OUT

RCK

SRCK

SER IN

SRCLR

MCU

PGND

LGND

图9-1. Typical Application With TLC6A598 to Drive LEDs

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9.2.1 Design Requirements

表9-1. System Specifications

DESCRIPTION

DESIGN PARAMETER

EXAMPLE VALUE

5 V to 50 V

V_supply

V_CC

V_LED

I_LED

Supply voltage for the LED strings

Supply voltage for the TLC6A598

LED forward voltage

3 V to 5.5 V

3.3 V (typical)

50 mA to 350 mA

LED current

9.2.2 Detailed Design Procedure

To begin the design process, the designer must decide on a few parameters, as follows:

• V_supply: LED supply voltage

• V_LEDx: LED forward voltage

• I_LED: LED current

• R_ON: Resistance for each output channels when it is on, 1-Ω typical, T_A= 25°C

With these parameters determined, the resistor in series with the LED can be calculated by using the 方程式3:

V

− V

LED

supply

I

R

=

− R

(3)

X

ON

LED

9.2.3 Application Curves

图9-2. Turn on Drain0/2/4/6

图9-3. Turn off Drain0/2/4/6

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9.3 Typical Application 2

图9-4 shows a typical cascade application circuit with two TLC6A598 chips configured in cascade topology. The

MCU generates all the input signals.

Vsupply

9 V - 40 V

VCC

3 V - 5.5 V

Rx

0.1 μF

LEDx

VCC

G

DRAIN0

DRAIN1

DRAIN2

DRAIN3

DRAIN4

DRAIN5

DRAIN6

DRAIN7

SER OUT

RCK

SRCK

SER IN

SRCLR

MCU

PGND

LGND

Vsupply

9 V - 40 V

VCC

3 V - 5.5 V

Rx

0.1 μF

LEDx

VCC

G

DRAIN0

DRAIN1

DRAIN2

DRAIN3

DRAIN4

DRAIN5

DRAIN6

DRAIN7

SER OUT

RCK

SRCK

SER IN

SRCLR

PGND

LGND

图9-4. Typical Application With Cascade TLC6A598

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9.3.1 Design Requirements

表9-2. System Specifications

DESIGN PARAMETER

DESCRIPTION

EXAMPLE VALUE

5 V to 50 V

V_supply

V_CC

V_LED

I_LED

Supply voltage for the LED strings

Supply voltage for the TLC6A598

LED forward voltage

3 V to 5.5 V

3.3 V (typical)

50 mA to 350 mA

LED current

9.3.2 Detailed Design Procedure

To begin the design process, the designer must decide on a few parameters, as follows:

• V_supply: LED supply voltage

• V_LEDx: LED forward voltage

• I_LED: LED current

• R_ON: Resistance for each output channels when it is on, 1-Ω typical, T_A= 25°C

With these parameters determined, the resistor in series with the LED can be calculated by using the 方程式4:

V

− V

LED

supply

I

R

=

− R

(4)

X

ON

LED

9.4 Typical Application 3

图 9-5 shows a typical application circuit with TLC6A598 to drive Relays. The MCU generates all the input

signals.

Please note that inductive loads, such as stepper motors or relays, can generate negative transients on the

DRAINx pins of the device. Typically, this event occurs when the output channel FET turns ON, pulling the

DRAINx node to ground. This event can cause the DRAINx node to go below the voltage rating listed in the

Absolute Maximum Ratings table, which in effect causes excessive ground current leakage.

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Vsupply

5 V – 50 V

VCC

3 V - 5.5 V

Lx

0.1 μF

VCC

G

DRAIN0

DRAIN1

DRAIN2

DRAIN3

DRAIN4

DRAIN5

DRAIN6

DRAIN7

SER OUT

RCK

SRCK

SER IN

SRCLR

MCU

PGND

LGND

图9-5. Typical Application With TLC6A598 to Drive Relays

9.4.1 Design Requirements

表9-3. System Specifications

DESIGN PARAMETER

DESCRIPTION

EXAMPLE VALUE

V_supply

V_CC

Supply voltage for the coil

Supply voltage for the TLC6A598

Output current for the coil

5 V to 50 V

3 V to 5.5 V

I_COIL

30 mA to 350 mA

9.4.2 Detailed Design Procedure

To begin the design process, the designer must decide on a few parameters, as follows:

• V_supply: LED supply voltage

• R_COIL: Coil resistance

• R_ON: Resistance for each output channels when it is on, 1-Ω typical, T_A= 25°C

With these parameters determined, the coil current can be calculated by using the 方程式5:

V

supply

I

=

(5)

COIL

R

+ R

COIL

ON

26

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TLC6A598

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10 Power Supply Recommendations

The TLC6A598 device is designed to operate with an input voltage supply range from 3 V to 5.5 V. This input

supply must be well regulated. TI recommends placing the ceramic bypass capacitors near the V_CCpin.

11 Layout

11.1 Layout Guidelines

There are no special layout requirements for the digital signal pins. The only requirement is placing the ceramic

bypass capacitors near the corresponding pins.

Maximize the copper coverage on the PCB to increase the thermal conductivity of the board. The major heat-

flow path from the package to the ambient is through the copper on the PCB. Maximizing the copper coverage is

extremely important when the design does not include heat sinks attached to the PCB on the other side of the

package.

Add as many thermal vias as possible directly under the package ground pad to optimize the thermal

conductivity of the board.

All thermal vias must be either plated shut or plugged and capped on both sides of the board to prevent solder

voids. To ensure reliability and performance, the solder coverage must be at least 85%.

11.2 Layout Example

24

23

22

21

20

19

18

17

16

15

14

13

1

2

DRAIN1

DRAIN0

SER IN

VCC

DRAIN2

DRAIN3

SRCLR

G

3

4

5

PGND

RCK

6

PGND

7

PGND

8

PGND

9

LGND

SRCK

DRAIN4

DRAIN5

10

11

12

SER OUT

DRAIN7

DRAIN6

图11-1. TLC6A598 Example Layout

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TLC6A598

ZHCSNT5C –JUNE 2021 –REVISED MARCH 2022

www.ti.com.cn

12 Device and Documentation Support

12.1 接收文档更新通知

要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新进行注册，即可每周接收产品信息更

改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

12.2 支持资源

TI E2E^™支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解

答或提出自己的问题可获得所需的快速设计帮助。

链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅

TI 的《使用条款》。

12.3 Trademarks

TI E2E^™is a trademark of Texas Instruments.

所有商标均为其各自所有者的财产。

12.4 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled

with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric changes could cause the device not to meet its published

specifications.

12.5 术语表

TI 术语表

本术语表列出并解释了术语、首字母缩略词和定义。

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most-

current data available for the designated device. This data is subject to change without notice and without

revision of this document. For browser-based versions of this data sheet, see the left-hand navigation pane.

28

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PACKAGE MATERIALS INFORMATION

www.ti.com

23-Feb-2022

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0

B0

K0

P1

W

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

TLC6A598MDWR

SOIC

DW

24

2000

330.0

24.4

10.75 15.7

2.7

12.0

24.0

Q1

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

23-Feb-2022

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SOIC DW 24

SPQ

Length (mm) Width (mm) Height (mm)

350.0 350.0 43.0

TLC6A598MDWR

2000

Pack Materials-Page 2

重要声明和免责声明

TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，

不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担

保。

这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验

证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。

这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。

您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成

本、损失和债务，TI 对此概不负责。

TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改

TI 针对 TI 产品发布的适用的担保或担保免责声明。

TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE

邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	TLC6A598
厂家：	TEXAS INSTRUMENTS
描述：	适用于航空电子应用的高功率 8 位相移高可靠性驱动器电子航空驱动驱动器
文件：	总33页 (文件大小：2778K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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