TLV6003DBVR [TI]
单路超低功耗 (980nA)、16V 精密轨到轨输入和输出运算放大器 | DBV | 5 | -40 to 125;
| 型号： | TLV6003DBVR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 单路超低功耗 (980nA)、16V 精密轨到轨输入和输出运算放大器 | DBV | 5 | -40 to 125 放大器 运算放大器 |
| 文件： | 总26页 (文件大小：1574K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TLV6003
ZHCSKC8 –OCTOBER 2019
TLV6003 980nA 16V 精密轨至轨输入和输出运算放大器
1 特性
3 说明
1
•
微功耗运行：1.2µA（最大值）
低输入失调电压：550µV（最大值）
TLV6003 是一款纳瓦级功耗运算放大器，每个通道仅
消耗 980nA 的电流，同时提供极低的最大失调电压。
逆向电池保护可在电池安装不当产生过大电流时保护放
大器。在恶劣环境下，输入电压可以比正电源轨高
5V，不会损坏器件。
•
•
•
•
•
高达 18V 的反向电池保护
轨至轨输入/输出
增益带宽积：5.5kHz
额定温度范围：
TA = –40°C 至 +125°C
低电源电流与低输入偏置电流耦合，使该器件可与高串
联电阻输入源（如 PIR 运动检测仪和一氧化碳传感
器）一起使用。在 550μV (25°C) 的低最大失调电压、
120dB 的典型 CMRR 和 112dB 的最小开环增益
(2.7V) 情况下可以保持直流精度。
•
•
工作温度范围：
TA = –55°C 至 +125°C
输入共模范围超过电源轨：
–0.1V 至 VCC + 5V
•
•
电源电压范围：2.5V 至 16V
最高额定工作电源电压为 2.5V 至 16V，电气特性在
2.7V、5V 和 15V 下指定。2.5V 工作电压使该器件与
锂离子电池供电系统兼容，从而使 TLV6003 成为输入
信号增益和低功耗微控制器（如 TI 的 MSP430）缓冲
的理想之选。
小封装：
–
5 引脚 SOT-23
2 应用
•
•
•
•
•
流量变送器
TLV6003 采用小型 SOT-23 封装。
压力变送器
器件信息(1)
运动检测器（PIR、uWave 等）
血糖监测仪
器件型号
TLV6003
封装
SOT-23 (5)
封装尺寸（标称值）
气体检测仪
2.90mm x 1.60mm
(1) 如需了解所有可用封装，请参阅数据表末尾的封装选项附录。
PIR 运动检测器缓冲器
失调电压与温度间的关系
800
700
600
500
400
300
200
100
0
-100
-200
-300
-400
-500
-600
-700
-800
5 Typical Units Shown
VOUT
+
IR
TLV6003
-55
-35
-15
5
25
45
65
85
105 125
Temperature (èC)
C001
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLOS981
TLV6003
ZHCSKC8 –OCTOBER 2019
www.ti.com.cn
目录
1
2
3
4
5
6
特性.......................................................................... 1
8
9
Application and Implementation ........................ 14
8.1 Application Information............................................ 14
8.2 Typical Application .................................................. 15
Power Supply Recommendations...................... 18
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information – TLV6003 ............................... 4
6.5 Electrical Characteristics........................................... 5
6.6 Typical Characteristics.............................................. 7
Detailed Description ............................................ 12
7.1 Overview ................................................................. 12
7.2 Functional Block Diagram ....................................... 12
7.3 Feature Description................................................. 13
7.4 Device Functional Modes........................................ 13
10 Layout................................................................... 18
10.1 Layout Guidelines ................................................. 18
10.2 Layout Example .................................................... 18
11 器件和文档支持 ..................................................... 19
11.1 器件支持................................................................ 19
11.2 文档支持................................................................ 19
11.3 接收文档更新通知 ................................................. 19
11.4 社区资源................................................................ 19
11.5 商标....................................................................... 19
11.6 静电放电警告......................................................... 19
11.7 Glossary................................................................ 19
12 机械、封装和可订购信息....................................... 19
7
4 修订历史记录
日期
修订版本
说明
2019 年 10 月
*
初始发行版。
2
Copyright © 2019, Texas Instruments Incorporated
TLV6003
www.ti.com.cn
ZHCSKC8 –OCTOBER 2019
5 Pin Configuration and Functions
DBV Package
5-pin SOT-23
Top View
OUT
GND
+IN
1
5
VCC
2
3
4
œIN
Not to scale
Pin Functions
PIN
I/O
DESCRIPTION
NAME
OUT
GND
+IN
DBV
1
2
3
4
5
O
–
I
Output
Negative (lowest) power supply
Noninverting input
–IN
I
Inverting input
VCC
–
Positive (highest) power supply
Copyright © 2019, Texas Instruments Incorporated
3
TLV6003
ZHCSKC8 –OCTOBER 2019
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
UNIT
VCC
Supply voltage(2)
Input voltage
–18
17
V
Singe-ended and common-mode input
voltage, VICR
–0.3
VCC + 5
VIN+, VIN–
V
Differential, VID
±20
±10
±10
Input current (any input)
Output current
mA
mA
IO
Continuous total power dissipation
Maximum junction temperature
Storage temperature
See Dissipation Rating
TJ
–55
–65
150
150
°C
°C
Tstg
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values, except differential voltages, are with respect to GND
6.2 ESD Ratings
VALUE
±450
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
Electrostatic
discharge
V(ESD)
V
±1000
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
2.5
NOM
MAX
16
UNIT
Single Supply
Split Supply
VCC
TA
Supply Voltage
V
±1.25
–55
±8
Operating free-air temperature
125
°C
6.4 Thermal Information – TLV6003
TLV6003
THERMAL METRIC(1)
DBV
5 PINS
166.0
89.9
UNIT
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
36.5
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
14.0
ψJB
36.3
RθJC(bot)
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
4
Copyright © 2019, Texas Instruments Incorporated
TLV6003
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ZHCSKC8 –OCTOBER 2019
6.5 Electrical Characteristics
at TA = 25°C, VCC = 2.7 V, 5 V, and 15 V, VICR = VO = VCC/2 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
DC PERFORMANCE
390
±550
µV
VIO
Input offset voltage(1)
TA = –55°C to +125°C
TA = –55°C to +125°C
1500
dVIO/dT
Offset voltage drift
2
µV/°C
VCC = 2.7 V
63
60
66
63
76
75
120
VCC = 2.7 V,
TA = –40°C to +125°C
VCC = 5 V
120
120
Common-mode
rejection ratio
CMRR
VICR = 0 V to VCC
dB
VCC = 5 V,
TA = –40°C to +125°C
VCC = 15 V
VCC = 15 V,
TA = –40°C to +125°C
VCC = 2.7 V, 0.2 V < VO < VCC – 0.2 V, RL = 500 kΩ
VCC = 15 V, 0.2 V < VO < VCC – 0.2 V, RL = 500 kΩ
112
123
dB
dB
AOL
Open-loop gain
INPUT
IIO
25
250
pA
Input offset current
Input bias current
TA = –40°C to +125°C
TA = –40°C to +125°C
1200
100
250
pA
2000
IIB
Differential input
resistance
ri(d)
300
3
MΩ
Common-mode input
capacitance
Ci(c)
f = 100 kHz
pF
DYNAMIC PERFORMANCE
UGBW
SR
Unity gain bandwidth
Slew rate at unity gain
Phase margin
RL = 500 kΩ, CL = 100 pF
5.5
2.5
60
kHz
V/ms
°
VO(pp) = 0.8 V, RL = 500 kΩ, CL = 100 pF
RL = 500 kΩ, CL = 100 pF
PM
Gain margin
RL = 500 kΩ, CL = 100 pF
15
dB
VCC = 2.7 or 5 V, V(STEP)PP = 1 V,
0.1%
1.84
AV = –1, CL = 100 pF, RL = 100 kΩ
ts
Settling time
ms
0.1%
6.1
32
VCC = 15 V, V(STEP)PP = 1 V,
AV = –1, CL = 100 pF, RL = 100 kΩ
0.01%
NOISE PERFORMANCE
f = 10 Hz
800
500
Equivalent input noise
voltage
Vn
nV/√Hz
fA/√Hz
f = 100 Hz
Equivalent input noise
current
In
f = 100 Hz
8
OUTPUT
VCC – 0.05
VCC – 0.07
VCC – 0.08
VCC – 0.1
VCC – 0.02
VCC – 0.05
0.090
IOL = 2 µA (sourcing)
IOL = 50 µA (sourcing)
IOH = 2 µA (sinking)
TA = –40°C to +125°C
TA = –40°C to +125°C
TA = –40°C to +125°C
TA = –40°C to +125°C
Voltage output swing
from the positive rail
VOL
V
0.150
0.180
0.230
0.260
μA
Voltage output swing
from the negative rail
VOH
0.180
IOH = 50 µA (sinking)
VO = 0.5 V from rail
IO
Output current
±200
(1) Input offset voltage and offset voltage drift are specified by characterization from TA = –55°C to +125°C. All other temperature
specifications cover the range of TA = –40°C to +125°C, as listed in the test conditions column.
Copyright © 2019, Texas Instruments Incorporated
5
TLV6003
ZHCSKC8 –OCTOBER 2019
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Electrical Characteristics (continued)
at TA = 25°C, VCC = 2.7 V, 5 V, and 15 V, VICR = VO = VCC/2 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
980
MAX UNIT
POWER SUPPLY
1200
VCC = 2.7 V and 5 V
VCC = 15 V
TA = –40°C to +125°C
1350
nA
1250
ICC
Supply current
1000
TA = –40°C to +125°C
1400
nA
Reverse supply current VCC = –18 V, VIN = 0 V, VO = open current
50
90
85
100
VCC = 2.7 to 5 V, no load
TA = –40°C to 125°C
Power supply rejection
ratio (ΔVCC/ΔVOS
PSRR
dB
)
100
95
110
VCC = 5 to 15 V, no load
TA = –40°C to 125°C
6
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TLV6003
www.ti.com.cn
ZHCSKC8 –OCTOBER 2019
6.6 Typical Characteristics
at TA = 25°C and VCC = 5 V (unless otherwise noted)
6
5
4
3
2
1
1400
1200
1000
800
600
400
200
0
–200
-600
-400
-200
0
200
400
600
–0.10.20 0.60 1.00 1.40 1.80 2.20 2.60 2.9
C002
V
– Common-Mode Input Voltage – V
VIO - Input Offset Voltage - mV
ICR
VCC = 2.7 V
图 2. Input Offset Voltage vs Common-Mode Input Voltage
图 1. Input Offset Voltage Histogram
100
400
300
200
0
–100
–200
–300
–400
100
0
–100
–200
–300
–400
0.4 1.0 1.6 2.2 2.8 3.4 4.0 4.6 5.2
–0.1
2.0
–0.1
4.2
6.4
8.6 10.8 13.0 15.2
V
– Common-Mode Input Voltage – V
V
– Common-Mode Input Voltage – V
ICR
ICR
VCC = 5 V
VCC = 15 V
图 3. Input Offset Voltage vs Common-Mode Input Voltage
图 4. Input Offset Voltage vs Common-Mode Input Voltage
600
600
500
400
300
200
100
500
400
300
200
100
I
IO
I
IO
0
0
I
IB
I
IB
–100
–200
–100
–200
–40 –25 –10
5
20 35 50 65 80 95 110 125
–40 –25 –10
5
20 35 50 65 80 95 110 125
T
A
– Free-Air Temperature – °C
T
A
– Free-Air Temperature – °C
VCC = 2.7 V
VCC = 5.0 V
图 5. Input Bias Current and Offset Current vs Free-Air
图 6. Input Bias Current and Offset Current vs Common-
Temperature
Mode Input Voltage
版权 © 2019, Texas Instruments Incorporated
7
TLV6003
ZHCSKC8 –OCTOBER 2019
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Typical Characteristics (接下页)
at TA = 25°C and VCC = 5 V (unless otherwise noted)
700
400
350
300
250
200
150
100
50
600
500
400
300
200
100
I
I
IO
I
IO
0
0
–50
–100
–150
IB
–100
I
IB
–200
–40 –25 –10
5
20 35 50 65 80 95 110 125
0.2 0.6 1.0 1.4 1.8 2.2 2.6 2.9
–0.1
T
A
– Free-Air Temperature – °C
V
– Common Mode Input Voltage – V
ICR
VCC = 15 V
VCC = 2.7 V
图 7. Input Bias Current and Offset Current vs Free-Air
图 8. Input Bias Current and Offset Current vs Common-
Temperature
Mode Input Voltage
200
150
100
50
250
200
150
100
50
I
IO
I
IO
0
0
–50
–50
I
IB
I
IB
–100
–150
–100
–150
–0.1
0.4 1.0 1.6 2.2 2.8 3.4 4.0 4.6 5.2
2.0
–0.1
4.2
6.4
8.6 10.8 13.0 15.2
V
– Common Mode Input Voltage – V
ICR
V
– Common-Mode Input Voltage –V
ICR
VCC = 5.0 V
VCC = 15.0 V
图 9. Input Bias Current and Offset Current vs Common-
图 10. Input Bias Current and Offset Current vs Common-
Mode Input Voltage
Mode Input Voltage
120
2.7
2.4
100
80
60
40
20
0
T
A
= –40°C
2.1
1.8
1.5
1.2
T
A
= –0°C
T
= 25 °C
= 70 °C
= 125 °C
A
T
A
T
A
0
50
100
150
200
1
10
100
1k
10k
f – Frequency – Hz
I
– High-Level Output Current – mA
OH
图 11. Common-Mode Rejection Ratio vs Frequency
图 12. High-Level Output Voltage vs High-Level Output
Current
8
版权 © 2019, Texas Instruments Incorporated
TLV6003
www.ti.com.cn
ZHCSKC8 –OCTOBER 2019
Typical Characteristics (接下页)
at TA = 25°C and VCC = 5 V (unless otherwise noted)
1.50
5.0
4.5
4.0
3.5
3.0
T
A
= –40°C
1.25
1.00
0.75
0.50
0.25
0
T
= 25 °C
= 0 °C
A
T
A
T
A
= –40°C
T
A
= –0°C
T
= 25 °C
= 70 °C
= 125 °C
A
T
= 70 °C
A
T
A
T
= 125 °C
A
T
A
0
50
100
150
200
0
50
100
150
200
I
– Low-Level Output Current – mA
I
– High-Level Output Current – mA
OL
OH
图 13. Low-Level Output Voltage vs Low-Level Output
图 14. High-Level Output Voltage vs High-Level Output
Current
Current
1.50
1.25
15.0
T
A
= 0 °C
14.5
T
= –40°C
A
1.00
0.75
0.50
0.25
0
T
A
= –0°C
T
= 25 °C
= 70 °C
= 125 °C
14.0
13.5
13
A
T
A
= 25 °C
= 70 °C
= 125 °C
T
A
T
A
T
A
T
A
T
A
= –40°C
0
50
100
150
200
0
50
100
150
200
I
– Low-Level Output Current – mA
I
– High-Level Output Current – mA
OL
OH
图 15. Low-Level Output Voltage vs Low-Level Output
图 16. High-Level Output Voltage vs High-Level Output
Current
Current
1.50
1.25
16
14
12
10
8
T
A
= –40°C
1.00
0.75
0.50
0.25
0
T
= –0°C
A
T
A
= 25 °C
= 70 °C
= 125 °C
6
T
A
T
A
4
2
V
= 5 V
CC
V
= 2.7 V
CC
0
0
50
100
150
200
10
100
f – Frequency – Hz
1k
I
– Low-Level Output Current – mA
OL
图 17. Low-Level Output Voltage vs Low-Level Output
图 18. Output Voltage Peak-to-Peak vs Frequency
Current
版权 © 2019, Texas Instruments Incorporated
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ZHCSKC8 –OCTOBER 2019
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Typical Characteristics (接下页)
at TA = 25°C and VCC = 5 V (unless otherwise noted)
10k
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
AV = 10
1k
AV = 1
T
= 125°C
= 70 °C
= 25 °C
= 0 °C
A
T
A
100
T
A
T
A
T
A
= –40°C
10
0
2
4
6
8
10 12 14 16
100
1k
10k
f – Frequency – Hz
V
– Supply Voltage – V
CC
图 19. Output Impedance vs Frequency
图 20. Supply Current vs Supply Voltage
120
60
135
50
110
100
90
40
30
20
10
90
45
80
70
0
0
60
–10
50
–20
–45
40
10
100
1k
10k
10
100
1k
10k
f – Frequency – Hz
f – Frequency – Hz
图 22. Open-Loop Gain and Phase vs Frequency
图 21. Power Supply Rejection Ratio vs Frequency
7
3.5
6
5
4
3
2
1
3.0
2.5
2.0
1.5
1.0
0.5
0
SR+
V
= 5, 15 V
CC
V
= 2.7 V
CC
V
= 2.7, 5, & 15 V
CC
SR–
0
2.5 4.0 5.5 7.0 8.5 10.0 11.5 13.0 14.5 16.0
–40 –25 –10
5
20 35 50 65 80 95 110 125
V
– Supply Voltage –V
T
A
– Free-Air Temperature – °C
CC
图 23. Gain Bandwidth Product vs Supply Voltage
图 24. Slew Rate vs Free-Air Temperature
10
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TLV6003
www.ti.com.cn
ZHCSKC8 –OCTOBER 2019
Typical Characteristics (接下页)
at TA = 25°C and VCC = 5 V (unless otherwise noted)
80
4
3
70
60
50
40
30
20
10
0
2
1
0
–1
–2
–3
–4
0
1
2
3
4
5
6
7
8
9
10
10
100
1k
10k
t – Time – s
C
– Capacitive Load – pF
L
图 26. Voltage Noise Over a 10-Second Period
图 25. Phase Margin vs Capacitive Load
4
2.0
3
V
3
IN
2
V
IN
2
1
0
1
0
0.5
4
0.0
–1
3
–1
–0.5
–1.0
–1.5
–2
2
V
O
1
V
O
0
0
1
2
3
4
5
6
0
1
2
3
4
5
6
7
t – Time – ms
t – Time – ms
AV = 1
AV = –1
图 27. Large-Signal Step Response
图 28. Large-Signal Step Response
120
100
80
50
300
200
V
V
IN
IN
150
0
100
0
–150
–100
0
60
V
O
40
–50
–100
–150
V
20
O
0
0
100 200 300 400 0 500
0
200 400 600 800 1000 1200
t – Time – ms
t – Time – ms
AV = 1
AV = –1
图 29. Small-Signal Step Response
图 30. Small-Signal Step Response
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TLV6003
ZHCSKC8 –OCTOBER 2019
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7 Detailed Description
7.1 Overview
The TLV6003 is a nanopower operational amplifier consuming only 980 nA per channel, while offering very low
maximum offset. Reverse battery protection guards the amplifier from overcurrent conditions due to improper
battery installation. The TLV6003 is based on a rail-to-rail bipolar technology that is specifically designed to allow
high common-mode-range functionality. For harsh environments, the inputs can be taken 5 V greater than the
positive supply rail without damage to the device. Offset is specified by characterization to an ambient
temperature of –55°C, making the TLV6003 a good choice for low-temperature industrial automation.
7.2 Functional Block Diagram
VCC
VBIAS1
INœ
IN+
Class AB
Control
Circuitry
OUT
VBIAS2
GND
12
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7.3 Feature Description
7.3.1 Reverse-Battery Protection
The TLV6003 is protected against reverse-battery voltage up to 18 V. When subjected to reverse-battery
conditions, the supply current is typically 50 nA at 25°C (inputs grounded and outputs open). This current is
determined by the leakage of internal Schottky diodes, and therefore increases as the ambient temperature
increases.
When subjected to reverse-battery conditions, and negative voltages are applied to the inputs or outputs, the
input ESD structure conducts current; limit this current to less than 10 mA. If the inputs or outputs are referred to
ground rather than midrail, no extra precautions are required.
7.3.2 Common-Mode Input Range
The TLV6003 has rail-to-rail inputs and outputs. For common-mode inputs from –0.1 V to VCC – 0.8 V, a PNP
differential pair provides the gain.
For inputs between VCC – 0.8 V and VCC, two NPN emitter followers buffering a second PNP differential pair
provide the gain.
This special combination of a NPN and PNP differential pair enables the inputs to be taken 5 V greater than VCC
.
As the inputs rise to greater than VCC, the NPNs change from functioning as transistors to functioning as diodes.
This change leads to an increase in input bias current. The second PNP differential pair continues to function
normally as the inputs exceed VCC
.
The TLV6003 has a negative common-mode input voltage range that can fall to less than VGND by 100 mV. If the
inputs are taken to less than VGND – 0.1, reduced open-loop gain will be observed.
7.4 Device Functional Modes
The TLV6003 has a single functional mode and is operational when the power-supply voltage is greater than 2.5
V. The maximum specified power-supply voltage for the TLV6003 is 16 V.
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8 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
8.1.1 Drive a Capacitive Load
The TLV6003 is internally compensated for stable unity-gain operation, with a 5.5-kHz typical gain bandwidth.
However, the unity gain follower is the most sensitive configuration to capacitive load. The combination of a
capacitive load placed directly on the output of an amplifier along with the amplifier output impedance creates a
phase lag, which reduces the phase margin of the amplifier. If the phase margin is significantly reduced, the
response will be underdamped, which causes peaking in the transfer function. This condition creates very low
phase margin, and leads to excessive ringing or oscillations.
In order to drive heavy (> 50 pF) capacitive loads, an isolation resistor (RISO) must be used, as shown in 图 31.
By using this isolation resistor, the capacitive load is isolated from the amplifier output. The higher the value of
RISO, the more stable the amplifier. If the value of RISO is sufficiently high, the feedback loop is stable,
independent of the value of CL. However, larger values of RISO result in reduced output swing and reduced
output current drive. The recommended value for RISO is 30 kΩ to 50 kΩ.
R
ISO
-
V
OUT
V
IN
+
C
L
图 31. Resistive Isolation of Capacitive Load
14
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TLV6003
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ZHCSKC8 –OCTOBER 2019
8.2 Typical Application
图 32 shows a simple micropower potentiostat circuit for use with three-terminal unbiased CO sensors; although,
the design is applicable to many other type of three-terminal gas sensors or electrochemical cells.
The basic sensor has three electrodes: the sense or working electrode (WE), counter electrode (CE) and
reference electrode (RE). A current flows between the CE and WE proportional to the detected concentration.
The RE monitors the potential of the internal reference point. For an unbiased sensor, the WE and RE electrodes
must be maintained at the same potential by adjusting the bias on CE. Through the potentiostat circuit formed by
U1, the servo feedback action maintains the RE pin at a potential set by VREF
.
R1 maintains stability due to the large capacitance of the sensor.
C1 and R2 form the potentiostat integrator and set the feedback time constant.
U2 forms a transimpedance amplifier (TIA) to convert the resulting sensor current into a proportional voltage. The
transimpedance gain, and resulting sensitivity, is set by RF according to 公式 1.
VTIA = (–I * RF) + VREF
(1)
RL is a load resistor with a value that is normally specified by the sensor manufacturer (typically, 10 Ω). The
potential at WE is set by the applied VREF.
Riso provides capacitive isolation and, combined with C2, form the output filter and ADC reservoir capacitor to
drive the ADC.
R1
10 kꢀ
C1
0.1µF
Potentiostat (Bias Loop)
CE
R2
10 kΩ
2.5V
RE
CO Sensor
U1
+
VREF
WE
Transimpedance Amplifier (I to V conversion)
RF
ISENS
Riso
49.9 kꢀ
RL
U2
VTIA
+
VREF
C2
1µF
图 32. Three Terminal CO Gas Sensor
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Typical Application (接下页)
8.2.1 Design Requirements
For this example, an electrical model of a CO sensor is used to simulate the sensor performance, as shown in 图
33. The simulation is designed to model a CO sensor with a sensitivity of 69 nA/ppm. The supply voltage and
maximum ADC input voltage is 2.5 V, and the maximum concentration is 300 ppm.
CO Sensor
Model
VCE
10 kΩ
CE
300 Ω
260 mF
10 µF
2 Ω
2 Ω
2.5 V
10 kΩ
RE
œ
VREF
+
TLV6003
130 mF
300 Ω
110 kΩ
VTIA
ISENS
0 - 20 µA
2.5 V
10 Ω
WE
œ
VREF
+
TLV6003
图 33. CO Sensor Simulation Schematic
表 1. Design Parameters
DESIGN PARAMETER
Supply voltage
EXAMPLE VALUE
2.5 V
Amplifier quiescent current
< 2 µA
Transimpedance amplifier
sensitivity
110 mV/µA
16
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TLV6003
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ZHCSKC8 –OCTOBER 2019
8.2.2 Detailed Design Procedure
First, determine the VREF voltage. This voltage is a compromise between maximum headroom and resolution, as
well as allowance for the minimum swing on the CE terminal because the CE terminal generally goes negative in
relation to the RE potential as the concentration (sensor current) increases. Bench measurements found the
difference between CE and RE to be 180 mV at 300 ppm for this particular sensor.
To allow for negative CE swing, footroom, and voltage drop across the 10-kΩ resistor, 300 mV is chosen for
VREF
.
Therefore, 300 mV is used as the minimum VZERO to add some headroom.
VZERO = VREF = 300 mV
where
•
•
VZERO is the zero concentration voltage.
VREF is the reference voltage (300 mV).
(2)
Next, calculate the maximum sensor current at highest expected concentration:
ISENSMAX = IPERPPM * ppmMAX = 69 nA * 300 ppm = 20.7 µA
where
•
•
•
ISENSMAX is the maximum expected sensor current.
IPERPPM is the manufacturer specified sensor current in Amps per ppm.
ppmMAX is the maximum required ppm reading.
(3)
(4)
Then, find the available output swing range greater than the reference voltage available for the measurement:
VSWING = VOUTMAX – VZERO = 2.5 V – 0.3 V = 2.2 V
where
•
•
VSWING is the expected change in output voltage
VOUTMAX is the maximum amplifer output swing (usually near VCC
)
Finally, calculate the transimpedance resistor (RF) value using the maximum swing and the maximum sensor
current:
RF = VSWING / ISENSMAX = 2.2 V / 20.7 µA = 106.28 kΩ (use 110 kΩ for a common value)
(5)
8.2.3 Application Curve
VTIA
VCE
ISENS
2.5 V
0.3 V
20 mA
Time (10 ms/div)
C012
图 34. Sensor Transient Response to Simulated 300-ppm CO Exposure
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ZHCSKC8 –OCTOBER 2019
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9 Power Supply Recommendations
The TLV6003 is specified for operation from 2.5 V to 16 V (±1.25 V to ±8 V) over a –40°C to +125°C temperature
range.
CAUTION
Supply voltages larger than 17 V can permanently damage the device.
For proper operation, the power supplies must be properly decoupled. For decoupling the supply lines, place 100
nF capacitors as close as possible to the operational amplifier power supply pins. For single-supply operation,
place a capacitor between VCC and GND supply leads. For dual supplies, place one capacitor between VCC and
ground, and one capacitor between GND and ground.
Low-bandwidth nanopower devices do not have good high-frequency (> 1 kHz) AC PSRR rejection against high-
frequency switching supplies and other 1-kHz and greater noise sources. Therefore, use extra supply filtering if
kilohertz or greater noise is expected on the power supply lines.
10 Layout
10.1 Layout Guidelines
•
•
•
•
•
Bypass the VCC pin to ground with a low ESR capacitor.
The best placement is closest to the VCC and ground pins.
Take care to minimize the loop area formed by the bypass capacitor connection between VCC and ground.
Connect the ground pin to the PCB ground plane at the pin of the device.
Place the feedback components as close as possible to the device to minimize strays.
10.2 Layout Example
Minimize parasitic
inductance by placing
bypass capacitor
VCC
CBYPASS
close to VCC
.
VOUT
OUT
VCC
GND
+IN
-IN
RF
Keep high
impedance input
signal away from
noisy traces.
VIN
Route trace under
package for output to
feedback resistor
connection.
图 35. SOT-23 Layout Example (Top View)
18
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TLV6003
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ZHCSKC8 –OCTOBER 2019
11 器件和文档支持
11.1 器件支持
11.1.1 开发支持
•
•
•
•
《基于 SPICE 的 TINA-TI 模拟仿真程序》
DIP 适配器评估模块
TI 通用运算放大器评估模块
TI 滤波器设计工具
11.2 文档支持
11.2.1 相关文档
请参阅如下相关文档：
•
•
•
《单电源、低侧、单向电流检测电路》应用报告
《使用纳瓦级功耗运算放大器简化功率敏感型工厂和楼宇自动化系统中的环境测量》应用手册
《由锂离子电池供电的个人电子产品中的 GPIO 引脚电源信号链》应用简介
11.3 接收文档更新通知
要接收文档更新通知，请导航至 ti.com. 上的器件产品文件夹。单击右上角的通知我进行注册，即可每周接收产品
信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
11.4 社区资源
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.5 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.6 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
11.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。
版权 © 2019, Texas Instruments Incorporated
19
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TLV6003DBVR
ACTIVE
SOT-23
DBV
5
3000 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
1NE9
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Oct-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TLV6003DBVR
SOT-23
DBV
5
3000
180.0
8.4
3.2
3.2
1.4
4.0
8.0
Q3
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Oct-2019
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SOT-23 DBV
SPQ
Length (mm) Width (mm) Height (mm)
210.0 185.0 35.0
TLV6003DBVR
5
3000
Pack Materials-Page 2
PACKAGE OUTLINE
DBV0005A
SOT-23 - 1.45 mm max height
S
C
A
L
E
4
.
0
0
0
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
0.1 C
1.75
1.45
1.45
0.90
B
A
PIN 1
INDEX AREA
1
2
5
(0.1)
2X 0.95
1.9
3.05
2.75
1.9
(0.15)
4
3
0.5
5X
0.3
0.15
0.00
(1.1)
TYP
0.2
C A B
NOTE 5
0.25
GAGE PLANE
0.22
0.08
TYP
8
0
TYP
0.6
0.3
TYP
SEATING PLANE
4214839/G 03/2023
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.25 mm per side.
5. Support pin may differ or may not be present.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X (0.95)
4
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214839/G 03/2023
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X(0.95)
4
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214839/G 03/2023
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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