TMUX6212RUMR [TI]

TMUX621x 36-V, Low-Ron, 1:1 (SPST), 4-Channel Precision Switches with 1.8-V Logic;


型号：	TMUX6212RUMR
厂家：	TEXAS INSTRUMENTS
描述：	TMUX621x 36-V, Low-Ron, 1:1 (SPST), 4-Channel Precision Switches with 1.8-V Logic
文件：	总26页 (文件大小：909K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TMUX6211, TMUX6212, TMUX6213

TMUX6211, T_SM_CU_DX_S46₃2₁1_–2_O, _CT_TM_OU_BEX_R6₂2₀1₂3₀

SCDS431 – OCTOBER 2020

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TMUX621x 36-V, Low-Ron, 1:1 (SPST), 4-Channel Precision Switches with 1.8-V Logic

1 Features

3 Description

•

Dual Supply Range: ±4.5 V to ±18 V

Single Supply Range: 4.5 V to 36 V

Low On-Resistance: 2 Ω

–40°C to +125°C Operating Temperature

Logic Levels: L8 V to VDD

Fail-Safe Logic

Rail-to-Rail Operation

Bidirectional Operation

Break-Before-Make Switching

ESD Protection HBM: 2000 V

The TMUX6211, TMUX6212, and TMUX6213 are

complementary metal-oxide semiconductor (CMOS)

switches with four independently selectable 1:1,

single-pole, singlethrow (SPST) switch channels. The

devices work well with dual supplies (±4.5 V to

±18 V), a single supply (4.5 V to 36 V), or asymmetric

supplies (such as V_DD= 12 V, V_SS= –5 V). The

TMUX621x supports bidirectional analog and digital

signals on the source (Sx) and drain (D) pins ranging

from V_SSto V_DD.

The switches of the TMUX6211 are turned on with

Logic 0 on the appropriate logic control inputs, while

Logic 1 is required to turn on switches in the

TMUX6212. The four channels of the TMUX6213 are

split with two switches supporting Logic 0, while the

other two switches support Logic 1. The TMUX6213

exhibits break-before-make switching, allowing the

device to be used in cross-point switching

applications.

2 Applications

•

Sample-and-Hold Circuits

Feedback Gain Switching

Signal Isolation

Field Transmitters

Programmable Logic Controllers (PLC)

Factory Automation and Control

Ultrasound Scanners

Patient Monitoring & Diagnostics

Electrocardiogram (ECG)

Data Acquisition Systems (DAQ)

Semiconductor Test Equipment

LCD Test

The TMUX621x are part of the precision switches and

multiplexers family of devices. These devices have

very low on and off leakage currents and low charge

injection, allowing them to be used in high precision

measurement applications.

Device Information ⁽¹⁾

PART NUMBER

PACKAGE

BODY SIZE (NOM)

Instrumentation: Lab, Analytical, Portable

Ultrasonic Smart Meters: Water and Gas

Optical Networking

TMUX6211

TSSOP (16) (PW)

5.00 mm × 4.40 mm

TMUX6212

WQFN (16) (RUM)

4.00 mm x 4.00 mm

Optical Test Equipment

TMUX6213

(1) For all available packages, see the package option

addendum at the end of the data sheet.

CHANNEL 1

CHANNEL 2

CHANNEL 3

CHANNEL 4

CHANNEL 1

CHANNEL 2

CHANNEL 3

CHANNEL 4

CHANNEL 2

CHANNEL 3

CHANNEL 4

SEL1

SEL2

SEL3

SEL4

SEL1

SEL2

SEL3

SEL4

SEL1

SEL2

SEL3

SEL4

TMUX1111

TMUX1112

ALL SWITCHES SHOWN FOR A LOGIC 0 INPUT

TMUX1113

TMUX621x Block Diagrams

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. ADVANCE INFORMATION for preproduction products; subject to change

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Table of Contents

1 Features............................................................................1

2 Applications.....................................................................1

3 Description.......................................................................1

4 Revision History.............................................................. 2

5 Device Comparison Table...............................................3

6 Pin Configuration and Functions...................................3

7 Specifications.................................................................. 4

7.1 Absolute Maximum Ratings ....................................... 4

7.2 ESD Ratings .............................................................. 4

7.3 Thermal Information ...................................................4

7.4 Recommended Operating Conditions ........................5

7.5 Source or Drain Continuous Current ..........................5

7.6 ±15 V Dual Supply: Electrical Characteristics ...........6

7.7 ±15 V Dual Supply: Switching Characteristics ..........7

7.8 12 V Single Supply: Electrical Characteristics .......... 8

7.9 12 V Single Supply: Switching Characteristics ......... 9

7.10 ±5 V Dual Supply: Electrical Characteristics .........10

7.11 ±5 V Dual Supply: Switching Characteristics .........11

8 Detailed Description......................................................12

8.1 Overview...................................................................12

8.2 Functional Block Diagram.........................................12

8.3 Feature Description...................................................12

8.4 Device Functional Modes..........................................13

8.5 Truth Tables.............................................................. 13

9 Application and Implementation..................................14

9.1 Application Information............................................. 14

9.2 Typical Application ................................................... 14

9.3 Design Requirements............................................... 15

9.4 Detailed Design Procedure.......................................15

10 Power Supply Recommendations..............................16

11 Layout...........................................................................17

11.1 Layout Guidelines................................................... 17

11.2 Layout Example...................................................... 18

12 Device and Documentation Support..........................19

12.1 Documentation Support.......................................... 19

12.2 Receiving Notification of Documentation Updates..19

12.3 Support Resources................................................. 19

12.4 Trademarks.............................................................19

12.5 Electrostatic Discharge Caution..............................19

12.6 Glossary..................................................................19

13 Mechanical, Packaging, and Orderable

Information.................................................................... 20

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

DATE

REVISION

NOTES

October 2020

Initial Release

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5 Device Comparison Table

PRODUCT

TMUX6211

TMUX6212

DESCRIPTION

Low-Leakage-Current, Precision, 4-Channel, 1:1 (SPST) Switches (Normally Closed)

Low-Leakage-Current, Precision, 4-Channel, 1:1 (SPST) Switches (Normally Open)

TMUX6213

Low-Leakage-Current, Precision, 4-Channel, 1:1 (SPST) Switches (Dual Open + Dual Closed)

6 Pin Configuration and Functions

SEL1

SEL2

VSS

GND

VSS

GND

VDD

N.C.

VDD

N.C.

Thermal

Pad

SEL4

SEL3

Not to scale

Figure 6-1. PW Package

16-Pin TSSOP

Figure 6-2. RUM Package

16-Pin WQFN

Top View

Table 6-1. Pin Functions

TYPE⁽¹⁾

DESCRIPTION⁽²⁾

NAME

TSSOP

WQFN

Logic control input 1, has internal pull-down resistor. Controls channel 1 state as shown in Section

8.5.

SEL1

I/O

Drain pin 1. Can be an input or output.

Source pin 1. Can be an input or output.

Negative power supply. This pin is the most negative power-supply potential. In single-supply

applications, this pin can be connected to ground. For reliable operation, connect a decoupling

capacitor ranging from 0.1 μF to 10 μF between V_SSand GND.

VSS

GND

Ground (0 V) reference

I/O

Source pin 4. Can be an input or output.

Drain pin 4. Can be an input or output.

Logic control input 4, has internal pull-down resistor. Controls channel 4 state as shown in Section

8.5.

SEL4

SEL3

Logic control input 3, has internal pull-down resistor. Controls channel 3 state as shown in Section

8.5.

I/O

Drain pin 3. Can be an input or output.

Source pin 3. Can be an input or output.

No internal connection.

N.C.

Positive power supply. This pin is the most positive power-supply potential. For reliable operation,

connect a decoupling capacitor ranging from 0.1 µF to 10 µF between V_DDand GND.

VDD

I/O

Source pin 2. Can be an input or output.

Drain pin 2. Can be an input or output.

Logic control input 2, has internal pull-down resistor. Controls channel 2 state as shown in Section

8.5.

SEL2

(1) I = input, O = output, I/O = input and output, P = power.

(2) Refer to Section 8.4 for what to do with unused pins.

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7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)^{(1) (2) (3)}

MIN

MAX

UNIT

V_DD–V_SS

V_DD

Supply voltage

–0.5

–38

V_SS

0.5

V_SELor V_EN

I_SELor I_EN

V_Sor V_D

I_IK

Logic control input pin voltage (SELx)⁽⁴⁾

Logic control input pin current (SELx)⁽⁴⁾

Source or drain voltage (Sx, Dx)⁽⁴⁾

Diode clamp current⁽⁴⁾

–0.5

–30

V_SS–0.5

–30

V_DD+0.5

°C

I_Sor I_{D (CONT)}

T_A

Source or drain continuous current (Sx, Dx)

Ambient temperature

I_DC+ 10 %⁽⁵⁾

–55

–65

135

150

140

T_stg

Storage temperature

T_J

Junction temperature

(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under

Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device

reliability.

(2) The algebraic convention, whereby the most negative value is a minimum and the most positive value is a maximum.

(3) All voltages are with respect to ground, unless otherwise specified.

(4) Pins are diode-clamped to the power-supply rails. Over voltage signals must be voltage and current limited to maximum ratings.

(5) Refer to Source or Drain Continuous Current table for I_DCspecifications.

7.2 ESD Ratings

VALUE

UNIT

Human body model (HBM), per ANSI/ESDA/

JEDEC JS-001, all pins⁽¹⁾

±2000

V_(ESD)

Electrostatic discharge

Charged device model (CDM), per JEDEC

specification JESD22-C101, all pins⁽²⁾

±500

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Thermal Information

TMUX721x

THERMAL METRIC⁽¹⁾

PW (TSSOP)

16 PINS

94.5

RUM (WQFN)

16 PINS

TBD

UNIT

R_θJA

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

°C/W

R_θJC(top)

R_θJB

25.5

TBD

41.1

TBD

Ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

1.1

TBD

Ψ_JB

40.4

TBD

R_θJC(bot)

N/A

TBD

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

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7.4 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

4.5

V_SS

NOM

MAX

UNIT

(1)

V_DD- V_SS

V_DD

Power supply voltage differential

Positive power supply voltage

V_Sor V_D

V_SELor V_EN

I_Sor I_{D (CONT)}

T_A

Signal path input/output voltage (source or drain pin) (Sx, D)

Address or enable pin voltage

V_DD

(2)

Source or drain continuous current (Sx, D)

Ambient temperature

I_DC

–40

125

°C

(1) V_DDand V_SScan be any value as long as 4.5 V ≤ (V_DD– V_SS) ≤ 36 V, and the minimum V_DDis met.

(2) Refer to Source or Drain Continuous Current table for I_DCspecifications.

7.5 Source or Drain Continuous Current

at supply voltage of V_DD± 10%, V_SS± 10 % (unless otherwise noted)

CONTINUOUS CURRENT PER CHANNEL (I_DC

PACKAGE TEST CONDITIONS

±15 V Dual Supply

)

T_A= 25°C

T_A= 85°C

T_A= 125°C

145

UNIT

370

240

+12 V Single Supply

±5 V Dual Supply

+5 V Single Supply

270

260

200

190

180

140

120

118

100

PW (TSSOP)

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7.6 ±15 V Dual Supply: Electrical Characteristics

V_DD= +15 V ± 10%, V_SS= –15 V ±10%, GND = 0 V (unless otherwise noted)

Typical at V_DD= +15 V, V_SS= –15 V, T_A= 25℃ (unless otherwise noted)

PARAMETER

TEST CONDITIONS

T_A

MIN

TYP

MAX UNIT

ANALOG SWITCH

25°C

3.9

V_S= –10 V to +10 V

I_D= –10 mA

R_ON

On-resistance

–40°C to +85°C

–40°C to +125°C

25°C

4.6

0.05

0.45

0.2

On-resistance mismatch between V_S= –10 V to +10 V

ΔR_ON

–40°C to +85°C

–40°C to +125°C

25°C

0.25

0.3

channels

I_D= –10 mA

0.65

0.8

V_S= –10 V to +10 V

I_S= –10 mA

R_{ON FLAT}On-resistance flatness

R_{ON DRIFT}On-resistance drift

–40°C to +85°C

–40°C to +125°C

25°C

0.95

V_S= 0 V, I_S= –10 mA

0.01

0.05

0.5

Ω/°C

V_DD= 16.5 V, V_SS= –16.5 V

Switch state is off

V_S= +10 V / –10 V

I_S(OFF)

Source off leakage current⁽¹⁾

Drain off leakage current⁽¹⁾

Channel on leakage current⁽²⁾

–40°C to +85°C

–40°C to +125°C

25°C

–35

–60

V_D= –10 V / + 10 V

V_DD= 16.5 V, V_SS= –16.5 V

Switch state is off

V_S= +10 V / –10 V

0.05

–40°C to +85°C

–40°C to +125°C

25°C

I_D(OFF)

V_D= –10 V / + 10 V

0.05

V_DD= 16.5 V, V_SS= –16.5 V

Switch state is on

V_S= V_D= ±10 V

I_S(ON)

I_D(ON)

–40°C to +85°C

–40°C to +125°C

LOGIC INPUTS (SEL / EN pins)

V_IH

V_IL

I_IH

Logic voltage high

–40°C to +125°C

1.3

0.8

1.2

Logic voltage low

Input leakage current

Logic input capacitance

0.4

µA

I_IL

–0.1 –0.005

C_IN

POWER SUPPLY

25°C

µA

V_DD= 16.5 V, V_SS= –16.5 V

Logic inputs = 0 V, 5 V, or V_DD

I_DD

V_DDsupply current

–40°C to +85°C

–40°C to +125°C

25°C

V_DD= 16.5 V, V_SS= –16.5 V

Logic inputs = 0 V, 5 V, or V_DD

I_SS

V_SSsupply current

–40°C to +85°C

–40°C to +125°C

(1) When V_Sis positive, V_Dis negative, or when V_Sis negative, V_Dis positive.

(2) When V_Sis at a voltage potential, V_Dis floating, or when V_Dis at a voltage potential, V_Sis floating.

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7.7 ±15 V Dual Supply: Switching Characteristics

V_DD= +15 V ± 10%, V_SS= –15 V ±10%, GND = 0 V (unless otherwise noted)

Typical at V_DD= +15 V, V_SS= –15 V, T_A= 25℃ (unless otherwise noted)

PARAMETER

TEST CONDITIONS

T_A

MIN

TYP

MAX UNIT

25°C

100

150

170

190

170

190

210

185

200

210

V_S= 10 V

R_L= 300 Ω, C_L= 35 pF

t_TRAN

Transition time from control input

–40°C to +85°C

–40°C to +125°C

25°C

130

110

V_S= 10 V

R_L= 300 Ω, C_L= 35 pF

t_ON

Turn-on time from control input

Turn-off time from control input

–40°C to +85°C

–40°C to +125°C

25°C

V_S= 10 V

R_L= 300 Ω, C_L= 35 pF

t_OFF

–40°C to +85°C

–40°C to +125°C

25°C

t_PD

Propagation delay

Charge injection

R_L= 50 Ω , C_L= 5 pF

V_S= 0 V, C_L= 1 nF

100

Q_INJ

25°C

R_L= 50 Ω , C_L= 5 pF

V_S= 0 V, f = 100 kHz

O_ISO

X_TALK

Off-isolation

Crosstalk

25°C

–70

–100

R_L= 50 Ω , C_L= 5 pF

V_S= 0 V, f = 100 kHz

R_L= 50 Ω , C_L= 5 pF

V_S= 0 V

–3dB Bandwidth

MHz

C_S(OFF)

C_D(OFF)

Source off capacitance

Drain off capacitance

V_S= 0 V, f = 1 MHz

25°C

C_S(ON),

C_D(ON)

On capacitance

V_S= 0 V, f = 1 MHz

25°C

145

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7.8 12 V Single Supply: Electrical Characteristics

V_DD= +12 V ± 10%, V_SS= 0 V, GND = 0 V (unless otherwise noted)

Typical at V_DD= +12 V, V_SS= 0 V, T_A= 25℃ (unless otherwise noted)

PARAMETER

TEST CONDITIONS

T_A

MIN

TYP

MAX UNIT

ANALOG SWITCH

25°C

6.2

7.5

V_S= 0 V to 10 V

I_D= –10 mA

R_ON

On-resistance

–40°C to +85°C

–40°C to +125°C

25°C

8.5

0.08

1.2

0.32

0.4

On-resistance mismatch between V_S= 0 V to 10 V

ΔR_ON

–40°C to +85°C

–40°C to +125°C

25°C

channels

I_D= –10 mA

0.45

2.2

V_S= 0 V to 10 V

I_S= –10 mA

R_{ON FLAT}On-resistance flatness

R_{ON DRIFT}On-resistance drift

–40°C to +85°C

–40°C to +125°C

25°C

2.6

2.8

V_S= 6 V, I_S= –10 mA

0.015

0.05

0.5

Ω/°C

V_DD= 13.2 V, V_SS= 0 V

Switch state is off

V_S= 10 V / 1 V

Source off leakage current⁽¹⁾

Drain off leakage current⁽¹⁾

Channel on leakage current⁽²⁾

–40°C to +85°C

–40°C to +125°C

25°C

I_S(OFF)

–35

–60

V_D= 1 V / 10 V

V_DD= 13.2 V, V_SS= 0 V

Switch state is off

V_S= 10 V / 1 V

0.05

–40°C to +85°C

–40°C to +125°C

25°C

I_D(OFF)

V_D= 1 V / 10 V

0.05

V_DD= 13.2 V, V_SS= 0 V

Switch state is on

V_S= V_D= 10 V or 1 V

I_S(ON)

I_D(ON)

–40°C to +85°C

–40°C to +125°C

LOGIC INPUTS (SEL / EN pins)

V_IH

V_IL

I_IH

Logic voltage high

–40°C to +125°C

1.3

0.8

1.2

Logic voltage low

Input leakage current

Logic input capacitance

0.4

µA

I_IL

–0.1 –0.005

C_IN

POWER SUPPLY

25°C

µA

V_DD= 13.2 V, V_SS= 0 V

Logic inputs = 0 V, 5 V, or V_DD

I_DD

V_DDsupply current

–40°C to +85°C

–40°C to +125°C

(1) When V_Sis positive, V_Dis negative, or when V_Sis negative, V_Dis positive.

(2) When V_Sis at a voltage potential, V_Dis floating, or when V_Dis at a voltage potential, V_Sis floating.

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7.9 12 V Single Supply: Switching Characteristics

V_DD= +12 V ± 10%, V_SS= 0 V, GND = 0 V (unless otherwise noted)

Typical at V_DD= +12 V, V_SS= 0 V, T_A= 25℃ (unless otherwise noted)

PARAMETER

TEST CONDITIONS

T_A

MIN

TYP

MAX UNIT

25°C

170

250

290

330

200

250

275

220

250

270

V_S= 8 V

R_L= 300 Ω, C_L= 35 pF

t_TRAN

Transition time from control input

–40°C to +85°C

–40°C to +125°C

25°C

170

200

V_S= 8 V

R_L= 300 Ω, C_L= 35 pF

t_ON

Turn-on time from control input

Turn-off time from control input

–40°C to +85°C

–40°C to +125°C

25°C

V_S= 8 V

R_L= 300 Ω, C_L= 35 pF

t_OFF

–40°C to +85°C

–40°C to +125°C

25°C

t_PD

Propagation delay

Charge injection

R_L= 50 Ω , C_L= 5 pF

V_S= 6 V, C_L= 1 nF

100

Q_INJ

25°C

R_L= 50 Ω , C_L= 5 pF

V_S= 6 V, f = 100 kHz

O_ISO

X_TALK

Off-isolation

Crosstalk

25°C

–70

–95

R_L= 50 Ω , C_L= 5 pF

V_S= 6 V, f = 100 kHz

R_L= 50 Ω , C_L= 5 pF

V_S= 6 V

–3dB Bandwidth

MHz

C_S(OFF)

C_D(OFF)

Source off capacitance

Drain off capacitance

V_S= 6 V, f = 1 MHz

25°C

C_S(ON),

C_D(ON)

On capacitance

V_S= 6 V, f = 1 MHz

25°C

142

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7.10 ±5 V Dual Supply: Electrical Characteristics

V_DD= +5 V ± 10%, V_SS= –5 V ±10%, GND = 0 V (unless otherwise noted)

Typical at V_DD= +5 V, V_SS= –5 V, T_A= 25℃ (unless otherwise noted)

PARAMETER

TEST CONDITIONS

T_A

MIN

TYP

MAX UNIT

ANALOG SWITCH

25°C

7.3

8.8

9.8

0.3

0.35

0.4

2.3

2.8

3.5

V_DD= +4.5 V, V_SS= –4.5 V

V_S= –4.5 V to +4.5 V

I_D= –10 mA

R_ON

On-resistance

–40°C to +85°C

–40°C to +125°C

25°C

0.1

1.8

On-resistance mismatch between V_S= –4.5 V to +4.5 V

ΔR_ON

–40°C to +85°C

–40°C to +125°C

25°C

channels

I_D= –10 mA

V_S= –4.5 V to +4.5 V

I_D= –10 mA

R_{ON FLAT}On-resistance flatness

R_{ON DRIFT}On-resistance drift

–40°C to +85°C

–40°C to +125°C

25°C

V_S= 0 V, I_S= –10 mA

0.02

0.05

0.5

Ω/°C

V_DD= +5.5 V, V_SS= –5.5 V

Switch state is off

V_S= +4.5 V / –4.5 V

V_D= –4.5 V / + 4.5 V

I_S(OFF)

Source off leakage current⁽¹⁾

Drain off leakage current⁽¹⁾

Channel on leakage current⁽²⁾

–40°C to +85°C

–40°C to +125°C

25°C

–35

–60

V_DD= +5.5 V, V_SS= –5.5 V

Switch state is off

V_S= +4.5 V / –4.5 V

V_D= –4.5 V / + 4.5 V

0.05

–40°C to +85°C

–40°C to +125°C

25°C

I_D(OFF)

0.05

V_DD= +5.5 V, V_SS= –5.5 V

Switch state is on

V_S= V_D= ±4.5 V

I_S(ON)

I_D(ON)

–40°C to +85°C

–40°C to +125°C

LOGIC INPUTS (SEL / EN pins)

V_IH

V_IL

I_IH

Logic voltage high

–40°C to +125°C

1.3

0.8

1.2

Logic voltage low

Input leakage current

Logic input capacitance

0.4

µA

I_IL

–0.1 –0.005

C_IN

POWER SUPPLY

25°C

µA

V_DD= +5.5 V, V_SS= –5.5 V

Logic inputs = 0 V, 5 V, or V_DD

I_DD

V_DDsupply current

–40°C to +85°C

–40°C to +125°C

25°C

V_DD= +5.5 V, V_SS= –5.5 V

Logic inputs = 0 V, 5 V, or V_DD

I_SS

V_SSsupply current

–40°C to +85°C

–40°C to +125°C

(1) When V_Sis positive, V_Dis negative, or when V_Sis negative, V_Dis positive.

(2) When V_Sis at a voltage potential, V_Dis floating, or when V_Dis at a voltage potential, V_Sis floating.

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7.11 ±5 V Dual Supply: Switching Characteristics

V_DD= +5 V ± 10%, V_SS= –5 V ±10%, GND = 0 V (unless otherwise noted)

Typical at V_DD= +5 V, V_SS= –5 V, T_A= 25℃ (unless otherwise noted)

PARAMETER

TEST CONDITIONS

T_A

MIN

TYP

MAX UNIT

25°C

270

400

465

510

250

285

315

270

300

315

V_S= 3 V

R_L= 300 Ω, C_L= 35 pF

t_TRAN

Transition time from control input

–40°C to +85°C

–40°C to +125°C

25°C

220

170

V_S= 3 V

R_L= 300 Ω, C_L= 35 pF

t_ON

Turn-on time from control input

Turn-off time from control input

–40°C to +85°C

–40°C to +125°C

25°C

V_S= 3 V

R_L= 300 Ω, C_L= 35 pF

t_OFF

–40°C to +85°C

–40°C to +125°C

25°C

t_PD

Propagation delay

Charge injection

R_L= 50 Ω , C_L= 5 pF

V_S= 0 V, C_L= 1 nF

100

Q_INJ

25°C

R_L= 50 Ω , C_L= 5 pF

V_S= 0 V, f = 100 kHz

O_ISO

X_TALK

Off-isolation

Crosstalk

25°C

–70

–95

R_L= 50 Ω , C_L= 5 pF

V_S= 0 V, f = 100 kHz

R_L= 50 Ω , C_L= 5 pF

V_S= 0 V

–3dB Bandwidth

MHz

C_S(OFF)

C_D(OFF)

Source off capacitance

Drain off capacitance

V_S= 0 V, f = 1 MHz

25°C

C_S(ON),

C_D(ON)

On capacitance

V_S= 0 V, f = 1 MHz

25°C

142

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8 Detailed Description

8.1 Overview

The TMUX6211, TMUX6212, and TMUX6213 are 1:1 (SPST), 4-Channel switches. The devices have four

independently selectable single-pole, single-throw switches that are turned-on or turned-off based on the state of

the corresponding select pin.

8.2 Functional Block Diagram

CHANNEL 1

CHANNEL 2

CHANNEL 3

CHANNEL 4

CHANNEL 1

CHANNEL 2

CHANNEL 3

CHANNEL 4

CHANNEL 1

CHANNEL 2

CHANNEL 3

CHANNEL 4

SEL1

SEL2

SEL3

SEL4

SEL1

SEL2

SEL3

SEL4

SEL1

SEL2

SEL3

SEL4

TMUX1111

TMUX1112

ALL SWITCHES SHOWN FOR A LOGIC 0 INPUT

TMUX1113

Figure 8-1. TMUX621x Functional Block Diagram

8.3 Feature Description

8.3.1 Bidirectional Operation

The TMUX621x conducts equally well from source (Sx) to drain (Dx) or from drain (Dx) to source (Sx). Each

channel has very similar characteristics in both directions and supports both analog and digital signals.

8.3.2 Rail-to-Rail Operation

The valid signal path input and output voltage for TMUX621x ranges from V_SSto V_DD

8.3.3 1.8 V Logic Compatible Inputs

The TMUX621x devices have 1.8-V logic compatible control for all logic control inputs. 1.8-V logic level inputs

allows the TMUX621x to interface with processors that have lower logic I/O rails and eliminates the need for an

external translator, which saves both space and BOM cost. For more information on 1.8 V logic implementations

refer to Simplifying Design with 1.8 V logic Muxes and Switches.

8.3.4 Fail-Safe Logic

The TMUX621x supports Fail-Safe Logic on the control input pins (SEL1, SEL2, SEL3, and SEL4) allowing for

operation up to 36 V, regardless of the state of the supply pin. This feature allows voltages on the control pins to

be applied before the supply pin, protecting the device from potential damage. Fail-Safe Logic minimizes system

complexity by removing the need for power supply sequencing on the logic control pins. For example, the Fail-

Safe Logic feature allows the select pins of the TMUX621x to be ramped to 36 V while V_DDand V_SS= 0 V. The

logic control inputs are protected against positive faults of up to 36 V in powered-off condition, but do not offer

protection against negative overvoltage conditions.

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8.4 Device Functional Modes

The TMUX621x devices have four independently selectable single-pole, single-throw switches that are turned-on

or turned-off based on the state of the corresponding select pin. The control pins can be as high as 36 V.

The TMUX621x devices can be operated without any external components except for the supply decoupling

capacitors. Unused logic control pins should be tied to GND or V_DDin order to ensure the device does not

consume additional current as highlighted in Implications of Slow or Floating CMOS Inputs. Unused signal path

inputs (Sx or Dx) should be connection to GND.

8.5 Truth Tables

Table 8-1, Table 8-2, and Table 8-3 show the truth tables for the TMUX6211, TMUX6212, and TMUX6213,

respectively.

Table 8-1. TMUX6211 Truth Table

SEL x ⁽¹⁾

CHANNEL x

Channel x ON

Channel x OFF

Table 8-2. TMUX6212 Truth Table

SEL x ⁽¹⁾

CHANNEL x

Channel x OFF

Channel x ON

Table 8-3. TMUX6213 Truth Table

SEL x ⁽¹⁾

CHANNEL 1 / CHANNEL 4

CHANNEL 2 / CHANNEL 3

OFF

(1) x denotes 1, 2, 3, or 4 for the corresponding channel.

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9 Application and Implementation

Note

Information in the following applications sections is not part of the TI component specification, and TI

does not warrant its accuracy or completeness. TI’s customers are responsible for determining

suitability of components for their purposes. Customers should validate and test their design

implementation to confirm system functionality.

9.1 Application Information

The TMUX621x is part of the precision switches and multiplexers family of devices. These devices operate with

dual supplies (±4.5 V to ±18 V), a single supply (4.5 V to 36 V), or asymmetric supplies (such as VDD = 12 V,

VSS = –5 V), and offer true rail-to-rail input and output.The TMUX621x offers low RON, low on and off leakage

currents and ultra-low charge injection performance. These features makes the TMUX621x a family of precision,

robust, high-performance analog multiplexer for high-voltage, industrial applications.

9.2 Typical Application

One example to take advantage of TMUX621x precision performance is the implementation of parametric

measurement unit (PMU) in the semiconductor automatic test equipment (ATE) application.

In Automated Test Equipment (ATE) systems, the Parametric Measurement Unit (PMU) is tasked to measure

device (DUT) parametric information in terms of voltage and current. When measuring voltage, current is applied

at the DUT pin, and current range adjustment can be done through changing the value of the internal sense

resistor. There is sometimes a need, depending on the DUT, to use even higher testing current than natively

supported by the system. A 4 channel SPST switch, together with external higher current amplifier and resistor,

can be used to achieve the flexibility. The PMU operating voltage is typically in mid voltage (up tp 20 V). An

appropriate switch like the TMUX621x with low leakage current (0.05 nA typical) works well in these applications

to ensure measurement accuracy and low R_ONand flat R_{ON_FLATNESS}allows the current range to be controlled

more precisely. Figure 9-1 shows simplified diagram of such implementations in memory and semiconductor test

equipment.

High

Current

Amplifier

High

Current

Amplifier

Force

Amplifier

Force

Amplifier

DAC

DUT

Measure

Current

Amplifier

Measure

Current

Amplifier

ADC

Measure

Voltage

Amplifier

Measure

Voltage

Amplifier

External Sense Resistor

Internal Sense Resistor

Figure 9-1. High Current Range Selection Using External Resistor

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9.3 Design Requirements

For this design example, use the parameters listed in Table 9-1.

Table 9-1. Design Parameters

PARAMETERS

Supply (V_DD

Supply (V_SS

VALUES

20 V

)

- 10 V

Input / Output signal range

Control logic thresholds

-10 V to 20 V (Rail-to-Rail)

1.8 V compatible

9.4 Detailed Design Procedure

The application shown in High Current Range Selection Using External Resistor figure demonstrates how the

TMUX621x can be used in semicoonductor test equipment for high-precision, high-voltage, multi-channel

measurement applications. The TMUX621x can support 1.8-V logic signals on the control input, allowing the

device to interface with low logic controls of an FPGA or MCU. The TMUX621x can be operated without any

external components except for the supply decoupling capacitors. The select pins have an internal pull-down

resistor to prevent floating input logic. All inputs to the switch must fall within the recommend operating

conditions of the TMUX621x including signal range and continuous current. For this design with a positive supply

of 20 V on V_DD, and negative supply of -10 V on V_SS, the signal range can be 20 V to -10 V. The max continuous

current (I_DC) can be up to 370 mA as shown in the Recommended Operating Conditions table for wide-range

current measurement.

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10 Power Supply Recommendations

The TMUX621x operates across a wide supply range of of ±4.5 V to ±18 V (4.5 V to 36 V in single-supply

mode). The device also perform well with asymmetrical supplies such as V_DD= 12 V and V_SS= –5 V.

Power-supply bypassing improves noise margin and prevents switching noise propagation from the supply rails

to other components. Good power-supply decoupling is important to achieve optimum performance. For

improved supply noise immunity, use a supply decoupling capacitor ranging from 0.1 μF to 10 μF at both the V_DD

and V_SSpins to ground. Place the bypass capacitors as close to the power supply pins of the device as possible

using low-impedance connections. TI recommends using multi-layer ceramic chip capacitors (MLCCs) that offer

low equivalent series resistance (ESR) and inductance (ESL) characteristics for power-supply decoupling

purposes. For very sensitive systems, or for systems in harsh noise environments, avoiding the use of vias for

connecting the capacitors to the device pins may offer superior noise immunity. The use of multiple vias in

parallel lowers the overall inductance and is beneficial for connections to ground planes. Always ensure the

ground (GND) connection is established before supplies are ramped.

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11 Layout

11.1 Layout Guidelines

When a PCB trace turns a corner at a 90° angle, a reflection can occur. A reflection occurs primarily because of

the change of width of the trace. At the apex of the turn, the trace width increases to 1.414 times the width. This

increase upsets the transmission-line characteristics, especially the distributed capacitance and self–inductance

of the trace which results in the reflection. Not all PCB traces can be straight and therefore some traces must

turn corners. Figure 11-1 shows progressively better techniques of rounding corners. Only the last example

(BEST) maintains constant trace width and minimizes reflections.

WORST

BETTER

BEST

1W min.

Figure 11-1. Trace Example

Route high-speed signals using a minimum of vias and corners which reduces signal reflections and impedance

changes. When a via must be used, increase the clearance size around it to minimize its capacitance. Each via

introduces discontinuities in the signal’s transmission line and increases the chance of picking up interference

from the other layers of the board. Be careful when designing test points, through-hole pins are not

recommended at high frequencies.

Figure 11-2 illustrates an example of a PCB layout with the TMUX621x.

Some key considerations are:

•

Decouple the supply pins with a 0.1-µF and 1 µF capacitor, placed lowest value capacitor as close to the pin

as possible. Make sure that the capacitor voltage rating is sufficient for the supply voltage.

Keep the input lines as short as possible.

Use a solid ground plane to help reduce electromagnetic interference (EMI) noise pickup.

Do not run sensitive analog traces in parallel with digital traces. Avoid crossing digital and analog traces if

possible, and only make perpendicular crossings when necessary.

•

Using multiple vias in parallel will lower the overall inductance and is beneficial for connection to ground

planes.

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11.2 Layout Example

SEL1

SEL2

Wide (low inductance)

trace for power

Wide (low inductance)

trace for power

VDD

VSS

GND

TMUX621x

N.C.

SEL3

SEL4

Via to ground plane

Figure 11-2. TMUX621x Layout Example

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12 Device and Documentation Support

12.1 Documentation Support

12.1.1 Related Documentation

Texas Instruments, Sample & Hold Glitch Reduction for Precision Outputs Reference Design.

Texas Instruments, True Differential, 4 x 2 MUX, Analog Front End, Simultaneous-Sampling ADC Circuit.

Texas Instruments, Improve Stability Issues with Low CON Multiplexers.

Texas Instruments, Simplifying Design with 1.8 V logic Muxes and Switches.

Texas Instruments, Eliminate Power Sequencing with Powered-off Protection Signal Switches.

Texas Instruments, System-Level Protection for High-Voltage Analog Multiplexers.

Texas Instruments, QFN/SON PCB Attachment.

Texas Instruments, Quad Flatpack No-Lead Logic Packages.

12.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on

Subscribe to updates to register and receive a weekly digest of any product information that has changed. For

change details, review the revision history included in any revised document.

12.3 Support Resources

TI E2E^™support forums are an engineer's go-to source for fast, verified answers and design help — straight

from the experts. Search existing answers or ask your own question to get the quick design help you need.

Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do

not necessarily reflect TI's views; see TI's Terms of Use.

12.4 Trademarks

TI E2E^™is a trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

12.5 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled

with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric changes could cause the device not to meet its published

specifications.

12.6 Glossary

TI Glossary

This glossary lists and explains terms, acronyms, and definitions.

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13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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PACKAGE OPTION ADDENDUM

www.ti.com

6-Nov-2020

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

PTMUX6212PWR

ACTIVE

TSSOP

2000

TBD

Call TI

-40 to 125

TMUX6211PWR

TMUX6211RUMR

TMUX6212PWR

TMUX6212RUMR

TMUX6213PWR

TMUX6213RUMR

PREVIEW

TSSOP

WQFN

TSSOP

WQFN

TSSOP

WQFN

RUM

2000

3000

2000

3000

2000

3000

TBD

Call TI

-40 to 125

RUM

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

6-Nov-2020

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2

PACKAGE OUTLINE

PW0016A

TSSOP - 1.2 mm max height

SMALL OUTLINE PACKAGE

SEATING

PLANE

6.6

6.2

TYP

0.1 C

PIN 1 INDEX AREA

14X 0.65

5.1

4.9

4.55

NOTE 3

0.30

16X

4.5

4.3

NOTE 4

1.2 MAX

0.19

0.1

C A B

(0.15) TYP

SEE DETAIL A

0.25

GAGE PLANE

0.15

0.05

0.75

0.50

0 -8

DETAIL A

TYPICAL

4220204/A 02/2017

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed 0.15 mm per side.

4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.

5. Reference JEDEC registration MO-153.

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EXAMPLE BOARD LAYOUT

PW0016A

TSSOP - 1.2 mm max height

SMALL OUTLINE PACKAGE

SYMM

16X (1.5)

(R0.05) TYP

16X (0.45)

SYMM

14X (0.65)

(5.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE: 10X

METAL UNDER

SOLDER MASK

OPENING

SOLDER MASK

OPENING

METAL

EXPOSED METAL

0.05 MAX

ALL AROUND

0.05 MIN

ALL AROUND

NON-SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

15.000

(PREFERRED)

SOLDER MASK DETAILS

4220204/A 02/2017

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

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EXAMPLE STENCIL DESIGN

PW0016A

TSSOP - 1.2 mm max height

SMALL OUTLINE PACKAGE

16X (1.5)

SYMM

(R0.05) TYP

16X (0.45)

SYMM

14X (0.65)

(5.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

SCALE: 10X

4220204/A 02/2017

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

9. Board assembly site may have different recommendations for stencil design.

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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD

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These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate

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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

TMUX6212RUMR [TI]

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