TMUX6219-Q1 [TI]
具有 1.8V 逻辑的汽车类 36V、低 Ron、2:1 (SPDT) 开关;型号: | TMUX6219-Q1 |
厂家: | TEXAS INSTRUMENTS |
描述: | 具有 1.8V 逻辑的汽车类 36V、低 Ron、2:1 (SPDT) 开关 开关 光电二极管 |
文件: | 总42页 (文件大小:2627K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
TMUX6219-Q1
ZHCSMY9A –JANUARY 2021 –REVISED JUNE 2021
具有1.8V 逻辑电平的TMUX6219-Q136V、低Ron、2:1 (SPDT) 开关
1 特性
3 说明
• 符合面向汽车应用的AEC-Q100 标准
TMUX6219-Q1 是一款互补金属氧化物半导体(CMOS)
开关,采用单通道 2:1 (SPDT) 配置。此器件在单电源
(4.5V 至36V)、双电源(±4.5V 至±18V)或非对称
电源(例如 VDD = 8V,VSS = -12V)供电时均能正常
运行。TMUX6219-Q1 可在源极 (Sx) 和漏极 (D) 引脚
上支持从VSS 到VDD 范围的双向模拟和数字信号。
– 器件温度等级1:–40°C 至125°C 的工作环境
温度范围
• 提供功能安全
– 可帮助进行功能安全系统设计的文档
• 双电源电压范围:±4.5V 至±18V
• 单电源电压范围:4.5V 至36V
• 低导通电阻:2.1Ω
可以通过控制 EN 引脚来启用或禁用 TMUX6219-Q1。
当禁用时,两个信号路径开关都断开。当启用时,SEL
引脚可用于导通信号路径 1(S1 至 D)或信号路径 2
(S2 至 D)。所有逻辑控制输入均支持 1.8V 到 VDD
的逻辑电平,因此,当器件在有效电源电压范围内运行
时,可确保 TTL 和CMOS 逻辑兼容性。失效防护逻辑
电路允许先在控制引脚上施加电压,然后在电源引脚上
施加电压,从而保护器件免受潜在的损害。
• 低电荷注入:-10pC
• 高电流支持:330mA(最大值)
• 兼容1.8V 逻辑电平
• 失效防护逻辑
• 轨至轨运行
• 双向信号路径
• 先断后合开关
TMUX6219-Q1 是精密开关和多路复用器系列器件。这
些器件具有非常低的导通和关断泄漏电流以及较低的电
荷注入,因此可用于高精度测量应用。
2 应用
• 电动汽车充电站电源模块
• 高级驾驶辅助系统(ADAS)
• 汽车网关
器件信息(1)
封装尺寸(标称值)
器件型号
封装
• 模拟和数字多路复用/多路信号分离
• 汽车音响主机
TMUX6219-Q1
VSSOP (8) (DGK)
3.00mm × 3.00mm
• 远程信息处理控制单元
• 紧急呼叫(eCall)
• 信息娱乐系统
(1) 如需了解所有可用封装,请参阅数据表末尾的可订购产品附
录。
• 车身控制模块(BCM)
• 车身电子装置和照明
• 电池管理系统(BMS)
• HVAC 控制器模块
• ADAS 域控制器
VSS
VDD
S1
S2
D
Decoder
EN SEL
TMUX6219-Q1 方框图
本文档旨在为方便起见,提供有关TI 产品中文版本的信息,以确认产品的概要。有关适用的官方英文版本的最新信息,请访问
www.ti.com,其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前,请务必参考最新版本的英文版本。
English Data Sheet: SCDS437
TMUX6219-Q1
ZHCSMY9A –JANUARY 2021 –REVISED JUNE 2021
www.ti.com.cn
Table of Contents
7.9 Charge Injection........................................................27
7.10 Off Isolation.............................................................27
7.11 Crosstalk................................................................. 28
7.12 Bandwidth............................................................... 28
7.13 THD + Noise........................................................... 29
7.14 Power Supply Rejection Ratio (PSRR)...................29
8 Detailed Description......................................................30
8.1 Overview...................................................................30
8.2 Functional Block Diagram.........................................30
8.3 Feature Description...................................................30
8.4 Device Functional Modes..........................................32
8.5 Truth Tables.............................................................. 32
9 Application and Implementation..................................33
9.1 Application Information............................................. 33
9.2 Typical Application.................................................... 33
10 Power Supply Recommendations..............................34
11 Layout...........................................................................35
11.1 Layout Guidelines................................................... 35
11.2 Layout Example...................................................... 35
12 Device and Documentation Support..........................36
12.1 Documentation Support.......................................... 36
12.2 Receiving Notification of Documentation Updates..36
12.3 支持资源..................................................................36
12.4 Trademarks.............................................................36
12.5 Electrostatic Discharge Caution..............................36
12.6 Glossary..................................................................36
13 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings ....................................... 4
6.2 ESD Ratings .............................................................. 4
6.3 Thermal Information ...................................................4
6.4 Recommended Operating Conditions ........................5
6.5 Source or Drain Continuous Current ..........................5
6.6 ±15 V Dual Supply: Electrical Characteristics ...........6
6.7 ±15 V Dual Supply: Switching Characteristics ..........7
6.8 36 V Single Supply: Electrical Characteristics .......... 9
6.9 36 V Single Supply: Switching Characteristics ....... 10
6.10 12 V Single Supply: Electrical Characteristics ...... 12
6.11 12 V Single Supply: Switching Characteristics ......13
6.12 ±5 V Dual Supply: Electrical Characteristics .........15
6.13 ±5 V Dual Supply: Switching Characteristics ........16
6.14 Typical Characteristics............................................18
7 Parameter Measurement Information..........................23
7.1 On-Resistance.......................................................... 23
7.2 Off-Leakage Current................................................. 23
7.3 On-Leakage Current................................................. 24
7.4 Transition Time......................................................... 24
7.5 tON(EN) and tOFF(EN) .................................................. 25
7.6 Break-Before-Make...................................................25
7.7 tON (VDD) Time............................................................26
7.8 Propagation Delay.................................................... 26
Information.................................................................... 36
4 Revision History
注:以前版本的页码可能与当前版本的页码不同
Changes from Revision * (January 2021) to Revision A (June 2021)
Page
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5 Pin Configuration and Functions
D
S1
1
2
3
4
8
7
6
5
S2
VSS
SEL
EN
GND
VDD
Not to scale
图5-1. DGK Package
8-Pin VSSOP
Top View
Pin Functions
PIN
TYPE(1)
DESCRIPTION(2)
NAME
DGK
D
1
I/O
I
Drain pin. Can be an input or output.
Active high logic enable, has internal pull-up resistor. When this pin is low, all switches are turned off.
When this pin is high, the SEL logic input determine which switch is turned on.
EN
5
GND
S1
3
2
8
6
P
I/O
I/O
I
Ground (0 V) reference
Source pin 1. Can be an input or output.
S2
Source pin 2. Can be an input or output.
SEL
Logic control input, has internal pull-down resistor. Controls the switch connection as shown in 表8-1.
Positive power supply. This pin is the most positive power-supply potential. For reliable operation,
connect a decoupling capacitor ranging from 0.1 µF to 10 µF between VDD and GND.
VDD
4
7
P
P
Negative power supply. This pin is the most negative power-supply potential. In single-supply
applications, this pin can be connected to ground. For reliable operation, connect a decoupling
capacitor ranging from 0.1 µF to 10 µF between VSS and GND.
VSS
(1) I = input, O = output, I/O = input and output, P = power.
(2) Refer to 节8.4 for what to do with unused pins.
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1) (2)
MIN
MAX
UNIT
V
Power supply voltage differential
Supply voltage
38
VDD–VSS
VDD
38
V
–0.5
–38
VSS
Supply voltage
0.5
V
VSEL or VEN
ISEL or IEN
VS or VD
IIK
Logic control input pin voltage (SEL, EN)(3)
Logic control input pin current (SEL, EN)(3)
Source or drain voltage (Sx, D)(3)
Diode clamp current(3)
38
V
–0.5
30
VDD+0.5
30
mA
V
–30
VSS–0.5
–30
mA
mA
°C
°C
°C
mW
IS or ID (CONT)
TA
Source or drain continuous current (Sx, D)
Ambient temperature
IDC + 10 %(4)
150
–55
–65
Tstg
Storage temperature
150
TJ
Junction temperature
150
Ptot
Total power dissipation(5)
460
(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) All voltages are with respect to ground, unless otherwise specified.
(3) Pins are diode-clamped to the power-supply rails. Over voltage signals must be voltage and current limited to maximum ratings.
(4) Refer to Source or Drain Continuous Current table for IDC specifications.
(5) For DGK package: Ptot derates linearily above TA = 70°C by 6.7mW/°C.
6.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per ANSI/ESDA/
JEDEC JS-001, all pins(1)
±2000
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per JEDEC
specification JESD22-C101, all pins(2)
±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Thermal Information
TMUX6219-Q1
THERMAL METRIC(1)
DGK (VSSOP)
8 PINS
152.1
48.4
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
73.2
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
4.1
ΨJT
71.8
ΨJB
RθJC(bot)
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.4 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
4.5
4.5
VSS
0
NOM
MAX
36
UNIT
V
(1)
VDD - VSS
VDD
Power supply voltage differential
Positive power supply voltage
36
V
VS or VD
VSEL or VEN
Signal path input/output voltage (source or drain pin) (Sx, D)
Address or enable pin voltage
VDD
36
V
V
(2)
IS or ID (CONT) Source or drain continuous current (Sx, D)
TA Ambient temperature
IDC
mA
°C
125
–40
(1) VDD and VSS can be any value as long as 4.5 V ≤(VDD –VSS) ≤36 V, and the minimum VDD is met.
(2) Refer to Source or Drain Continuous Current table for IDC specifications.
6.5 Source or Drain Continuous Current
at supply voltage of VDD ± 10%, VSS ± 10 % (unless otherwise noted)
CONTINUOUS CURRENT PER CHANNEL (IDC
PACKAGE TEST CONDITIONS
±15 V Dual Supply
)
TA = 25°C
TA = 85°C
210
TA = 125°C
UNIT
330
120
mA
mA
mA
mA
mA
+36 V Single Supply(1)
+12 V Single Supply
±5 V Dual Supply
300
240
240
180
190
160
160
120
110
100
100
80
DGK (VSSOP)
+5 V Single Supply
(1) Specified for nominal supply voltage only.
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MAX UNIT
6.6 ±15 V Dual Supply: Electrical Characteristics
VDD = +15 V ± 10%, VSS = –15 V ±10%, GND = 0 V (unless otherwise noted)
Typical at VDD = +15 V, VSS = –15 V, TA = 25℃ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
ANALOG SWITCH
25°C
2.1
2.9
3.8
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
VS = –10 V to +10 V
ID = –10 mA
Refer to On-Resistance
RON
On-resistance
–40°C to +85°C
–40°C to +125°C
25°C
4.5
0.05
0.5
0.25
0.3
VS = –10 V to +10 V
ID = –10 mA
Refer to On-Resistance
On-resistance mismatch between
channels
–40°C to +85°C
–40°C to +125°C
25°C
ΔRON
0.35
0.6
VS = –10 V to +10 V
IS = –10 mA
Refer to On-Resistance
0.7
RON FLAT On-resistance flatness
RON DRIFT On-resistance drift
–40°C to +85°C
–40°C to +125°C
0.85
VS = 0 V, IS = –10 mA
Refer to On-Resistance
0.01
0.1
–40°C to +125°C
Ω/°C
25°C
0.3
3
nA
nA
VDD = 16.5 V, VSS = –16.5 V
Switch state is off
VS = +10 V / –10 V
–0.3
–3
–40°C to +85°C
IS(OFF)
Source off leakage current(1)
VD = –10 V / + 10 V
Refer to Off-Leakage Current
50
nA
–40°C to +125°C
–50
25°C
0.1
0.1
2
5
nA
nA
VDD = 16.5 V, VSS = –16.5 V
Switch state is off
VS = +10 V / –10 V
VD = –10 V / + 10 V
Refer to Off-Leakage Current
–2
–5
–40°C to +85°C
ID(OFF)
Drain off leakage current(1)
70
nA
–40°C to +125°C
–70
25°C
2
5
nA
nA
nA
–2
–5
VDD = 16.5 V, VSS = –16.5 V
Switch state is on
VS = VD = ±10 V
IS(ON)
ID(ON)
Channel on leakage current(2)
–40°C to +85°C
–40°C to +125°C
Refer to On-Leakage Current
70
–70
LOGIC INPUTS (SEL / EN pins)
VIH
VIL
IIH
Logic voltage high
1.3
0
36
0.8
1
V
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
Logic voltage low
V
Input leakage current
Input leakage current
Logic input capacitance
0.005
µA
µA
pF
IIL
–1 –0.005
CIN
3
POWER SUPPLY
25°C
30
3
40
48
62
10
15
25
µA
µA
µA
µA
µA
µA
VDD = 16.5 V, VSS = –16.5 V
Logic inputs = 0 V, 5 V, or VDD
IDD
VDD supply current
–40°C to +85°C
–40°C to +125°C
25°C
VDD = 16.5 V, VSS = –16.5 V
Logic inputs = 0 V, 5 V, or VDD
ISS
VSS supply current
–40°C to +85°C
–40°C to +125°C
(1) When VS is positive, VD is negative, or when VS is negative, VD is positive.
(2) When VS is at a voltage potential, VD is floating, or when VD is at a voltage potential, VS is floating.
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6.7 ±15 V Dual Supply: Switching Characteristics
VDD = +15 V ± 10%, VSS = –15 V ±10%, GND = 0 V (unless otherwise noted)
Typical at VDD = +15 V, VSS = –15 V, TA = 25℃ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX UNIT
25°C
120
175
190
210
170
185
200
180
195
210
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ms
ms
VS = 10 V
RL = 300 Ω, CL = 35 pF
Refer to Transition Time
tTRAN
Transition time from control input
–40°C to +85°C
–40°C to +125°C
25°C
VS = 10 V
100
100
50
RL = 300 Ω, CL = 35 pF
Refer to Turn-on and Turn-off
Time
tON
Turn-on time from enable
Turn-off time from enable
Break-before-make time delay
–40°C to +85°C
–40°C to +125°C
25°C
(EN)
VS = 10 V
RL = 300 Ω, CL = 35 pF
Refer to Turn-on and Turn-off
Time
tOFF
–40°C to +85°C
–40°C to +125°C
25°C
(EN)
VS = 10 V,
RL = 300 Ω, CL = 35 pF
Refer to Break-Before-Make
1
1
tBBM
–40°C to +85°C
–40°C to +125°C
25°C
0.19
0.2
VDD rise time = 100ns
RL = 300 Ω, CL = 35 pF
Refer to Turn-on (VDD) Time
Device turn on time
(VDD to output)
TON (VDD)
–40°C to +85°C
–40°C to +125°C
0.2
RL = 50 Ω, CL = 5 pF
Refer to Propagation Delay
tPD
Propagation delay
Charge injection
25°C
25°C
700
ps
VD = 0 V, CL = 1 nF
Refer to Charge Injection
QINJ
pC
–10
RL = 50 Ω, CL = 5 pF
VS = 0 V, f = 100 kHz
Refer to Off Isolation
OISO
Off-isolation
Off-isolation
Crosstalk
25°C
25°C
25°C
25°C
dB
dB
dB
dB
–75
–55
RL = 50 Ω, CL = 5 pF
VS = 0 V, f = 1 MHz
Refer to Off Isolation
OISO
RL = 50 Ω, CL = 5 pF
VS = 0 V, f = 100 kHz
Refer to Crosstalk
XTALK
–117
–106
RL = 50 Ω, CL = 5 pF
VS = 0 V, f = 1MHz
Refer to Crosstalk
XTALK
Crosstalk
RL = 50 Ω, CL = 5 pF
VS = 0 V
Refer to Bandwidth
BW
IL
25°C
25°C
40
MHz
dB
–3dB Bandwidth
RL = 50 Ω, CL = 5 pF
VS = 0 V, f = 1 MHz
Insertion loss
–0.18
VPP = 0.62 V on VDD and VSS
RL = 50 Ω, CL = 5 pF,
f = 1 MHz
ACPSRR AC Power Supply Rejection Ratio
25°C
25°C
dB
%
–64
Refer to ACPSRR
VPP = 15 V, VBIAS = 0 V
RL = 10 kΩ, CL = 5 pF,
f = 20 Hz to 20 kHz
THD+N
Total Harmonic Distortion + Noise
0.0005
Refer to THD + Noise
CS(OFF)
CD(OFF)
Source off capacitance
Drain off capacitance
VS = 0 V, f = 1 MHz
VS = 0 V, f = 1 MHz
25°C
25°C
33
48
pF
pF
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VDD = +15 V ± 10%, VSS = –15 V ±10%, GND = 0 V (unless otherwise noted)
Typical at VDD = +15 V, VSS = –15 V, TA = 25℃ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX UNIT
CS(ON)
CD(ON)
,
On capacitance
VS = 0 V, f = 1 MHz
25°C
148
pF
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6.8 36 V Single Supply: Electrical Characteristics
VDD = +36 V ± 10%, VSS = 0 V, GND = 0 V (unless otherwise noted)
Typical at VDD = +36 V, VSS = 0 V, TA = 25℃ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX UNIT
ANALOG SWITCH
25°C
2.5
3.2
4.2
4.9
0.2
0.25
0.3
1
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
VS = 0 V to 30 V
ID = –10 mA
Refer to On-Resistance
RON
On-resistance
–40°C to +85°C
–40°C to +125°C
25°C
0.1
0.3
VS = 0 V to 30 V
ID = –10 mA
Refer to On-Resistance
On-resistance mismatch between
channels
–40°C to +85°C
–40°C to +125°C
25°C
ΔRON
VS = 0 V to 30 V
IS = –10 mA
Refer to On-Resistance
1.5
2
RON FLAT On-resistance flatness
RON DRIFT On-resistance drift
–40°C to +85°C
–40°C to +125°C
VS = 18 V, IS = –10 mA
Refer to On-Resistance
0.009
0.1
–40°C to +125°C
Ω/°C
VDD = 39.6 V, VSS = 0 V
Switch state is off
VS = 30 V / 1 V
25°C
0.5
5
nA
nA
–0.5
–5
–40°C to +85°C
IS(OFF)
Source off leakage current(1)
VD = 1 V / 30 V
Refer to Off-Leakage Current
70
nA
–40°C to +125°C
–70
VDD = 39.6 V, VSS = 0 V
Switch state is off
VS = 30 V / 1 V
VD = 1 V / 30 V
Refer to Off-Leakage Current
25°C
0.1
0.1
2
nA
nA
–2
10
–40°C to +85°C
–10
ID(OFF)
Drain off leakage current(1)
80
nA
–40°C to +125°C
–80
25°C
2
10
80
nA
nA
nA
VDD = 39.6 V, VSS = 0 V
Switch state is on
VS = VD = 30 V or 1 V
Refer to On-Leakage Current
–2
–10
–80
IS(ON)
ID(ON)
Channel on leakage current(2)
–40°C to +85°C
–40°C to +125°C
LOGIC INPUTS (SEL / EN pins)
VIH
VIL
IIH
Logic voltage high
1.3
0
36
0.8
1
V
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
Logic voltage low
V
Input leakage current
Input leakage current
Logic input capacitance
0.005
µA
µA
pF
IIL
–1 –0.005
CIN
3
POWER SUPPLY
25°C
28
50
58
70
µA
µA
µA
VDD = 39.6 V, VSS = 0 V
Logic inputs = 0 V, 5 V, or VDD
IDD
VDD supply current
–40°C to +85°C
–40°C to +125°C
(1) When VS is positive, VD is negative, or when VS is negative, VD is positive.
(2) When VS is at a voltage potential, VD is floating, or when VD is at a voltage potential, VS is floating.
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6.9 36 V Single Supply: Switching Characteristics
VDD = +36 V ± 10%, VSS = 0 V, GND = 0 V (unless otherwise noted)
Typical at VDD = +36 V, VSS = 0 V, TA = 25℃ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
25°C
110
170
185
200
180
190
200
180
195
200
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ms
ms
VS = 18 V
RL = 300 Ω, CL = 35 pF
Refer to Transition Time
tTRAN
Transition time from control input
–40°C to +85°C
–40°C to +125°C
25°C
VS = 18 V
110
90
RL = 300 Ω, CL = 35 pF
Refer to Turn-on and Turn-off
Time
tON
Turn-on time from enable
Turn-off time from enable
Break-before-make time delay
–40°C to +85°C
–40°C to +125°C
25°C
(EN)
VS = 18 V
RL = 300 Ω, CL = 35 pF
Refer to Turn-on and Turn-off
Time
tOFF
–40°C to +85°C
–40°C to +125°C
25°C
(EN)
44
VS = 18 V,
RL = 300 Ω, CL = 35 pF
Refer to Break-Before-Make
1
1
tBBM
–40°C to +85°C
–40°C to +125°C
25°C
0.17
0.19
0.19
VDD rise time = 100ns
RL = 300 Ω, CL = 35 pF
Refer to Turn-on (VDD) Time
Device turn on time
(VDD to output)
TON (VDD)
–40°C to +85°C
–40°C to +125°C
RL = 50 Ω, CL = 5 pF
Refer to Propagation Delay
tPD
Propagation delay
Charge injection
25°C
25°C
920
ps
VD = 18 V, CL = 1 nF
Refer to Charge Injection
QINJ
pC
–13
RL = 50 Ω, CL = 5 pF
VS = 6 V, f = 100 kHz
Refer to Off Isolation
OISO
Off-isolation
Off-isolation
Crosstalk
25°C
25°C
25°C
25°C
dB
dB
dB
dB
–75
–55
RL = 50 Ω, CL = 5 pF
VS = 6 V, f = 1 MHz
Refer to Off Isolation
OISO
RL = 50 Ω, CL = 5 pF
VS = 6 V, f = 100 kHz
Refer to Crosstalk
XTALK
–117
–106
RL = 50 Ω, CL = 5 pF
VS = 6 V, f = 1MHz
Refer to Crosstalk
XTALK
Crosstalk
RL = 50 Ω, CL = 5 pF
VS = 6 V,
Refer to Bandwidth
BW
IL
25°C
25°C
38
MHz
dB
–3dB Bandwidth
RL = 50 Ω, CL = 5 pF
VS = 6 V, f = 1 MHz
Insertion loss
–0.19
VPP = 0.62 V on VDD and VSS
RL = 50 Ω, CL = 5 pF,
f = 1 MHz
ACPSRR AC Power Supply Rejection Ratio
25°C
25°C
dB
%
–60
Refer to ACPSRR
VPP =18 V, VBIAS = 18 V
RL = 10 kΩ, CL = 5 pF,
f = 20 Hz to 20 kHz
THD+N
Total Harmonic Distortion + Noise
0.0004
Refer to THD + Noise
CS(OFF)
CD(OFF)
Source off capacitance
Drain off capacitance
VS = 6 V, f = 1 MHz
VS = 6 V, f = 1 MHz
25°C
25°C
35
49
pF
pF
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VDD = +36 V ± 10%, VSS = 0 V, GND = 0 V (unless otherwise noted)
Typical at VDD = +36 V, VSS = 0 V, TA = 25℃ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX UNIT
CS(ON),
CD(ON)
On capacitance
VS = 6 V, f = 1 MHz
25°C
146
pF
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MAX UNIT
6.10 12 V Single Supply: Electrical Characteristics
VDD = +12 V ± 10%, VSS = 0 V, GND = 0 V (unless otherwise noted)
Typical at VDD = +12 V, VSS = 0 V, TA = 25℃ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
ANALOG SWITCH
25°C
4.6
6
7.5
8.4
0.2
0.32
0.35
2
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
VS = 0 V to 10 V
ID = –10 mA
Refer to On-Resistance
RON
On-resistance
–40°C to +85°C
–40°C to +125°C
25°C
0.08
1.2
VS = 0 V to 10 V
ID = –10 mA
Refer to On-Resistance
On-resistance mismatch between
channels
–40°C to +85°C
–40°C to +125°C
25°C
ΔRON
VS = 0 V to 10 V
IS = –10 mA
Refer to On-Resistance
2.2
2.4
RON FLAT On-resistance flatness
RON DRIFT On-resistance drift
–40°C to +85°C
–40°C to +125°C
VS = 6 V, IS = –10 mA
Refer to On-Resistance
0.017
0.1
–40°C to +125°C
Ω/°C
VDD = 13.2 V, VSS = 0 V
Switch state is off
VS = 10 V / 1 V
25°C
1
5
nA
nA
–1
–5
–40°C to +85°C
IS(OFF)
Source off leakage current(1)
VD = 1 V / 10 V
Refer to Off-Leakage Current
50
nA
–40°C to +125°C
–50
VDD = 13.2 V, VSS = 0 V
Switch state is off
VS = 10 V / 1 V
VD = 1 V / 10 V
Refer to Off-Leakage Current
25°C
0.1
0.1
2
5
nA
nA
–2
–5
–40°C to +85°C
ID(OFF)
Drain off leakage current(1)
70
nA
–40°C to +125°C
–70
25°C
2
5
nA
nA
nA
VDD = 13.2 V, VSS = 0 V
Switch state is on
VS = VD = 10 V or 1 V
Refer to On-Leakage Current
–2
–5
IS(ON)
ID(ON)
Channel on leakage current(2)
–40°C to +85°C
–40°C to +125°C
70
–70
LOGIC INPUTS (SEL / EN pins)
VIH
VIL
IIH
Logic voltage high
1.3
0
36
0.8
1
V
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
Logic voltage low
V
Input leakage current
Input leakage current
Logic input capacitance
0.005
µA
µA
pF
IIL
–1 –0.005
CIN
3
POWER SUPPLY
25°C
10
35
45
55
µA
µA
µA
VDD = 13.2 V, VSS = 0 V
Logic inputs = 0 V, 5 V, or VDD
IDD
VDD supply current
–40°C to +85°C
–40°C to +125°C
(1) When VS is positive, VD is negative, or when VS is negative, VD is positive.
(2) When VS is at a voltage potential, VD is floating, or when VD is at a voltage potential, VS is floating.
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6.11 12 V Single Supply: Switching Characteristics
VDD = +12 V ± 10%, VSS = 0 V, GND = 0 V (unless otherwise noted)
Typical at VDD = +12 V, VSS = 0 V, TA = 25℃ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX UNIT
25°C
180
185
215
235
180
210
230
210
235
250
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ms
ms
VS = 8 V
RL = 300 Ω, CL = 35 pF
Refer to Transition Time
tTRAN
Transition time from control input
–40°C to +85°C
–40°C to +125°C
25°C
VS = 8 V
120
130
40
RL = 300 Ω, CL = 35 pF
Refer to Turn-on and Turn-off
Time
tON
Turn-on time from enable
Turn-off time from enable
Break-before-make time delay
–40°C to +85°C
–40°C to +125°C
25°C
(EN)
VS = 8 V
RL = 300 Ω, CL = 35 pF
Refer to Turn-on and Turn-off
Time
tOFF
–40°C to +85°C
–40°C to +125°C
25°C
(EN)
VS = 8 V,
RL = 300 Ω, CL = 35 pF
Refer to Break-Before-Make
1
1
tBBM
–40°C to +85°C
–40°C to +125°C
25°C
0.19
0.2
VDD rise time = 100ns
RL = 300 Ω, CL = 35 pF
Refer to Turn-on (VDD) Time
Device turn on time
(VDD to output)
TON (VDD)
–40°C to +85°C
–40°C to +125°C
0.2
RL = 50 Ω, CL = 5 pF
Refer to Propagation Delay
tPD
Propagation delay
Charge injection
25°C
25°C
740
ps
VD = 6 V, CL = 1 nF
Refer to Charge Injection
QINJ
pC
–6
RL = 50 Ω, CL = 5 pF
VS = 6 V, f = 100 kHz
Refer to Charge Injection
OISO
Off-isolation
Off-isolation
Crosstalk
25°C
25°C
25°C
25°C
dB
dB
dB
dB
–75
–55
RL = 50 Ω, CL = 5 pF
VS = 6 V, f = 1 MHz
Refer to Off Isolation
OISO
RL = 50 Ω, CL = 5 pF
VS = 6 V, f = 100 kHz
Refer to Crosstalk
XTALK
–117
–106
RL = 50 Ω, CL = 5 pF
VS = 6 V, f = 1MHz
Refer to Crosstalk
XTALK
Crosstalk
RL = 50 Ω, CL = 5 pF
VS = 6 V
Refer to Bandwidth
BW
IL
25°C
25°C
42
MHz
dB
–3dB Bandwidth
RL = 50 Ω, CL = 5 pF
VS = 6 V, f = 1 MHz
Insertion loss
–0.3
VPP = 0.62 V on VDD and VSS
RL = 50 Ω, CL = 5 pF,
f = 1 MHz
ACPSRR AC Power Supply Rejection Ratio
25°C
25°C
dB
%
–65
Refer to ACPSRR
VPP = 6 V, VBIAS = 6 V
RL = 10 kΩ, CL = 5 pF,
f = 20 Hz to 20 kHz
THD+N
Total Harmonic Distortion + Noise
0.0009
Refer to THD + Noise
CS(OFF)
CD(OFF)
Source off capacitance
Drain off capacitance
VS = 6 V, f = 1 MHz
VS = 6 V, f = 1 MHz
25°C
25°C
38
56
pF
pF
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VDD = +12 V ± 10%, VSS = 0 V, GND = 0 V (unless otherwise noted)
Typical at VDD = +12 V, VSS = 0 V, TA = 25℃ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX UNIT
CS(ON)
CD(ON)
,
On capacitance
VS = 6 V, f = 1 MHz
25°C
150
pF
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6.12 ±5 V Dual Supply: Electrical Characteristics
VDD = +5 V ± 10%, VSS = –5 V ±10%, GND = 0 V (unless otherwise noted)
Typical at VDD = +5 V, VSS = –5 V, TA = 25℃ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX UNIT
ANALOG SWITCH
25°C
4
7.2
8.6
VDD = +4.5 V, VSS = –4.5 V
VS = –4.5 V to +4.5 V
ID = –10 mA
Ω
Ω
–40°C to +85°C
RON
On-resistance
10
0.3
–40°C to +125°C
25°C
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Refer to On-Resistance
0.1
1.3
VS = –4.5 V to +4.5 V
ID = –10 mA
Refer to On-Resistance
On-resistance mismatch between
channels
0.35
0.4
–40°C to +85°C
–40°C to +125°C
25°C
ΔRON
2.2
VS = –4.5 V to +4.5 V
ID = –10 mA
Refer to On-Resistance
2.5
RON FLAT On-resistance flatness
RON DRIFT On-resistance drift
–40°C to +85°C
–40°C to +125°C
2.8
VS = 0 V, IS = –10 mA
Refer to On-Resistance
0.019
0.1
–40°C to +125°C
Ω/°C
25°C
1
4
nA
nA
VDD = +5.5 V, VSS = –5.5 V
Switch state is off
VS = +4.5 V / –4.5 V
–1
–4
–40°C to +85°C
IS(OFF)
Source off leakage current(1)
VD = –4.5 V / + 4.5 V
Refer to Off-Leakage Current
50
nA
–40°C to +125°C
–50
25°C
0.1
0.1
2
5
nA
nA
VDD = +5.5 V, VSS = –5.5 V
Switch state is off
VS = +4.5 V / –4.5 V
VD = –4.5 V / + 4.5 V
Refer to Off-Leakage Current
–2
–5
–40°C to +85°C
ID(OFF)
Drain off leakage current(1)
50
nA
–40°C to +125°C
–50
25°C
2
5
nA
nA
nA
–2
–5
VDD = +5.5 V, VSS = –5.5 V
Switch state is on
VS = VD = ±4.5 V
IS(ON)
ID(ON)
Channel on leakage current(2)
–40°C to +85°C
–40°C to +125°C
Refer to On-Leakage Current
50
–50
LOGIC INPUTS (SEL / EN pins)
VIH
VIL
IIH
Logic voltage high
1.3
0
36
0.8
1
V
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
Logic voltage low
V
Input leakage current
Input leakage current
Logic input capacitance
0.005
µA
µA
pF
IIL
–1 –0.005
CIN
3
POWER SUPPLY
25°C
20
35
40
50
5
µA
µA
µA
µA
µA
µA
VDD = +5.5 V, VSS = –5.5 V
Logic inputs = 0 V, 5 V, or VDD
IDD
VDD supply current
–40°C to +85°C
–40°C to +125°C
25°C
0.001
VDD = +5.5 V, VSS = –5.5 V
Logic inputs = 0 V, 5 V, or VDD
8
ISS
VSS supply current
–40°C to +85°C
–40°C to +125°C
15
(1) When VS is positive, VD is negative, or when VS is negative, VD is positive.
(2) When VS is at a voltage potential, VD is floating, or when VD is at a voltage potential, VS is floating.
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6.13 ±5 V Dual Supply: Switching Characteristics
VDD = +5 V ± 10%, VSS = –5 V ±10%, GND = 0 V (unless otherwise noted)
Typical at VDD = +5 V, VSS = –5 V, TA = 25℃ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
25°C
300
400
490
550
300
350
380
280
330
350
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ms
ms
VS = 3 V
RL = 300 Ω, CL = 35 pF
Refer to Transition Time
tTRAN
Transition time from control input
–40°C to +85°C
–40°C to +125°C
25°C
VS = 3 V
220
210
50
RL = 300 Ω, CL = 35 pF
Refer to Turn-on and Turn-off
Time
tON
Turn-on time from enable
Turn-off time from enable
Break-before-make time delay
–40°C to +85°C
–40°C to +125°C
25°C
(EN)
VS = 3 V
RL = 300 Ω, CL = 35 pF
Refer to Turn-on and Turn-off
Time
tOFF
–40°C to +85°C
–40°C to +125°C
25°C
(EN)
VS = 3 V,
RL = 300 Ω, CL = 35 pF
Refer to Break-Before-Make
1
1
tBBM
–40°C to +85°C
–40°C to +125°C
25°C
0.19
0.19
0.19
VDD rise time = 100ns
RL = 300 Ω, CL = 35pF
Refer to Turn-on (VDD) Time
Device turn on time
(VDD to output)
1
1
TON (VDD)
–40°C to +85°C
–40°C to +125°C
RL = 50 Ω, CL = 5 pF
Refer to Propagation Delay
tPD
Propagation delay
Charge injection
25°C
25°C
650
ps
VD = 0 V, CL = 1 nF
Refer to Charge Injection
QINJ
pC
–5
RL = 50 Ω, CL = 5 pF
VS = 0 V, f = 1 MHz
Refer to Off Isolation
OISO
Off-isolation
Crosstalk
Crosstalk
25°C
25°C
25°C
dB
dB
dB
–55
–117
–106
RL = 50 Ω, CL = 5 pF
VS = 0 V, f = 100 kHz
Refer to Crosstalk
XTALK
RL = 50 Ω, CL = 5 pF
VS = 0 V, f = 1MHz
Refer to Crosstalk
XTALK
RL = 50 Ω, CL = 5 pF
VS = 0 V,
Refer to Bandwidth
BW
IL
25°C
25°C
43
MHz
dB
–3dB Bandwidth
RL = 50 Ω, CL = 5 pF
VS = 0 V, f = 1 MHz
Insertion loss
–0.35
VPP = 0.62 V on VDD and VSS
RL = 50 Ω, CL = 5 pF,
f = 1 MHz
ACPSRR AC Power Supply Rejection Ratio
25°C
25°C
25°C
dB
%
–68
0.001
Refer to ACPSRR
VPP = 5 V, VBIAS = 0 V
RL = 10 kΩ, CL = 5 pF,
f = 20 Hz to 20 kHz
THD+N
THD+N
Total Harmonic Distortion + Noise
Total Harmonic Distortion + Noise
Refer to THD + Noise
VPP = 5 V, VBIAS = 0 V
RL = 10 MΩ, CL = 5 pF,
f = 20 Hz to 20 kHz
0.0006
%
Refer to THD + Noise
CS(OFF)
CD(OFF)
Source off capacitance
Drain off capacitance
VS = 0 V, f = 1 MHz
VS = 0 V, f = 1 MHz
25°C
25°C
40
60
pF
pF
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VDD = +5 V ± 10%, VSS = –5 V ±10%, GND = 0 V (unless otherwise noted)
Typical at VDD = +5 V, VSS = –5 V, TA = 25℃ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX UNIT
CS(ON),
CD(ON)
On capacitance
VS = 0 V, f = 1 MHz
25°C
150
pF
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6.14 Typical Characteristics
at TA = 25°C
4
VDD = 18 V, VSS = –18 V
VDD = 15 V, VSS = –15 V
3.5
3
2.5
2
1.5
1
-20
-15
-10
-5
0
5
10
15
20
VS or VD - Source or Drain Voltage (V)
图6-1. On-Resistance vs Source or Drain Voltage –Dual
图6-2. On-Resistance vs Source or Drain Voltage –Dual
Supply
Supply
5
VDD = 36 V, VSS = 0 V
VDD = 24 V, VSS = 0 V
VDD = 18 V, VSS = 0 V
4
3
2
1
0
4
8
12
16
20
24
28
32
36
VS or VD - Source or Drain Voltage (V)
图6-3. On-Resistance vs Source or Drain Voltage –Single
图6-4. On-Resistance vs Source or Drain Voltage –Single
Supply
Supply
VDD = 15 V, VSS = -15 V
VDD = 5 V, VSS = -5 V
图6-5. On-Resistance vs Temperature
图6-6. On-Resistance vs Temperature
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6.14 Typical Characteristics (continued)
at TA = 25°C
VDD = 12 V, VSS = 0 V
VDD = 36 V, VSS = 0 V
图6-7. On-Resistance vs Temperature
图6-8. On-Resistance vs Temperature
15
ID(OFF) VS/VD = –4.5 V/4.5 V
ID(OFF) VS/VD = 4.5 V/–4.5 V
ION –4.5 V
ION 4.5 V
IS(OFF) VS/VD = –4.5 V/4.5 V
IS(OFF) VS/VD = 4.5 V/–4.5 V
10
5
0
-5
-10
-15
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
VDD = 5 V, VSS = -5 V
VDD = 15 V, VSS = -15 V
图6-9. Leakage Current vs Temperature
图6-10. Leakage Current vs Temperature
VDD = 36 V, VSS = 0 V
VDD = 12 V, VSS = 0 V
图6-11. Leakage Current vs Temperature
图6-12. Leakage Current vs Temperature
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6.14 Typical Characteristics (continued)
at TA = 25°C
50
100
80
60
40
20
0
VDD = 15 V, VSS = –15 V
VDD = 5 V, VSS = –5 V
VDD = 12 V, VSS = 0 V
VDD = 5 V, VSS = 0 V
VDD = 15 V, VSS = –15 V
VDD = 5 V, VSS = –5 V
45
40
35
30
25
20
15
-20
-40
-60
0
4
8
12
16
20
24
28
32
36
-20
-15
-10
-5
0
5
10
15
20
Logic Voltage (V)
Source Voltage (V)
D015
图6-14. Charge Injection vs Source Voltage –Dual Supplies
图6-13. Supply Current vs Logic Voltage
80
130
VDD = 15 V, VSS = –15 V
VDD = 5 V, VSS = –5 V
VDD = 36 V, VSS = 0 V
VDD = 20 V, VSS = 0 V
VDD = 15 V, VSS = 0 V
VDD = 12 V, VSS = 0 V
110
60
40
20
0
90
VDD = 5 V, VSS = 0 V
70
50
30
10
-10
-30
-50
-70
-20
-40
-20
-15
-10
-5
0
5
10
15
20
0
4
8
12
16
20
24
28
32
36
Drain Voltage (V)
Source Voltage (V)
D018
图6-15. Charge Injection vs Drain Voltage –Dual Supplies
图6-16. Charge Injection vs Source Voltage –Single Supplies
120
VDD = 36 V, VSS = 0 V
100
80
60
40
20
0
VDD = 20 V, VSS = 0 V
VDD = 15 V, VSS = 0 V
VDD = 12 V, VSS = 0 V
VDD = 5 V, VSS = 0 V
-20
-40
-60
0
4
8
12
16
20
24
28
32
36
Drain Voltage (V)
VDD = 15 V, VSS = -15 V
图6-17. Charge Injection vs Drian Voltage –Single Supplies
图6-18. TTRANSITION vs Temperature
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6.14 Typical Characteristics (continued)
at TA = 25°C
120
Transiton_Falling
Transiton_Rising
115
110
105
100
95
90
85
80
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
VDD = 36 V, VSS = 0 V
VDD = 15 V, VSS = -15 V
图6-19. TTRANSITION vs Temperature
图6-20. TON and TOFF vs Temperature
120
115
110
105
100
95
0
T(OFF)
T(ON)
VDD = 15V, VSS = –15V
VDD = 36V, VSS = 0V
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
90
85
80
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
100
1k
10k
100k
1M
10M
100M
Frequency (Hz)
VDD = 36 V, VSS = 0 V
图6-21. TON and TOFF vs Temperature
图6-22. Off-Isolation vs Frequency
Switch ON (EN = 1)
Switch OFF (EN = 0)
图6-23. Crosstalk vs Frequency
图6-24. Crosstalk vs Frequency
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6.14 Typical Characteristics (continued)
at TA = 25°C
0.002
VDD = 15 V, VSS = –15 V
VDD = 5 V, VSS = –5V
0.001
0.0008
0.0007
0.0006
0.0005
0.0004
0.0003
10
100
1k
10k
Frequency (Hz)
图6-26. THD+N vs Frequency (Single Supplies)
图6-25. THD+N vs Frequency (Dual Supplies)
VDD = 15 V, VSS = -15 V
VDD = +15 V, VSS = -15 V
图6-27. On Response vs Frequency
图6-28. ACPSRR vs Frequency
VDD = +15 V, VSS = -15 V
VDD = 12 V, VSS = 0 V
图6-29. Capacitance vs Source Voltage or Drain Voltage
图6-30. Capacitance vs Source Voltage or Drain Voltage
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7 Parameter Measurement Information
7.1 On-Resistance
The on-resistance of a device is the ohmic resistance between the source (Sx) and drain (D) pins of the device.
The on-resistance varies with input voltage and supply voltage. The symbol RON is used to denote on-
resistance. 图 7-1 shows the measurement setup used to measure RON. Voltage (V) and current (ISD) are
measured using the following setup, where RON is computed as RON = V / ISD
:
V
ISD
Sx
Dx
VS
图7-1. On-Resistance
7.2 Off-Leakage Current
There are two types of leakage currents associated with a switch during the off state:
1. Source off-leakage current.
2. Drain off-leakage current.
Source leakage current is defined as the leakage current flowing into or out of the source pin when the switch is
off. This current is denoted by the symbol IS(OFF)
Drain leakage current is defined as the leakage current flowing into or out of the drain pin when the switch is off.
This current is denoted by the symbol ID(OFF)
图7-2 shows the setup used to measure both off-leakage currents.
.
.
VDD
VSS
VDD
VSS
Is (OFF)
ID (OFF)
S1
S2
S1
S2
A
D
D
A
VS
VS
VD
VD
GND
GND
IS(OFF)
ID(OFF)
图7-2. Off-Leakage Measurement Setup
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7.3 On-Leakage Current
Source on-leakage current is defined as the leakage current flowing into or out of the source pin when the switch
is on. This current is denoted by the symbol IS(ON)
.
Drain on-leakage current is defined as the leakage current flowing into or out of the drain pin when the switch is
on. This current is denoted by the symbol ID(ON)
.
Either the source pin or drain pin is left floating during the measurement. 图 7-3 shows the circuit used for
measuring the on-leakage current, denoted by IS(ON) or ID(ON)
.
VDD
VSS
VDD
VSS
Is (ON)
ID (ON)
S1
S2
S1
S2
N.C.
A
D
D
A
N.C.
VS
VS
VS
GND
GND
IS(ON)
ID(ON)
图7-3. On-Leakage Measurement Setup
7.4 Transition Time
Transition time is defined as the time taken by the output of the device to rise or fall 90% after the address signal
has risen or fallen past the logic threshold. The 90% transition measurement is utilized to provide the timing of
the device. System level timing can then account for the time constant added from the load resistance and load
capacitance. 图7-4 shows the setup used to measure transition time, denoted by the symbol tTRANSITION
.
VDD
VSS
0.1 µF
0.1 µF
VS
3 V
0 V
VDD
VSS
VSEL
tr < 20 ns
tf < 20 ns
50%
50%
S1
S2
D
Output
CL
tTRANSITION
tTRANSITION
90%
RL
SEL
Output
10%
GND
VSEL
0 V
图7-4. Transition-Time Measurement Setup
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7.5 tON(EN) and tOFF(EN)
Turn-on time is defined as the time taken by the output of the device to rise to 90% after the enable has risen
past the logic threshold. The 90% measurement is utilized to provide the timing of the device. System level
timing can then account for the time constant added from the load resistance and load capacitance. 图 7-5
shows the setup used to measure turn-on time, denoted by the symbol tON(EN)
.
Turn-off time is defined as the time taken by the output of the device to fall to 10% after the enable has fallen
past the logic threshold. The 10% measurement is utilized to provide the timing of the device. System level
timing can then account for the time constant added from the load resistance and load capacitance. 图 7-5
shows the setup used to measure turn-off time, denoted by the symbol tOFF(EN)
.
VDD
VSS
0.1 µF
0.1 µF
3 V
VDD
VSS
VEN
tr < 20 ns
tf < 20 ns
50%
50%
S1
S2
VS
0 V
D
Output
CL
tON
tOFF
90%
RL
EN
Output
10%
GND
VEN
0 V
图7-5. Turn-On and Turn-Off Time Measurement Setup
7.6 Break-Before-Make
Break-before-make delay is a safety feature that prevents two inputs from connecting when the device is
switching. The output first breaks from the on-state switch before making the connection with the next on-state
switch. The time delay between the break and the make is known as break-before-make delay. 图7-6 shows the
setup used to measure break-before-make delay, denoted by the symbol tOPEN(BBM)
.
VDD
VSS
0.1 µF
0.1 µF
3 V
VDD
VSS
VSEL
tr < 20ns
tf < 20ns
S1
S2
VS
0 V
D
Output
CL
RL
80%
SEL
Output
0 V
tBBM
1
tBBM 2
VSEL
GND
tOPEN (BBM) = min ( tBBM 1, tBBM 2)
图7-6. Break-Before-Make Delay Measurement Setup
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7.7 tON (VDD) Time
The tON (VDD) time is defined as the time taken by the output of the device to rise to 90% after the supply has
risen past the supply threshold. The 90% measurement is used to provide the timing of the device turning on in
the system. 图7-7 shows the setup used to measure turn on time, denoted by the symbol tON (VDD)
.
VSS
0.1 µF
0.1 µF
VDD
Supply
Ramp
VDD
VDD
VSS
tr = 10 µs
4.5 V
VS
S2
S1
0 V
D
Output
CL
tON
90%
RL
EN
Output
3 V
SEL
GND
0 V
图7-7. tON (VDD) Time Measurement Setup
7.8 Propagation Delay
Propagation delay is defined as the time taken by the output of the device to rise or fall 50% after the input signal
has risen or fallen past the 50% threshold. 图 7-8 shows the setup used to measure propagation delay, denoted
by the symbol tPD
.
VDD
VSS
0.1 µF
0.1 µF
250 mV
Input
(VS)
VDD
S1
S2
VSS
50%
50%
tr < 40ps
tf < 40ps
50 ꢀ
VS
0 V
D
Output
CL
tPD
1
tPD 2
RL
Output
0 V
50%
50%
GND
tProp Delay = max ( tPD 1, tPD 2)
图7-8. Propagation Delay Measurement Setup
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7.9 Charge Injection
The TMUX6219-Q1 has a transmission-gate topology. Any mismatch in capacitance between the NMOS and
PMOS transistors results in a charge injected into the drain or source during the falling or rising edge of the gate
signal. The amount of charge injected into the source or drain of the device is known as charge injection, and is
denoted by the symbol QC. 图 7-9 shows the setup used to measure charge injection from source (Sx) to drain
(D).
VDD
VSS
0.1 µF
0.1 µF
3 V
VEN
VDD
VSS
tr < 20 ns
tf < 20 ns
Output
S1
S2
D
0 V
VD
CL
N.C.
Output
VD
EN
VOUT
QINJ = CL ×
VOUT
VEN
GND
图7-9. Charge-Injection Measurement Setup
7.10 Off Isolation
Off isolation is defined as the ratio of the signal at the drain pin (D) of the device when a signal is applied to the
source pin (Sx) of an off-channel. 图 7-10 shows the setup used to measure, and the equation used to calculate
off isolation.
VDD
VSS
0.1 µF
0.1 µF
VDD
VSS
Network Analyzer
VS
S1
D
50Ω
VOUT
VSIG
50Ω
S2
50Ω
GND
8176
1BB +OKH=PEKJ = 20 × .KC
8
5
图7-10. Off Isolation Measurement Setup
≈
∆
«
’
÷
◊
VOUT
VS
Off Isolation = 20 ∂ Log
(1)
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7.11 Crosstalk
Crosstalk is defined as the ratio of the signal at the drain pin (D) of a different channel, when a signal is applied
at the source pin (Sx) of an on-channel. 图 7-11 shows the setup used to measure, and the equation used to
calculate crosstalk.
VDD
VSS
0.1 µF
0.1 µF
VDD
VSS
Network Analyzer
VS
S1
S2
D
50Ω
VOUT
50Ω
VSIG
50Ω
GND
8176
%NKOOP=HG = 20 × .KC
8
5
图7-11. Crosstalk Measurement Setup
7.12 Bandwidth
Bandwidth is defined as the range of frequencies that are attenuated by less than 3 dB when the input is applied
to the source pin (Sx) of an on-channel, and the output is measured at the drain pin (D) of the device. 图 7-12
shows the setup used to measure bandwidth.
VDD
VSS
0.1 µF
0.1 µF
VDD
VSS
Network Analyzer
VS
S1
D
50Ω
VOUT
VSIG
50Ω
S2
50Ω
GND
8176
$=J@SE@PD = 20 × .KC
8
5
图7-12. Bandwidth Measurement Setup
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7.13 THD + Noise
The total harmonic distortion (THD) of a signal is a measurement of the harmonic distortion, and is defined as
the ratio of the sum of the powers of all harmonic components to the power of the fundamental frequency at the
mux output.
The on-resistance of the device varies with the amplitude of the input signal and results in distortion when the
drain pin is connected to a low-impedance load. Total harmonic distortion plus noise is denoted as THD + N.
VDD
VSS
0.1 µF
0.1 µF
VDD
VSS
Audio Precision
S1
D
40 Ω
VOUT
VS
RL
Other
Sx pins
50Ω
GND
图7-13. THD + N Measurement Setup
7.14 Power Supply Rejection Ratio (PSRR)
PSRR measures the ability of a device to prevent noise and spurious signals that appear on the supply voltage
pin from coupling to the output of the switch. The DC voltage on the device supply is modulated by a sine wave
of 620 mVPP. The ratio of the amplitude of signal on the output to the amplitude of the modulated signal is the
ACPSRR. A high ratio represents a high degree of tolerance to supply rail variation.
This helps stabilize the supply and immediately filter as much of the supply noise as possible.
VDD
Network Analyzer
VSS
DC Bias
Injector
With & Without
Capacitor
50 Ω
0.1 µF
0.1 µF
VDD
S1
VSS
620 mVPP
VIN
VBIAS
50 Ω
S2
50 Ω
VOUT
D
RL
GND
CL
8176
2544 = 20 × .KC
8
+0
图7-14. ACPSRR Measurement Setup
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8 Detailed Description
8.1 Overview
The TMUX6219-Q1 is a 2:1, 1-channel switch. Each input is turned on or turned off based on the state of the
select line and enable pin.
8.2 Functional Block Diagram
VSS
VDD
S1
S2
D
Decoder
EN SEL
图8-1. TMUX6219-Q1 Functional Block Diagram
8.3 Feature Description
8.3.1 Bidirectional Operation
The TMUX6219-Q1 conducts equally well from source (Sx) to drain (D) or from drain (D) to source (Sx). Each
channel has very similar characteristics in both directions and supports both analog and digital signals.
8.3.2 Rail to Rail Operation
The valid signal path input or output voltage for TMUX6219-Q1 ranges from VSS to VDD
.
8.3.3 1.8 V Logic Compatible Inputs
The TMUX6219-Q1 has 1.8-V logic compatible control for all logic control inputs. 1.8-V logic level inputs allows
the TMUX6219-Q1 to interface with processors that have lower logic I/O rails and eliminates the need for an
external translator, which saves both space and BOM cost. For more information on 1.8 V logic implementations
refer to Simplifying Design with 1.8 V logic Muxes and Switches.
8.3.4 Fail-Safe Logic
The TMUX6219-Q1 supports Fail-Safe Logic on the control input pins (EN, SEL) allowing for operation up to 36
V above ground, regardless of the state of the supply pins. This feature allows voltages on the control pins to be
applied before the supply pin, protecting the device from potential damage. Fail-Safe Logic minimizes system
complexity by removing the need for power supply sequencing on the logic control pins. For example, the Fail-
Safe Logic feature allows the logic input pins of the TMUX6219-Q1 to be ramped to +36 V while VDD and VSS
=
0 V. The logic control inputs are protected against positive faults of up to +36 V in powered-off condition, but do
not offer protection against negative overvoltage conditions.
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8.3.5 Latch-Up Immune
Latch-Up is a condition where a low impedance path is created between a supply pin and ground. This condition
is caused by a trigger (current injection or overvoltage), but once activated, the low impedance path remains
even after the trigger is no longer present. This low impedance path may cause system upset or catastrophic
damage due to excessive current levels. The Latch-Up condition typically requires a power cycle to eliminate the
low impedance path.
The TMUX62xx family of devices are constructed on Silicon on Insulator (SOI) based process where an oxide
layer is added between the PMOS and NMOS transistor of each CMOS switch to prevent parasitic structures
from forming. The oxide layer is also known as an insulating trench and prevents triggering of latch up events
due to overvoltage or current injections. The latch-up immunity feature allows the TMUX62xx family of switches
and multiplexers to be used in harsh environments.
8.3.6 Ultra-Low Charge Injection
The TMUX6219-Q1 has a transmission gate topology, as shown in 图 8-2. Any mismatch in the stray
capacitance associated with the NMOS and PMOS causes an output level change whenever the switch is
opened or closed.
OFF ON
CGDN
CGSN
D
S
CGSP
CGDP
OFF ON
图8-2. Transmission Gate Topology
The TMUX6219-Q1 contains specialized architecture to reduce charge injection on the source (Sx). To further
reduce charge injection in a sensitive application, a compensation capacitor (Cp) can be added on the drain (D).
This will ensure that excess charge from the switch transition will be pushed into the compensation capacitor on
the drain (D) instead of the source (Sx). As a general rule of thumb, Cp should be 20× larger than the equivalent
load capacitance on the source (Sx). 图 8-3 shows charge injection variation with source voltage with different
compensation capacitors on the Drain side.
图8-3. Charge Injection Compensation
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8.4 Device Functional Modes
When the EN pin of the TMUX6219-Q1 is pulled high, one of the switches is closed based on the state of the
SEL pin. When the EN pin is pulled low, both of the switches are in an open state regardless of the state of the
SEL pin. The control pins can be as high as 36 V.
The TMUX6219-Q1 can be operated without any external components except for the supply decoupling
capacitors. The EN pin has an internal pull-up resistor of 4 MΩ and SEL pin has internal pull-down resistor of 4
MΩ. If unused, EN pin must be tied to VDD and SEL pin must be tied to GND in order to ensure the device does
not consume additional current as highlighted in Implications of Slow or Floating CMOS Inputs. Unused signal
path inputs (S1, S2, or D) should be connected to GND.
8.5 Truth Tables
表8-1 show the truth tables for the TMUX6219-Q1.
表8-1. TMUX6219-Q1 Truth Table
EN SEL
Selected Source Connected To Drain (D) Pin
0
1
1
X(1)
All sources are off (HI-Z)
0
S1
S2
1
(1) X denotes don't care.
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9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Application Information
TMUX6219-Q1 is part of the precision switches and multiplexers family of devices. TMUX6219-Q1 offers low
RON, low on and off leakage currents and ultra-low charge injection performance. These properties make
TMUX6219-Q1 ideal for implementing high precision industrial systems requiring selection of one of two inputs
or outputs.
9.2 Typical Application
9.2.1 PWM Signal Generation (EV Charging Station)
One application of the TMUX6219-Q1 is in Electric Vehicle Service Equipment (EVSE). The EVSE is a system
that monitors and controls the high voltage power path from the grid to the vehicle. One key feature of an EVSE
is the pilot signal wire communication support that requires a 1-kHz, ±12-V PWM signal to be transmitted down
the length of the charger cable to the vehicle.
The TMUX6219-Q1 can be used to generate 1kHz ±12V PWM signal for EVSE control pilot. A 1 kHz square
wave at ±12 V generated by the EVSE on the control pilot line is used to detect the presence of the vehicle,
communicate the maximum allowable charging current, and control charging.
图9-1 shows the TMUX6219-Q1 configured for PWM signal generation for EVSE control pilot.
+12V
+12 V
0V
+12V
–12V
±12 V, 1kHz
EVSE
Control
Electric
Vehicle
–12V
SEL
TMUX6219-
Q1
–12 V
0 V to 5 V, 1kHz
图9-1. PWM Signal Generation (EV Charging Station)
9.2.2 Design Requirements
For the design example, use the parameters listed in 表9-1 .
表9-1. Design Parameters
PARAMETERS
Supply (VDD
Supply (VSS
VALUES
12 V
)
)
-12 V
MUX I/O signal range
Control logic thresholds
EN
-12 V to 12 V (Rail-to-Rail)
1.8 V compatiable (up to VDD
)
EN pulled high to enable the switch
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9.2.3 Detailed Design Procedure
The application shown in 图 9-1 demonstrates how to generate a ±12V PWM signal that is created by toggling
the TMUX6219-Q1. This PWM signal generated by the EVSE on the control pilot line signals to the car the
available current of the charger, and the car will respond with a charging status. This handshake results in a safe
method for supplying power to vehicle. The TMUX6219-Q1 can support 1.8 V logic signals on the control input,
allowing the device to interface with low logic controls of an FPGA or MCU. The TMUX6219-Q1 can be operated
without any external components except for the supply decoupling capacitors. The select pin has an internal
pull-down resistor to prevent floating input logic. All inputs to the switch must fall within the recommend operating
conditions of the TMUX6219-Q1 including signal range and continuous current. For this design with a positive
supply of 12 V on VDD, and negative supply of -12 V on VSS, the signal range can be 12 V to -12 V. The max
continuous current (IDC) can be up to 330 mA as shown in the Recommended Operating Conditions table for
wide-range current measurement.
10 Power Supply Recommendations
The TMUX6219-Q1 operates across a wide supply range of of ±4.5 V to ±18 V (4.5 V to 36 V in single-supply
mode). It also performs well with asymmetrical supplies such as VDD = 8 V and VSS = –12 V.
Power-supply bypassing improves noise margin and prevents switching noise propagation from the supply rails
to other components. Good power-supply decoupling is important to achieve optimum performance. For
improved supply noise immunity, use a supply decoupling capacitor ranging from 0.1 μF to 10 μF at both the
VDD and VSS pins to ground. Place the bypass capacitors as close to the power supply pins of the device as
possible using low-impedance connections. TI recommends using multi-layer ceramic chip capacitors (MLCCs)
that offer low equivalent series resistance (ESR) and inductance (ESL) characteristics for power-supply
decoupling purposes. For very sensitive systems, or for systems in harsh noise environments, avoiding the use
of vias for connecting the capacitors to the device pins may offer superior noise immunity. The use of multiple
vias in parallel lowers the overall inductance and is beneficial for connections to power and ground planes.
Always ensure the ground (GND) connection is established before supplies are ramped.
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11 Layout
11.1 Layout Guidelines
When a PCB trace turns a corner at a 90° angle, a reflection can occur. A reflection occurs primarily because of
the change of width of the trace. At the apex of the turn, the trace width increases to 1.414 times the width. This
increase upsets the transmission-line characteristics, especially the distributed capacitance and self–inductance
of the trace which results in the reflection. Not all PCB traces can be straight and therefore some traces must
turn corners. 图 11-1 shows progressively better techniques of rounding corners. Only the last example (BEST)
maintains constant trace width and minimizes reflections.
WORST
BETTER
BEST
2W
1W min.
W
图11-1. Trace Example
Route high-speed signals using a minimum of vias and corners which reduces signal reflections and impedance
changes. When a via must be used, increase the clearance size around it to minimize its capacitance. Each via
introduces discontinuities in the signal’s transmission line and increases the chance of picking up interference
from the other layers of the board. Be careful when designing test points, through-hole pins are not
recommended at high frequencies.
图11-2 illustrates an example of a PCB layout with the TMUX6219-Q1. Some key considerations are:
• Decouple the supply pins with a 0.1-µF and 1 µF capacitor, placed lowest value capacitor as close to the pin
as possible. Make sure that the capacitor voltage rating is sufficient for the supply voltage.
• Keep the input lines as short as possible.
• Use a solid ground plane to help reduce electromagnetic interference (EMI) noise pickup.
• Do not run sensitive analog traces in parallel with digital traces. Avoid crossing digital and analog traces if
possible, and only make perpendicular crossings when necessary.
• Using multiple vias in parallel will lower the overall inductance and is beneficial for connection to ground
planes.
11.2 Layout Example
S2
VSS
SEL
EN
D
TMUX6219-Q1
S1
GND
VDD
Wide (low inductance)
trace for power
C
C
Wide (low inductance)
trace for power
Via to ground plane
图11-2. TMUX6219-Q1 Layout Example
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation, see the following:
• Texas Instruments, Improve Stability Issues with Low CON Multiplexers application brief
• Texas Instruments, Improving Signal Measurement Accuracy in Automated Test Equipment application brief
• Texas Instruments, Multiplexers and Signal Switches Glossary application report
• Texas Instruments, QFN/SON PCB Attachment application report
• Texas Instruments, Quad Flatpack No-Lead Logic Packages application report
• Texas Instruments, Simplifying Design with 1.8 V logic Muxes and Switches application brief
• Texas Instruments, System-Level Protection for High-Voltage Analog Multiplexers application report
• Texas Instruments, TMUX6219-Q1 Functional Safety, FIT Rate, Failure Mode Distribution and Pin FMA
functional safety FIT rate, FMD and Pin-FMA
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.3 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料,可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范,并且不一定反映 TI 的观点;请参阅
TI 的《使用条款》。
12.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.6 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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重要声明和免责声明
TI 提供技术和可靠性数据(包括数据表)、设计资源(包括参考设计)、应用或其他设计建议、网络工具、安全信息和其他资源,不保证没
有瑕疵且不做出任何明示或暗示的担保,包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担保。
这些资源可供使用TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任:(1) 针对您的应用选择合适的TI 产品,(2) 设计、验
证并测试您的应用,(3) 确保您的应用满足相应标准以及任何其他安全、安保或其他要求。这些资源如有变更,恕不另行通知。TI 授权您仅可
将这些资源用于研发本资源所述的TI 产品的应用。严禁对这些资源进行其他复制或展示。您无权使用任何其他TI 知识产权或任何第三方知
识产权。您应全额赔偿因在这些资源的使用中对TI 及其代表造成的任何索赔、损害、成本、损失和债务,TI 对此概不负责。
TI 提供的产品受TI 的销售条款(https:www.ti.com/legal/termsofsale.html) 或ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI
提供这些资源并不会扩展或以其他方式更改TI 针对TI 产品发布的适用的担保或担保免责声明。重要声明
邮寄地址:Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2021,德州仪器(TI) 公司
PACKAGE MATERIALS INFORMATION
www.ti.com
4-Jul-2021
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TMUX6219DGKRQ1
VSSOP
DGK
8
2500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
4-Jul-2021
*All dimensions are nominal
Device
Package Type Package Drawing Pins
VSSOP DGK
SPQ
Length (mm) Width (mm) Height (mm)
366.0 364.0 50.0
TMUX6219DGKRQ1
8
2500
Pack Materials-Page 2
重要声明和免责声明
TI 提供技术和可靠性数据(包括数据表)、设计资源(包括参考设计)、应用或其他设计建议、网络工具、安全信息和其他资源,不保证没
有瑕疵且不做出任何明示或暗示的担保,包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担保。
这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任:(1) 针对您的应用选择合适的 TI 产品,(2) 设计、验
证并测试您的应用,(3) 确保您的应用满足相应标准以及任何其他安全、安保或其他要求。这些资源如有变更,恕不另行通知。TI 授权您仅可
将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。您无权使用任何其他 TI 知识产权或任何第三方知
识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成本、损失和债务,TI 对此概不负责。
TI 提供的产品受 TI 的销售条款 (https:www.ti.com.cn/zh-cn/legal/termsofsale.html) 或 ti.com.cn 上其他适用条款/TI 产品随附的其他适用条款
的约束。TI 提供这些资源并不会扩展或以其他方式更改 TI 针对 TI 产品发布的适用的担保或担保免责声明。IMPORTANT NOTICE
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