TMUX7234PWR_技术文档

TMUX7234

ZHCSNF7F –FEBRUARY 2021 –REVISED DECEMBER 2022

TMUX7234 具有闩锁效应抑制和1.8V 逻辑电平的

44V、低RON、2:1、4 通道精密开关

1 特性

3 说明

• 闩锁效应抑制

TMUX7234 是支持闩锁效应抑制的互补金属氧化物半

导体 (CMOS) 多路复用器。TMUX7234 包含四个独立

控制的 SPDT 开关和一个用于启用或禁用全部四个通

道的 EN 引脚。该器件支持单电源（4.5V 至 44V）、

双电源（±4.5V 至 ±22V）或非对称电源（例如，V_DD

= 12V，V_SS= –5V）。TMUX7234 可在源极 (Sx) 和

漏极 (D) 引脚上支持从 V_SS到 V_DD范围的双向模拟和

数字信号。

• 双电源电压范围：±4.5 V 至±22 V

• 单电源电压范围：4.5 V 至44 V

• 低导通电阻：3Ω

• 低电荷注入：3pC

• 高电流支持：400 mA（最大值）

• –40°C 至+125°C 工作温度

• 1.8V 逻辑兼容输入

• 失效防护逻辑

• 轨到轨运行

• 双向信号路径

• 先断后合开关

所有逻辑控制输入均支持1.8V 到V_DD的逻辑电平，因

此，当器件在有效电源电压范围内运行时，可确保

TTL 和 CMOS 逻辑兼容性。失效防护逻辑电路允许先

在控制引脚上施加电压，然后在电源引脚上施加电压，

从而保护器件免受潜在的损害。

2 应用

• 工厂自动化和控制

• 流量变送器

• 可编程逻辑控制器(PLC)

• 模拟输入模块

• 数据采集系统(DAQ)

• 半导体测试设备

• 电池测试设备

TMUX72xx 系列具有闩锁效应抑制特性，可防止器件

内寄生结构之间通常由过压事件引起的大电流不良事

件。闩锁状态通常会一直持续到电源轨关闭为止，并可

能导致器件故障。闩锁效应抑制特性使得 TMUX72xx

系列开关和多路复用器能够在恶劣的环境中使用。

封装信息⁽¹⁾

封装尺寸（标称值）

器件型号

TMUX7234

封装

• 超声波扫描仪

• 患者监护和诊断

• 光纤网络

• 光学测试设备

PW（TSSOP，20） 6.50mm × 4.40mm

RRQ（WQFN，20） 4.00mm × 4.00mm

(1) 如需了解所有可用封装，请参阅数据表末尾的封装选项附录。

• 有线网络

• 远程射频单元(RRU)

• 有源天线系统mMIMO (AAS)

+15

+15V

S1A

S1B

D1

D2

V_DD

V_SS

THS3091

S2A

S2B

S1A

S1B

D1

D2

D3

D4

MSP430

-15

-15V

+15

+15V

S2A

S2B

S3A

S3B

D3

D4

THS3091

S3A

S3B

S4A

S4B

-15

-15V

S4A

S4B

应用示意图

SEL1

SEL2

SEL3

SEL4

Logic Decoder

EN

TMUX7234

简化版图表

本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问

www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SCDS429

TMUX7234

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ZHCSNF7F –FEBRUARY 2021 –REVISED DECEMBER 2022

Table of Contents

7.9 Charge Injection........................................................24

7.10 Off Isolation.............................................................24

7.11 Crosstalk................................................................. 25

7.12 Bandwidth............................................................... 25

7.13 THD + Noise........................................................... 26

7.14 Power Supply Rejection Ratio (PSRR)...................26

8 Detailed Description......................................................27

8.1 Overview...................................................................27

8.2 Functional Block Diagram.........................................27

8.3 Feature Description...................................................27

8.4 Device Functional Modes..........................................29

8.5 Truth Tables.............................................................. 29

9 Application and Implementation..................................30

9.1 Application Information............................................. 30

9.2 Typical Application.................................................... 30

10 Power Supply Recommendations..............................32

11 Layout...........................................................................32

11.1 Layout Guidelines................................................... 32

11.2 Layout Example...................................................... 33

12 Device and Documentation Support..........................34

12.1 Documentation Support.......................................... 34

12.2 Receiving Notification of Documentation Updates..34

12.3 支持资源..................................................................34

12.4 Trademarks.............................................................34

12.5 Electrostatic Discharge Caution..............................34

12.6 术语表..................................................................... 34

13 Mechanical, Packaging, and Orderable

1 特性................................................................................... 1

2 应用................................................................................... 1

3 说明................................................................................... 1

4 Revision History.............................................................. 2

5 Pin Configuration and Functions...................................3

6 Specifications.................................................................. 5

6.1 Absolute Maximum Ratings........................................ 5

6.2 ESD Ratings............................................................... 5

6.3 Thermal Information....................................................5

6.4 Recommended Operating Conditions.........................6

6.5 Source or Drain Continuous Current...........................6

6.6 ±15 V Dual Supply: Electrical Characteristics ............7

6.7 ±15 V Dual Supply: Switching Characteristics ...........8

6.8 ±20 V Dual Supply: Electrical Characteristics.............9

6.9 ±20 V Dual Supply: Switching Characteristics..........10

6.10 44 V Single Supply: Electrical Characteristics ....... 11

6.11 44 V Single Supply: Switching Characteristics .......12

6.12 12 V Single Supply: Electrical Characteristics ....... 13

6.13 12 V Single Supply: Switching Characteristics ...... 14

6.14 Typical Characteristics............................................15

7 Parameter Measurement Information..........................20

7.1 On-Resistance.......................................................... 20

7.2 Off-Leakage Current................................................. 20

7.3 On-Leakage Current................................................. 21

7.4 Transition Time......................................................... 21

7.5 t_ON(EN)and t_OFF(EN).................................................. 22

7.6 Break-Before-Make...................................................22

7.7 t_{ON (VDD)}Time............................................................23

7.8 Propagation Delay.................................................... 23

Information.................................................................... 34

4 Revision History

注：以前版本的页码可能与当前版本的页码不同

Changes from Revision E (August 2021) to Revision F (November 2022)

Page

• 将PW 封装状态从预发布更改为正在供货........................................................................................................ 1

Changes from Revision D (August 2021) to Revision E (August 2021)

Page

• Updated ESD HBM spec.................................................................................................................................... 5

Changes from Revision C (June 2021) to Revision D (August 2021)

Page

• 将状态从：预告信息更改为量产数据................................................................................................................ 1

2

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ZHCSNF7F –FEBRUARY 2021 –REVISED DECEMBER 2022

5 Pin Configuration and Functions

SEL1

S1A

D1

1

2

3

4

5

6

7

8

9

10

20

19

18

17

16

15

14

13

12

11

SEL4

S4A

D4

D1

S1B

VSS

GND

S2B

1

2

3

4

5

15

14

13

12

11

D4

S1B

VSS

GND

S2B

D2

S4B

VDD

S4B

VDD

S3B

D3

Thermal

Pad

S3B

D3

S2A

SEL2

S3A

SEL3

Not to scale

图5-2. TMUX7234 RRQ Package, 20-Pin WQFN

图5-1. TMUX7234 PW Package, 20-Pin TSSOP (Top

(Top View)

View)

表5-1. Pin Functions TMUX7234

PW NO.

TYPE⁽¹⁾

DESCRIPTION⁽²⁾

NAME

SEL1

S1A

RRQ NO.

1

2

3

4

19

20

1

I

Logic control input 1; has internal pull-down resistor. Controls switch 1 (see 节8.5).

Source pin 1A. Can be an input or output.

I/O

D1

Drain pin 1. Can be an input or output.

S1B

2

Source pin 1B. Can be an input or output.

Negative power supply. This pin has the most negative power-supply potential. This pin

can be connected to ground in single supply applications. Connect a decoupling capacitor

ranging from 0.1 μF to 10 μF between VSS and GND for reliable operation.

VSS

5

3

P

GND

S2B

D2

6

7

4

5

P

I/O

I

Ground (0 V) reference.

Source pin 2B. Can be an input or output.

8

6

Drain pin 2. Can be an input or output.

S2A

SEL2

SEL3

S3A

D3

9

7

Source pin 2A. Can be an input or output.

10

11

12

13

14

8

Logic control input 2; has internal pull-down resistor. Controls switch 2 (see 节8.5).

Logic control input 3; has internal pull-down resistor. Controls switch 3 (see 节8.5).

Source pin 3A. Can be an input or output.

9

I

10

11

12

I/O

Drain pin 3. Can be an input or output.

S3B

Source pin 3B. Can be an input or output.

Active low logic enable; has internal pull-down resistor. The SELx logic inputs determine

switch connections when this pin is low (see 节8.5).

EN

15

16

18

13

I

Positive power supply. This pin has the most positive power-supply potential. For reliable

operation, connect a decoupling capacitor ranging from 0.1 μF to 10 μF between VDD

and GND.

VDD

P

S4B

D4

17

18

19

20

14

15

16

17

I/O

I

Source pin 4B. Can be an input or output.

Drain pin 4. Can be input or output

S4A

SEL4

Source pin 4A. Can be an input or output.

Logic control input 4, has internal pull-down resistor. Controls switch 4 (see 节8.5).

The thermal pad is not connected internally. There is no requirement to solder this pad. If

connected, it is recommended to leave the pad floating or tied to GND.

Thermal Pad

—

(1) I = input, O = output, I/O = input and output, P = power.

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(2) Refer to 节8.4 for what to do with unused pins.

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6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)^{(1) (2)}

MIN

MAX

UNIT

V

48

V_DD–V_SS

V_DD

Supply voltage

48

V

–0.5

–48

V_SS

0.5

V

V_SELor V_EN

Logic control input pin voltage (SELx, EN)

Logic control input pin current (SELx, EN)

Source or drain voltage (SxA, SxB, Dx)

Diode clamp current⁽³⁾

48

30

V

–0.5

I_SELor I_EN

mA

V

–30

V_Sor V_D

V_DD+0.5

30

V_SS–0.5

–30

I_IK

mA

°C

mW

I_Sor I_{D (CONT)}

Source or drain continuous current (SxA, SxB, Dx)

Ambient temperature

I_DC± 10 %⁽⁴⁾

150

T_A

–55

–65

T_stg

T_J

Storage temperature

150

Junction temperature

150

P_tot

Total power dissipation (QFN package)⁽⁵⁾

1680

(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under

Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device

reliability.

(2) All voltages are with respect to ground, unless otherwise specified.

(3) Pins are diode-clamped to the power-supply rails. Over voltage signals must be voltage and current limited to maximum ratings.

(4) Refer to Source or Drain Continuous Current table for I_DCspecifications.

(5) For QFN package: P_totderates linearily above T_A= 70°C by 24.8mW/°C.

6.2 ESD Ratings

VALUE

UNIT

Human body model (HBM), per ANSI/ESDA/

JEDEC JS-001, all pins⁽¹⁾

±1000

V_(ESD)

Electrostatic discharge

V

Charged device model (CDM), per ANSI/ESDA/

JEDEC JS-002, all pins⁽²⁾

±500

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Thermal Information

TMUX7234

THERMAL METRIC⁽¹⁾

PW (TSSOP)

20 PINS

74.7

RRQ (WQFN)

20 PINS

40.5

UNIT

R_θJA

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

°C/W

R_θJC(top)

R_θJB

19.9

24.2

32.3

16.4

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

0.7

0.2

Ψ_JT

31.7

16.4

Ψ_JB

R_θJC(bot)

N/A

2.8

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

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6.4 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

4.5

V_SS

0

NOM

MAX

UNIT

V

(1)

Power supply voltage differential

44

V_DD–V_SS

V_DD

Positive power supply voltage

V

V_Sor V_D

V_SELor V_EN

I_Sor I_{D (CONT)}

T_A

Signal path input/output voltage (source or drain pin) (SxA, SxB, Dx)

Address or enable pin voltage

V_DD

V

44

V

(2)

Source or drain continuous current (SxA, SxB, Dx)

Ambient temperature

I_DC

mA

°C

125

–40

(1) V_DDand V_SScan be any value as long as 4.5 V ≤(V_DD–V_SS) ≤44 V, and the minimum V_DDis met.

(2) Refer to Source or Drain Continuous Current table for I_DCspecifications.

6.5 Source or Drain Continuous Current

at supply voltage of V_DD± 10%, V_SS± 10 % (unless otherwise noted)

CONTINUOUS CURRENT PER CHANNEL

T_A= 25°C

T_A= 85°C

230

T_A= 125°C

129

UNIT

PACKAGE

TEST CONDITIONS

+44 V Single Supply⁽¹⁾

350

mA

±15 V Dual Supply

+12 V Single Supply

±5 V Dual Supply

360

260

255

170

400

300

240

235

177

175

129

230

180

150

130

108

105

80

PW (TSSOP)

+5 V Single Supply

+44 V Single Supply⁽¹⁾

±15 V Dual Supply

+12 V Single Supply

±5 V Dual Supply

120

100

85

RRQ (WQFN)

+5 V Single Supply

(1) Specified for nominal supply voltage only.

6

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6.6 ±15 V Dual Supply: Electrical Characteristics

V_DD= +15 V ± 10%, V_SS= –15 V ±10%, GND = 0 V (unless otherwise noted)

Typical at V_DD= +15 V, V_SS= –15 V, T_A= 25℃ (unless otherwise noted)

PARAMETER

TEST CONDITIONS

T_A

MIN

TYP

MAX UNIT

ANALOG SWITCH

25°C

3.6

5.5

7.1

8.4

0.7

0.8

0.9

1.5

1.7

1.9

Ω

V_S= –10 V to +10 V

I_D= –10 mA

Refer to On-Resistance

R_ON

On-resistance

–40°C to +85°C

–40°C to +125°C

25°C

0.2

0.4

V_S= –10 V to +10 V

I_D= –10 mA

Refer to On-Resistance

On-resistance mismatch between

channels

–40°C to +85°C

–40°C to +125°C

25°C

ΔR_ON

V_S= –10 V to +10 V

I_S= –10 mA

Refer to On-Resistance

R_{ON FLAT}On-resistance flatness

R_{ON DRIFT}On-resistance drift

–40°C to +85°C

–40°C to +125°C

V_S= 0 V, I_S= –10 mA

Refer to On-Resistance

0.015

0.01

–40°C to +125°C

Ω/°C

25°C

0.4

1

nA

V_DD= 16.5 V, V_SS= –16.5 V

Switch state is off

V_S= +10 V / –10 V

–0.4

–1

–40°C to +85°C

I_S(OFF)

Source off leakage current⁽¹⁾

V_D= –10 V / + 10 V

Refer to Off-Leakage Current

8

nA

–40°C to +125°C

–8

25°C

0.02

0.5

4

nA

V_DD= 16.5 V, V_SS= –16.5 V

Switch state is off

V_S= +10 V / –10 V

V_D= –10 V / + 10 V

Refer to Off-Leakage Current

–0.5

–4

–40°C to +85°C

I_D(OFF)

Drain off leakage current⁽¹⁾

12

nA

–40°C to +125°C

–12

25°C

0.5

4

nA

–0.5

–4

V_DD= 16.5 V, V_SS= –16.5 V

Switch state is on

V_S= V_D= ±10 V

I_S(ON)

I_D(ON)

Channel on leakage current⁽²⁾

–40°C to +85°C

–40°C to +125°C

Refer to On-Leakage Current

8

–8

LOGIC INPUTS (SEL / EN pins)

V_IH

V_IL

I_IH

Logic voltage high

1.3

0

44

0.8

1.2

V

–40°C to +125°C

Logic voltage low

V

Input leakage current

Logic input capacitance

0.6

µA

pF

I_IL

–0.1 –0.005

C_IN

3

POWER SUPPLY

25°C

45

8

70

80

95

25

30

40

µA

V_DD= 16.5 V, V_SS= –16.5 V

Logic inputs = 0 V, 5 V, or V_DD

I_DD

V_DDsupply current

–40°C to +85°C

–40°C to +125°C

25°C

V_DD= 16.5 V, V_SS= –16.5 V

Logic inputs = 0 V, 5 V, or V_DD

I_SS

V_SSsupply current

–40°C to +85°C

–40°C to +125°C

(1) When V_Sis positive, V_Dis negative. Or when V_Sis negative, V_Dis positive.

(2) When V_Sis at a voltage potential, V_Dis floating. Or when V_Dis at a voltage potential, V_Sis floating.

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MAX UNIT

ZHCSNF7F –FEBRUARY 2021 –REVISED DECEMBER 2022

6.7 ±15 V Dual Supply: Switching Characteristics

V_DD= +15 V ± 10%, V_SS= –15 V ±10%, GND = 0 V (unless otherwise noted)

Typical at V_DD= +15 V, V_SS= –15 V, T_A= 25℃ (unless otherwise noted)

PARAMETER

TEST CONDITIONS

T_A

MIN

TYP

25°C

90

180

190

200

180

190

210

140

150

160

ns

ms

V_S= 10 V

R_L= 300 Ω, C_L= 35 pF

Refer to Transition Time

t_TRAN

Transition time from control input

–40°C to +85°C

–40°C to +125°C

25°C

V_S= 10 V

110

80

R_L= 300 Ω, C_L= 35 pF

Refer to Turn-on and Turn-off

Time

t_ON

Turn-on time from enable

Turn-off time from enable

Break-before-make time delay

–40°C to +85°C

–40°C to +125°C

25°C

(EN)

V_S= 10 V

R_L= 300 Ω, C_L= 35 pF

Refer to Turn-on and Turn-off

Time

t_OFF

–40°C to +85°C

–40°C to +125°C

25°C

(EN)

50

V_S= 10 V,

R_L= 300 Ω, C_L= 35 pF

Refer to Break-Before-Make

1

t_BBM

–40°C to +85°C

–40°C to +125°C

25°C

0.16

V_DDrise time = 1µs

R_L= 300 Ω, C_L= 35 pF

Refer to Turn-on (VDD) Time

Device turn on time

(V_DDto output)

T_{ON (VDD)}

–40°C to +85°C

–40°C to +125°C

R_L= 50 Ω, C_L= 5 pF

Refer to Propagation Delay

t_PD

Propagation delay

Charge injection

25°C

450

3

ps

V_D= 0 V, C_L= 100 pF

Refer to Charge Injection

Q_INJ

pC

R_L= 50 Ω, C_L= 5 pF

V_S= 0 V, f = 100 kHz

Refer to Off Isolation

O_ISO

X_TALK

Off-isolation

Crosstalk

25°C

dB

–82

–62

R_L= 50 Ω, C_L= 5 pF

V_S= 0 V, f = 1 MHz

Refer to Off Isolation

R_L= 50 Ω, C_L= 5 pF

V_S= 0 V, f = 1MHz

Refer to Crosstalk

–105

R_L= 50 Ω, C_L= 5 pF

V_S= 0 V

Refer to Bandwidth

BW

I_L

25°C

100

MHz

dB

–3dB Bandwidth

R_L= 50 Ω, C_L= 5 pF

V_S= 0 V, f = 1 MHz

Insertion loss

–0.3

V_PP= 0.62 V on V_DDand V_SS

R_L= 10 MΩ, C_L= 5 pF,

f = 1 MHz

ACPSRR AC Power Supply Rejection Ratio

25°C

dB

%

–48

Refer to ACPSRR

V_PP= 15 V, V_BIAS= 0 V

R_L= 10 kΩ, C_L= 5 pF,

f = 20 Hz to 20 kHz

THD+N

Total Harmonic Distortion + Noise

0.0004

Refer to THD + Noise

C_S(OFF)

C_D(OFF)

Source off capacitance

Drain off capacitance

V_S= 0 V, f = 1 MHz

25°C

16

28

pF

C_S(ON),

C_D(ON)

On capacitance

V_S= 0 V, f = 1 MHz

25°C

77

pF

8

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6.8 ±20 V Dual Supply: Electrical Characteristics

V_DD= +20 V ± 10%, V_SS= –20 V ±10%, GND = 0 V (unless otherwise noted)

Typical at V_DD= +20 V, V_SS= –20 V, T_A= 25℃ (unless otherwise noted)

PARAMETER

TEST CONDITIONS

T_A

MIN

TYP

MAX UNIT

ANALOG SWITCH

25°C

3.2

5.4

6.7

7.9

0.7

0.8

0.9

1.5

1.7

1.9

Ω

V_S= –15 V to +15 V

I_D= –10 mA

Refer to On-Resistance

R_ON

On-resistance

–40°C to +85°C

–40°C to +125°C

25°C

0.2

0.6

V_S= –15 V to +15 V

I_D= –10 mA

Refer to On-Resistance

On-resistance mismatch between

channels

–40°C to +85°C

–40°C to +125°C

25°C

ΔR_ON

V_S= –15 V to +15 V

I_S= –10 mA

Refer to On-Resistance

R_{ON FLAT}On-resistance flatness

R_{ON DRIFT}On-resistance drift

–40°C to +85°C

–40°C to +125°C

V_S= 0 V, I_S= –10 mA

Refer to On-Resistance

0.014

0.02

–40°C to +125°C

Ω/°C

25°C

1

2

nA

V_DD= 22 V, V_SS= –22 V

Switch state is off

V_S= +15 V / –15 V

–1

–2

–40°C to +85°C

I_S(OFF)

Source off leakage current⁽¹⁾

V_D= –15 V / + 15 V

Refer to Off-Leakage Current

12

nA

–40°C to +125°C

–12

25°C

0.04

1

4

nA

V_DD= 22 V, V_SS= –22 V

Switch state is off

V_S= +15 V / –15 V

V_D= –15 V / + 15 V

Refer to Off-Leakage Current

–1

–4

–40°C to +85°C

I_D(OFF)

Drain off leakage current⁽¹⁾

30

nA

–40°C to +125°C

–30

25°C

1

4

nA

–1

–4

V_DD= 22 V, V_SS= –22 V

Switch state is on

V_S= V_D= ±15 V

I_S(ON)

I_D(ON)

Channel on leakage current⁽²⁾

–40°C to +85°C

–40°C to +125°C

Refer to On-Leakage Current

30

–30

LOGIC INPUTS (SEL / EN pins)

V_IH

V_IL

I_IH

Logic voltage high

1.3

0

44

0.8

1.2

V

–40°C to +125°C

Logic voltage low

V

Input leakage current

Logic input capacitance

0.6

µA

pF

I_IL

–0.1 –0.005

C_IN

3

POWER SUPPLY

25°C

50

10

80

95

µA

V_DD= 22 V, V_SS= –22 V

Logic inputs = 0 V, 5 V, or V_DD

I_DD

V_DDsupply current

–40°C to +85°C

–40°C to +125°C

25°C

110

30

V_DD= 22 V, V_SS= –22 V

Logic inputs = 0 V, 5 V, or V_DD

35

I_SS

V_SSsupply current

–40°C to +85°C

–40°C to +125°C

45

(1) When V_Sis positive, V_Dis negative. Or when V_Sis negative, V_Dis positive.

(2) When V_Sis at a voltage potential, V_Dis floating. Or when V_Dis at a voltage potential, V_Sis floating.

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MAX UNIT

ZHCSNF7F –FEBRUARY 2021 –REVISED DECEMBER 2022

6.9 ±20 V Dual Supply: Switching Characteristics

V_DD= +20 V ± 10%, V_SS= –20 V ±10%, GND = 0 V (unless otherwise noted)

Typical at V_DD= +20 V, V_SS= –20 V, T_A= 25℃ (unless otherwise noted)

PARAMETER

TEST CONDITIONS

T_A

MIN

TYP

25°C

90

190

200

210

190

200

210

140

150

160

ns

ms

V_S= 10 V

R_L= 300 Ω, C_L= 35 pF

Refer to Transition Time

t_TRAN

Transition time from control input

–40°C to +85°C

–40°C to +125°C

25°C

V_S= 10 V

110

75

R_L= 300 Ω, C_L= 35 pF

Refer to Turn-on and Turn-off

Time

t_ON

Turn-on time from enable

Turn-off time from enable

Break-before-make time delay

–40°C to +85°C

–40°C to +125°C

25°C

(EN)

V_S= 10 V

R_L= 300 Ω, C_L= 35 pF

Refer to Turn-on and Turn-off

Time

t_OFF

–40°C to +85°C

–40°C to +125°C

25°C

(EN)

50

V_S= 10 V,

R_L= 300 Ω, C_L= 35 pF

Refer to Break-Before-Make

1

t_BBM

–40°C to +85°C

–40°C to +125°C

25°C

V_DDrise time = 1µs

R_L= 300 Ω, C_L= 35 pF

Refer to Turn-on and Turn-

offTime

0.16

Device turn on time

(V_DDto output)

T_{ON (VDD)}

–40°C to +85°C

–40°C to +125°C

R_L= 50 Ω, C_L= 5 pF

Refer to Propagation Delay

t_PD

Propagation delay

Charge injection

25°C

470

3

ps

V_D= 0 V, C_L= 100 pF

Refer to Charge Injection

Q_INJ

pC

R_L= 50 Ω, C_L= 5 pF

V_S= 0 V, f = 100 kHz

Refer to Off Isolation

O_ISO

X_TALK

Off-isolation

Crosstalk

25°C

dB

–82

–62

R_L= 50 Ω, C_L= 5 pF

V_S= 0 V, f = 1 MHz

Refer to Off Isolation

R_L= 50 Ω, C_L= 5 pF

V_S= 0 V, f = 1MHz

Refer to Crosstalk

–105

R_L= 50 Ω, C_L= 5 pF

V_S= 0 V

Refer to Bandwidth

BW

I_L

25°C

95

MHz

dB

–3dB Bandwidth

R_L= 50 Ω, C_L= 5 pF

V_S= 0 V, f = 1 MHz

Insertion loss

–0.25

V_PP= 0.62 V on V_DDand V_SS

R_L= 10 MΩ, C_L= 5 pF,

f = 1 MHz

ACPSRR AC Power Supply Rejection Ratio

25°C

dB

%

–48

Refer to ACPSRR

V_PP= 20 V, V_BIAS= 0 V

R_L= 10 kΩ, C_L= 5 pF,

f = 20 Hz to 20 kHz

THD+N

Total Harmonic Distortion + Noise

0.002

Refer to THD + Noise

C_S(OFF)

C_D(OFF)

Source off capacitance

Drain off capacitance

V_S= 0 V, f = 1 MHz

25°C

16

26

pF

C_S(ON),

C_D(ON)

On capacitance

V_S= 0 V, f = 1 MHz

25°C

77

pF

10

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ZHCSNF7F –FEBRUARY 2021 –REVISED DECEMBER 2022

6.10 44 V Single Supply: Electrical Characteristics

V_DD= +44 V, V_SS= 0 V, GND = 0 V (unless otherwise noted)

Typical at V_DD= +44 V, V_SS= 0 V, T_A= 25℃ (unless otherwise noted)

PARAMETER

TEST CONDITIONS

T_A

MIN

TYP

MAX UNIT

ANALOG SWITCH

25°C

3

5.8

7.2

8.9

0.7

0.8

0.9

2

Ω

V_S= 0 V to 40 V

I_D= –10 mA

Refer to On-Resistance

R_ON

On-resistance

–40°C to +85°C

–40°C to +125°C

25°C

0.2

1.5

V_S= 0 V to 40 V

I_D= –10 mA

Refer to On-Resistance

On-resistance mismatch between

channels

–40°C to +85°C

–40°C to +125°C

25°C

ΔR_ON

V_S= 0 V to 40 V

I_D= –10 mA

Refer to On-Resistance

2.5

3.3

R_{ON FLAT}On-resistance flatness

R_{ON DRIFT}On-resistance drift

–40°C to +85°C

–40°C to +125°C

V_S= 22 V, I_S= –10 mA

Refer to On-Resistance

0.012

0.02

–40°C to +125°C

Ω/°C

V_DD= 44 V, V_SS= 0 V

Switch state is off

V_S= 40 V / 1 V

25°C

1

4

nA

–1

–4

–40°C to +85°C

I_S(OFF)

Source off leakage current⁽¹⁾

V_D= 1 V / 40 V

Refer to Off-Leakage Current

20

nA

–40°C to +125°C

–20

V_DD= 44 V, V_SS= 0 V

Switch state is off

V_S= 40 V / 1 V

V_D= 1 V / 40 V

Refer to Off-Leakage Current

25°C

0.04

1

8

nA

–1

–8

–40°C to +85°C

I_D(OFF)

Drain off leakage current⁽¹⁾

40

nA

–40°C to +125°C

–40

25°C

1

8

nA

V_DD= 44 V, V_SS= 0 V

Switch state is on

V_S= V_D= 40 V or 1 V

Refer to On-Leakage Current

–1

–8

I_S(ON)

I_D(ON)

Channel on leakage current⁽²⁾

–40°C to +85°C

–40°C to +125°C

40

–40

LOGIC INPUTS (SEL / EN pins)

V_IH

V_IL

I_IH

Logic voltage high

1.3

0

44

0.8

1.2

V

–40°C to +125°C

Logic voltage low

V

Input leakage current

Logic input capacitance

0.6

µA

pF

I_IL

–0.1 –0.005

C_IN

3

POWER SUPPLY

25°C

70

110

118

140

µA

V_DD= 44 V, V_SS= 0 V

Logic inputs = 0 V, 5 V, or V_DD

I_DD

V_DDsupply current

–40°C to +85°C

–40°C to +125°C

(1) When V_Sis 40 V, V_Dis 1 V. Or when V_Sis 1 V, V_Dis 40 V.

(2) When V_Sis at a voltage potential, V_Dis floating. Or when V_Dis at a voltage potential, V_Sis floating.

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MAX UNIT

ZHCSNF7F –FEBRUARY 2021 –REVISED DECEMBER 2022

6.11 44 V Single Supply: Switching Characteristics

V_DD= +44 V, V_SS= 0 V, GND = 0 V (unless otherwise noted)

Typical at V_DD= +44 V, V_SS= 0 V, T_A= 25℃ (unless otherwise noted)

PARAMETER

TEST CONDITIONS

T_A

MIN

TYP

25°C

90

200

220

240

200

220

240

180

200

220

ns

ms

V_S= 18 V

R_L= 300 Ω, C_L= 35 pF

Refer to Transition Time

t_TRAN

Transition time from control input

–40°C to +85°C

–40°C to +125°C

25°C

V_S= 18 V

100

90

R_L= 300 Ω, C_L= 35 pF

Refer to Turn-on and Turn-off

Time

t_ON

Turn-on time from enable

Turn-off time from enable

Break-before-make time delay

–40°C to +85°C

–40°C to +125°C

25°C

(EN)

V_S= 18 V

R_L= 300 Ω, C_L= 35 pF

Refer to Turn-on and Turn-off

Time

t_OFF

–40°C to +85°C

–40°C to +125°C

25°C

(EN)

45

V_S= 18 V,

R_L= 300 Ω, C_L= 35 pF

Refer to Break-Before-Make

1

t_BBM

–40°C to +85°C

–40°C to +125°C

25°C

0.13

V_DDrise time = 1µs

R_L= 300 Ω, C_L= 35 pF

Refer to Turn-on (VDD) Time

Device turn on time

(V_DDto output)

T_{ON (VDD)}

–40°C to +85°C

–40°C to +125°C

R_L= 50 Ω, C_L= 5 pF

Refer to Propagation Delay

t_PD

Propagation delay

Charge injection

25°C

570

3

ps

V_D= 22 V, C_L= 100 pF

Refer to Charge Injection

Q_INJ

pC

R_L= 50 Ω, C_L= 5 pF

V_S= 6 V, f = 100 kHz

Refer to Off Isolation

O_ISO

X_TALK

Off-isolation

Crosstalk

25°C

dB

–82

–62

R_L= 50 Ω, C_L= 5 pF

V_S= 6 V, f = 1 MHz

Refer to Off Isolation

R_L= 50 Ω, C_L= 5 pF

V_S= 6 V, f = 1MHz

Refer to Crosstalk

–105

R_L= 50 Ω, C_L= 5 pF

V_S= 6 V

Refer to Bandwidth

BW

I_L

25°C

92

MHz

dB

–3dB Bandwidth

R_L= 50 Ω, C_L= 5 pF

V_S= 6 V, f = 1 MHz

Insertion loss

–0.3

V_PP= 0.62 V on V_DDand V_SS

R_L= 10 MΩ, C_L= 5 pF,

f = 1 MHz

ACPSRR AC Power Supply Rejection Ratio

25°C

dB

–45

Refer to ACPSRR

C_S(OFF)

C_D(OFF)

Source off capacitance

Drain off capacitance

V_S= 22 V, f = 1 MHz

25°C

16

28

pF

C_S(ON),

C_D(ON)

On capacitance

V_S= 22 V, f = 1 MHz

25°C

77

pF

12

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ZHCSNF7F –FEBRUARY 2021 –REVISED DECEMBER 2022

6.12 12 V Single Supply: Electrical Characteristics

V_DD= +12 V ± 10%, V_SS= 0 V, GND = 0 V (unless otherwise noted)

Typical at V_DD= +12 V, V_SS= 0 V, T_A= 25℃ (unless otherwise noted)

PARAMETER

TEST CONDITIONS

T_A

MIN

TYP

MAX UNIT

ANALOG SWITCH

25°C

6.2

12

15

Ω

V_S= 0 V to 10 V

I_D= –10 mA

Refer to On-Resistance

R_ON

On-resistance

–40°C to +85°C

–40°C to +125°C

25°C

18

0.2

2.4

0.7

0.8

0.9

3.6

3.9

4.8

V_S= 0 V to 10 V

I_D= –10 mA

Refer to On-Resistance

On-resistance mismatch between

channels

–40°C to +85°C

–40°C to +125°C

25°C

ΔR_ON

V_S= 0 V to 10 V

I_S= –10 mA

Refer to On-Resistance

R_{ON FLAT}On-resistance flatness

R_{ON DRIFT}On-resistance drift

–40°C to +85°C

–40°C to +125°C

V_S= 6 V, I_S= –10 mA

Refer to On-Resistance

0.025

0.01

–40°C to +125°C

Ω/°C

V_DD= 13.2 V, V_SS= 0 V

Switch state is off

V_S= 10 V / 1 V

25°C

0.4

1

nA

–0.4

–1

–40°C to +85°C

I_S(OFF)

Source off leakage current⁽¹⁾

V_D= 1 V / 10 V

Refer to Off-Leakage Current

8

nA

–40°C to +125°C

–8

V_DD= 13.2 V, V_SS= 0 V

Switch state is off

V_S= 10 V / 1 V

V_D= 1 V / 10 V

Refer to Off-Leakage Current

25°C

0.02

0.5

4

nA

–0.5

–4

–40°C to +85°C

I_D(OFF)

Drain off leakage current⁽¹⁾

12

nA

–40°C to +125°C

–12

25°C

0.5

4

nA

V_DD= 13.2 V, V_SS= 0 V

Switch state is on

V_S= V_D= 10 V or 1 V

Refer to On-Leakage Current

–0.5

–4

I_S(ON)

I_D(ON)

Channel on leakage current⁽²⁾

–40°C to +85°C

–40°C to +125°C

8

–8

LOGIC INPUTS (SEL / EN pins)

V_IH

V_IL

I_IH

Logic voltage high

1.3

0

44

0.8

1.2

V

–40°C to +125°C

Logic voltage low

V

Input leakage current

Logic input capacitance

0.6

µA

pF

I_IL

–0.1 –0.005

C_IN

3

POWER SUPPLY

25°C

36

55

65

75

µA

V_DD= 13.2 V, V_SS= 0 V

Logic inputs = 0 V, 5 V, or V_DD

I_DD

V_DDsupply current

–40°C to +85°C

–40°C to +125°C

(1) When V_Sis 10 V, V_Dis 1 V. Or when V_Sis 1 V, V_Dis 10 V.

(2) When V_Sis at a voltage potential, V_Dis floating. Or when V_Dis at a voltage potential, V_Sis floating.

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MAX UNIT

ZHCSNF7F –FEBRUARY 2021 –REVISED DECEMBER 2022

6.13 12 V Single Supply: Switching Characteristics

V_DD= +12 V ± 10%, V_SS= 0 V, GND = 0 V (unless otherwise noted)

Typical at V_DD= +12 V, V_SS= 0 V, T_A= 25℃ (unless otherwise noted)

PARAMETER

TEST CONDITIONS

T_A

MIN

TYP

25°C

105

200

220

250

200

220

250

190

210

240

ns

ms

V_S= 8 V

R_L= 300 Ω, C_L= 35 pF

Refer to Transition Time

t_TRAN

Transition time from control input

–40°C to +85°C

–40°C to +125°C

25°C

V_S= 8 V

110

105

60

R_L= 300 Ω, C_L= 35 pF

Refer to Turn-on and Turn-off

Time

t_ON

Turn-on time from enable

Turn-off time from enable

Break-before-make time delay

–40°C to +85°C

–40°C to +125°C

25°C

(EN)

V_S= 8 V

R_L= 300 Ω, C_L= 35 pF

Refer to Turn-on and Turn-off

Time

t_OFF

–40°C to +85°C

–40°C to +125°C

25°C

(EN)

V_S= 8 V,

R_L= 300 Ω, C_L= 35 pF

Refer to Break-Before-Make

1

t_BBM

–40°C to +85°C

–40°C to +125°C

25°C

0.16

V_DDrise time = 1µs

R_L= 300 Ω, C_L= 35 pF

Refer to Turn-on (VDD) Time

Device turn on time

(V_DDto output)

T_{ON (VDD)}

–40°C to +85°C

–40°C to +125°C

R_L= 50 Ω, C_L= 5 pF

Refer to Propagation Delay

t_PD

Propagation delay

Charge injection

Off-isolation

25°C

490

1

ps

pC

dB

V_D= 6 V, C_L= 100 pF

Refer to Charge Injection

Q_INJ

O_ISO

R_L= 50 Ω, C_L= 5 pF

V_S= 6 V, f = 100 kHz

–82

R_L= 50 Ω, C_L= 5 pF

V_S= 6 V, f = 1 MHz

Refer to Off Isolation

O_ISO

Off-isolation

Crosstalk

25°C

dB

–62

R_L= 50 Ω, C_L= 5 pF

V_S= 6 V, f = 1MHz

Refer to Crosstalk

X_TALK

–105

R_L= 50 Ω, C_L= 5 pF

V_S= 6 V

Refer to Bandwidth

BW

I_L

25°C

130

MHz

dB

–3dB Bandwidth

R_L= 50 Ω, C_L= 5 pF

V_S= 6 V, f = 1 MHz

Insertion loss

–0.5

V_PP= 0.62 V on V_DDand V_SS

R_L= 10 MΩ, C_L= 5 pF,

f = 1 MHz

ACPSRR AC Power Supply Rejection Ratio

25°C

dB

%

–50

Refer to ACPSRR

V_PP= 6 V, V_BIAS= 6 V

R_L= 10 kΩ, C_L= 5 pF,

f = 20 Hz to 20 kHz

THD+N

Total Harmonic Distortion + Noise

0.0016

Refer to THD + Noise

C_S(OFF)

C_D(OFF)

Source off capacitance

Drain off capacitance

V_S= 6 V, f = 1 MHz

25°C

19

33

pF

C_S(ON),

C_D(ON)

On capacitance

V_S= 6 V, f = 1 MHz

25°C

78

pF

14

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6.14 Typical Characteristics

at T_A= 25°C (unless otherwise noted)

.

图6-1. On-Resistance vs Source or Drain Voltage –Dual

图6-2. On-Resistance vs Source or Drain Voltage –Dual

Supply

.

图6-3. On-Resistance vs Source or Drain Voltage –Single

图6-4. On-Resistance vs Source or Drain Voltage –Single

Supply

V_DD= 15 V, V_SS= -15 V

V_DD= 20 V, V_SS= -20 V

图6-5. On-Resistance vs Temperature

图6-6. On-Resistance vs Temperature

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ZHCSNF7F –FEBRUARY 2021 –REVISED DECEMBER 2022

6.14 Typical Characteristics (continued)

at T_A= 25°C (unless otherwise noted)

V_DD= 12 V, V_SS= 0 V

V_DD= 20 V, V_SS= -20 V

图6-7. On-Resistance vs Temperature

图6-8. Leakage Current vs Temperature

V_DD= 15 V, V_SS= -15 V

V_DD= 12 V, V_SS= 0 V

图6-9. Leakage Current vs Temperature

图6-10. Leakage Current vs Temperature

80

60

40

20

0

V_DD= 20 V, V_SS= −20 V

V_DD= 15 V, V_SS= −15 V

V_DD= 5 V, V_SS= −5 V

-20

-40

-20

-15

-10

-5

0

5

10

15

20

Drain Voltage (V)

.

图6-12. Charge Injection vs Drain Voltage –Dual Supply

.

图6-11. Supply Current vs Logic Voltage

16

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ZHCSNF7F –FEBRUARY 2021 –REVISED DECEMBER 2022

6.14 Typical Characteristics (continued)

at T_A= 25°C (unless otherwise noted)

80

110

100

90

80

70

60

50

40

30

V_DD= 20 V, V_SS= −20 V

V_DD= 15 V, V_SS= −15 V

V_DD= 5 V, V_SS= −5 V

V_DD= 36 V, V_SS= 0 V

V_DD= 20 V, V_SS= 0 V

V_DD= 15 V, V_SS= 0 V

V_DD= 12 V, V_SS= 0 V

V_DD= 5 V, V_SS= 0 V

60

40

20

0

20

10

0

-10

-20

-30

-40

-50

-20

-40

0

4

8

12 16 20 24 28 32 36 40 44

Drain Voltage (V)

-20

-15

-10

-5

0

5

10

15

20

Source Voltage (V)

.

图6-14. Charge Injection vs Drain Voltage –Single Supply

图6-13. Charge Injection vs Source Voltage –Dual Supply

110

V_DD= 44 V, V_SS= 0 V

V_DD= 20 V, V_SS= 0 V

V_DD= 15 V, V_SS= 0 V

V_DD= 12 V, V_SS= 0 V

V_DD= 5 V, V_SS= 0 V

100

90

80

70

60

50

40

30

20

10

0

-10

-20

-30

-40

-50

0

4

8

12 16 20 24 28 32 36 40 44

Source Voltage (V)

.

图6-15. Charge Injection vs Source Voltage –Single Supply

.

图6-16. T_TRANSITIONvs Temperature

.

V_DD= 15 V, V_SS= -15 V

图6-17. T_TRANSITIONvs Temperature

图6-18. T_ONand T_OFFvs Temperature

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6.14 Typical Characteristics (continued)

at T_A= 25°C (unless otherwise noted)

V_DD= 44 V, V_SS= 0 V

V_DD= 15 V, V_SS= -15 V, T_A= 25°C .

图6-19. T_ONand T_OFFvs Temperature

图6-20. Off-Isolation vs Frequency

0.005

0.004

V_DD= 5 V, V_SS= −5 V

V_DD= 15 V, V_SS= −15 V

0.003

0.002

0.001

0.0007

0.0005

0.0004

0.0003

0.0002

10

100

Frequency (Hz)

1k

.

V_DD= 15 V, V_SS= -15 V .

图6-22. THD+N vs Frequency (Dual Supply)

图6-21. Crosstalk vs Frequency

.

V_DD= 15 V, V_SS= -15 V .

图6-23. THD+N vs Frequency (Single Supply)

图6-24. On Response vs Frequency

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6.14 Typical Characteristics (continued)

at T_A= 25°C (unless otherwise noted)

V_DD= +15 V, V_SS= -15 V

图6-25. ACPSRR vs Frequency

图6-26. Capacitance vs Source Voltage or Drain Voltage

V_DD= 12 V, V_SS= 0 V

图6-27. Capacitance vs Source Voltage or Drain Voltage

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7 Parameter Measurement Information

7.1 On-Resistance

The on-resistance of a device is the ohmic resistance between the source (Sx) and drain (D) pins of the device.

The on-resistance varies with input voltage and supply voltage. The symbol R_ONis used to denote on-

resistance. 图 7-1 shows the measurement setup used to measure R_ON. Voltage (V) and current (I_SD) are

measured using this setup, and R_ONis computed with R_ON= V / I_SD

.

V

I_SD

Sx

Dx

V_S

图7-1. On-Resistance Measurement Setup

7.2 Off-Leakage Current

There are two types of leakage currents associated with a switch during the off state:

• Source off-leakage current

• Drain off-leakage current

Source leakage current is defined as the leakage current flowing into or out of the source pin when the switch is

off. This current is denoted by the symbol I_S(OFF)

Drain leakage current is defined as the leakage current flowing into or out of the drain pin when the switch is off.

This current is denoted by the symbol I_D(OFF)

图7-2 shows the setup used to measure both off-leakage currents.

.

V_DD

V_SS

V_DD

V_SS

I_{s (OFF)}

I_{D (OFF)}

S1A

S1B

S1A

S1B

A

D1

A

V_S

V_D

V_S

V_D

I_{s (OFF)}

I_{D (OFF)}

S4A

S4B

S4A

S4B

D4

A

D4

V_S

GND

V_D

I_S(OFF)

I_D(OFF)

图7-2. Off-Leakage Measurement Setup

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7.3 On-Leakage Current

Source on-leakage current is defined as the leakage current flowing into or out of the source pin when the switch

is on. This current is denoted by the symbol I_S(ON)

.

Drain on-leakage current is defined as the leakage current flowing into or out of the drain pin when the switch is

on. This current is denoted by the symbol I_D(ON)

.

Either the source pin or drain pin is left floating during the measurement. 图 7-3 shows the circuit used for

measuring the on-leakage current, denoted by I_S(ON)or I_D(ON)

.

V_DD

V_SS

V_DD

V_SS

I_{s (ON)}

A

I_{D (ON)}

S1A

S1B

S1A

S1B

N.C.

D1

A

N.C.

V_S

N.C.

V_D

I_{s (ON)}

A

S4A

S4B

S4A

S4B

N.C.

D4

N.C.

A

V_S

N.C.

V_D

GND

I_S(ON)

图7-3. On-Leakage Measurement Setup

I_D(ON)

7.4 Transition Time

Transition time is defined as the time taken by the output of the device to rise or fall 90% after the address signal

has risen or fallen past the logic threshold. The 90% transition measurement is utilized to provide the timing of

the device. System level timing can then account for the time constant added from the load resistance and load

capacitance. 图7-4 shows the setup used to measure transition time, denoted by the symbol t_TRANSITION

.

V_DD

V_SS

0.1 µF

V_S

3 V

0 V

V_DD

S1A

V_SS

V_SEL

t_r< 20 ns

t_f< 20 ns

50%

D1

Output

C_L

S1B

t_TRANSITION

R_L

90%

Output

0 V

S4A

S4B

V_S

D4

Output

C_L

10%

R_L

SELx

GND

V_SEL

图7-4. Transition-Time Measurement Setup

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7.5 t_ON(EN)and t_OFF(EN)

Turn-on time is defined as the time taken by the output of the device to rise to 90% after the enable has risen

past the logic threshold. The 90% measurement is utilized to provide the timing of the device. System level

timing can then account for the time constant added from the load resistance and load capacitance. 图 7-7

shows the setup used to measure turn-on time, denoted by the symbol t_ON(EN)

.

Turn-off time is defined as the time taken by the output of the device to fall to 10% after the enable has fallen

past the logic threshold. The 10% measurement is utilized to provide the timing of the device. System level

timing can then account for the time constant added from the load resistance and load capacitance. 图 7-7

shows the setup used to measure turn-off time, denoted by the symbol t_OFF(EN)

.

V_DD

V_SS

0.1 µF

3 V

V_DD

V_SS

V_EN

t_r< 20 ns

t_f< 20 ns

50%

S1A

S1B

0 V

V_S

D1

D4

Output

C_L

t_ON

t_OFF

R_L

90%

Output

0 V

S4A

S4B

V_S

Output

C_L

10%

R_L

EN

GND

V_EN

图7-5. Turn-On and Turn-Off Time Measurement Setup

7.6 Break-Before-Make

Break-before-make delay is a safety feature that prevents two inputs from connecting when the device is

switching. The output first breaks from the on-state switch before making the connection with the next on-state

switch. The time delay between the break and the make is known as break-before-make delay. 图7-6 shows the

setup used to measure break-before-make delay, denoted by the symbol t_OPEN(BBM)

.

V_DD

V_SS

0.1 µF

3 V

V_DD

V_SS

V_SEL

t_r< 20ns

t_f< 20ns

S1A

S1B

V_S

0 V

D1

D4

Output

C_L

R_L

80%

Output

0 V

S4A

S4B

V_S

t_BBM

1

t_BBM2

Output

C_L

R_L

t_{OPEN (BBM)}= min ( t_BBM1, t_BBM2)

SELx

GND

V_SEL

图7-6. Break-Before-Make Delay Measurement Setup

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7.7 t_{ON (VDD)}Time

The t_{ON (VDD)}time is defined as the time taken by the output of the device to rise to 90% after the supply has

risen past the supply threshold. The 90% measurement is used to provide the timing of the device turning on in

the system. 图7-7 shows the setup used to measure turn on time, denoted by the symbol t_{ON (VDD)}

.

V_SS

0.1 µF

V_DD

Supply

V_DD

S1A

V_SS

t_r= 10 µs

4.5 V

Ramp

V_S

0 V

Output

D1

D4

S1B

t_ON

R_L

C_L

90%

Output

0 V

V_S

S4A

S4B

Output

C_L

R_L

EN

3 V

SELx

GND

图7-7. t_{ON (VDD)}Time Measurement Setup

7.8 Propagation Delay

Propagation delay is defined as the time taken by the output of the device to rise or fall 50% after the input signal

has risen or fallen past the 50% threshold. 图 7-8 shows the setup used to measure propagation delay, denoted

by the symbol t_PD

.

V_DD

V_SS

250 mV

0 V

0.1 µF

V_DD

S1A

V_SS

Input

(V_S)

50%

t_r< 40ps

t_f< 40ps

50

V_S

D1

Output

C_L

t_PD

1

t_{PD 2}

S1B

R_L

Output

0 V

50%

50

S4A

S4B

V_S

D4

Output

C_L

t_{Prop Delay}= max ( t_PD1, t_PD2)

R_L

GND

图7-8. Propagation Delay Measurement Setup

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7.9 Charge Injection

The TMUX7234 has a transmission-gate topology. Any mismatch in capacitance between the NMOS and PMOS

transistors results in a charge injected into the drain or source during the falling or rising edge of the gate signal.

The amount of charge injected into the source or drain of the device is known as charge injection, and is

denoted by the symbol Q_INJ. 图 7-9 shows the setup used to measure charge injection from source (Sx) to drain

(D).

V_DD

V_SS

0.1 µF

3 V

V_EN

V_DD

V_SS

S1A

t_r< 20 ns

t_f< 20 ns

Output

D1

D4

V_D

0 V

C_L

S1B

Output

C_L

Output

V_S

V_OUT

Q_INJ= C_L

×

V_OUT

S4A

S4B

Output

V_D

C_L

EN

V_EN

GND

图7-9. Charge-Injection Measurement Setup

7.10 Off Isolation

Off isolation is defined as the ratio of the signal at the drain pin (D) of the device when a signal is applied to the

source pin (Sx) of an off-channel. 图 7-10 shows the setup used to measure, and the equation used to calculate

off isolation.

V_DD

V_SS

0.1 µF

V_DD

V_SS

Network Analyzer

V_S

S

D

50

V_OUT

V_SIG

50

SxA / SxB / Dx

GND

50

图7-10. Off Isolation Measurement Setup

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7.11 Crosstalk

Crosstalk is defined as the ratio of the signal at the drain pin (D) of a different channel, when a signal is applied

at the source pin (Sx) of an on-channel. 图 7-11 shows the setup used to measure and the equation used to

calculate crosstalk.

V_DD

V_SS

0.1 µF

V_DD

V_SS

Network Analyzer

V_S

S1A

S4A

D

50

V_OUT

50

V_SIG

50

SxA / SxB / Dx

GND

50

图7-11. Crosstalk Measurement Setup

7.12 Bandwidth

Bandwidth is defined as the range of frequencies that are attenuated by less than 3 dB when the input is applied

to the source pin (Sx) of an on-channel, and the output is measured at the drain pin (D) of the device. 图 7-12

shows the setup used to measure bandwidth.

V_DD

V_SS

0.1 µF

V_DD

V_SS

Network Analyzer

V_S

S

D

50

V_OUT

V_SIG

50

SxA / SxB / Dx

GND

50

图7-12. Bandwidth Measurement Setup

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7.13 THD + Noise

The total harmonic distortion (THD) of a signal is a measurement of the harmonic distortion, and is defined as

the ratio of the sum of the powers of all harmonic components to the power of the fundamental frequency at the

mux output. The on-resistance of the device varies with the amplitude of the input signal and results in distortion

when the drain pin is connected to a low-impedance load. Total harmonic distortion plus noise is denoted as

THD.

V_DD

V_SS

0.1 µF

V_DD

V_SS

Audio Precision

S

D

40

V_OUT

V_S

R_L

SxA / SxB / Dx

GND

50

图7-13. THD Measurement Setup

7.14 Power Supply Rejection Ratio (PSRR)

PSRR measures the ability of a device to prevent noise and spurious signals that appear on the supply voltage

pin from coupling to the output of the switch. The DC voltage on the device supply is modulated by a sine wave

of 620 mVPP. The ratio of the amplitude of signal on the output to the amplitude of the modulated signal is the

ACPSRR. A high ratio represents a high degree of tolerance to supply rail variation.

图 7-14 shows how the decoupling capacitors reduce high frequency noise on the supply pins. This helps

stabilize the supply and immediately filter as much of the supply noise as possible.

V_DD

Network Analyzer

V_SS

DC Bias

Injector

With & Without

Capacitor

50 Ω

0.1 µF

V_DD

V_SS

620 mV_PP

V_IN

S

V_BIAS

50 Ω

SxA / SxB / Dx

50 Ω

V_OUT

D

R_L

GND

C_L

图7-14. ACPSRR Measurement Setup

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8 Detailed Description

8.1 Overview

The TMUX7234 contains four independently controlled SPDT switches with an EN pin to enable or disable all

four switches.

8.2 Functional Block Diagram

V_DD

V_SS

S1A

S1B

D1

D2

D3

D4

S2A

S2B

S3A

S3B

S4A

S4B

SEL1

SEL2

SEL3

SEL4

Logic Decoder

EN

TMUX7234

8.3 Feature Description

8.3.1 Bidirectional Operation

The TMUX7234 conducts equally well from source (Sx) to drain (Dx) or from drain (Dx) to source (Sx). Each

channel has very similar characteristics in both directions and supports both analog and digital signals.

8.3.2 Rail-to-Rail Operation

The valid signal path input or output voltage for the TMUX7234 ranges from V_SSto V_DD

.

8.3.3 1.8 V Logic Compatible Inputs

The TMUX7234 has 1.8 V logic compatible control for all logic control inputs. 1.8 V logic level inputs allows the

switch to interface with processors that have lower logic I/O rails and eliminates the need for an external

translator, which saves both space and BOM cost. For more information on 1.8 V logic implementations refer to

Simplifying Design with 1.8 V logic Muxes and Switches.

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8.3.4 Fail-Safe Logic

TMUX7234 supports Fail-Safe Logic on the control input pins (EN and SELx) allowing it to operate up to 44 V,

regardless of the state of the supply pins. This feature allows voltages on the control pins to be applied before

the supply pin, protecting the device from potential damage. Fail-Safe Logic minimizes system complexity by

removing the need for power supply sequencing on the logic control pins. For example, the Fail-Safe Logic

feature allows the TMUX7234 logic input pins to ramp up to +44 V while V_DDand V_SS= 0 V. The logic control

inputs are protected against positive faults of up to +44 V in powered-off condition, but do not offer protection

against negative overvoltage conditions.

8.3.5 Latch-Up Immune

Latch-Up is a condition where a low impedance path is created between a supply pin and ground. This condition

is caused by a trigger (current injection or overvoltage), but once activated, the low impedance path remains

even after the trigger is no longer present. This low impedance path may cause system upset or catastrophic

damage due to excessive current levels. The Latch-Up condition typically requires a power cycle to eliminate the

low impedance path.

The TMUX72xx family of devices are constructed on Silicon on Insulator (SOI) based process where an oxide

layer is added between the PMOS and NMOS transistor of each CMOS switch to prevent parasitic structures

from forming. The oxide layer is also known as an insulating trench and prevents triggering of latch up events

due to overvoltage or current injections. The latch-up immunity feature allows the TMUX72xx family of switches

and multiplexers to be used in harsh environments. For more information on latch-up immunity refer to Using

Latch Up Immune Multiplexers to Help Improve System Reliability.

8.3.6 Ultra-Low Charge Injection

The TMUX7234 has a transmission gate topology, as shown in 图 8-1. Any mismatch in the stray capacitance

associated with the NMOS and PMOS causes an output level change whenever the switch is opened or closed.

OFF ON

C_GDN

C_GSN

D

S

C_GSP

C_GDP

OFF ON

图8-1. Transmission Gate Topology

The TMUX7234 contains specialized architecture to reduce charge injection on the source (Sx). To further

reduce charge injection in a sensitive application, a compensation capacitor (Cp) can be added on the drain (D).

This will ensure that excess charge from the switch transition will be pushed into the compensation capacitor on

the drain (D) instead of the source (Sx). As a general rule of thumb, Cp should be 20x larger than the equivalent

load capacitance on the source (Sx). 图 8-2 shows charge injection variation with different compensation

capacitors on the drain side. This plot was captured on the TMUX7219 as part of the TMUX72xx family with a

100pF load capacitance.

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图8-2. Charge Injection Compensation

8.4 Device Functional Modes

The enable EN pin is an active-low logic pin that controls the connection between the source (SxA and SxB) and

drain (Dx) pins of the device. The TMUX7234 SELx logic control inputs determine which source pin is connected

to the drain pin for each channel. When the EN pin of the TMUX7234 is pulled low, the SELx logic control inputs

determine which source input is selected. When the EN pin is pulled high, all of the switches are in an open state

regardless of the state of the SELx logic control inputs. The control pins can be as high as 44 V.

The TMUX7234 can be operated without any external components except for the supply decoupling capacitors.

The EN and SELx pins have internal pull-down resistors of 4 MΩ. If unused, EN and SELx pins should be tied to

GND in order to ensure the device does not consume additional current as highlighted in Implications of Slow or

Floating CMOS Inputs. Unused signal path inputs (Sx or Dx) should be connected to GND.

8.5 Truth Tables

表8-1 shows the truth tables for the TMUX7234.

表8-1. TMUX7234 Truth Table

Selected Source Pins Connected to

EN

SEL1

SEL2

SEL3

SEL4

Drain Pins

S1B to D1

S1A to D1

S2B to D2

S2A to D2

S3B to D3

S3A to D3

S4B to D4

S4A to D4

Hi-Z (OFF)

0

1

0

1

X⁽¹⁾

X

0

X

0

X

0

1

X

1

X

1

X

(1) X means do not care.

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9 Application and Implementation

备注

以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客户应负责确定

器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。

9.1 Application Information

The TMUX7234 is part of the precision switches and multiplexers family of devices. This device operates with

dual supplies (±4.5 V to ±22 V), a single supply (4.5 V and 44 V), or asymmetric supplies (such as, V_DD= 12 V

and V_SS= −5 V), and offers rail-to-rail input and output. The TMUX7234 offers low R_ON, low on and off leakage

currents and ultra-low charge injection performance. These features makes the TMUX7234 a precision, robust,

high-performance analog multiplexer for high-voltage, industrial applications.

9.2 Typical Application

One key application of the TMUX7234 is in the ultrasonic water flow measurement system. Ultrasonic flow

meters use time of flight (ToF) of an ultrasonic wave and its dependency and behavior in the medium using two

transducer pairs for upstream and downstream paths. The signal waveforms are transmitted between two

adjacent transducers. One transducer transmits an upstream path signal and the other transducer receives a

downstream signal path. The flight time for the signal can be calculated using the known velocity of sound and

length between the transducers. The upstream and downstream waveforms are processed on the main MCU to

obtain the volume. 图9-1 shows a circuit example utilizing the MSP430FR66047 MCU, high voltage low

distortion operational amplifiers (THS3091), along with TMUX7234, 2:1, 4 channel precision switches. The

TMUX7234 is used to select the Rx and Tx path of the transducer. The TMUX7234 offers low on-state

resistance, flat capacitance performance, and low propagation delay which leads to very low signal distortion.

The break-before-make feature allows transferring of a signal from one port to another, without shorting the

inputs together. This device also offers low charge injection which makes this device suitable for high precision

data acquisition systems.

+15

+15V

S1A

S1B

D1

D2

THS3091

S2A

S2B

MSP430

-15

-15V

+15

+15V

S3A

S3B

D3

D4

THS3091

S4A

S4B

-15

-15V

图9-1. Ultrasonic Water Flow Measurement System

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9.2.1 Design Requirements

For this design example, use the parameters listed in 表9-1.

表9-1. Design Parameters

PARAMETERS

VALUES

15 V

Supply (V_DD

)

Supply (V_SS

)

-15 V

MUX I/O signal range

Control logic thresholds

EN

-15 V to 15 V (Rail-to-Rail)

1.8 V compatiable (up to V_DD

)

EN pulled low to enable the switch

9.2.2 Detailed Design Procedure

The TMUX7234 can operate without any external components except for the supply decoupling capacitors. All

inputs passing through the switch must fall within the recommended operating conditions of the TMUX7234,

including signal range and continuous current. 节6.4 shows how the signal range for this design can be -15 V to

+15 V and the maximum continuous current can be up to 400 mA for wide-range current measurement with a

positive supply of 15 V on V_DDand negative supply of -15 V on V_SS. The TMUX7234 device are bidirectional,

single-pole double-throw (SPDT) switches that offer low on-resistance, low leakage, and low power. These

features make these devices suitable for portable and power sensitive applications such as ultrasonic water

metering systems. For a more detailed analysis of the ultrasonic water flow measurement system refer to the

reference design.

9.2.3 Application Curve

The low on and off leakage currents of TMUX7234 and ultra-low charge injection performance make this device

ideal for implementing high precision industrial systems. The TMUX7234 contains specialized architecture to

reduce charge injection on the Source side (Sx) (For more details, see 节 8.3.6). 图 9-2 shows the plot for the

charge injection versus drain voltage for the TMUX7234.

80

V_DD= 20 V, V_SS= −20 V

V_DD= 15 V, V_SS= −15 V

V_DD= 5 V, V_SS= −5 V

60

40

20

0

-20

-40

-20

-15

-10

-5

0

5

10

15

20

Drain Voltage (V)

T_A= 25°C

图9-2. Charge Injection vs Drain Voltage

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10 Power Supply Recommendations

TMUX7234 operates across a wide supply range of ±4.5 V to ±22 V (4.5 V to 44 V in single-supply mode).

TMUX7234 also perform well with asymmetrical supplies such as V_DD= 12 V and V_SS= –5 V.

Power-supply bypassing improves noise margin and prevents switching noise propagation from the supply rails

to other components. Good power-supply decoupling is important to achieve optimum performance. Use a

supply decoupling capacitor ranging from 0.1 μF to 10 μF at both the V_DDand V_SSpins to ground for an

improved supply noise immunity. Place the bypass capacitors as close to the power supply pins of the device as

possible using low-impedance connections. TI recommends using multi-layer ceramic chip capacitors (MLCCs)

that offer low equivalent series resistance (ESR) and inductance (ESL) characteristics for power-supply

decoupling purposes. For very sensitive systems, or for systems in harsh noise environments, avoiding the use

of vias for connecting the capacitors to the device pins may offer superior noise immunity. The use of multiple

vias in parallel lowers the overall inductance and is beneficial for connections to ground and power planes.

Always ensure the ground (GND) connection is established before supplies are ramped.

11 Layout

11.1 Layout Guidelines

A reflection can occur when a PCB trace turns a corner at a 90° angle. A reflection occurs primarily because of

the change of width of the trace. The trace width increases to 1.414 times the width at the apex of the turn. This

increase upsets the transmission-line characteristics, especially the distributed capacitance and self–inductance

of the trace which results in the reflection. Not all PCB traces can be straight and therefore some traces must

turn corners. 图 11-1 shows progressively better techniques of rounding corners. Only the last example (BEST)

maintains constant trace width and minimizes reflections.

WORST

BETTER

BEST

2W

1W min.

W

图11-1. Trace Example

Route high-speed signals using a minimum of vias and corners which reduces signal reflections and impedance

changes. When a via must be used, increase the clearance size around it to minimize its capacitance. Each via

introduces discontinuities in the signal’s transmission line and increases the chance of picking up interference

from the other layers of the board. Be careful when designing test points, through-hole pins are not

recommended at high frequencies.

图11-2 and 图11-3 illustrates an example of a PCB layout with the TMUX7234. Some key considerations are:

• Decouple the supply pins with a 0.1 µF and 1 µF capacitor, placed lowest value capacitor as close to the pin

as possible. Make sure that the capacitor voltage rating is sufficient for the supply voltage.

• Keep the input lines as short as possible.

• Use a solid ground plane to help reduce electromagnetic interference (EMI) noise pickup.

• Do not run sensitive analog traces in parallel with digital traces. Avoid crossing digital and analog traces if

possible, and only make perpendicular crossings when necessary.

• Using multiple vias in parallel will lower the overall inductance and is beneficial for connection to ground

planes.

32

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TMUX7234

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ZHCSNF7F –FEBRUARY 2021 –REVISED DECEMBER 2022

11.2 Layout Example

图11-2 shows an example board layout for the TMUX7234.

SEL1

SEL4

S1A

S4A

D4

Wide (low inductance)

trace for power

D1

Wide (low inductance)

trace for power

S1B

S4B

TMUX7234

VSS

GND

S2B

D2

VDD

EN

S3B

D3

S2A

S3A

SEL3

SEL2

Via to ground plane

图11-2. TMUX7234PW Layout Example

Wide (low inductance)

trace for power

Wide (low inductance)

trace for power

D1

D4

S4B

VDD

S3B

D3

S1B

VSS

GND

S2B

Via to ground plane

图11-3. TMUX7234RRQ Layout Example

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33

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TMUX7234

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ZHCSNF7F –FEBRUARY 2021 –REVISED DECEMBER 2022

12 Device and Documentation Support

12.1 Documentation Support

12.1.1 Related Documentation

• Texas Instruments, Using Latch Up Immune Multiplexers to Help Improve System Reliability application

report

• Texas Instruments, Improve Stability Issues with Low CON Multiplexers application brief

• Texas Instruments, Improving Signal Measurement Accuracy in Automated Test Equipment application brief

• Texas Instruments, Sample & Hold Glitch Reduction for Precision Outputs Reference Design reference guide

• Texas Instruments, Simplifying Design with 1.8 V logic Muxes and Switches application brief

• Texas Instruments, System-Level Protection for High-Voltage Analog Multiplexers application report

• Texas Instruments, True Differential, 4 x 2 MUX, Analog Front End, Simultaneous-Sampling ADC Circuit

application report

• Texas Instruments, QFN/SON PCB Attachment application report

• Texas Instruments, Quad Flatpack No-Lead Logic Packages application report

12.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper

right corner, click on Alert me to register and receive a weekly digest of any product information that has

changed. For change details, review the revision history included in any revised document.

12.3 支持资源

TI E2E^™支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解

答或提出自己的问题可获得所需的快速设计帮助。

链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅

TI 的《使用条款》。

12.4 Trademarks

TI E2E^™is a trademark of Texas Instruments.

所有商标均为其各自所有者的财产。

12.5 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled

with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric changes could cause the device not to meet its published

specifications.

12.6 术语表

TI 术语表

本术语表列出并解释了术语、首字母缩略词和定义。

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical packaging and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

34

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PACKAGE OUTLINE

PW0020A

TSSOP - 1.2 mm max height

S

C

A

L

E

2

.

5

0

SMALL OUTLINE PACKAGE

SEATING

PLANE

C

6.6

6.2

TYP

A

0.1 C

PIN 1 INDEX AREA

18X 0.65

20

1

2X

5.85

6.6

6.4

NOTE 3

10

B

11

0.30

20X

4.5

4.3

NOTE 4

0.19

1.2 MAX

0.1

C A B

(0.15) TYP

SEE DETAIL A

0.25

GAGE PLANE

0.15

0.05

0.75

0.50

A

20

0 -8

DETAIL A

TYPICAL

4220206/A 02/2017

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed 0.15 mm per side.

4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.

5. Reference JEDEC registration MO-153.

www.ti.com

EXAMPLE BOARD LAYOUT

PW0020A

TSSOP - 1.2 mm max height

SMALL OUTLINE PACKAGE

SYMM

20X (1.5)

(R0.05) TYP

20

1

20X (0.45)

SYMM

18X (0.65)

11

10

(5.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE: 10X

METAL UNDER

SOLDER MASK

OPENING

SOLDER MASK

OPENING

METAL

EXPOSED METAL

0.05 MAX

ALL AROUND

0.05 MIN

ALL AROUND

NON-SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

15.000

(PREFERRED)

SOLDER MASK DETAILS

4220206/A 02/2017

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com

EXAMPLE STENCIL DESIGN

PW0020A

TSSOP - 1.2 mm max height

SMALL OUTLINE PACKAGE

20X (1.5)

SYMM

(R0.05) TYP

20

1

20X (0.45)

SYMM

18X (0.65)

10

11

(5.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

SCALE: 10X

4220206/A 02/2017

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

9. Board assembly site may have different recommendations for stencil design.

www.ti.com

PACKAGE OUTLINE

RRQ0020A

WQFN - 0.8 mm max height

S

C

A

L

E

3

.

5

0

PLASTIC QUAD FLATPACK - NO LEAD

4.1

3.9

A

B

PIN 1 INDEX AREA

4.1

3.9

0.8

0.7

C

SEATING PLANE

0.08 C

0.05

0.00

2.5 0.1

2X 2

(0.2) TYP

SYMM

6

10

EXPOSED

THERMAL PAD

5

11

15

SYMM

21

2X 2

16X 0.5

1

PIN 1 ID

0.3

20X

0.2

16

0.5

20

0.1

C A B

20X

0.05

0.3

4224817/A 03/2019

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

www.ti.com

EXAMPLE BOARD LAYOUT

RRQ0020A

WQFN - 0.8 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

(

2.5)

SYMM

20

16

SEE SOLDER MASK

DETAIL

20X (0.6)

20X (0.25)

16X (0.5)

(1)

1

15

21

SYMM

(3.8)

5

11

(R0.05) TYP

(

0.2) TYP

VIA

6

10

(1)

(3.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE: 20X

0.07 MIN

ALL AROUND

0.07 MAX

ALL AROUND

METAL UNDER

SOLDER MASK

METAL EDGE

EXPOSED METAL

SOLDER MASK

OPENING

EXPOSED

METAL

SOLDER MASK

OPENING

NON SOLDER MASK

SOLDER MASK DEFINED

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4224817/A 03/2019

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

www.ti.com

EXAMPLE STENCIL DESIGN

RRQ0020A

WQFN - 0.8 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

(0.65) TYP

16

20

20X (0.6)

20X (0.25)

16X (0.5)

1

15

(0.65) TYP

(3.8)

21

SYMM

4X ( 1.1)

11

(R0.05) TYP

5

10

6

SYMM

(3.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 MM THICK STENCIL

SCALE: 20X

EXPOSED PAD 21

77% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE

4224817/A 03/2019

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

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邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	TMUX7234PWR
厂家：	TEXAS INSTRUMENTS
描述：	具有 1.8V 逻辑的 44V、闩锁效应抑制、2:1 四通道精密多路复用器 \| PW \| 20 \| -40 to 125 复用器
文件：	总46页 (文件大小：2220K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TMUX7234PWR [TI]

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