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TPS22994

ZHCSCV5B –AUGUST 2014–REVISED SEPTEMBER 2014

TPS22994 具有通用输入输出 (GPIO) 和 I²C 控制功能的四通道负载开关

1 特性

2 应用

1

•

输入电压：1.0V 至 3.6V

•

超薄个人电脑

•

低导通状态电阻 (V_BIAS= 7.2V)

笔记本电脑

平板电脑

服务器

–

V_IN= 3.3V 时，R_ON= 41mΩ

V_IN= 1.8V 时，R_ON= 41mΩ

V_IN= 1.5V 时，R_ON= 41mΩ

V_IN= 1.0V 时，R_ON= 41mΩ

一体机

3 说明

•

VBIAS 电压范围：2.7V 至 17.2V

适合于 1S/2S/3S/4S 锂离子电池拓扑结构

TPS22994 是一款多通道、低 R_ON负载开关，此开关

具有用户可编程特性。此器件包括四个 N 通道属氧化

物半导体场效应晶体管 (MOSFET)，能够在 1.0V 至

3.6V 输入电压范围内运行。由于开关可通过 I²C 控

制，因此非常适用于 GPIO 有限的处理器。

–

•

每通道持续电流最大为 1A

静态电流

–

单通道 < 12µA

全部四通道 < 22µA

TPS22994 器件的上升时间受到内部控制以避免浪涌

电流。 TPS22994 具有五个可编程转换率选项、四个

接通延迟选项和四个快速输出放电 (QOD) 电阻选项。

•

关断电流（全部四通道）< 7µA

四个 1.2V 兼容 GPIO 控制输入

I²C 配置（每通道）

此器件的通道可由 GPIO 或 I²C 控制。缺省运行模式

为通过 ONx 端子的 GPIO 控制。 I²C 从地址端子可接

至高电平或低电平，以分配 7 个唯一的器件地址。

–

开/关控制

可编程转换率控制（5 个选项）

可编程接通延迟（4 个选项）

可编程输出放电（4 个选项）

TPS22994 采用节省空间的 RUK 封装（焊球间距

0.4mm），并可在 -40°C 至 85°C 的自然通风温度范

围内运行。

•

I²C SwitchALL™ 用于多通道/多芯片控制的命令

四方扁平无引线 (QFN)-20 封装，3mm x 3mm，高

度 0.75mm

器件信息⁽¹⁾

部件号

TPS22994

封装

WQFN (20)

封装尺寸（标称值）

3.00mm x 3.00mm

(1) 要了解所有可用封装，请见数据表末尾的可订购产品附录。

4 简化电路原理图

VBIAS

(2.7 V to 17.2 V)

VIN1

VOUT1

ON1

C_L

R_L

VIN2

VOUT2

ON2

C_L

R_L

PMIC or

PMU

TPS22994

VOUT3

VIN3

ON3

C_L

R_L

VOUT4

VIN4

ON4

ADD1

C_L

R_L

ADD2

ADD3

SDA SCL

µC

VDD

(1.62 to 3.6)

1

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

English Data Sheet: SLVSCL4

TPS22994

ZHCSCV5B –AUGUST 2014–REVISED SEPTEMBER 2014

www.ti.com.cn

1

2

3

4

5

6

7

8

特性.......................................................................... 1

应用.......................................................................... 1

说明.......................................................................... 1

简化电路原理图........................................................ 1

修订历史记录 ........................................................... 2

Device Comparison Table..................................... 3

Pin Configuration and Functions......................... 4

Specifications......................................................... 5

8.1 Recommended Operating Conditions....................... 5

8.2 Absolute Maximum Ratings ..................................... 5

8.3 Handling Ratings....................................................... 5

8.4 Thermal Information.................................................. 6

8.5 Electrical Characteristics........................................... 6

8.6 Switching Characteristics, V_BIAS= 7.2 V................... 9

8.7 Switching Characteristics, V_BIAS= 3.3 V .................. 9

8.8 Typical Characteristics............................................ 11

9

Detailed Description ............................................ 18

9.1 Overview ................................................................. 18

9.2 Functional Block Diagram ....................................... 18

9.3 Feature Description................................................. 19

9.4 Device Functional Modes........................................ 24

9.5 Register Map........................................................... 25

10 Applications and Implementation...................... 27

10.1 Application Information.......................................... 27

10.2 Typical Application ................................................ 30

11 Layout................................................................... 35

11.1 Board Layout......................................................... 35

12 器件和文档支持 ..................................................... 36

12.1 商标....................................................................... 36

12.2 静电放电警告......................................................... 36

12.3 术语表 ................................................................... 36

13 机械封装和可订购信息 .......................................... 36

5 修订历史记录

Changes from Revision A (September 2014) to Revision B

Page

•

Updated MAX limits in the Electrical Characteristics table. ................................................................................................... 6

Updated Detailed Design Procedure for Parallel Channels Application. ............................................................................. 30

Changes from Original (August 2014) to Revision A

Page

•

初始发布的完整版数据表 ....................................................................................................................................................... 1

2

TPS22994

www.ti.com.cn

ZHCSCV5B –AUGUST 2014–REVISED SEPTEMBER 2014

6 Device Comparison Table

TPS22994

R_ONTYPICAL AT 3.3 V (V_BIAS= 7.2 V)

41 mΩ

(1)

RISE TIME

Programmable

1 A

(1)

ON DELAY

(1) (2)

QUICK OUTPUT DISCHARGE

MAXIMUM OUTPUT CURRENT (per channel)

GPIO ENABLE

Active High

–40°C to 85°C

OPERATING TEMP

(1) See Application Information section.

(2) This feature discharges output of the switch to GND through an internal resistor, preventing the output from floating. See Application

information section.

3

TPS22994

ZHCSCV5B –AUGUST 2014–REVISED SEPTEMBER 2014

www.ti.com.cn

7 Pin Configuration and Functions

Bottom View

Top View

11

12

13

14

15

14

13

12

11

10

9

16

17

18

ON1

ON2

ADD2

SCL

10

9

16

17

18

ADD2

SCL

ON1

ON2

ON3

ON4

ADD1

Exposed

Thermal Pad

Exposed

Thermal Pad

ON3

8

VDD

SDA

8

VDD

SDA

ON4

7

6

19

20

7

6

19

20

ADD1

ADD3

5

4

3

2

1

2

3

4

5

Pin Functions

NAME

I/O

DESCRIPTION

NO.

Exposed Thermal

Pad

-

Exposed thermal pad for thermal relief. Tie to GND.

1

2

VOUT2

VIN2

O

I

Channel 2 output.

Channel 2 input.

Bias voltage. Power supply to the device. Recommended voltage range for this pin is 2.7 V to 17.2 V. See

the Applications and Implementation section.

3

VBIAS

I

4

5

VIN1

I

Channel 1 input.

Channel 1 output.

VOUT1

O

Device address pin. Tie high or low. Do not leave floating. See the Applications and Implementation

section.

6

ADD1

I

7

ON4

I

Active high channel 4 control input. Do not leave floating.

Active high channel 3 control input. Do not leave floating.

Active high channel 2 control input. Do not leave floating.

Active high channel 1 control input. Do not leave floating.

Channel 4 output.

8

ON3

9

ON2

I

10

11

12

13

14

15

16

17

ON1

I

VOUT4

VIN4

GND

VIN3

VOUT3

ADD2

SCL

O

I

Channel 4 input.

-

Device ground.

I

Channel 3 input.

O

I

Channel 3 output.

Device address pin. Tie high or low. See the Applications and Implementation section.

Serial clock input.

I

I²C device supply input. Tie this pin to the I²C SCL/SDA pull-up voltage. See the Applications and

Implementation section.

18

VDD

I

19

20

SDA

I/O

I

Serial data input/output.

ADD3

Device address pin. Tie high or low. See the Applications and Implementation section.

4

TPS22994

www.ti.com.cn

ZHCSCV5B –AUGUST 2014–REVISED SEPTEMBER 2014

8 Specifications

8.1 Recommended Operating Conditions

Over operating free-air temperature range (unless otherwise noted)

MIN

1.0

2.7

1.62

0

MAX

UNIT

For V_BIAS< 4.6 V

(V_BIAS– 1 V)

Input voltage for VIN1, VIN2, VIN3,

VIN4

V_INx

V

For V_BIAS≥ 4.6 V

3.6

17.2

3.6

V_BIAS

V_DD

Supply voltage for VBIAS

V

Supply voltage for VDD

V_ADDx

V_ONx

V_OUTx

C_INx

Input voltage for ADD1, ADD2, ADD3

Input voltage for ON1, ON2, ON3, ON4

V_DD

5

V

0

V

Output voltage for VOUT1, VOUT2, VOUT3, VOUT4

Input capacitor on VIN1, VIN2, VIN3, VIN4

0

1⁽¹⁾

V_INx

V

µF

(1) Refer to application section.

8.2 Absolute Maximum Ratings⁽¹⁾

Over operating free-air temperature range (unless otherwise noted)

VALUE

UNIT⁽²⁾

MIN

–0.3

MAX

4

V_INx

Input voltage for VIN1, VIN2, VIN3, VIN4

Supply voltage for VBIAS

V

V_BIAS

20

4

V_OUTx

Output voltage for VOUT1, VOUT2, VOUT3, VOUT4

V_DD, V_SCL

,

Input voltage for VDD, SCL, SDA, ADD1, ADD2, ADD3

–0.3

4

V

V_SDA, V_ADDx

V_ONx

I_MAX

Input voltage for ON1, ON2, ON3, ON4

Maximum continuous switch current per channel

Operating free-air temperature⁽³⁾

6

1

V

A

T_A

–40

85

°C

T_J

Maximum junction temperature

125

300

T_LEAD

Maximum lead temperature (10-s soldering time)

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating

conditions is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.

(2) All voltage values are with respect to network ground pin.

(3) In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may

have to be derated. Maximum ambient temperature [TA(max)] is dependent on the maximum operating junction temperature [T_J(max)],

the maximum power dissipation of the device in the application [PD(max)], and the junction-to-ambient thermal resistance of the

part/package in the application (_θJA), as given by the following equation: T_A(max)= T_J(max)– (θ_JA× P_D(max)

)

8.3 Handling Ratings

MIN

–65

MAX

150

UNIT

°C

V

T_stg

Storage temperature

Human-Body Model (HBM)⁽²⁾

Charged-Device Model (CDM)⁽³⁾

–2000

–-500

2000

500

ESD⁽¹⁾

Electrostatic discharge protection

V

(1) Electrostatic discharge (ESD) to measure device sensitivity and immunity to damage caused by assembly line electrostatic discharges in

to the device.

(2) Level listed above is the passing level per ANSI/ESDA/JEDEC JS-001. JEDEC document JEP155 states that 500V HBM allows safe

manufacturing with a standard ESD control process.

(3) Level listed above is the passing level per EIA-JEDEC JESD22-C101. JEDEC document JEP157 states that 250V CDM allows safe

manufacturing with a standard ESD control process.

5

TPS22994

ZHCSCV5B –AUGUST 2014–REVISED SEPTEMBER 2014

www.ti.com.cn

8.4 Thermal Information

TPS22994

RUK

20 PINS

46

THERMAL METRIC^{(1) (2)}

UNIT

Θ_JA

Junction-to-ambient thermal resistance

Θ_JC(top)

Θ_JB

Junction-to-case(top) thermal resistance

Junction-to-board thermal resistance

50

18

°C/W

Ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case(bottom) thermal resistance

0.7

Ψ_JB

18

Θ_JC(bottom)

4.2

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

(2) For thermal estimates of this device based on PCB copper area, see the TI PCB Thermal Calculator.

8.5 Electrical Characteristics

The specification applies over the operating ambient temperature –40°C ≤ T_A≤ 85°C (Full) (unless otherwise noted). Typical

values are for T_A= 25°C. V_BIAS= 7.2 V (unless otherwise noted).

PARAMETER

TEST CONDITIONS

T_A

MIN

TYP

MAX

UNIT

POWER SUPPLIES CURRENTS AND LEAKAGES

V_BIAS= 2.7 V

V_BIAS= 3.3 V

V_BIAS= 4.5 V

V_BIAS= 5.2 V

V_BIAS= 7.2 V

V_BIAS= 10.8 V

V_BIAS= 12.6 V

V_BIAS= 17.2 V

V_BIAS= 2.7 V

V_BIAS= 3.3 V

V_BIAS= 4.5 V

V_BIAS= 5.2 V

V_BIAS= 7.2 V

V_BIAS= 10.8 V

V_BIAS= 12.6 V

V_BIAS= 17.2 V

V_DD= 1.8 V

18.3

18.9

19.4

19.9

21.1

21.2

8.3

27.6

28.6

29.9

30.3

33.6

34.8

35.0

35.7

16.6

17.6

18.9

19.6

22.5

23.6

23.8

24.4

1.1

I_OUT1,2,3,4= 0 A,

V_IN1,2,3,4= lower of (V_BIAS-1 V) or 3.6

V,

V_ON1,2,3,4= 3.6 V,

V_DD= 0 V

Quiescent current for VBIAS

(all four channels)

Full

µA

I_{Q, VBIAS}

8.8

I_OUT1,2,3,4= 0 A,

V_IN1= lower of (V_BIAS-1 V) or 3.6 V,

V_ON1= 3.6 V,

V_IN2,3,4= V_ON2,3,4= 0 V,

V_DD= 0 V

9.5

9.9

Quiescent current for VBIAS

(single channel)

Full

µA

11.3

11.7

11.9

0.6

I_OUT1,2,3,4= 0 A,

I_{Q, VDD}

Quiescent current for VDD

V_IN1,2,3,4= V_ON1,2,3,4= 3.6 V,

f_SCL= 0 Hz

Full

µA

V_DD= 3.6 V

V_DD= 1.8 V

V_DD= 3.6 V

1.2

7.7

1.9

I_OUT1,2,3,4= 0 A,

V_IN1,2,3,4= V_ON1,2,3,4= 3.6 V,

f_SCL= 1 MHz

Average dynamic current for

VDD during I²C

communication

I_{DYN, VDD}

19.0

V_BIAS= 3.3 V

V_BIAS= 5.2 V

V_BIAS= 7.2 V

V_BIAS= 10.8 V

V_BIAS= 12.6 V

V_BIAS= 17.2 V

V_BIAS= 3.3 V

V_BIAS= 5.2 V

V_BIAS= 7.2 V

V_BIAS= 10.8 V

V_BIAS= 12.6 V

V_BIAS= 17.2 V

65.0

66.9

68.4

68.5

68.6

69.1

48.0

58.2

58.9

60.2

60.7

I_OUT1,2,3,4= 0 A,

V_IN1,2,3,4= lower of (V_BIAS-1 V) or 3.6

V,

V_ON1,2,3,4= 3.6 V,

f_SCL=1 MHz

Average dynamic current for

VBIAS (all four channels)

during I²C communication

Full

µA

I_{DYN, VBIAS}

I_OUT1,2,3,4= 0 A,

V_IN1,2,3,4= lower of (V_BIAS-1 V) or 3.6

V,

V_ON1,2,3,4= 3.6 V,

V_IN2,3,4= V_ON2,3,4= 0 V,

f_SCL= 1 MHz

Average dynamic current for

VBIAS (single channel) during

I²C communication

Full

µA

6

TPS22994

www.ti.com.cn

ZHCSCV5B –AUGUST 2014–REVISED SEPTEMBER 2014

Electrical Characteristics (continued)

The specification applies over the operating ambient temperature –40°C ≤ T_A≤ 85°C (Full) (unless otherwise noted). Typical

values are for T_A= 25°C. V_BIAS= 7.2 V (unless otherwise noted).

PARAMETER

TEST CONDITIONS

T_A

MIN

TYP

MAX

UNIT

V_ON1,2,3,4= 0 V, V_OUT1,2,3,4= 0 V, V_DD= 3.6 V,

V_BIAS= 17.2V

Shutdown current for VBIAS

(all four channels)

I_{SD, VBIAS}

I_{SD, VDD}

Full

6.5

12.8

µA

V_ON1,2,3,4= 0 V, V_OUT1,2,3,4= 0 V,

V_DD= 3.6 V

Shutdown current for VDD

Shutdown current for VINx

Full

1.2

1.9

µA

V_INx= 3.6 V

0.005

0.004

0.003

0.002

1.0

0.5

0.1

0.2

V_INx= 3.3 V

I_{SD, VINx}

V_ONx= 0 V, V_OUTx= 0 V, V_DD= 3.6 V V_INx= 1.8 V

V_INx= 1.5 V

V_INx= 1.0 V

I_ONx

I_ADDx

I_SCL

I_SDA

Leakage current for ONx

Leakage current for ADDx

Leakage current for SCL

Leakage current for SDA

V_ONx= 5 V

Full

µA

V_ADDx= 3.6 V

V_SCL= 3.6 V

V_SDA= 3.6 V

RESISTANCE CHARACTERISTICS

25°C

Full

40.6

40.5

60.4

44.7

41.5

40.8

40.6

114.2

64.2

55.4

48.0

50.3

58.5

50.2

58.5

50.1

58.5

50.1

58.5

49.9

58.5

64.0

71.0

53.1

65.2

50.3

60.9

50.3

60.5

50.1

60.3

166.0

175.0

85.9

94.4

69.5

81.0

57.9

70.0

V_IN= 3.3 V

V_IN= 2.5 V

mΩ

25°C

Full

25°C

Full

V_BIAS= 7.2 V, I_OUT= –200 mA

V_IN= 1.8 V

V_IN= 1.5 V

V_IN= 1.0 V

V_IN= 3.3 V

V_IN= 2.5 V

V_IN= 1.8 V

V_IN= 1.5 V

V_IN= 1.0 V

V_IN= 2.3 V

V_IN= 1.8 V

V_IN= 1.5 V

V_IN= 1.0 V

25°C

Full

25°C

Full

25°C

Full

25°C

Full

R_ON

On-state resistance

25°C

Full

V_BIAS= 5.2 V, I_OUT= –200 mA

25°C

Full

25°C

Full

25°C

Full

25°C

Full

V_BIAS= 3.3 V, I_OUT= –200 mA

25°C

Full

25°C

Full

V_IN= 3.3 V, V_ON= 0 V, I_OUT= 1 mA, QOD[1:0] = 00

V_IN= 3.3 V, V_ON= 0 V, I_OUT= 1 mA, QOD[1:0] = 01

V_IN= 3.3 V, V_ON= 0 V, I_OUT= 1 mA, QOD[1:0] = 10

V_IN= 3.3 V, V_ON= 0 V, I_OUT= 1 mA, QOD[1:0] = 11

25°C

93

470

940

R_PD

Output pulldown resistance

Ω

No

QOD

7

TPS22994

ZHCSCV5B –AUGUST 2014–REVISED SEPTEMBER 2014

www.ti.com.cn

Electrical Characteristics (continued)

The specification applies over the operating ambient temperature –40°C ≤ T_A≤ 85°C (Full) (unless otherwise noted). Typical

values are for T_A= 25°C. V_BIAS= 7.2 V (unless otherwise noted).

PARAMETER

TEST CONDITIONS

T_A

MIN

TYP

MAX

UNIT

THRESHOLD CHARACTERISTICS

High-level input voltage for

ADDx

0.7 ×

V_DD

V_{IH, ADDx}

V_{IL, ADDx}

V_{IH, ONx}

V_{IL, ONx}

Full

V

Low-level input voltage for

ADDx

0.3×V_DD

High-level input voltage for

ONx

1.05

0

5

Low-level input voltage for

ONx

0.4

V_BIAS= 2.7 V

V_BIAS= 5.2 V

V_BIAS= 7.2 V

V_BIAS= 10.8 V

V_BIAS= 12.6 V

V_BIAS= 17.2 V

107

105

107

108

109

108

V_{HYS, ONx}

Hysteresis for ONx

25°C

mV

I²C CHARACTERISTICS

(1)

f_SCL

Clock frequency

Full

1

MHz

ns

(1)

t_{SU, SDA}

t_{HD, SDA}

I_{OL, SDA}

Setup time for SDA

Hold time for SDA

f_SCL= 1 MHz (fast mode plus)

V_OL,SDA= 0.4 V

50

0

Full

ns

SDA output low current

25°C

8

mA

High-level input voltage for

SDA

0.7 ×

V_DD

V_{IH, SDA}

V_{IH, SCL}

V_{IL, SDA}

V_{IL, SCL}

Full

V_DD

V

High-level input voltage for

SCL

0.7 ×

V_DD

Low-level input voltage for

SDA

0

0.3×V_DD

Low-level input voltage for

SCL

(1) Parameter verified by design.

8

TPS22994

www.ti.com.cn

ZHCSCV5B –AUGUST 2014–REVISED SEPTEMBER 2014

8.6 Switching Characteristics, V_BIAS= 7.2 V

Values below are typical values at T_A= 25°C. V_BIAS= 7.2V (unless otherwise noted).

VIN VOLTAGE

PARAMETER

TEST CONDITION

UNIT

3.3 V

10.2

220

1.8 V

1.5 V

9.9

1.0 V

9.9

Slew rate[4:2] = 000

Slew rate[4:2] = 001

Slew rate[4:2] = 010

Slew rate[4:2] = 011

Slew rate[4:2] = 100

10.0

159

274

486

967

V_BIAS= 7.2 V,

R_L= 10 Ω, C_L= 0.1 µF,

QOD[1:0] = 10,

147

252

446

888

124

213

377

749

t_ON

t_OFF

t_R

VOUTx turn-on time

VOUTx turn-off time

VOUTx rise time

380

µs

674

ON-delay[6:5] = 00

1334

V_BIAS= 7.2 V, R_L=10 Ω, C_L=0.1 µF, QOD[1:0] = 10, ON-delay[6:5] =

2.5

00

Slew rate[4:2] = 000

Slew rate[4:2] = 001

1.4

271

471

835

1674

0.9

178

309

549

1096

0.8

158

275

489

976

0.7

125

218

390

774

V_BIAS= 7.2 V, R_L= 10 Ω, C_L= 0.1 µF,

QOD[1:0] = 10, ON-delay[6:5] = 00

Slew rate[4:2] = 010

Slew rate[4:2] = 011

Slew rate[4:2] = 100

V_BIAS= 7.2 V, R_L= 10 Ω, C_L= 0.1 µF, QOD[1:0] = 10, ON-delay[6:5] =

00

t_F

VOUTx fall time

2.3

µs

ON delay[4:2] = 00

9.6

87

9.6

87

9.6

87

9.6

87

ON delay[4:2] = 01

ON delay[4:2] = 10

ON delay[4:2] = 11

V_BIAS= 7.2 V, R_L= 10 Ω, C_L= 0.1 µF,

QOD[1:0] = 10, Slew rate[6:5] = 000

t_D

VOUTx ON delay time

295

846

295

846

295

846

295

846

8.7 Switching Characteristics, V_BIAS= 3.3 V

Values below are typical values at T_A= 25°C. V_BIAS= 3.3 V (unless otherwise noted).

VIN VOLTAGE

1.5V

8.3

PARAMETER

TEST CONDITION

UNIT

1.8V

8.4

1.0V

Slew rate[4:2] = 000

Slew rate[4:2] = 001

Slew rate[4:2] = 010

Slew rate[4:2] = 011

Slew rate[4:2] = 100

8.1

129

221

389

773

2.8

V_BIAS= 3.3 V,

R_L=10 Ω, C_L=0.1 µF,

QOD[1:0] = 10,

165

283

502

997

2.5

152

t_ON

t_OFF

t_R

VOUTx turn-on time

VOUTx turn-off time

VOUTx rise time

260

µs

460

ON-delay[6:5] = 00

915

V_BIAS= 3.3 V, R_L=10 Ω, C_L=0.1 µF, QOD[1:0] = 10, ON-delay[6:5] = 00

Slew rate[4:2] = 000

2.6

2.8

2.4

1.8

Slew rate[4:2] = 001

184

318

565

1126

2.2

163

128

224

398

791

2.1

V_BIAS= 3.3 V, R_L=10 Ω, C_L=0.1 µF,

QOD[1:0] = 10, ON-delay[6:5] = 00

Slew rate[4:2] = 010

283

Slew rate[4:2] = 011

Slew rate[4:2] = 100

501

1002

2.2

t_F

VOUTx fall time

V_BIAS= 3.3 V, R_L=10 Ω, C_L= 0.1 µF, QOD[1:0] = 10, ON-delay[6:5] = 00

µs

ON delay[4:2] = 00

7.3

ON delay[4:2] = 01

ON delay[4:2] = 10

ON delay[4:2] = 11

89

V_BIAS= 3.3 V, R_L=10 Ω, C_L=0.1 µF,

QOD[1:0] = 10, Slew rate[6:5] = 000

t_D

VOUTx ON delay time

296

846

296

846

9

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V_IN

V_OUT

C_IN= 1 µF

ON

+

-

ON

C_L

(A)

R_L

OFF

VBIAS

GND

TPS22994

GND

Single channel shown for clarity.

A. Rise and fall times of the control signal is 100 ns.

B. All switching measurements are done using GPIO control only.

Figure 1. Test Circuit

V_ON

50%

t_F

t_OFF

t_R

V_OUT

t_ON

90%

V_OUT

50%

10%

t_D

Figure 2. t_ON/t_OFFWaveforms

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8.8 Typical Characteristics

1.5

1.4

1.3

1.2

1.1

1

-40°C

25°C

85°C

-40°C

25°C

85°C

1.4

1.3

1.2

1.1

1

0.9

0.8

0.7

0.6

0.5

0.4

0.9

0.8

0.7

0.6

0.5

0.4

1.6 1.8

2

2.2 2.4 2.6 2.8

V_DD(V)

3

3.2 3.4 3.6

1.6 1.8

2

2.2 2.4 2.6 2.8

V_DD(V)

3

3.2 3.4 3.6

D001

D002

V_BIAS= 7.2 V

V_INx= 3.6 V

V_BIAS= 7.2 V

V_INx= 3.6 V

Figure 3. I_Q,VDDvs. V_DD

Figure 4. I_SD,VDDvs. V_DD

24

22

20

18

16

14

13

12

11

10

9

-40°C

25°C

85°C

-40°C

25°C

85°C

8

7

2.7

4.7

6.7

8.7

10.7

12.7

14.7

16.7

2.7

4.7

6.7

8.7

10.7

12.7

14.7

16.7

V_BIAS(V)

D003

D004

V_INx= lower of

V_DD= 3.6 V

V_INx= lower of

V_DD= 3.6 V

(V_BIAS-1V) or 3.6 V

Figure 5. I_Q,VBIASvs. V_BIAS(all channels)

Figure 6. I_Q,VBIASvs. V_BIAS(single channel)

8

7.5

7

0.08

0.07

0.06

0.05

0.04

0.03

0.02

0.01

0

-40°C

25°C

85°C

6.5

6

5.5

5

-40°C

25°C

85°C

4.5

4

2.7

4.7

6.7

8.7

V_BIAS(V)

10.7

12.7

14.7

16.7

1

1.2 1.4 1.6 1.8

2

2.2 2.4 2.6 2.8

V_IN(V)

3

3.2 3.4 3.6

D005

D006

V_INx= lower of

V_DD= 3.6 V

V_BIAS= 7.2 V

V_DD= 3.6 V

(V_BIAS-1V) or 3.6 V

Figure 8. I_SD,VINvs. V_IN

Figure 7. I_SD,VBIASvs. V_BIAS

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Typical Characteristics (continued)

48

50

47

44

41

38

35

32

29

26

23

44

40

36

32

28

-40qC

25qC

85qC

-40°C

25°C

85°C

1

1.3

1.6

1.9

2.2

2.5

2.8

3.1

3.4 3.6

1

1.3

1.6

1.9

2.2

2.5

2.8

3.1

3.4 3.6

V_IN(V)

D007

D008

V_BIAS= 7.2 V

I_OUT= 200 mA

V_BIAS= 7.2 V

I_OUT= 1 A

Figure 9. R_ONvs. V_IN

Figure 10. R_ONvs. V_IN(single channel)

170

0.825

0.8

VBIAS = 2.7V

VBIAS = 3.3V

VBIAS = 4.5V

VBIAS = 5.2V

VBIAS = 7.2V

VBIAS = 10.8V

VBIAS = 12.6V

VBIAS = 14V

VIL,ONx

VIH,ONx

150

130

110

90

VBIAS = 17.2V

0.775

0.75

0.725

0.7

70

0.675

0.65

0.625

50

30

1

1.2 1.4 1.6 1.8

2

2.2 2.4 2.6 2.8

V_IN(V)

3

3.2 3.4 3.6

2.7

4.7

6.7

8.7

V_BIAS(V)

10.7

12.7

14.7

16.7

D009

D010-011

T_A= 25°C

V_INx= lower of

T_A= 25°C

(V_BIAS-1 V) or 3.6 V

Figure 11. R_ONvs. V_IN

Figure 12. V_IH/V_ILfor ONx vs. V_BIAS

1200

1000

800

600

400

200

0

0.15

QOD = 00

QOD = 01

QOD = 10

0.14

0.13

0.12

0.11

0.1

0.09

0.08

0.07

0.06

0.05

2.7

4.7

6.7

8.7

10.7

12.7

14.7

16.7

2.7

4.7

6.7

8.7

10.7

12.7

14.7

16.7

V_BIAS(V)

D012

D013

V_INx= lower of

T_A= 25°C

(V_BIAS-1 V) or 3.6 V

Figure 14. R_PDvs. V_BIAS

Figure 13. V_{HYS, ONx}vs. V_BIAS

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Typical Characteristics (continued)

1.8

3

2.8

2.6

2.4

2.2

2

-40°C

25°C

85°C

-40°C

25°C

85°C

1.6

1.4

1.2

1

0.8

0.6

1.8

1

1.3

1.6

1.9

2.2

V_IN(V)

2.5

2.8

3.1

3.4 3.6

1

1.1

1.2

1.3

1.4

V_IN(V)

1.5

1.6

1.7

1.8

D014a

D014b

V_BIAS= 7.2 V

V_DD= 3.6 V

R_L= 10 Ω

V_BIAS= 3.3 V

V_DD= 3.6 V

R_L= 10 Ω

Slew rate[4:2] =

000

Slew rate[4:2] =

000

Figure 15. t_Rvs. V_IN

Figure 16. t_Rvs. V_IN

350

200

-40°C

25°C

-40°C

25°C

85°C

325

190

85°C

300

180

275

250

225

200

175

150

125

100

170

160

150

140

130

1

1.2 1.4 1.6 1.8

2

2.2 2.4 2.6 2.8

V_IN(V)

3

3.2 3.4 3.6

1

1.1

1.3

1.4

V_IN(V)

1.5

1.6

1.8

D015a

D0145b

V_BIAS= 7.2 V

V_DD= 3.6 V

R_L= 10 Ω

V_BIAS= 3.3 V

V_DD= 3.6 V

R_L= 10 Ω

Slew rate[4:2] =

001

Slew rate[4:2] =

001

Figure 17. t_Rvs. V_IN

Figure 18. t_Rvs. V_IN

520

340

-40°C

25°C

85°C

-40°C

25°C

85°C

480

440

400

360

320

280

240

200

320

300

280

260

240

220

1

1.3

1.6

1.9

2.2

2.5

2.8

3.1

3.4 3.6

1

1.1

1.3

1.4

1.5

1.6

1.8

V_IN(V)

D016a

D0164b

V_BIAS= 7.2 V

V_DD= 3.6 V

R_L= 10 Ω

V_BIAS= 3.3 V

V_DD= 3.6 V

R_L= 10 Ω

Slew rate[4:2] =

010

Slew rate[4:2] =

010

Figure 19. t_Rvs. V_IN

Figure 20. t_Rvs. V_IN

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Typical Characteristics (continued)

960

600

560

520

480

440

400

360

-40°C

25°C

85°C

-40°C

25°C

85°C

880

800

720

640

560

480

400

320

1

1.3

1.6

1.9

2.2

V_IN(V)

2.5

2.8

3.1

3.4 3.6

1

1.1

1.2

6.7

1.3

1.4

V_IN(V)

1.5

1.6

1.7

1.8

D017a

D0174b

V_BIAS= 7.2 V

V_DD= 3.6 V

R_L= 10 Ω

V_BIAS= 3.3 V

V_DD= 3.6 V

R_L= 10 Ω

Slew rate[4:2] =

011

Slew rate[4:2] =

011

Figure 21. t_Rvs. V_IN

Figure 22. t_Rvs. V_IN

1920

-40°C

1200

-40°C

25°C

1120

1040

960

25°C

85°C

1760

1600

1440

1280

1120

960

85°C

880

800

640

720

1

1.3

1.6

1.9

2.2

V_IN(V)

2.5

2.8

3.1

3.4 3.6

1

1.1

1.3

1.4

V_IN(V)

1.5

1.6

1.7

1.8

D018a

D0184b

V_BIAS= 7.2 V

V_DD= 3.6 V

R_L= 10 Ω

V_BIAS= 3.3 V

V_DD= 3.6 V

R_L= 10 Ω

Slew rate[4:2] =

100

Slew rate[4:2] =

100

Figure 23. t_Rvs. V_IN

Figure 24. t_Rvs. V_IN

14

12

10

8

94

92

90

88

86

84

82

80

6

4

-40°C

25°C

85°C

-40°C

25°C

85°C

2

0

2.7

4.7

6.7

8.7

10.7

12.7

14.7

16.7

2.7

4.7

8.7

10.7

12.7

14.7

16.7

V_BIAS(V)

D019

D020

ON-delay[6:5] = 00

V_DD= 3.6 V

R_L= 10 Ω

ON-delay[6:5] = 01

V_DD= 3.6 V

R_L= 10 Ω

Figure 25. t_Dvs. V_BIAS

Figure 26. t_Dvs. V_BIAS

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Typical Characteristics (continued)

310

306

302

298

294

290

286

282

278

274

270

880

870

860

850

840

830

820

810

800

-40°C

25°C

85°C

-40°C

25°C

85°C

2.7

4.7

6.7

8.7

10.7

12.7

14.7

16.7

2.7

4.7

6.7

8.7

10.7

12.7

14.7

16.7

V_BIAS(V)

D021

D022

ON-delay[6:5] = 10

V

V_DD= 3.6 V

R_L= 10 Ω

ON-delay[6:5] = 11

V_DD= 3.6 V

R_L= 10 Ω

Figure 28. t_Dvs. V_BIAS

Figure 27. t_Dvs. V_BIAS

14

10.5

-40°C

25°C

85°C

-40°C

25°C

85°C

10

13

12

11

10

9

9.5

9

8.5

8

7.5

7

8

1

1.3

1.6

1.9

2.2

2.5

2.8

3.1

3.4 3.6

1

1.1

1.2

1.3

1.4

1.5

1.6

1.7

1.8

V_IN(V)

D023a

D023b

V_BIAS= 7.2 V

V_DD= 3.6 V

R_L= 10 Ω

V_BIAS= 3.3 V

V_DD= 3.6 V

R_L= 10 Ω

Slew rate[4:2] =

000

Slew rate[4:2] =

000

Figure 29. t_ONvs. V_IN

Figure 30. t_ONvs. V_IN

275

190

-40°C

25°C

85°C

-40°C

25°C

85°C

180

250

225

200

175

150

125

170

160

150

140

130

120

1

1.2 1.4 1.6 1.8

2

2.2 2.4 2.6 2.8

V_IN(V)

3

3.2 3.4 3.6

1

1.1

1.2

1.3

1.4

V_IN(V)

1.5

1.6

1.7

1.8

D024a

D024b

V_BIAS= 7.2 V

V_DD= 3.6 V

R_L= 10 Ω

V_BIAS= 3.3 V

V_DD= 3.6 V

R_L= 10 Ω

Slew rate[4:2] =

001

Slew rate[4:2] =

001

Figure 31. t_ONvs. V_IN

Figure 32. t_ONvs. V_IN

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Typical Characteristics (continued)

275

190

180

170

160

150

140

130

120

-40°C

25°C

85°C

-40°C

25°C

85°C

250

225

200

175

150

125

1

1.2 1.4 1.6 1.8

2

2.2 2.4 2.6 2.8

V_IN(V)

3

3.2 3.4 3.6

1

1.1

1.2

1.3

1.4

V_IN(V)

1.5

1.6

1.7

1.8

D024a

D024b

V_BIAS= 7.2 V

V_DD= 3.6 V

R_L= 10 Ω

V_BIAS= 3.3 V

V_DD= 3.6 V

R_L= 10 Ω

Slew rate[4:2] =

010

Slew rate[4:2] =

010

Figure 33. t_ONvs. V_IN

Figure 34. t_ONvs. V_IN

800

560

-40°C

25°C

85°C

-40°C

25°C

85°C

750

700

650

600

550

500

450

400

350

540

520

500

480

460

440

420

400

380

1

1.2 1.4 1.6 1.8

2

2.2 2.4 2.6 2.8

V_IN(V)

3

3.2 3.4 3.6

1

1.1

1.3

1.4

V_IN(V)

1.5

1.6

1.7

1.8

D026a

D026b

V_BIAS= 7.2 V

V_DD= 3.6 V

R_L= 10 Ω

V_BIAS= 3.3 V

V_DD= 3.6 V

R_L= 10 Ω

Slew rate[4:2] =

011

Slew rate[4:2] =

011

Figure 35. t_ONvs. V_IN

Figure 36. t_ONvs. V_IN

1560

-40°C

1125

-40°C

25°C

85°C

1100

1075

1050

1025

1000

975

950

925

900

875

25°C

1440

85°C

1320

1200

1080

960

850

825

800

775

840

720

750

1

1.2 1.4 1.6 1.8

2

2.2 2.4 2.6 2.8

V_IN(V)

3

3.2 3.4 3.6

1

1.1

1.3

1.4

V_IN(V)

1.5

1.6

1.7

1.8

D027a

D027b

V_BIAS= 7.2 V

V_DD= 3.6 V

R_L= 10 Ω

V_BIAS= 3.3 V

V_DD= 3.6 V

R_L= 10 Ω

Slew rate[4:2] =

100

Slew rate[4:2] =

100

Figure 37. t_ONvs. V_IN

Figure 38. t_ONvs. V_IN

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Typical Characteristics (continued)

4

3.5

3

-40°C

25°C

-40°C

25°C

85°C

3.5

85°C

3

2.5

2

2.5

2

1.5

1

1.5

1

0.5

0

0.5

0

1

1.2 1.4 1.6 1.8

2

2.2 2.4 2.6 2.8

V_IN(V)

3

3.2 3.4 3.6

1

1.1

1.2

1.3

1.4

V_IN(V)

1.5

1.6

1.7

1.8

D028a

D028b

V_BIAS= 7.2 V

V_DD= 3.6 V

R_L= 10 Ω

V_BIAS= 3.3 V

V_DD= 3.6 V

R_L= 10 Ω

Figure 39. t_Fvs. V_IN

Figure 40. t_Fvs. V_IN

4

3.5

3

4

3.5

3

2.5

2

2.5

2

1.5

1

1.5

1

-40°C

25°C

85°C

-40°C

25°C

85°C

0.5

0

0.5

0

1

1.3

1.6

1.9

2.2

V_IN(V)

2.5

2.8

3.1

3.4 3.6

1

1.08 1.16 1.24 1.32 1.4 1.48 1.56 1.64 1.72 1.8

V_IN(V)

D029a

D029b

V_BIAS= 7.2 V

V_DD= 3.6 V

R_L= 10 Ω

V_BIAS= 3.3 V

V_DD= 3.6 V

R_L= 10 Ω

Figure 41. t_OFFvs. V_IN

Figure 42. t_OFFvs. V_IN

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9 Detailed Description

9.1 Overview

The TPS22994 is a GPIO controllable and I²C programmable, quad-channel load switch. The device comes in a

20-pin QFN package and is designed to handle up to 3.6 V and 1 A per channel (per VINx/VOUTx). The VBIAS

pin of the device is designed to interface directly with battery voltages or adapter input voltages as high as 17.2

V. To increase efficiency during standby power, the device implements each channel with an N-channel

MOSFET without the use of a chargepump. This allows the quiescent current (I_Q,VBIAS) to be much lower than

traditional GPIO-based load switches, thus increasing efficiency during standby.

The TPS22994 can be programmed via standard I²C commands. This allows the user to select between 5 slew

rates, 4 on-delays, and 4 quick output discharge (QOD) options. The combination of these options allows the

user to program the power sequencing for downstream modules via software. Each individual channel can also

be controlled (enabling and disabling channels only) via GPIO when I²C communication is not present. The

TPS22994 contains a special function called SwitchALL^TMthat allows multiple devices (either the TPS22993 or

TPS22994) to be enabled or disabled synchronously via a single I²C command, allowing the user to switch

system power states synchronously.

9.2 Functional Block Diagram

Power supply

and bandgap

VBIAS

VIN1

Driver

VOUT1

PD_EN

ON1

ON2

ON3

ON4

VIN2

GPIO ON

Buffer

Driver

VOUT2

PD_EN

ADD1

ADD2

ADD3

Address

Buffers &

Level Shifters

I2C

Digital Control

VIN3

Driver

VDD

VOUT3

SCL

SDA

I2C

PD_EN

SCL/SDA

Buffers &

Level Shifters

VIN4

Driver

VOUT4

PD_EN

* PD_EN = Pulldown Enable

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9.3 Feature Description

9.3.1 Operating Frequency

The TPS22994 is designed to be compatible with fast-mode plus and operate up to 1 MHz clock frequency for

bus communication. The device is also compatible with standard-mode (100 kHz) and fast-mode (400 kHz). This

device can reside on the same bus as high-speed mode (3.4MHz) devices, but the device is not designed to for

I²C commands for frequencies greater than 1 MHz. See table below for characteristics of the fast-mode plus,

fast-mode, and standard-mode bus speeds.

Table 1. I²C Interface Timing Requirements⁽¹⁾

STANDARD

MODE

FAST MODE

PLUS (FM+)

I²C BUS

FAST MODE

I²C BUS

PARAMETER

UNIT

MIN

0

MAX

MIN

0

MAX

MIN

0

MAX

f_scl

t_sch

t_scl

t_sp

I²C clock frequency

I²C clock high time

I²C clock low time

I²C spike time

I²C serial data setup time

I²C serial data hold time

100

50

400

1000

kHz

μs

ns

μs

4

0.6

1.3

0.26

0.5

4.7

50

t_sds

t_sdh

t_icr

250

0

100

0

50

0

I2C input rise time

1000

20

300

120

t_buf

t_sts

t_sth

t_sps

I²C bus free time between Stop and Start

I²C Start or repeater Start condition setup time

I²C Start or repeater Start condition hold time

I²C Stop condition setup time

4.7

4

1.3

0.6

0.3

0.5

0.26

4

t_vd(data)Valid data time; SCL low to SDA output valid

3.45

0.9

0.45

Valid data time of ACK condition; ACK signal from SCL

low to SDA (out) low

t_vd(ack)

0.3

μs

(1) over operating free-air temperature range (unless otherwise noted)

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9.3.2 SDA/SCL Pin Configuration

The SDA and SCL pins of the device operate use an open-drain configuration, and therefore, need pull up

resistors to communicate on the I²C bus. The graph below shows recommended values for max pull-up resistors

(R_P) and bus capacitances (C_b) to ensure proper bus communications. The SDA and SCL pins should be pulled

up to VDD through an appropriately sized R_Pbased on the graphs below.

9.3.3 Address (ADDx) Pin Configuration

The TPS22994 can be configured with an unique I²C slave addresses by using the ADDx pins. There are 3

ADDx pins that can be tied high to VDD or low to GND (independent of each other) to get up to 7 different slave

addresses. The ADDx pins should be tied to GND if the I²C functionality of the device is not to be used. External

pull-up resistors for the ADDx are optional as the ADDx inputs are high impedance. The following table shows

the ADDx pin tie-offs with their associated slave addresses (assuming an eight bit word, where the LSB is the

read/write bit and the device address bits are the 7 MSB bits) :

Hex Address

E0/E1

ADD3

GND

VDD

ADD2

ADD1

GND

VDD

GND

VDD

GND

VDD

GND

E2/E3

GND

E4/E5

VDD

E6/E7

VDD

E8/E9

GND

EA/EB

EC/ED

GND

VDD

Invalid unique device address.

EE

This address is the SwitchALL^TMaddress.

9.3.4 On-Delay Control

Using the I²C interface, the configuration register for each channel can be set for different ON delays for power

sequencing. The typical options for delay are as follows (see Switching Characteristics, V_BIAS= 7.2 V table):

00 = 11 µs delay (default register value)

01 = 105 µs delay

10 = 330 µs delay

11 = 950 µs delay

It is not recommended to change the delay value for the duration of the delay that is programmed when the

channel is enabled (except for ON-delay setting of '00' which requires a minimum of 100µs wait time before

changing the setting). This could result in erratic behavior where the output could toggle unintentionally but would

eventually recover by the end of the delay time programmed at the time of channel enable.

9.3.5 Slew Rate Control

Using the I²C interface, the configuration register for each channel can be set for different slew rates for inrush

current control and power sequencing. The typical options for slew rate are as follows (see Switching

Characteristics table for VOUTx rise times):

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000 = 1 µs/V

001 = 150 µs/V

010 = 250 µs/V

011 = 460 µs/V (default register value)

100 = 890 µs/V

101 = invalid slew rate

110 = invalid slew rate

111 = reserved

9.3.6 Quick Output Discharge (QOD) Control

Using the I²C interface, the configuration register for each channel can be set for different output discharge

resistors. The typical options for QOD are as follows (see Electrical Characteristics table):

00 = 110 Ω

01 = 490 Ω

10 = 951 Ω (default register value)

11 = No QOD (high impedance)

9.3.7 Mode Registers

Using the I²C interface, the mode registers can be programmed to the desired on/off status for each channel.

The contents of these registers are copied over to the control registers when a SwitchALL™ command is issued,

allowing all channels of the device to transition to their desired output states synchronously. See the I²C Protocol

section and the Application Scenario section for more information on how to use the mode registers in

conjunction with the SwitchALL^TMcommand.

9.3.8 SwitchALL™ Command

I²C controlled channels can respond to a common slave address. This feature allows multiple load switches on

the same I²C bus to respond simultaneously. The SwitchALL™ address is EEh. During a SwitchALL™

command, the lower four bits (bits 0 through 3) of the mode register is copied to the lower four bits (bits 0

through 3) of the control register. The mode register to be invoked is referenced in the body of the SwitchALL™

command. The structure of the SwitchALL™ command is as follows (as shown in Figure 43):

<start><SwitchALL™ addr><mode addr><stop>. See the I²C Protocol section and the Application Scenario

section for more information on how to use the SwitchALL^TMcommand in conjunction with the mode registers.

SCL

SwitchALL^TMAddress

Mode Register Address

SDA ST 1

1

0

1

0

A D7 D6 D5 D4 D3 D2 D1 D0 A SP

Start

W/R

Ack

from

slave

Ack. from slave

Figure 43. Composition of SwitchALL™ Command

9.3.9 V_DDSupply For I²C Operation

Stop

The SDA and SCL pins of the device must be pulled up to the VDD voltage of the device for proper I²C bus

communication. See Recommended Operating Conditions for VDD operating range.

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9.3.10 Input Capacitor (Optional)

To limit the voltage drop on the input supply caused by transient in-rush currents when the switch turns on into a

discharged load capacitor or short-circuit, a capacitor needs to be placed between V_INand GND. A 1-µF ceramic

capacitor, C_IN, placed close to the pins, is usually sufficient. Higher values of C_INcan be used to further reduce

the voltage drop during high-current application. When switching heavy loads, it is recommended to have an

input capacitor about 10 times higher than the output capacitor to avoid excessive voltage drop. For the fastest

slew rate setting of the device, a CIN to CL ratio of at least 100 to 1 is recommended to avoid excessive voltage

drop.

9.3.11 Output Capacitor (Optional)

Due to the integrated body diode of the NMOS switch, a C_INgreater than C_Lis highly recommended. A C_L

greater than C_INcan cause V_OUTto exceed V_INwhen the system supply is removed. This could result in current

flow through the body diode from V_OUTto V_IN. A C_INto C_Lratio of at least 10 to 1 is recommended for minimizing

V_INdip caused by inrush currents during startup. For the fastest slew rate setting of the device, a CIN to CL ratio

of at least 100 to 1 is recommended to minimize V_INdip caused by inrush currents during startup.

9.3.12 I²C Protocol

The following section will cover the standard I²C protocol used in the TPS22994. In the I²C protocol, the following

basic blocks are present in every command (except for the SwitchALL^TMcommand):

•

Start/stop bit – marks the beginning and end of each command.

Slave address – the unique address of the slave device.

Sub address – this includes the register address and the auto-increment bit.

Data byte – data being written to the register. Eight bits must always be transferred even if a single bit is

being written or read.

•

Auto-increment bit – setting this bit to ‘1’ turns on the auto-increment functionality; setting this bit to ‘0’ turns

off the auto-increment functionality.

Write/read bit – this bit signifies if the command being sent will result in reading from a register or writing to a

register. Setting this bit to ‘0’ signifies a write, and setting this bit to ‘1’ signifies a read.

Acknowledge bit – this bit signifies if the master or slave has received the preceding data byte.

9.3.12.1 Start and Stop Bit

In the I²C protocol, all commands contain a START bit and a STOP bit. A START bit, defined by high to low

transition on the SDA line while SCL is high, marks the beginning of a command. A STOP bit, defined by low to

high transition on the SDA line while SCL is high, marks the end of a command. The START and STOP bits are

generated by the master device on the I²C bus. The START bit indicates to other devices that the bus is busy,

and some time after the STOP bit the bus is assumed to be free.

9.3.12.2 Auto-increment Bit

The auto-increment feature in the I²C protocol allows users to read from and write to consecutive registers in

fewer clock cycles. Since the register addresses are consecutive, this eliminates the need to resend the register

address. The I²C core of the device automatically increments the register address pointer by one when the auto-

increment bit is set to ‘1’. When this bit is set to ‘0’, the auto-increment functionality is disabled.

9.3.12.3 Write Command

During the write command, the write/read bit is set to ‘0’, signifying that the register in question will be written to.

Figure 44 the composition of the write protocol to a single register:

SCL

Slave Address

Sub Address

Data Byte

SDA ST A6 A5 A4 A3 A2 A1 A0

0

A

0

A

D7 D6 D5 D4 D3 D2 D1 D0

A

D7 D6 D5 D4 D3 D2 D1 D0 A SP

Start

W/R

Ack. from slave

Auto-Inc.

Ack

from

slave

Data to Register N

Ack

from

slave

Data to Register N

Ack Stop

from

slave

Register Address N

Figure 44. Data Write to a Single Register

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Number of clock cycles for single register write: 29

If multiple consecutive registers must be written to, a short-hand version of the write command can be used.

Using the auto-increment functionality of I²C, the device will increment the register address after each byte.

Figure 45 shows the composition of the write protocol to multiple consecutive registers:

SCL

Slave Address

Sub Address

Data Byte

SDA ST A6 A5 A4 A3 A2 A1 A0

0

A

1

0

A

D7 D6 D5 D4 D3 D2 D1 D0

A

D7 D6 D5 D4 D3 D2 D1 D0 A

Start

W/R

Ack. from slave

Auto-Inc.

Ack

from

slave

Data to Register N

Ack

from

slave

Data to Register N+1 Ack

from

slave

Register Address N

Figure 45. Data Write to Consecutive Registers

Number of clock cycles for consecutive register write: 20 + (Number of registers) x 9

The write command is always ended with a STOP bit after the desired registers have been written to. If multiple

non-consecutive registers must be written to, then the format in Figure 44 must be followed.

9.3.12.4 Read Command

During the read command, the write/read bit is set to ‘1’, signifying that the register in question will be read from.

However, a read protocol includes a “dummy” write sequence to ensure that the memory pointer in the device is

pointing to the correct register that will be read. Failure to precede the read command with a write command may

result in a read from a random register. Figure 46 shows the composition of the read protocol to a single register:

SCL

Slave Address

Sub Address

Slave Address

Data Byte

SDA ST A6 A5 A4 A3 A2 A1 A0

0

A

0

A

RS A6 A5 A4 A3 A2 A1 A0

1

A

D7 D6 D5 D4 D3 D2 D1 D0 NA SP

Start

W/R

Ack. from slave

Auto-Inc.

Ack Re-Start

from

slave

W/R

Data from Register N

Stop

Register Address

Ack. from slave

No Ack. from master (message ends)

Continued

Figure 46. Data Read to a Single Register

Number of clock cycles for single register read: 39

If multiple registers must be read from, a short-hand version of the read command can be used. Using the auto-

increment functionality of I²C, the device will increment the register address after each byte. Figure 47 shows the

composition of the read protocol to multiple consecutive registers:

SCL

Slave Address

Sub Address

Slave Address

Data Byte

SDA ST A6 A5 A4 A3 A2 A1 A0

0

A

1

0

A RS A6 A5 A4 A3 A2 A1 A0

1

A

D7 D6 D5 D4 D3 D2 D1 D0

Start

W/R

Ack. from slave

Auto-Inc.

Ack Re-Start

from

slave

W/R

Ack. from slave

Data from Register N

Register Address

Continued

Data Byte

A

D7 D6 D5 D4 D3 D2 D1 D0

Data from Register N+1

A D7 D6 D5 D4 D3 D2 D1 D0 NA SP

Data from Register N+2

Stop

Ack. from master

No Ack. from master (Message ends)

Figure 47. Data Read to Consecutive Registers

Number of clock cycles for consecutive register write: 30 + (Number of registers) x 9

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The read command is always ended with a STOP bit after the desired registers have been read from. If multiple

non-consecutive registers must be read from, then the format in Figure 46 must be followed.

9.3.12.5 SwitchALL^TMCommand

The SwitchALL^TMcommand allows multiple devices in the same I²C bus to respond synchronously to the same

command from the master. Every TPS22994 device has a shared address which allows for multiple devices to

respond or execute a pre-determined action with a single command. Figure 48 shows the composition of the

SwitchALL^TMcommand:

SCL

SwitchALL^TMAddress

Mode Register Address

SDA ST 1

Start

1

0

1

0

A D7 D6 D5 D4 D3 D2 D1 D0 A SP

W/R

Ack

from

slave

Ack. from slave

Stop

Figure 48. SwitchALL^TMCommand Structure

Number of clock cycles for a SwitchALL^TMcommand: 20

9.4 Device Functional Modes

9.4.1 I²C Control

When power is applied to VBIAS, the device comes up in its default mode of GPIO operation where the channel

outputs can be controlled solely via the ON pins. At any time, if SDA and SCL are present and valid, the device

can be configured to be controlled via I²C (if in GPIO control) or GPIO (if in I²C control).

The control register (address 05h) can be configured for GPIO or I²C enable on a per channel basis.

9.4.2 GPIO Control

There are four ON pins to enable/disable the four channels. Each ON pin controls the state of the switch by

default upon power up. Asserting ON high enables the switch. ON is active high and has a low threshold, making

it capable of interfacing with low-voltage signals. The ON pin is compatible with standard GPIO logic threshold. It

can be used with any microcontroller with 1.2 V or higher voltage GPIO.

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9.5 Register Map

Configuration registers (default register values shown below)

Channel 1 configuration register (Address: 01h)

BIT

B7

B6

B5

B4

B3

B2

B1

B0

QUICK OUTPUT

DISCHARGE

DESCRIPTION

DEFAULT

X

ON-DELAY

SLEW RATE

1

X

0

1

0

Channel 2 configuration register (Address: 02h)

BIT

B7

B6

B5

B4

B3

B2

B1

B0

QUICK OUTPUT

DISCHARGE

DESCRIPTION

DEFAULT

X

ON-DELAY

SLEW RATE

1

X

0

1

0

Channel 3 configuration register (Address: 03h)

BIT

B7

B6

B5

B4

B3

B2

B1

B0

QUICK OUTPUT

DISCHARGE

DESCRIPTION

DEFAULT

X

ON-DELAY

SLEW RATE

1

X

0

1

0

Channel 4 configuration register (Address: 04h)

BIT

B7

B6

B5

B4

B3

B2

B1

B0

QUICK OUTPUT

DISCHARGE

DESCRIPTION

DEFAULT

X

ON-DELAY

SLEW RATE

1

X

0

1

0

Control register (default register values shown below)

Control register (Address: 05h)

BIT

B7

B6

B5

B4

B3

B2

B1

B0

GPIO/I²C ch GPIO/I²C ch GPIO/I²C ch GPIO/I²C ch ENABLE CH ENABLE CH ENABLE CH ENABLE CH

DESCRIPTION

DEFAULT

4

3

2

1

4

3

2

1

0

Mode registers (default register values shown below)

Mode1 (Address: 06h)

BIT

B7

X

B6

X

B5

X

B4

X

B3

B2

B1

B0

ENABLE CH ENABLE CH ENABLE CH ENABLE CH

DESCRIPTION

DEFAULT

4

3

2

1

X

0

Mode2 (Address: 07h)

BIT

B7

X

B6

X

B5

X

B4

X

B3

B2

B1

B0

ENABLE CH ENABLE CH ENABLE CH ENABLE CH

DESCRIPTION

DEFAULT

4

3

2

1

X

0

Mode3 (Address: 08h)

BIT

B7

X

B6

X

B5

X

B4

X

B3

B2

B1

B0

ENABLE CH ENABLE CH ENABLE CH ENABLE CH

DESCRIPTION

DEFAULT

4

3

2

1

X

0

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Mode4 (Address: 09h)

BIT

B7

X

B6

X

B5

X

B4

X

B3

B2

B1

B0

ENABLE CH ENABLE CH ENABLE CH ENABLE CH

DESCRIPTION

DEFAULT

4

0

3

0

2

0

1

0

X

Mode5 (Address: 0Ah)

BIT

B7

X

B6

X

B5

X

B4

X

B3

B2

B1

B0

ENABLE CH ENABLE CH ENABLE CH ENABLE CH

DESCRIPTION

DEFAULT

4

3

2

1

X

0

Mode6 (Address: 0Bh)

BIT

B7

X

B6

X

B5

X

B4

X

B3

B2

B1

B0

ENABLE CH ENABLE CH ENABLE CH ENABLE CH

DESCRIPTION

DEFAULT

4

3

2

1

X

0

Mode7 (Address: 0Ch)

BIT

B7

X

B6

X

B5

X

B4

X

B3

B2

B1

B0

ENABLE CH ENABLE CH ENABLE CH ENABLE CH

DESCRIPTION

DEFAULT

4

3

2

1

X

0

Mode8 (Address: 0Dh)

BIT

B7

X

B6

X

B5

X

B4

X

B3

B2

B1

B0

ENABLE CH ENABLE CH ENABLE CH ENABLE CH

DESCRIPTION

DEFAULT

4

3

2

1

X

0

Mode9 (Address: 0Eh)

BIT

B7

X

B6

X

B5

X

B4

X

B3

B2

B1

B0

ENABLE CH ENABLE CH ENABLE CH ENABLE CH

DESCRIPTION

DEFAULT

4

3

2

1

X

0

Mode10 (Address: 0Fh)

BIT

B7

B6

X

B5

X

B4

X

B3

B2

B1

B0

ENABLE CH ENABLE CH ENABLE CH ENABLE CH

DESCRIPTION

DEFAULT

X

4

3

2

1

X

0

Mode11 (Address: 10h)

BIT

B7

B6

X

B5

X

B4

X

B3

B2

B1

B0

ENABLE CH ENABLE CH ENABLE CH ENABLE CH

DESCRIPTION

DEFAULT

X

4

3

2

1

X

0

Mode12 (Address: 11h)

BIT

B7

B6

X

B5

X

B4

X

B3

B2

B1

B0

ENABLE CH ENABLE CH ENABLE CH ENABLE CH

DESCRIPTION

DEFAULT

X

4

3

2

1

X

0

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10 Applications and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

10.1 Application Information

This section will cover applications of I²C in the TPS22994. Registers discussed here are specific to the

TPS22994.

10.1.1 Input Capacitor (Optional)

To limit the voltage drop on the input supply caused by transient in-rush currents when the switch turns on into a

discharged load capacitor or short-circuit, a capacitor needs to be placed between V_INand GND. A 1-µF ceramic

capacitor, C_IN, placed close to the pins, is usually sufficient. Higher values of C_INcan be used to further reduce

the voltage drop during high-current application. When switching heavy loads, it is recommended to have an

input capacitor about 10 times higher than the output capacitor to avoid excessive voltage drop. For the fastest

slew rate setting of the device, a CIN to CL ratio of at least 100 to 1 is recommended to avoid excessive voltage

drop.

10.1.2 Output Capacitor (Optional)

Due to the integrated body diode of the NMOS switch, a C_INgreater than C_Lis highly recommended. A C_L

greater than C_INcan cause V_OUTto exceed V_INwhen the system supply is removed. This could result in current

flow through the body diode from V_OUTto V_IN. A C_INto C_Lratio of at least 10 to 1 is recommended for minimizing

V_INdip caused by inrush currents during startup. For the fastest slew rate setting of the device, a CIN to CL ratio

of at least 100 to 1 is recommended to minimize V_INdip caused by inrush currents during startup.

10.1.3 Switch from GPIO Control to I²C Control (and vice versa)

The TPS22994 can be switched from GPIO control to I²C (and vice versa) mode by writing to the control register

of the device. Each device has a single control register and is located at register address 05h. The register’s

composition is as follows:

Control register (Address: 05h)

BIT

B7

B6

B5

B4

B3

B2

B1

B0

DESCRIPTION

GPIO/I²C CH GPIO/I²C CH GPIO/I²C CH GPIO/I²C CH ENABLE CH ENABLE CH ENABLE CH ENABLE CH

4

0

3

0

2

0

1

0

4

0

3

0

2

0

1

0

DEFAULT

Figure 49. Control Register Composition

The higher four bits of the control register dictates if the device is in GPIO control (bit set to ‘0’) or I²C control (bit

set to ‘1’). The transition from GPIO control to I²C control can be made with a single write command to the

control register. See Figure 44 for the composition of a single write command. It is recommended that the

channel of interest is transitioned from GPIO control to I²C control with the first write command and followed by a

second write command to enable the channel via I²C control. This will ensure a smooth transition from GPIO

control to I²C control.

10.1.4 Configuration of Configuration Registers

The TPS22994 contains four configuration registers (one for each channel) and are located at register addresses

01h through 04h. The register’s composition is as follows (single channel shown for clarity):

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Channel 1 configuration register (Address: 01h)

BIT

B7

B6

B5

B4

B3

B2

B1

B0

DESCRIPTION

X

ON-DELAY

SLEW RATE

QUICK OUTPUT

DISCHARGE

DEFAULT

X

0

1

0

1

0

Figure 50. Configuration Register Composition

10.1.4.1 Single Register Configuration

A single configuration register can be written to using the write command sequence shown in Figure 44.

Multiple register writes to non-consecutive registers is treated as multiple single register writes and follows the

same write command as that of a single register write as shown in Figure 44.

10.1.4.2 Multi-register Configuration (Consecutive Registers)

Multiple consecutive configuration registers can be written to using the write command sequence shown in

Figure 45.

10.1.5 Configuration of Mode Registers

The TPS22994 contains twelve mode registers located at register addresses 06h through 11h. These mode

registers allow the user to turn-on or turn-off multiple channels in a single TPS22994 or multiple channels

spanning multiple TPS22994 devices with a single SwitchALL^TMcommand.

For example, an application may have multiple power states (e.g. sleep, active, idle, etc.) as shown in Figure 51.

SwitchALL^TMcommand with Mode2

register

SwitchALL^TMcommand with Mode1

register

Sleep

Active

Idle

Figure 51. Application Example of Power States

In each of the different power states, different combinations of channels may be on or off. Each power state may

be associated with a single mode register (Mode1, Mode2, etc.) across multiple TPS22994 as shown in Table 2.

For example, with 7 quad-channel devices, up to 28 rails can be enabled/disabled with a single SwitchALL^TM

command.

Table 2. Application Example of State of Each Channel in Multiple TPS22994 in Different Power States

Load Switch #1

Load Switch #2

Load Switch #N

Mode

Register

Power

State

Ch. 1

Off

Ch. 2

Off

Ch. 3

Off

Ch. 4

Off

Ch. 1

Off

Ch. 2

Off

Ch. 3

Off

Ch. 4

Off

Ch. 1

Off

Ch. 2

Off

Ch. 3

Off

Ch. 4

Off

Mode1

Mode2

Mode3

Sleep

Active

Idle

On

Off

On

Off

On

Off

On

Off

On

Off

On

Off

On

28

TPS22994

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ZHCSCV5B –AUGUST 2014–REVISED SEPTEMBER 2014

The contents of the lower four bits of the mode register is copied into the lower four bits of the control register

during an SwitchALL^TMcommand. The address of the mode register to be copied is specified in the SwitchALL^TM

command (see Figure 48 for the structure of the SwitchALL^TMcommand). By executing a SwitchALL^TM

command, the application will apply the different on/off combinations for the various power states with a single

command rather than having to turn on/off each channel individually by re-configuring the control register. This

reduces the latency and allows the application to control multiple channels synchronously. The example above

shows the application using three mode registers, but the TPS22994 contains twelve mode registers, allowing for

up to twelve power states.

The mode register’s composition is as follows (single mode register shown for clarity):

Mode1 (Address: 06h)

BIT

B7

B6

B5

B4

B3

B2

B1

B0

DESCRIPTION

X

ENABLE

CH 4

ENABLE

CH 3

ENABLE

CH 2

ENABLE

CH 1

DEFAULT

X

0

Figure 52. Mode Register Composition

The lower four bits of the mode registers are copied into the lower four bits of the control register during an all-

call command.

10.1.6 Turn-on/Turn-off of Channels

By default upon power up VBIAS, all the channels of the TPS22994 are controlled via the ONx pins. Using the

I²C interface, each channel be controlled via I²C control as well. The channels of the TPS22994 can also be

switched on or off by writing to the control register of the device. Each device has a single control register and is

located at register address 05h. The register’s composition is as follows:

Control Register (Address: 05h)

BIT

B7

B6

B5

B4

B3

B2

B1

B0

GPIO/I²C CH GPIO/I²C CH GPIO/I²C CH GPIO/I²C CH ENABLE CH ENABLE CH ENABLE CH ENABLE CH

DESCRIPTION

DEFAULT

4

0

3

0

2

0

1

0

4

0

3

0

2

0

1

0

Figure 53. Control Register Composition

The lower four bits of the control register dictate if the channels of the device are off (bit set to ‘0’) or on (bit set

to ‘1’) during I²C control. The transition from off to on can be made with a single write command to the control

register. See Figure 44 for the composition of a single write command.

29

TPS22994

ZHCSCV5B –AUGUST 2014–REVISED SEPTEMBER 2014

www.ti.com.cn

10.2 Typical Application

10.2.1 Tying Multiple Channels in Parallel

Two or more channels of the device can be tied in parallel for applications that require lower R_ONand/or more

continous current. Tying two channels in parallel will result in half of the R_ONand two times the I_MAXcapability.

Tying three channels in parallel will result in one-third of the R_ONand three times the I_MAXcapability. Tying four

channels in parallel will result in one-fourth of the R_ONand four times the I_MAXcapability. For the channels that

are tied in parallel, it is recommended that the ONx pins be tied together for synchronous control of the channels

when in GPIO control. In I²C control, all four channels can be enabaled or disabled synchronously by writing to

the control register of the device. Figure 54 shows an application example of tying all four channels in parallel.

VBIAS

(2.7 V to 17.2 V)

VIN1

VOUT1

PMIC or

PMU

ON1

C_L

R_L

VIN2

VOUT2

VOUT3

ON2

TPS22994

VIN3

ON3

VOUT4

VIN4

ON4

ADD1

ADD2

ADD3

GPIO >>

SDA SCL

µC

VDD

(1.62 to 3.6)

Figure 54. Parallel Channels

10.2.1.1 Design Requirements

Refer to Design Requirements .

10.2.1.2 Detailed Design Procedure

Refer to Detailed Design Procedure.

The only difference between single channel and multiple channels in parallel is the resulting R_ONand voltage

drop from VINx to VOUTx. Thus, the design procedure is identical to Detailed Design Procedure. The VINx to

VOUTx voltage drop in the device is determined by the R_ONof the device and the load current. The R_ONof the

device depends upon the VIN conditions of the device. Refer to the R_ONspecification of the device in the

Electrical Characteristics table of this datasheet. Once the R_ONof the device is determined based upon the VINx

conditions, use the following equation to calculate the VINx to VOUTx voltage drop:

∆V = I_LOAD× (R_ON/K)

(1)

Where:

ΔV = voltage drop from VINx to VOUTx

I_LOAD= load current

R_ON= On-resistance of the device for a specific V_IN

K = number of channels in parallel (2, 3, or 4)

An appropriate I_LOADmust be chosen such that the I_MAXspecification per channel of the device is not violated.

10.2.1.3 Application Curves

Refer to Application Curves.

30

TPS22994

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ZHCSCV5B –AUGUST 2014–REVISED SEPTEMBER 2014

Typical Application (continued)

10.2.2 Cold Boot Programming of All Registers

Since the TPS22994 has a digital core with volatile memory, upon power cycle of the VBIAS pin, the registers

will revert back to their default values (see register map for default values). Therefore, the application must

reprogram the configuration registers, control register, and mode registers if non-default values are desired. The

TPS22994 contains 17 programmable registers (4 configuration registers, 1 control register, 12 mode registers)

in total.

During cold boot when the microcontroller and the I²C bus is not yet up and running, the channels of the

TPS22994 can still be enabled via GPIO control. One method to achieve this is to tie the ONx pin to the

respective VINx pin for the channels that need to turn on by default during cold boot. With this method, when

VINx is applied to the TPS22994, the channel will be enabled as well. Once the I²C bus is active, the channel

can be switched over to I²C control to be disabled. See Figure 55 for an example of how the ONx pins can be

tied to VINx for default enable during cold boot.

VBIAS

(2.7 V to 17.2 V)

VIN1

VOUT1

ON1

C_L

R_L

VIN2

VOUT2

VOUT3

ON2

PMIC or

PMU

TPS22994

VIN3

ON3

VOUT4

VIN4

ON4

ADD1

C_L

ADD2

ADD3

SDA SCL

µC

VDD

(1.62 to 3.6)

Figure 55. Cold Boot Programming

10.2.2.1 Design Requirements

Refer to Design Requirements.

10.2.2.2 Detailed Design Procedure

Refer to Design Requirements.

10.2.2.3 Application Curves

Refer to Application Curves.

31

TPS22994

ZHCSCV5B –AUGUST 2014–REVISED SEPTEMBER 2014

www.ti.com.cn

Typical Application (continued)

10.2.3 Power Sequencing Without I²C

It is also possible to power sequence the channels of the device during a cold boot when there is no I²C bus

present for control. One method to accomplish this it to tie the VOUT of one channel to the ON pin of the next

channel in the sequence. For example, if the desired power up sequence is VOUT3, VOUT1, VOUT2, and

VOUT4 (in that order), then the device can be configured for GPIO control as shown in Figure 56. The device will

power up with default slew rate, ON-delay, and QOD values as specified in the register map.

VBIAS

(2.7 V to 17.2 V)

VIN1

VOUT1

ON1

C_L

R_L

VIN2

VOUT2

VOUT3

ON2

C_L

PMIC or

PMU

TPS22994

VIN3

ON3

C_L

VOUT4

VIN4

ON4

ADD1

C_L

R_L

ADD2

ADD3

SDA SCL

µC

VDD

(1.62 to 3.6)

Figure 56. Power Sequencing Without I²C Schematic

10.2.3.1 Design Requirements

10.2.3.1.1 Reading From the Registers

Reading any register from the TPS22994 follows the same standard I²C read protocol as outlined in the I²C

Protocol section of this datasheet.

For this design example, use the following as the input parameters:

DESIGN PARAMETER

V_INx

EXAMPLE VALUE

3.3 V

1 A

Load Current

10.2.3.2 Detailed Design Procedure

To begin the design process, the designer needs to know the following:

•

V_INxvoltage

Load Current

32

TPS22994

www.ti.com.cn

ZHCSCV5B –AUGUST 2014–REVISED SEPTEMBER 2014

10.2.3.2.1 VIN to VOUT Voltage Drop

The VINx to VOUTx voltage drop in the device is determined by the R_ONof the device and the load current. The

R_ONof the device depends upon the VIN conditions of the device. Refer to the R_ONspecification of the device in

the Electrical Characteristics table of this datasheet. Once the R_ONof the device is determined based upon the

VINx conditions, use Equation 2 to calculate the VINx to VOUTx voltage drop:

∆V = I_LOAD× R_ON

(2)

Where:

ΔV = voltage drop from VINx to VOUTx

I_LOAD= load current

R_ON= On-resistance of the device for a specific V_IN

An appropriate I_LOADmust be chosen such that the I_MAXspecification of the device is not violated.

10.2.3.2.2 Inrush Current

To determine how much inrush current will be caused by the C_Lcapacitor, use Equation 3:

dV_OUT

I

= C_L´

INRUSH

dt

(3)

Where:

I_INRUSH= amount of inrush caused by C_L

C_L= capacitance on VOUTx

dt = rise time in VOUT during the ramp up of VOUTx when the device is enabled

dV_OUT= change in VOUT during the ramp up of VOUTx when the device is enabled

An appropriate C_Lvalue should be placed on VOUTx such that the I_MAXspecifications of the device are not

violated.

10.2.3.3 Application Curves

4

3.5

3

4

3.5

3

2.5

2

2.5

2

1.5

1

1.5

1

ONx

Slew 000

Slew 001

Slew 010

Slew 011

Slew 100

ONx

On Delay 00

On Delay 01

On Delay 10

On Delay 11

0.5

0

0.5

0

-0.5

-0.4

0.1

0.6

1.1

1.6

Time (ms)

2.1

2.6

3.1

3.6

-0.2

0

0.2 0.4 0.6 0.8

Time (s)

1

1.2 1.4 1.6 1.8

D00412

D045

V_BIAS= 7.2V

V_INx= 3.6V

T_A= 25°C

V_DD= 3.6V

V_BIAS= 7.2V

V_INx= 3.6V

T_A= 25°C

V_DD= 3.6V

R_L= 10Ω

Figure 57. +Power Up With Different Slew Rate Settings

Figure 58. Power Up With Different tD Settings

33

TPS22994

ZHCSCV5B –AUGUST 2014–REVISED SEPTEMBER 2014

www.ti.com.cn

4

3.5

3

ONx

3.5

3

QOD 00

QOD 01

QOD 10

QOD 11

2.5

2

2.5

2

ONx

QOD 00

QOD 01

QOD 10

QOD 11

1.5

1

1.5

1

0.5

0

0.5

0

-0.5

-1

-1.5

-0.5

-1

0

1

2

3

4

4.5

-0.1

0

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

Time (ms)

Time (Ps)

D043

D044

V_BIAS= 7.2V

V_INx= 3.6V

T_A= 25°C

V_DD= 3.6V

V_BIAS= 7.2V

R_L= Open

V_INx= 3.6V

T_A= 25°C

V_DD= 3.6V

R_L= 10Ω

Figure 59. Power Down With Different QOD Settings With

Figure 60. Power Down With Different QOD Settings With

R_L= Open

R_L= 10 Ω

V_BIAS= 7.2V

V_INx= 3.6V

T_A= 25°C

V_DD= 3.6V

V_BIAS= 7.2V

V_INx= 3.6V

T_A= 25°C

V_DD= 3.6V

R_L= 10Ω

This example shows the channel of the device being turned on

when a I2C "enable" command is written to the register.

This example shows the channel of the device being turned on

when a I2C "enable" command is written to the register.

Figure 61. I2C Read Sequence

Figure 62. I2C Write Sequence

V_BIAS= 7.2V

V_INx= 3.6V

T_A= 25°C

V_DD= 3.6V

R_L= 10Ω

Figure 63. Enabling Channel 1 Across Two TPS22994 Devices With the SwitchALL^TMCommand

34

TPS22994

www.ti.com.cn

ZHCSCV5B –AUGUST 2014–REVISED SEPTEMBER 2014

11 Layout

11.1 Board Layout

•

VINx and VOUTx traces should be as short and wide as possible to accommodate for high current.

Use vias under the exposed thermal pad for thermal relief for high current operation.

The VINx terminals should be bypassed to ground with low ESR ceramic bypass capacitors. The typical

recommended bypass capacitance is 1-µF ceramic with X5R or X7R dielectric. This capacitor should be

placed as close to the device terminals as possible.

•

The VOUTx terminals should be bypassed to ground with low ESR ceramic bypass capacitors. The typical

recommended bypass capacitance is one-tenth of the VIN bypass capacitor of X5R or X7R dielectric rating.

This capacitor should be placed as close to the device terminals as possible.

•

The VBIAS terminal should be bypassed to ground with low ESR ceramic bypass capacitors. The typical

recommended bypass capacitance is 0.1-µF ceramic with X5R or X7R dielectric.

The VDD terminal should be bypassed to ground with low ESR ceramic bypass capacitors. The typical

recommended bypass capacitance is 0.1-µF ceramic with X5R or X7R dielectric.

ADDx pins should be tied high to VDD through a pull-up resistor or tied low to GND through a pull-down

resistor.

The maximum IC junction temperature should be restricted to 125°C under normal operating conditions. To

calculate the maximum allowable power dissipation, P_D(max)for a given output current and ambient temperature,

use the following equation:

T

_J(max)- T_A

P

=

D(max)

Q_JA

(4)

Where:

P_D(max)= maximum allowable power dissipation

T_J(max)= maximum allowable junction temperature (125°C for the TPS22994)

T_A= ambient temperature of the device

Θ_JA= junction to air thermal impedance. See Thermal Information section. This parameter is highly

dependent upon board layout.

The figure below shows an example of a layout.

VOUT2

VIN2

VOUT3

VIN3

To Bias Supply

GND

VBIAS

VIN1

VIN4

VOUT4

VOUT1

Exposed Thermal

Pad Area

35

TPS22994

ZHCSCV5B –AUGUST 2014–REVISED SEPTEMBER 2014

www.ti.com.cn

12 器件和文档支持

12.1 商标

SwitchALL is a trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

12.2 静电放电警告

这些装置包含有限的内置 ESD 保护。存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损

伤。

12.3 术语表

SLYZ022 — TI 术语表。

这份术语表列出并解释术语、首字母缩略词和定义。

13 机械封装和可订购信息

以下页中包括机械封装和可订购信息。这些信息是针对指定器件可提供的最新数据。这些数据会在无通知且不对

本文档进行修订的情况下发生改变。欲获得该数据表的浏览器版本，请查阅左侧的导航栏。

36

PACKAGE OUTLINE

RUK0020B

WQFN - 0.8 mm max height

S

C

A

L

E

4

.

0

PLASTIC QUAD FLATPACK - NO LEAD

3.1

2.9

B

A

0.5

0.3

PIN 1 INDEX AREA

3.1

2.9

0.25

0.15

DETAIL

OPTIONAL TERMINAL

TYPICAL

DIMENSION A

OPTION 01

OPTION 02

(0.1)

(0.2)

C

0.8 MAX

SEATING PLANE

0.08 C

0.05

0.00

(DIM A) TYP

OPT 02 SHOWN

1.7 0.05

6

10

EXPOSED

THERMAL PAD

16X 0.4

5

11

21

SYMM

4X

1.6

1

15

SEE TERMINAL

DETAIL

0.25

20X

0.15

0.1

C A

B

20

16

PIN 1 ID

SYMM

0.05

(OPTIONAL)

0.5

0.3

20X

4222676/A 02/2016

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

www.ti.com

EXAMPLE BOARD LAYOUT

RUK0020B

WQFN - 0.8 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

(

1.7)

SYMM

20

16

20X (0.6)

1

15

20X (0.2)

(0.6)

TYP

21

SYMM

(2.8)

16X (0.4)

5

11

(R0.05)

TYP

(

0.2) TYP

VIA

6

10

(2.8)

LAND PATTERN EXAMPLE

SCALE:20X

0.05 MIN

ALL AROUND

0.05 MAX

ALL AROUND

SOLDER MASK

OPENING

METAL

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

NON SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4222676/A 02/2016

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

www.ti.com

EXAMPLE STENCIL DESIGN

RUK0020B

WQFN - 0.8 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

SYMM

(0.47) TYP

16

(R0.05) TYP

20

20X (0.6)

1

15

21

20X (0.2)

(0.47)

TYP

SYMM

(2.8)

16X (0.4)

11

5

METAL

TYP

6

10

4X ( 0.75)

(2.8)

SOLDER PASTE EXAMPLE

BASED ON 0.1 mm THICK STENCIL

EXPOSED PAD 21:

78% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE

SCALE:20X

4222676/A 02/2016

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

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邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	TPS22994RUKT
厂家：	TEXAS INSTRUMENTS
描述：	可通 I2C 进行控制的 4 通道、3.6V、1A、41mΩ 负载开关 \| RUK \| 20 \| -40 to 85 开关
文件：	总44页 (文件大小：1984K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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