TPS43337-Q1_技术文档

TPS43337-Q1

www.ti.com.cn

ZHCSBJ4A –AUGUST 2013–REVISED SEPTEMBER 2013

低 I_Q，单升压，固定电压双同步降压控制器

查询样品: TPS43337-Q1

1

特性

•

峰值栅极驱动电流 1.5A

耐热增强型 38 引脚散热薄型小外形尺寸封装

(HTSSOP)(DAP) PowerPAD™ 封装

2

•

符合汽车应用要求

具有符合 AEC-Q100 的下列结果：

•

–

器件温度 1 级：-40℃ 至 +125℃ 的环境运行温

度范围

应用范围

•

汽车启停、信息娱乐、导航仪表板系统

工业和汽车用多轨直流配电系统和电子控制单元

器件人体模型 (HBM) 静电放电 (ESD) 分类等级

H2

器件充电器件模型 (CDM) ESD 分类等级 C2

说明

•

两个同步降压控制器

TPS43337-Q1 包含两个电流模式同步降压控制器和一

个电压模式升压控制器。此器件非常适合于作为对 I_Q

要求较低的预稳压器级，并且适用于在遇到由意外事件

引起的电源中断时，需要不对系统造成损害的应用。

集成升压控制器使得器件能够在输入低至 2V 时运行，

而又不会出现降压稳压器输出级的下降。在轻负载

时，可以启用降压控制器来自动运行在低功耗模式下，

消耗的静态电流仅为 34μA。

BuckA：3.4V 的固定输出电压

BuckB：1.235V 的固定输出电压

一个预升压控制器

当启用升压时，输入电压范围高达 40V，（瞬态电

压高达 60V），运行电压低至 2V

•

低功耗模式 I_Q：34µA（一个降压控制器打

开），43µA（两个降压控制器打开）

•

低关断电流 I_sh< 4µA

可选升压输出：7V，8.85V 或 10V

降压转换器有独立的软启动功能和电源正常指示器。

降压控制器中的电流折返和升压控制器中的逐周期电流

限制提供了外部金属氧化物半导体场效应晶体管

(MOSFET) 保护。开关频率可在 150kHz 至 600kHz

之间进行设定或者可将它与一个处于同一范围内的外部

时钟同步。

可编程频率和外部同步范围：150kHz 至 600kHz

独立的使能输入（ENA，ENB，ENC）

轻负载时，可选择强制持续模式或自动低功耗模式

感应电阻器或者电感器 DCR 感测对于降压控制器

降压通道之间的异相切换

VBAT

VBuckA

TPS43337-Q1

VBuckB

2 V

图 1. 典型应用图

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2

PowerPAD is a trademark of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

English Data Sheet: SLVSBC2

TPS43337-Q1

ZHCSBJ4A –AUGUST 2013–REVISED SEPTEMBER 2013

www.ti.com.cn

MAX UNIT

space

ABSOLUTE MAXIMUM RATINGS⁽¹⁾

MIN

–0.3

–0.7

–1

Voltage

Input voltage: VIN, VBAT

60

68

60

V

°C

Enable inputs: ENA, ENB

Bootstrap inputs: CBA, CBB

Phase inputs: PHA, PHB

Phase inputs: PHA, PHB (for 150 ns)

Feedback inputs: FBA, FBB

Error amplifier outputs: COMPA, COMPB

High-side MOSFET driver: GA1–PHA, GB1–PHB

Low-side MOSFET drivers: GA2, GB2

Current-sense voltage: SA1, SA2, SB1, SB2

Soft start: SSA, SSB

–0.3

–40

13

Voltage

(buck function:

BuckA and BuckB)

8.8

13

Power-good output: PGA, PGB

Power-good delay: DLYAB

13

Switching-frequency timing resistor: RT

SYNC, EXTSUP

13

Low-side MOSFET driver: GC1

Error amplifier output: COMPC

Enable input: ENC

8.8

13

Voltage

(boost function)

13

Current-limit sense: DS

60

Output-voltage select: DIV

8.8

60

P-channel MOSFET driver: GC2

P-channel MOSFET driver: VIN–GC2

Gate-driver supply: VREG

Voltage

(PMOS driver)

8.8

150

125

165

Junction temperature: T_J

Temperature

Operating temperature: T_A

–40

Storage temperature: T_S

–55

Human-body model (HBM) AEC-Q100

Classification Level H2

±2

kV

VBAT, ENC, SYNC, VIN

All other pins

±750

±500

±150

±200

Charged-device model (CDM) AEC-Q100

Classification Level C2

Electrostatic

discharge ratings

V

PGA, PGB

Machine model (MM)

All other pins

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating

Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage

values are with respect to GND.

2

TPS43337-Q1

www.ti.com.cn

ZHCSBJ4A –AUGUST 2013–REVISED SEPTEMBER 2013

THERMAL INFORMATION

TPS43337-Q1

THERMAL METRIC⁽¹⁾

HTSSOP-DAP

38 PINS

27.3

UNIT

θ_JA

Junction-to-ambient thermal resistance⁽²⁾

Junction-to-case (top) thermal resistance⁽³⁾

Junction-to-board thermal resistance⁽⁴⁾

Junction-to-top characterization parameter⁽⁵⁾

Junction-to-board characterization parameter⁽⁶⁾

Junction-to-case (bottom) thermal resistance⁽⁷⁾

°C/W

θ_JCtop

θ_JB

19.6

15.9

ψ_JT

0.24

ψ_JB

6.6

θ_JCbot

1.2

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as

specified in JESD51-7, in an environment described in JESD51-2a.

(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-

standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB

temperature, as described in JESD51-8.

(5) The junction-to-top characterization parameter, ψ_JT, estimates the junction temperature of a device in a real system and is extracted

from the simulation data for obtaining θ_JA, using a procedure described in JESD51-2a (sections 6 and 7).

(6) The junction-to-board characterization parameter, ψ_JB, estimates the junction temperature of a device in a real system and is extracted

from the simulation data for obtaining θ_JA, using a procedure described in JESD51-2a (sections 6 and 7).

(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific

JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

Spacer

RECOMMENDED OPERATING CONDITIONS

MIN

MAX

40

UNIT

Input voltage: VIN, VBAT

Enable inputs: ENA, ENB

Boot inputs: CBA, CBB

Phase inputs: PHA, PHB

Current-sense voltage: SA1, SA2, SB1, SB2

Power-good output: PGA, PGB

SYNC, EXTSUP

4

0

40

4

–0.6

0

48

Buck function:

BuckA and BuckB

voltage

40

V

11

0

11

0

9

Enable input: ENC

0

9

Boost function

Voltage sense: DS

40

V

DIV

0

VREG

125

Operating Temperature: T_A

–40

°C

3

TPS43337-Q1

ZHCSBJ4A –AUGUST 2013–REVISED SEPTEMBER 2013

www.ti.com.cn

DC ELECTRICAL CHARACTERISTICS

VIN = 8 to 18 V, T_J= –40°C to +150°C (unless otherwise noted)

NO.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

1.0

Input Supply

Boost controller enabled, after initial start-up

condition is satisfied

1.1

1.2

V_BAT

Supply voltage

2

6.5

4

40

V

Input voltage required for device

on initial start-up

V_IN

V

Buck regulator operating range

after initial start-up

40

V_INfalling. After a reset, initial start-up conditions

may apply.⁽¹⁾

3.5

3.6

3.8

1.3

V_{IN UV}

Buck undervoltage lockout

Boost unlock threshold

V_INrising. After a reset, initial start-up conditions

may apply.⁽¹⁾

3.8

8.5

4

V

1.4

1.5

V_{BOOST_UNLOCK}

V_BATrising

8.2

8.8

V_IN= 13 V, BuckA: LPM, BuckB: off, T_A= 25°C

V_IN= 13 V, BuckB: LPM, BuckA: off, T_A= 25°C

V_IN= 13 V, BuckA, B: LPM, T_A= 25°C

V_IN= 13 V, BuckA: LPM, BuckB: off, T_A= 125°C

V_IN= 13 V, BuckB: LPM, BuckA: off, T_A= 125°C

V_IN= 13 V, BuckA and BuckB: LPM, T_A= 125°C

SYNC = 5 V, T_A= 25°C

34

43

44

53

46

57

56

67

µA

LPM quiescent current:

I_{Q_LPM}

(2)

LPM quiescent current:

1.6

1.7

I_{Q_LPM}

(2)

V_IN= 13 V, BuckA: CCM, BuckB: off, T_A= 25°C

V_IN= 13 V, BuckB: CCM, BuckA: off, T_A= 25°C

V_IN= 13 V, BuckA and BuckB: CCM, T_A= 25°C

SYNC = 5 V, T_A= 125°C

4.85

7

5.3

7.6

5.5

Quiescent current:

I_{Q_NRM}

mA

normal (PWM) mode⁽²⁾

V_IN= 13 V, BuckA: CCM, BuckB: off, T_A= 125°C

V_IN= 13 V, BuckB: CCM, BuckA: off, T_A= 125°C

V_IN= 13 V, BuckA, B: CCM, T_A= 125°C

BuckA and BuckB: off, VBat = 13 V , T_A= 25°C

BuckA and BuckB: off, VBat = 13 V, T_A= 125°C

V_INfalling

5

Quiescent current:

1.8

I_{Q_NRM}

normal (PWM) mode⁽²⁾

7.5

2.5

3

8

4

1.9

1.10

1.11

1.12

1.13

2.0

I_{bat_sh}

Shutdown current

VIN level to exit LPM

µA

V

I_{bat_sh}

5

VIN_LPMexit

VIN_LPMentry

VIN_LPMhys

7.7

8.2

0.4

8

8.3

8.8

0.6

VIN level to enable entering LPM V_INrising

Hysteresis V_INrising or falling

8.5

0.5

V

Input Voltage V_BAT- Undervoltage Lockout

V_BATfalling. After a reset, initial start-up conditions

may apply.⁽¹⁾

1.8

1.9

2.5

2

V

2.1

V_BATUV

Boost-input undervoltage

V_BATrising. After a reset, initial start-up conditions

may apply.⁽¹⁾

2.4

2.6

2.2

2.3

3.0

UVLO_Hys

UVLO_filter

Hysteresis

Filter time

500

600

5

700

mV

µs

Input Voltage V_IN- Overvoltage Lockout

V_INrising

V_INfalling

45

43

1

46

44

2

47

45

3

3.1

V_OVLO

Overvoltage shutdown

V

3.2

3.3

OVLO_Hys

OVLO_filter

Hysteresis

Filter time

V

5

µs

(1) If VBAT and VREG remain adequate, the buck can continue to operate if VIN is > 3.8 V.

(2) Quiescent current specification includes the current in the internal-feedback resistor divider.

4

TPS43337-Q1

www.ti.com.cn

ZHCSBJ4A –AUGUST 2013–REVISED SEPTEMBER 2013

DC ELECTRICAL CHARACTERISTICS (continued)

VIN = 8 to 18 V, T_J= –40°C to +150°C (unless otherwise noted)

NO.

4.0

4.1

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

V

Boost Controller

V_boost7-VIN

Boost V_OUT= 7 V

DIV = low, V_BAT= 2 to 7 V

6.8

7.5

7

8

7.3

8.5

Boost-enable threshold

Boost-disable threshold

Boost hysteresis

Boost V_OUT= 7 V, V_BATfalling

4.2

4.3

4.4

4.5

4.6

V_boost7-th

Boost V_OUT= 7 V, V_BATrising

8

8.5

9

V

Boost V_OUT= 7 V, V_BATrising or falling

DIV = open, V_BAT= 2 to 10 V

0.4

0.5

0.6

V_boost10-VIN

V_boost10-th

V_{boost8.85-VIN}

V_boost8.85-th

Boost V_OUT= 10 V

9.7

10

10.4

11.5

12

V

Boost-enable threshold

Boost-disable threshold

Boost hysteresis

Boost V_OUT= 10 V, V_BATfalling

Boost V_OUT= 10 V, V_BATrising

Boost V_OUT= 10 V, V_BATrising or falling

DIV = V_REG, V_BAT= 2 to 8.85 V

Boost V_OUT= 8.85 V, V_BATfalling

Boost V_OUT= 8.85 V, V_BATrising

Boost V_OUT= 8.85 V, V_BATrising or falling

10.5

11

11.5

0.5

V

0.4

0.6

Boost V_OUT= 8.85 V

Boost-enable threshold

Boost-disable threshold

Boost hysteresis

8.35

9.15

9.65

0.4

8.85

9.85

10.35

0.5

9.35

10.45

10.85

0.6

V

Boost-Switch Current Limit

4.7

4.8

V_DS

t_DS

Current-limit sensing

Leading-edge blanking

DS input with respect to PGNDA

0.175

0.2

0.225

V

200

ns

Gate Driver for Boost Controller

I_{GC1 Peak}Gate-driver peak current

r_DS(on)Source and sink driver

Gate Driver for PMOS

4.9

1.5

A

4.10

V_REG= 5.8 V, IGC1 current = 200 mA

2

20

10

Ω

4.11

4.12

4.13

r_DS(on)

PMOS OFF

10

5

Ω

mA

µs

I_{PMOS_ON}

t_{delay_ON}

Gate current

Turnon delay

V_IN= 13.5 V, Vgs = –5 V

C = 10 nF

10

Boost-Controller Switching Frequency

4.14

4.15

f_sw-Boost

D_Boost

Boost switching frequency

Boost duty cycle

f_{SW_Buck}/ 2

90%

kHz

Error Amplifier (OTA) for Boost Converters

V_BAT= 12 V

V_BAT= 5 V

0.8

1.35

0.65

4.16

Gm_BOOST

Forward transconductance

mS

V

0.35

5.0

Buck Controllers

V_{BuckA_NRM}

Fixed output voltage in normal

mode

5.1a

5.1b

5.2a

3.345

3.311

1.216

3.396

1.235

3.447

3.481

1.253

Included resistor-feedback-divider, measured at

FBA pin

V_{BuckA_LPM}

Fixed output in low-power mode

Fixed output voltage in normal

mode

V_{BuckB_NRM}

Included resistor-feedback-divider, measured at

FBB pin

V

Fixed output voltage in low-

power mode

5.2b

5.4

V_{BuckB_LPM}

1.204

60

1.235

75

1.266

90

V sense for forward-current limit Measured across Sx1 and Sx2, FBx at 94% of

in CCM typical value (low duty-cycle)

mV

V_sense

V sense for reverse-current limit Measured across Sx1 and Sx2, FBx at 125% of

5.5

5.6

5.7

–65

17

–37.5

32.5

–23

48

mV

ns

in CCM

typical value

V_I-Foldback

t_dead

V sense for output short

Measured across Sx1 and Sx2, FBx = 0 V

Shoot-through delay, blanking

time

20

High-side minimum on-time

100

ns

5.8

5.9

DC_NRM

DC_LPM

Maximum duty cycle (digitally

controlled)

98.75%

Duty cycle, LPM

80%

5

TPS43337-Q1

ZHCSBJ4A –AUGUST 2013–REVISED SEPTEMBER 2013

www.ti.com.cn

DC ELECTRICAL CHARACTERISTICS (continued)

VIN = 8 to 18 V, T_J= –40°C to +150°C (unless otherwise noted)

NO.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

LPM entry-threshold load current

as fraction of maximum set load

current

(3)

I_{LPM_Entry}

1%

.

5.10

LPM exit-threshold load current

as fraction of maximum set load

current

(3)

I_{LPM_Exit}

10%

1.5

High-Side External NMOS Gate Drivers for Buck Controller

5.11

5.12

I_{GX1_peak}

r_DS(on)

Gate-driver peak current

Source and sink driver

A

V_REG= 5.8 V, I_GX1current = 200 mA

V_REG= 5.8 V, I_GX2current = 200 mA

2

Ω

Low-Side NMOS Gate Drivers for Buck Controller

5.13

5.14

I_{GX2_peak}

R_{DS ON}

Gate driver peak current

Source and sink driver

1.5

1

A

2

Ω

Error Amplifier (OTA) for Buck Converters

Gm_BUCKTransconductance

Digital Inputs: ENA, ENB, ENC, SYNC

COMPA, COMPB = 0.8 V,

source/sink = 5 µA, test in feedback loop

5.15

0.72

1.7

1.35

mS

6.0

6.1

6.2

6.3

6.4

V_IH

Higher threshold

V_IN= 13 V

V_SYNC= 5 V

V_ENC= 5 V

V

V_IL

Lower threshold

0.7

2

R_{IH_SYNC}

R_{IL_ENC}

Pulldown resistance on SYNC

Pulldown resistance on ENC

500

kΩ

Pullup current source on ENA,

ENB

6.5

I_{IL_ENx}

V_ENx= 0 V

0.5

µA

7.0

7.1

7.2

7.3

8.0

8.1

8.2

Boost Output Voltage: DIV

V_{IH_DIV}

V_{IL_DIV}

V_{oz_DIV}

Higher threshold

V_REG= 5.8 V

Vreg – 0.2

V

Lower threshold

0.2

Voltage on DIV if unconnected

Vreg / 2

Switching Parameter – Buck DC-DC Controllers

f_{SW_Buck}

Buck switching frequency

RT pin: GND

360

400

440

kHz

RT pin: 60-kΩ external resistor

Buck adjustable range with

external resistor

8.3

f_{SW_adj}

f_SYNC

RT pin: external resistor

External clock input

150

600

kHz

8.4

9.0

Buck synchronization range

Internal Gate-Driver Supply

Internal regulated supply

V_IN= 8 to 18 V, V_EXTSUP= 0 V, SYNC = high

5.5

7.2

5.8

0.2%

7.5

6.1

1%

7.8

1%

V

9.1

V_REG

I_VREG= 0 to 100 mA, V_EXTSUP= 0 V,

SYNC = high

Load regulation

Internal regulated supply

Load regulation

V_EXTSUP= 8.5 V

9.2

9.3

V_REG(EXTSUP)

I_EXTSUP= 0 to 125 mA, SYNC = High

V_EXTSUP= 8.5 to 13 V

0.2%

EXTSUP switch-over voltage

threshold

I_VREG= 0 to 100 mA,

V_EXTSUPramping positive

V_EXTSUP-th

4.4

4.6

4.8

V

9.4

9.5

V_EXTSUP-Hys

I_REG-Limit

EXTSUP switch-over hysteresis

Current limit on VREG

150

100

250

400

mV

mA

V_EXTSUP= 0 V, normal mode as well as LPM

Current limit on VREG when

using EXTSUP

I_VREG= 0 to 100 mA,

V_EXTSUP= 8.5 V, SYNC = High

9.6

I_{REG_EXTSUP-Limit}

125

400

mA

10.0

10.1

11.0

11.1

Soft Start

I_SSx

Soft-start source current

V_SSAand V_SSB= 0 V

40

50

60

µA

V

Oscillator (RT)

V_RT

Oscillator reference voltage

1.2

(3) The exit threshold specification must always higher than the entry threshold.

6

TPS43337-Q1

www.ti.com.cn

ZHCSBJ4A –AUGUST 2013–REVISED SEPTEMBER 2013

DC ELECTRICAL CHARACTERISTICS (continued)

VIN = 8 to 18 V, T_J= –40°C to +150°C (unless otherwise noted)

NO.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

12.0

Power Good / Delay

12.1a PG_thA

12.1b PG_thB

FBA falling

FBB falling

3.09

3.158

1.148

2%

3.226

1.173

Power-good threshold

V

1.124

12.2

12.3

12.4

12.5

12.6

PG_hys

Hysteresis

PG_drop

Voltage drop

I_PGA= 5 mA

I_PGA= 1 mA

450

100

1

mV

µA

µs

PG_leak

t_deglitch

Power-good leakage

Sx2 = PGx = 13 V

Power-good deglitch time

2

16

External capacitor = 1 nF

V_BUCKx< PG_thx

12.7

12.8

12.9

t_delay

t_{delay_fix}

I_OH

Reset delay

1

20

40

ms

µs

Fixed reset delay

No external capacitor, pin open

50

Activate current source (current

to charge external capacitor)

30

µA

Activate current sink (current to

discharge external capacitor)

12.10 I_IL

40

50

µA

13.0

13.1

13.2

Overtemperature Protection

Junction-temperature shutdown

threshold

T_shutdown

T_hys

150

165

15

°C

Junction-temperature hysteresis

7

TPS43337-Q1

ZHCSBJ4A –AUGUST 2013–REVISED SEPTEMBER 2013

www.ti.com.cn

DEVICE INFORMATION

DAP PACKAGE

(TOP VIEW)

1

2

3

4

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

VBAT

DS

VIN

EXTSUP

DIV

GC1

GC2

VREG

CBB

5

6

7

8

CBA

GA1

GB1

PHA

PHB

GA2

GB2

9

PGNDA

SA1

PGNDB

SB1

10

11

SA2

SB2

12

13

14

15

FBA

FBB

COMPA

SSA

COMPB

SSB

PGA

ENA

PGB

16

17

18

AGND

RT

ENB

COMPC

ENC

DLYAB

SYNC

19

20

PIN FUNCTIONS

NAME

NO.

I/O

DESCRIPTION

AGND

23

O

Analog ground reference

A capacitor on this pin acts as the voltage supply for the high-side N-channel MOSFET gate-drive circuitry in buck

controller BuckA. When the buck is in a dropout condition, the device automatically reduces the duty cycle of the

high-side MOSFET to approximately 95% on every fourth cycle to allow the capacitor to recharge.

CBA

5

I

A capacitor on this pin acts as the voltage supply for the high-side N-channel MOSFET gate-drive circuitry in buck

controller BuckB. When the buck is in a dropout condition, the device automatically reduces the duty cycle of the

high-side MOSFET to approximately 95% on every fourth cycle to allow the capacitor to recharge.

CBB

34

13

26

I

Error-amplifier output of BuckA and compensation node for voltage-loop stability. The voltage at this node sets the

target for the peak current through the inductor of BuckA. Clamping this voltage on the upper and lower ends

provides current-limit protection for the external MOSFETs.

COMPA

COMPB

O

Error-amplifier output of BuckB and compensation node for voltage-loop stability. The voltage at this node sets the

target for the peak current through the inductor of BuckB. Clamping this voltage on the upper and lower ends

provides current-limit protection for the external MOSFETs.

COMPC

DIV

18

36

O

I

Error-amplifier output and loop-compensation node of the boost regulator

The status of this pin defines the output voltage of the boost regulator. A high input regulates the boost converter

at 8.85 V, a low input sets the value at 7 V, and a floating pin sets 10 V.

The capacitor at the DLYAB pin sets the power-good delay interval used to de-glitch the outputs of the power-

good comparators. Leaving this pin open sets the power-good delay to an internal default value of 20 μs, typical.

DLYAB

DS

21

2

O

I

This input monitors the voltage on the external boost-converter low-side MOSFET for overcurrent protection. An

alternative connection for better noise immunity is to place a sense resistor between the source of the low-side

MOSFET and ground via a filter network.

Enable inputs for BuckA (active-high with an internal pullup current source). An input voltage higher than 1.5 V

enables the controller, whereas an input voltage lower than 0.7 V disables the controller. When both ENA and

ENB are low, the device shuts down and consumes less than 4 µA of current.

ENA

16

I

8

TPS43337-Q1

www.ti.com.cn

ZHCSBJ4A –AUGUST 2013–REVISED SEPTEMBER 2013

PIN FUNCTIONS (continued)

NAME

ENB

NO.

I/O

DESCRIPTION

Enable inputs for BuckB (active-high with an internal pullup current source). An input voltage higher than 1.5 V

enables the controller, whereas an input voltage lower than 0.7 V disables the controller. When both ENA and

ENB are low, the device shuts down and consumes less than 4 µA of current.

17

19

37

I

This input enables and disables the boost regulator. An input voltage higher than 1.5 V enables the controller.

Voltages lower than 0.7 V disable the controller. When enabled, the controller starts switching as soon as VBAT

falls below the boost threshold, depending upon the programmed output voltage.

ENC

I

One uses EXTSUP to supply the VREG regulator from one of the TPS43337-Q1 buck regulator rails to reduce

power dissipation in cases where there is an expectation of high VIN. When EXTSUP is open or lower than 4.6 V,

the regulator power comes from VIN.

EXTSUP

Feedback voltage pin for BuckA. The buck controller regulates this feedback voltage to 3.4 V through the internal

resistor-divider network. Connect FBA to the output voltage of BuckA.

FBA

FBB

12

27

I

Feedback voltage pin for BuckB. The buck controller regulates this feedback voltage to 1.235 V through the

internal resistor-divider network. Connect FBB to the output voltage of BuckB.

This output drives an external high-side N-channel MOSFET for buck regulator BuckA. The output provides high

peak currents to drive capacitive loads. The gate-drive reference is to a floating ground provided by PHA that has

a voltage swing provided by CBA.

GA1

GA2

GB1

6

8

O

This output drives an external high-side N-channel MOSFET for buck regulator BuckA. The output provides high

peak currents to drive capacitive loads. VREG provides the voltage swing on this pin.

This output drives an external high-side N-channel MOSFET for buck regulator BuckB. The output provides high

peak currents to drive capacitive loads. The gate-drive reference is to a floating ground provided by PHB that has

a voltage swing provided by CBB.

33

This output drives an external high-side N-channel MOSFET for buck regulator BuckB. The output provides high

peak currents to drive capacitive loads. VREG provides the voltage swing on this pin.

GB2

GC1

31

3

O

This output drives an external low-side N-channel MOSFET for the boost regulator. This output provides high

peak currents to drive capacitive loads. VREG provides the voltage swing on this pin.

This pin makes a floating output drive available to control the external P-channel MOSFET. This MOSFET

bypasses the boost rectifier diode or a reverse-protection diode when the boost status is non-switching or

disabled, and thus reduces power losses.

GC2

PGA

PGB

4

O

Open-drain power-good indicator pin for BuckA. An internal power-good comparator monitors the voltage at the

feedback pin and pulls this output low when the output voltage falls below 93% of the set value, or if either VIN or

VBAT drops below the respective undervoltage threshold.

15

24

Open-drain power-good indicator pin for BuckB. An internal power-good comparator monitors the voltage at the

feedback pin and pulls this output low when the output voltage falls below 93% of the set value, or if either VIN or

VBAT drops below the respective undervoltage threshold.

PGNDA

PGNDB

9

O

Power-ground connection to the source of the low-side N-channel MOSFETs of BuckA.

Power-ground connection to the source of the low-side N-channel MOSFETs of BuckB.

30

Switching terminal of buck regulator BuckA; provides a floating ground reference for the high-side MOSFET gate-

driver circuitry and senses current reversal in the inductor when discontinuous-mode operation is desired.

PHA

PHB

7

O

Switching terminal of buck regulator BuckB; provides a floating ground reference for the high-side MOSFET gate-

driver circuitry and senses current reversal in the inductor when discontinuous-mode operation is desired.

32

Connecting a resistor to ground on this pin sets the operating switching frequency of the buck and boost

controllers. A short circuit to ground on this pin defaults operation to 400 kHz for the buck controllers and 200 kHz

for the boost controller.

RT

22

O

SA1

SA2

SB1

SB2

10

11

29

28

I

High-impedance differential-voltage inputs from the current-sense element (sense resistor or inductor DCR) for

each buck controller. Choose the current-sense element to set the maximum current through the inductor based

on the current-limit threshold (subject to tolerances) and considering the typical characteristics across duty cycle

and VIN. (SA1 positive node, SA2 negative node)

High-impedance differential voltage inputs from the current-sense element (sense resistor or inductor DCR) for

each buck controller. Choose the current-sense element to set the maximum current through the inductor based

on the current-limit threshold (subject to tolerances) and considering the typical characteristics across duty cycle

and VIN. (SB1 positive node, SB2 negative node)

Soft-start or tracking input for buck controller BuckA. The buck controller regulates the FBA voltage to the lower of

0.8 V or the SSA pin voltage. An internal pullup current source of 50 μA is present at the pin. Connect an

appropriate capacitor here to set the soft-start ramp interval, or connect a resistor divider connected to another

supply to provide a tracking input to this pin.

SSA

SSB

14

25

O

Soft-start or tracking input for buck controller BuckB. The buck controller regulates the FBA voltage to the lower of

0.8 V or the SSA pin voltage. An internal pullup current source of 50 μA is present at the pin. Connect an

appropriate capacitor here to set the soft-start ramp interval, or connect a resistor divider connected to another

supply to provide a tracking input to this pin.

9

TPS43337-Q1

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www.ti.com.cn

PIN FUNCTIONS (continued)

NAME

NO.

I/O

DESCRIPTION

If an external clock is present on this pin, the device detects it, and the internal PLL locks on to the external clock.

This overrides the internal oscillator frequency. The device can synchronize to frequencies from 150 kHz to 600

kHz. A high logic level on this pin ensures forced continuous-mode operation of the buck controllers and inhibits

transition to low-power mode. An open or low allows discontinuous-mode operation and entry into low-power

mode at light loads.

SYNC

20

I

Battery input sense for the boost controller. With the boost controller enabled, if the voltage at VBAT falls below

the boost threshold, the device activates the boost controller and regulates the voltage at VIN to the programmed

boost output voltage.

VBAT

VIN

1

I

Main input pin. This is the buck controller input pin as well as the output of the boost regulator. Additionally, VIN

powers the internal control circuits of the device.

38

35

This pin requires an external capacitor to provide a regulated supply for the gate drivers of the buck and boost

controllers. TI recommends a capacitance on the order of 4.7 μF. Either VIN or EXTSUP can power the regulator.

This pin has current-limit protection, so do not use it to drive any other loads.

VREG

O

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www.ti.com.cn

ZHCSBJ4A –AUGUST 2013–REVISED SEPTEMBER 2013

5

CBA

Duplicate for second

Buck controller channel

Internal ref

(Band gap)

38

VIN

6

7

8

9

GA1

Gate Driver

Supply

37

35

EXTSUP

VREG

PWM

Logic

PHA

VREG

GA2

PGNDA

Internal

Oscillator

22

20

Slope

Comp

RT

Current sense

Amp

10

11

SA1

SA2

PWM

comp

SYNC and

LPM

SYNC

OTA

Gm

12

FBA

0.8 V

Source

and

Sink

SSA

4

GC2

Logic

13

COMPA

FBA

ENC

50 µA

15

PGA

14

16

25

SSA

ENA

SSB

VIN

ENA

Filter Timer

500 nA

40 µA

VIN

50 µA

21

DLYAB

ENB

500 nA

34

33

32

31

30

29

28

27

26

24

CBB

17

2

ENB

DS

GB1

OCP

OTA

Gm

VIN

V_boostxV

PHB

0.2 V

18

36

COMPC

DIV

GB2

Second

Buck

Controller

Channel

PGNDB

SB1

Ramp

V_boost7V-th

V_{boost8.85V-th}

V_boost10V-th

1

VBAT

SB2

MUX

FBB

COMPB

PGB

PWM

comp

VREG

3

GC1

ENC

PWM

Logic

19

23

PGNDA

AGND

Figure 2. Functional Block Diagram

11

TPS43337-Q1

ZHCSBJ4A –AUGUST 2013–REVISED SEPTEMBER 2013

www.ti.com.cn

TYPICAL CHARACTERISTICS

BuckA EFFICIENCY AND POWER LOSSES

V_IN= 12 V, Inductor = 10 µH, R_sense= 20 mΩ, Switching

Frequency = 400 kHz, EXTSUP open

BuckB EFFICIENCY AND POWER LOSSES

V_IN= 12 V, Inductor = 4.7 µH, R_sense= 10 mΩ, Switching

Frequency = 400 kHz, EXTSUP open

100

90

80

70

60

50

40

30

20

10

0

10

100

10

Efficiency, SYNC=HIGH

Efficiency, SYNC=LOW

Power Loss, SYNC=HIGH

Power Loss, SYNC=LOW

Efficiency, SYNC=LOW

90

80

70

60

50

40

30

20

10

Power Loss, SYNC=HIGH

Power Loss, SYNC=LOW

1

0.1

0.01

0.001

0.0001

0.01

0.001

0.0001

0

1.00E-07

1.00E-05

1.00E-03

I_Load (A)

Figure 3.

1.00E-01

1.00E-07

1.00E-05

1.00E-03

I_Load (A)

Figure 4.

1.00E-01

C001

C002

BuckA LOAD STEP 1 A - 2 A

BuckB LOAD STEP 1 A - 2 A

V_IN= 12 V, Inductor = 10 µH, R_sense= 20 mΩ, C_OUT= 100 µF,

V_IN= 12 V, Inductor = 4.7 µH, R_sense= 10 mΩ, C_OUT= 320 µF,

Switching Frequency = 400 kHz

V_OUTBuckA - AC Coupled

50 mV / DIV

V_OUTBuckB - AC Coupled

100 mV / DIV

I_IND

1 A / DIV

I_IND

1 A / DIV

1 ms / DIV

Figure 5.

Figure 6.

BuckB LOAD STEP UP 0 A - 1 A

BuckB LOAD STEP DOWN 1 A - 0 A

V_IN= 12 V, Inductor = 4.7 µH, R_sense= 10 mΩ, C_OUT= 320 µF,

Switching Frequency = 400 kHz

I_IND

50 mV / DIV

V_OUTBuckB - AC Coupled

50 mV / DIV

V_OUTBuckB - AC Coupled

I_IND

0.2 A / DIV

100 ꢀs / DIV

Figure 7.

Figure 8.

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TPS43337-Q1

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ZHCSBJ4A –AUGUST 2013–REVISED SEPTEMBER 2013

TYPICAL CHARACTERISTICS (continued)

SOFT-START OUTPUTS

BuckA and BuckB

V_IN(BOOST OUTPUT) = 10 V, SWITCHING FREQUENCY = 200 kHz,

INDUCTOR = 1 µH, R_SENSE= 7.5 mW

100

90

V_OUTBuckA, 1V / DIV

V_BAT= 8 V

80

70

V_BAT= 5 V

60

V_OUTBuckB, 0.5 V / DIV

V_BAT= 3 V

50

40

30

20

10

0

5 ms / DIV

0.01

1

10

Output Current (A)

Figure 10.

Figure 9.

V_IN(BOOST OUTPUT) = 10 V, BuckA = 5 V AT 1.5 A,

BuckB = 3.3 V AT 3.5 A, SWITCHING FREQUENCY = 200 kHz,

INDUCTOR = 1 µH, R_SENSE= 7.5 mW, C_IN= 440 µF, C_OUT= 660 µF

V_BAT(BOOST INPUT) = 5 V, V_IN(BOOST OUTPUT) = 10 V,

SWITCHING FREQUENCY = 200 kHz, INDUCTOR = 1 µH,

R_SENSE= 7.5 mW, C_IN= 440 µF, C_OUT= 660 µF

V_BAT(BOOST INPUT)

5 V/DIV

500 mV/DIV

V_IN(BOOST OUTPUT) AC-COUPLED

0 V

200 mV/DIV

V_OUTBuckA AC-COUPLED

V_OUTBuckB AC-COUPLED

5 A/DIV

10 A/DIV

0 A

I_IND

2 ms/DIV

20 ms/DIV

Figure 11.

Figure 12.

V_IN(BOOST OUTPUT) = 10 V, BuckA = 5 V AT 1.5 A,

BuckB = 3.3V AT 3.5A, SWITCHING FREQUENCY = 200 kHz,

INDUCTOR = 1 µH, R_SENSE= 7.5 mW, C_IN= 440 µF, C_OUT= 660 µF

V_BAT(BOOST INPUT) = 5 V, V_IN(BOOST OUTPUT) = 10 V,

SWITCHING FREQUENCY = 200 kHz, INDUCTOR = 1 µH,

R_SENSE= 7.5 mW, C_IN= 440 µF, C_OUT= 660 µF

V_BAT(BOOST INPUT)

5 V/DIV

3-A LOAD

5 A/DIV

0 V

V_IN(BOOST OUTPUT)

5 V/DIV

100-mA LOAD

0V

10 A/DIV

5 A/DIV

I_IND

0 A

2 µs/DIV

20 ms/DIV

Figure 13.

Figure 14.

13

TPS43337-Q1

ZHCSBJ4A –AUGUST 2013–REVISED SEPTEMBER 2013

www.ti.com.cn

TYPICAL CHARACTERISTICS (continued)

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

75

62.5

50

150°C

37.5

25

12.5

0

SYNC = LOW

–12.5

–25

–37.5

25°C

–0.1

–0.2

–0.3

SYNC = HIGH

0.8 0.95

0

1

2

3

4

5

6

7

8

9

10 11 12

0.65

1.1

1.25

1.4

1.55

Output Voltage (V)

COMPx Voltage (V)

Figure 15.

Figure 16.

80

70

60

50

40

30

20

10

0

FOLDBACK CURRENT LIMIT (BUCK)

80

70

60

50

40

30

20

10

0

V_IN= 8 V

V_IN= 12 V

0

10 20 30 40 50 60 70 80 90 100

Duty Cycle (%)

0

0.25

0.5

0.75

1

Normalized V_OUT

Figure 17.

Figure 18.

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TPS43337-Q1

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ZHCSBJ4A –AUGUST 2013–REVISED SEPTEMBER 2013

DETAILED DESCRIPTION

BUCK CONTROLLERS: NORMAL-MODE PWM OPERATION

Frequency Selection and External Synchronization

The buck controllers operate using constant-frequency peak-current-mode control for optimal transient behavior

and ease of component choices. The switching frequency is programmable between 150 kHz and 600 kHz,

depending upon the resistor value at the RT pin. A short circuit to ground at this pin sets the default switching

frequency to 400 kHz. the frequency is also set by a resistor at RT according to Equation 1.

X

f_SW

=

(X = 24 kW´MHz)

RT

10⁹

f_SW= 24´

RT

(1)

For example,

600 kHz requires 40 kΩ.

150 kHz requires 160 kΩ.

Synchronizing to an external clock at the SYNC pin in the same frequency range of 150 to 600 kHz is also

possible. The device detects clock pulses at this pin, and an internal PLL locks on to the external clock within the

specified range. The device also detects a loss of clock at this pin, and on detecting this loss, the device sets the

switching frequency to the internal oscillator. The two buck controllers operate at identical switching frequencies,

180 degrees out of phase.

Enable Inputs

Independent enable inputs from the ENA and ENB pins enable the buck controllers. These are high-voltage pins,

with a threshold of 1.5 V for high level, and with direct connection directly to the battery for self-bias. The low

threshold is 0.7 V. Both these pins have internal pullup currents of 0.5 µA (typical). As a result, an open circuit on

these pins enables the respective buck controllers. When both buck controllers are disabled, the device shuts

down and consumes a current less than 4 µA.

Feedback Inputs

An internal voltage divider presets the output voltage. Connect each FBx pin to the output of the respective

regulator of the pin.

Soft-Start Inputs

In order to avoid large inrush currents, each buck controller has an independent, programmable soft-start timer.

The voltage at the SSx pins acts as the soft-start reference voltage. A 50-µA pullup current available at the SSx

pins, in combination with a suitably chosen capacitor, generates a ramp of the desired soft-start speed. After

start-up, the pullup current ensures that this node is higher than the internal reference of 0.8 V; 0.8 V then

becomes the reference for the buck controllers. Equation 2 calculates the soft-start ramp time.

I

_SS´ Dt

C_SS

=

(Farads)

DV

where,

•

I_SS= 50 µA (typical)

∆V = 0.8 V

C_SSis the required capacitor for ∆t, the desired soft-start time.

(2)

Alternatively, the soft-start pins are used as tracking inputs. In this case, connect these pins to the supply to be

tracked via a suitable resistor-divider network.

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TPS43337-Q1

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Current-Mode Operation

Peak-current-mode control regulates the peak current through the inductor to maintain the output voltage at the

set value. The error between the feedback voltage at FBx and the internal voltage divider produces a signal at

the output of the error amplifier (COMPx), which serves as the target for the peak inductor current. The device

senses the current through the inductor as a differential voltage at Sx1–Sx2 and compares the voltage with this

target during each cycle. A fall or rise in load current produces a fall or rise in voltage at FBx, causing COMPx to

fall or rise respectively, thus increasing or decreasing the current through the inductor until the average current

matches the load. This process maintains the output voltage in regulation.

The top N-channel MOSFET turns on at the beginning of each clock cycle and stays on until the inductor current

reaches the peak value. When this MOSFET turns off, and after a small delay (shoot-through delay), the lower

N-channel MOSFET turns on until the start of the next clock cycle. In dropout operation, the high-side MOSFET

stays on continuously. In every fourth clock cycle, there is a limit on the duty cycle of 95% in order to charge the

bootstrap capacitor at CBx, which allows a maximum duty cycle of 98.75% for the buck regulators. During

dropout, the buck regulator switches at one-fourth of its normal frequency.

Current Sensing and Current Limit With Foldback

Clamping of the maximum value of COMPx is such as to limit the maximum current through the inductor to a

specified value. When the output of the buck regulator (and hence the feedback value at FBx) falls to a low value

due to a short-circuit or overcurrent condition, the clamped voltage at COMPx successively decreases, thus

providing current foldback protection, which protects the high-side external MOSFET from excess current

(forward-direction current limit).

Similarly, if due to a fault condition the output is shorted to a high voltage and the low-side MOSFET turns fully

on, the COMPx node drops low. A clamp is on the lower end as well, in order to limit the maximum current in the

low-side MOSFET (reverse-direction current limit).

An external resistor senses the current through the inductor. Choose the sense resistor such that the maximum

forward-peak current in the inductor generates a voltage of 75 mV across the sense pins. This specified typical

value is for low duty cycles only. At typical duty-cycle conditions around 28% (assuming 3.4 V output and 12 V

input), 55 mV is a more reasonable value, considering tolerances and mismatches. The typical characteristics

(see Figure 18) provide a guide for using the correct current-limit sense voltage.

The current-sense pins Sx1 and Sx2 are high-impedance pins with low leakage across the entire output range,

thus allowing DCR current sensing using the dc resistance of the inductor for higher efficiency. Figure 19 shows

DCR sensing. Here, the series resistance (DCR) of the inductor is the sense element. Place the filter

components close to the device for noise immunity. Remember that while the DCR sensing gives high efficiency,

it is inaccurate due to the temperature sensitivity and a wide variation of the parasitic inductor series resistance.

Hence using the more-accurate sense resistor for current sensing is advantageous.

Inductor L

TPS43337-Q1

V_BuckX

DCR

R11

C11

Sx22

V_C

Sx11

Figure 19. DCR Sensing Configuration

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ZHCSBJ4A –AUGUST 2013–REVISED SEPTEMBER 2013

Slope Compensation

Optimal slope compensation, which is adaptive to changes in input voltage and duty cycle, allows stable

operation at all conditions. For optimal performance of this circuit, choose the inductor and sense resistor

according to Equation 3.

L ´ f_SW

= 200

R_S

where

•

L is the buck regulator inductor in henries.

R_Sis the sense resistor in ohms.

f_swis the buck regulator switching frequency in hertz.

(3)

Power-Good Outputs and Filter Delays

Each buck controller has an independent power-good comparator monitoring the feedback voltage at the FBx

pins and indicating whether the output voltage has fallen below a specified power-good threshold. This threshold

has a typical value of 93% of the regulated output voltage. The power-good indicator is available as an open-

drain output at the PGx pins. Shutdown of a buck controller causes an internal pulldown of the power-good

indicator. Connecting the external pullup resistor to a rail other than the output of that particular buck channel

causes a constant current flow through the external resistor during a powered-down state of the buck controller.

In order to avoid triggering the power-good indicators due to noise or fast transients on the output voltage, the

device uses an internal delay circuit for de-glitching. Similarly, when the output voltage returns to the set value

after a long negative transient, assertiohn of the power-good indicator (release of the open-drain pin) occurs after

the same delay. Use of this delay can pause the reset of circuits powered from the buck regulator rail. Program

the delay of this circuit by using a suitable capacitor at the DLYAB pin according to Equation 4.

t_DELAY

1 msec

=

C_DLYAB

1 nF

(4)

When the DLYAB pin is open, the delay is set to a default value of 20 µs (typical). The power-good delay timing

is common to both the buck rails, but the power-good comparators and indicators function independently.

Light-Load PFM Mode

An external clock or a high level on the SYNC pin results in forced continuous-mode operation of the bucks.

When the SYNC pin is low or open, the buck controllers are allowed to operate in discontinuous mode at light

loads by turning off the low-side MOSFET whenever a zero-crossing in the inductor current is detected.

In discontinuous mode, as the load decreases, the duration of the clock-period when both the high-side as well

the low-side MOSFET is turned-off, increases (deep discontinuous mode). In case the duration exceeds 60% of

the clock period and VBAT > 8 V, the buck controller switches to a low-power operation mode. The design

ensures that this typically occurs at 1% of the set full-load current if the inductor and the sense resistor have

been chosen appropriately as recommended in the Slope Compensation section.

In low-power PFM mode, the buck monitors the FBx voltage and compares it with the 0.8 V internal reference

voltage through the internal voltage divider. Whenever the FBx value falls below the internal threshold, the high-

side MOSFET is turned on for a pulse duration inversely proportional to the difference VIN – Sx2. At the end of

this on-time, the high-side MOSFET is turned off and the current in the inductor decays until it becomes zero.

The low-side MOSFET is not turned on. The next pulse occurs the next time FBx falls below the threshold value

which results in a constant volt-second t_onhysteretic operation with a total-device quiescent-current consumption

of 34 µA when a single buck channel is active and 43 µA when both channels are active.

As the load increases, the pulses become more and more frequent and move closer to each other until the

current in the inductor becomes continuous. At this point, the buck controller returns to normal fixed-frequency

current-mode control. Another criterion to exit the low-power mode is when VIN falls low enough to require higher

than 80% duty cycle of the high-side MOSFET.

During low-power mode, the TPS43337-Q1 supports the full-current load until the transition to normal mode

takes place. The design ensures the low-power-mode exit occurs at 10% (typical) of full-load current if the

inductor and sense resistor have been chosen as recommended. Moreover, there is always a hysteresis

between the entry and exit thresholds to avoid oscillating between the two modes.

17

TPS43337-Q1

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In the event that both buck controllers are active, low-power mode is only possible when both buck controllers

have light loads that are low enough for entry into low-power mode. When the boost controller is enabled, low-

power mode is possible only if VBAT is high enough to prevent the boost from switching and if DIV is open or set

to GND. If DIV is high (VREG), low-power mode is inhibited.

Boost Controller

The boost controller has a fixed-frequency voltage-mode architecture and includes a cycle-by-cycle current-limit

protection for the external N-channel MOSFET. The switching frequency is derived from and set to one-half of

the buck-controller switching frequency. The output voltage of the boost controller at the VIN pin is set by an

internal resistor-divider network and is programmable to 7 V, 8.85 V, and 10 V based on the low, open, and high

status of the DIV pin, respectively. A change of the DIV setting is not recognized while the device is in low-power

mode.

The boost controller is enabled by the active-high ENC pin and is active when the input voltage at the VBAT pin

has crossed the unlock threshold of 8.5 V at least once. After that, the boost controller is armed and starts

switching as soon as VIN falls below the value set by the DIV pin, and regulates the VIN voltage. Thus, the boost

regulator maintains a stable input voltage for the buck regulators during transient events such as a cranking

pulse at VBAT.

Whenever the voltage at the DS pin exceeds 200 mV, the boost-external MOSFET is turned off by pulling the

CG1 pin low. By connecting the DS pin to the drain of the MOSFET or to a sense resistor between the MOSFET

source and ground, cycle-by-cycle overcurrent protection for the MOSFET can be achieved. The on-resistance of

the MOSFET or the value of the sense resistor must be chosen in such a way that the on-state voltage at DS

does not exceed 200 mV at the maximum load and minimum input-voltage conditions. When a sense resistor is

used, connecting a filter network between the DS pin and the sense resistor is recommended for better noise

immunity.

The boost output (VIN) is also used to supply other circuits in the system, however, they should be high-voltage

tolerant. The boost output is regulated to the programmed value only when VIN is low, and so VIN can reach

battery levels.

Vbat

VIN

DS

TPS43337-Q1

GC1

Figure 20. External Drain-Source Voltage Sensing

Vbat

VIN

TPS43337-Q1

GC1

R_IFLT

DS

C_IFLT

R_ISEN

Figure 21. External Current Shunt Resistor

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Table 1. Mode Control

SYNC

Terminal

Comments

External clock

Device in forced into continuous mode, internal PLL locks into the external clock between 150 kHz and 600 kHz

Device can enter discontinuous mode. Automatic LPM entry and exit, depending on load conditions

Device in forced into continuous mode

Low or open

High

Table 2. Mode of Operation

ENABLE AND INHIBIT PINS

DRIVER STATUS

DEVICE STATUS

QUIESCENT CURRENT

ENA ENB ENC SYNC BUCK CONTROLLERS

BOOST CONTROLLER

Disabled

Low

X

Shutdown

Approximately 4 µA

Approximately 34 µA (light loads)

mA range

Low

High

Low

High

BuckB: LPM enabled

BuckB: LPM inhibited

BuckA: LPM enabled

BuckA: LPM inhibited

Low

High

Low

BuckB running

Disabled

Approximately 34 µA (light loads)

mA range

High

Low

BuckA running

BuckA and BuckB: LPM

enabled

Low

Approximately 43 µA (light loads)

BuckA and BuckB

running

High

Disabled

BuckA and BuckB: LPM

inhibited

High

X

mA range

Low

Shutdown

Approximately 4 µA

Approximately 54 µA (no boost,

light loads)

Low

High

Low

High

Low

BuckB: LPM enabled

BuckB: LPM inhibited

BuckA: LPM enabled

BuckA: LPM inhibited

Boost running for VIN < set

boost output

High

BuckB running

mA range

Approximately 54 µA (no boost,

light loads)

Boost running for VIN < set

boost output

High

Low

High

BuckA running

mA range

BuckA and BuckB: LPM

enabled

Approximately 68 µA (no boost,

light loads)

BuckA and BuckB

running

Boost running for VIN < set

boost output

High

BuckA and BuckB: LPM

inhibited

High

mA range

Gate Driver Supply (VREG, EXTSUP)

The gate drivers of the buck and boost controllers are supplied from an internal linear regulator whose output

(5.8 V, typical) is available at the VREG pin and requires decoupling with a ceramic capacitor in the range of 3.3

µF to 10 µF. This pin has internal current-limit protection and should not be used to power any other circuits.

The VREG linear regulator is powered from VIN by default when the EXTSUP voltage is lower than 4.6 V

(typical). In case VIN is expected to go to high levels, there can be excessive power dissipation in this regulator,

especially at high switching frequencies and when using large external MOSFETs. In this case, powering this

regulator from the EXTSUP pin is advantageous, which can be connected to a supply lower than VIN but high

enough to provide the gate drive. When EXTSUP is connected to a voltage greater than 4.6 V, the linear

regulator automatically switches to EXTSUP as its input to provide this advantage. Efficiency improvements are

possible when one of the switching regulator rails from the TPS43337-Q1 or any other voltage available in the

system is used to power EXTSUP. The maximum voltage that should be applied to EXTSUP is 9 V.

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VIN

EXTSUP

LDO

VIN

LDO

EXTSUP

typ 5.8 V

typ 7.5 V

typ 4.6 V

VREG

Figure 22. Internal Gate-Driver Supply

Using a voltage above 5.8 V (sourced by VIN) for EXTSUP is advantageous as it provides a large gate drive and

therefore better on-resistance of the external MOSFETs.

During low-power mode, the EXTSUP functionality is not available. The internal regulator operates as a shunt

regulator powered from VIN and has a typical value of 7.5 V. Current-limit protection for VREG is available in

low-power mode as well. If EXTSUP is unused, leave the pin open without a capacitor installed.

External P-Channel Drive (GC2) and Reverse Battery Protection

The TPS43337-Q1 includes a gate driver for an external P-channel MOSFET, which can be connected across

the rectifier diode of the boost regulator which is useful to reduce power losses when the boost controller is not

switching. The gate driver provides a swing of 6 V typical below the VIN voltage in order to drive a P-channel

MOSFET. When VBAT falls below the boost enable threshold, the gate driver turns off the P-channel MOSFET,

and the diode is no longer bypassed.

The gate driver can also be used to bypass any additional protection diodes connected in series as shown in

Figure 23. Figure 24 also shows a different scheme of reverse battery protection which may require only a

smaller-sized diode to protect the N-channel MOSFET, as the diode conducts only for a part of the switching

cycle. Because the diode is not always in the series path, the system efficiency improves.

R10

GC2

TPS43337-Q1

D3

Q7

Q6

L3

Fuse (S1)

Vbat

VIN

DS

D1

D2

C17

C15

C16

C14

GC1

COMPC

C13

R9

VBAT

Figure 23. Reverse-Battery-Protection Option for Buck-Boost Configuration

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GC2

VIN

VBAT

Fuse

TPS43337-Q1

DS

GC1

COMPC

VBAT

Figure 24. Reverse-Battery-Protection Option for Buck-Boost Configuration

Undervoltage Lockout and Overvoltage Protection

The TPS43337-Q1 starts up at a VIN voltage of 6.5 V (minimum), required for the internal supply (VREG). Once

the has started up, it operates down to a VIN voltage of 3.6 V; below this voltage level, the undervoltage lockout

disables the device.

NOTE

If V_INdrops, V_REGdrops as well, reducing the gate-drive voltage, while the digital logic

remains fully functional. Even if ENC is high, exceeding the boost-unlock voltage of

typically 8.5 V one time is required before boost activation takes place (see the Boost

Controller section).

A voltage of 46 V at VIN triggers the overvoltage comparator, which shuts down the device. In order to prevent

transient spikes from shutting down the device, the undervoltage and overvoltage protection have filter times of 5

µs (typical).

When the voltages return to the normal-operating region, the enabled switching regulators start including a new

soft-start ramp for the buck regulators.

When the boost controller is enabled, a voltage less than 1.9 V (typical) on VBAT triggers an undervoltage

lockout and pulls the boost gate driver (GC1) low (this action has a filter delay of 5 µs, typical). As a result, VIN

falls at a rate dependent on the capacitor and load, eventually triggering VIN undervoltage. A short falling

transient at VBAT even lower than 2 V can thus be survived, if VBAT returns above 2.5 V before VIN is

discharged to the undervoltage threshold.

Thermal Protection

The TPS43337-Q1 protects itself from overheating using an internal thermal shutdown circuit. If the die

temperature exceeds the thermal shutdown threshold of 165°C due to excessive power dissipation (for example,

due to fault conditions such as a short circuit at the gate drivers or VREG), the controllers are turned off, and

then restarted when the temperature has fallen by 15°C.

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APPLICATION INFORMATION

The following example illustrates the design process and component selection for the TPS43337-Q1. The design

goal parameters are given in Table 3.

Table 3. Design Goal Parameters Example

PARAMETER

V_BUCKA

V_BUCKB

BOOST

V_IN6 to 30 V

12 V - typical

V_IN6 to 30 V

12 V - typical

V_BAT= 5 (cranking pulse

input) to 30 V

Input voltage

Output voltage, V_OUTx

3.396 V

3 A

1.235 V

2 A

10 V

Maximum output current, I_OUTx

2.5 A

Load step output tolerance, ∆V_OUT

ΔV_OUT(Ripple)

+

±0.2 V

±0.12 V

±0.5 V

Current output load step, ∆I_OUTx

0.1 to 3 A

400 kHz

0.1 to 2 A

400 kHz

0.1 to 2.5 A

200 kHz

Converter switching frequency, f_SW

This example is a starting point and theoretical representation of the values to be used for the application; further

optimization of the components derived may be required to improve the performance of the device.

Boost Component Selection

A boost converter operating in continuous-conduction mode (CCM) has a right-half-plane (RHP) zero in the

transfer function. The RHP zero is inversely related to the load current and inductor value and directly related to

the input voltage. The RHP zero limits the maximum bandwidth achievable for the boost regulator. If the

bandwidth is too close to the RHP zero frequency, the regulator may become unstable.

Thus, for high-power systems with low input voltages, a low inductor value is chosen. This value increases the

amplitude of the ripple currents in the N-channel MOSFET, the inductor and the capacitors for the boost

regulator. They must be designed with the ripple/RHP zero trade-off in mind and considering the power

dissipation effects in the components due to parasitic series resistance.

A boost converter that operates in the discontinuous mode does not contain the RHP-zero in transfer function.

However, designing for the discontinuous mode demands an even lower inductor value that has high ripple

currents. Also, ensure that the regulator never enters the continuous-conduction mode; otherwise, the regulator

becomes unstable.

VIN

C _O

7V

OTA-gm_EA

COMPx

R _ESR

-

8.85

V

C 1

R3

+

VREF

C 2

10V

Figure 25. Boost Compensation Components

This design is done assuming continuous-conduction mode. During light load conditions, the boost converter

operates in discontinuous mode without affecting stability. Hence, the assumptions here cover the worst case for

stability.

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Boost Maximum Input Current I_{IN_MAX}

The maximum input current is drawn at the minimum input voltage and maximum load. The efficiency for VBAT =

5 V at 2.3 A is 80%, based on the typical characteristics plot.

P_OUT

25 W

0.8

P

=

= 31.3 W

INmax

Efficiency

(5)

(6)

Hence,

31.3 W

I

(at V_BAT= 5 V) =

= 6.3 A

INmax

5 V

Boost Inductor Selection, L

Allow input ripple current of 40% of I_{IN max}at V_BAT= 5 V

V

_BAT´ t_ON

V_BAT

5 V

L =

=

= 4.9 mH

I

_INripplemax´ 2´ f_SW

2.52 A ´ 2´ 200 kHz

INripplemax

(7)

Choose a lower value of 3.9 µH in order to ensure a high RHP-zero frequency while making a compromise that

expects a high current ripple. This inductor selection also makes the boost converter operate in discontinuous

conduction mode, where it is easier to compensate.

The inductor saturation current must be higher than the peak inductor current and some percentage higher than

the maximum current-limit value set by the external resistive sensing element.

This rating should be determined at the minimum input voltage, maximum output current, and maximum core

temperature for the application.

Inductor Ripple Current, I_RIPPLE

Based on an Inductor value of 3.9 µH, the ripple current is approximately 3.1 A.

Peak Current in Low-Side FET, I_PEAK

I_RIPPLE

3.1 A

I_PEAK= I_INmax

+

= 6.3 A +

= 7.85 A

2

(8)

Based on this peak current value (see Equation 8), the external current-sense resistor R_SENSEis calculated in .

0.2 V

R_SENSE

=

= 25 mW

7.85 A

Select 20 mΩ, allowing for tolerance.

The filter component values R_IFLTand C_IFLTfor current sense are 1.5 kΩ and 1 nF, respectively, which allows for

good noise immunity.

Right Half-Plane Zero RHP Frequency, f_RHP

V_{BAT min}

f_RHP

=

= 32 kHz

2p´I_{In max}´L

(9)

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Output Capacitor, C_O

To ensure stability, the output capacitor C_Ois chosen such that

f

RHP

f_LC

£

10

V_BATmin

10

£

2p´I_INmax´L

2p´ L ´ C_OUTx

ö²

÷

æ

ç

è

ö²

÷

ø

10´I

æ

10´ 6.3 A

5 V

INmax

C_OUTx

³

´L =

´ 3.9 mH

ç

V_BATmin

è

ø

C_OUTxmin³ 635 mF

(10)

Select C_OUTx= 680 µF.

This capacitor is usually aluminum electrolytic with ESR in the tens-of-milliohms which is good for loop stability,

because it provides a phase boost due to the ESR. The output filter components L and C create a double pole

(180 degree phase-shift) at a frequency f_LC, and the ESR of the output capacitor R_ESRcreates a zero for the

modulator at frequency f_ESR. These frequencies can be determined by Equation 11.

1

f_ESR

=

Hz, assume R_ESR= 40 mW

2p´ C_OUTx´R_ESR

1

f_ESR

=

= 6 kHz

2p´ 680 mF´ 0.04

1

f_LC

=

= 3.1 kHz

2p´ L ´ C_OUTx

2p´ 4 mH´ 680 mF

(11)

This satisfies f_LC≤ 0.1 f_RHP

.

Bandwidth of Boost Converter, f_C

Use the following guidelines to set the frequency poles, zeroes, and crossover values for the trade-off between

stability and transient response:

f_LC< f_ESR< f_C< f_{RHP Zero}

f_C< f_{RHP Zero}/ 3

f_C< f_SW/ 6

f_LC< f_C/ 3

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Output Ripple Voltage Due to Load Transients, ∆V_O

Assume a bandwidth of f_C= 10 kHz.

DI

OUTx

DV_OUTx= R_ESR´ DI_OUTx

+

4 ´ C

´ f_C

OUTx

2.5 A

= 0.04 W ´ 2.5 A +

= 0.19 V

4 ´ 660 mF´10 kHz

(12)

Because the boost converter is active only during brief events such as a cranking pulse, and the buck converters

are high-voltage tolerant, a higher excursion on the boost output may be tolerable in some cases. In such cases,

smaller component choices for the boost output may be used.

Selection of Components for Type II Compensation

The required loop gain for unity gain bandwidth (UGB) is shown in Equation 13.

æ

ö

æ

ö

f_C

G = 40 log

- 20 log

ç

÷

ç

÷

ç

÷

ç

÷

f_LC

f_ESR

è

ø

è

ø

æ

ç

è

ö

æ

ö

10 kHz

3.1kHz

10 kHz

6 kHz

- 20 log

= 15.9 dB

÷

ç

÷

ø

è

ø

(13)

The boost converter error amplifier (OTA) has a Gm that is proportional to the V_BATvoltage which allows a

constant loop response across the input voltage range and makes it easier to compensate by removing the

dependency on V_BAT

.

10^G/20

85 ´10^-6A / V²´ V_OUTx

R3 =

C1=

C2 =

= 7.2 kW

10

=

= 22 nF

2p´ f_C´R3 2p´10 kHz ´ 7.2 kW

C1

22 nF

=

= 223 pF

choose 220 pF

f

200 kHz

2

æ

ö

æ

ö

SW

2p´ 7.2 kW ´ 22nF ´

-1

2p´R3 ´ C1´

-1

ç

÷

ç

÷

2

è

ø

è

ø

(14)

Input Capacitor, C_IN

The input ripple required is lower than 50 mV.

I_RIPPLE

DV_C1

=

= 10 mV

8´ f_SW´C_IN

I_RIPPLE

C_IN

=

= 194-μF

8´ f_SW´ DV_C1

DV_ESR= I_RIPPLE´R_ESR= 40 mV

(15)

25

Therefore, TI recommends 220 µF with 10-mΩ ESR.

TPS43337-Q1

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Output Schottky Diode D1 Selection

A Schottky diode with low forward-conducting voltage V_Fover temperature and fast switching characteristics is

required to maximize efficiency. The reverse breakdown voltage should be higher than the maximum input

voltage, and the component should have low reverse-leakage current. Additionally, the peak forward current

should be higher than the peak inductor current. The power dissipation in the Schottky diode is given in

Equation 16.

P = I_D(PEAK)´ V_F´(1- D)

D

V

5V

INMIN

D = 1-

= 1-

= 0.53

V_OUT+ V_F

10V + 0.6V

P = 7.85 A ´ 0.6 V ´(1- 0.53) = 2.2 W

D

(16)

Low-Side MOSFET (BOT_SW3)

V ´I

æ

ö

= (I_Pk)²´r_DS(on)(1+ TC)´D +

´(t_r+ t_f)´ f_sw

I

Pk

P

BOOSTFET

ç

÷

2

è

ø

V ´I

æ

ö

= (7.85 A)²´ 0.02 W ´(1+ 0.4)´ 0.53 +

´(20 ns + 20 ns)´ 200 kHz = 1.07 W

I

Pk

P

BOOSTFET

ç

÷

2

è

ø

(17)

The times t_rand t_fdenote the rising and falling times of the switching node and are related to the gate-driver

strength of the TPS43337-Q1 and gate Miller capacitance of the MOSFET. The first term denotes the conduction

losses, which are minimized when the on-resistance of the MOSFET is low. The second term denotes the

transition losses which arise due to the full application of the input voltage across the drain-source of the

MOSFET as it turns on or off. They are higher at high output currents and low input voltages (due to the large

input peak current) and when the switching time is low.

NOTE: The on-resistance r_DS(on)has a positive temperature coefficient, which produces the (TC = d × ΔT) term

that signifies the temperature dependence. (Temperature coefficient d is available as a normalized value from

MOSFET data sheets and can be assumed to be 0.005 / ºC as a starting value.)

BuckA Component Selection

Minimum ON Time, t_{ON min}

V_O

3.4 V

t_{ON min}

=

= 283 ns

V_{IN max}´ f_SW30 V ´ 400 kHz

(18)

As shown in Equation 18, t_{ON min}is higher than the minimum duty cycle specified (100 ns, typical). Hence the

minimum duty cycle is achievable at this frequency.

Current-Sense Resistor R_SENSE

Based on the typical characteristics for V_SENSElimit with V_INversus duty cycle, the sense limit is approximately 70

mV (at VIN = 12 V and duty cycle of 3.4 V / 12 V = 0.283). Allowing for tolerances and ripple currents, choose

V_SENSEmaximum of 55 mV.

55 mV

R_SENSE

=

= 18 mW

3 A

Select 18 mΩ.

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Inductor Selection L

As explained in the description of the buck controllers (see Detailed Description), for optimal slope compensation

and loop response, the inductor should be chosen such that:

R_SENSE

18 mW

L = K_FLR

´

= 200´

= 9.2mH

f_SW

400 kHz

•

K_FLR= Coil selection constant = 200

(19)

Choose a standard value of 10 µH. For the buck converter, the inductor saturation currents and core should be

chosen to sustain the maximum currents.

Inductor Ripple Current I_RIPPLE

At the nominal input voltage of 12 V, this gives a ripple current of 25% of I_OUTmax≈ 1 A.

Output Capacitor C_O

Select an output capacitance C_Oof 100 µF with low ESR in the range of 10 mΩ. This gives ∆V_O(Ripple)≈ 15 mV

and ∆V drop of ≈ 180 mV during a load step, which does not trigger the power-good comparator and is within the

required limits.

2´ DI_OUTA

=

f_SW´ DV_OUTA400 kHz ´0.2 V

2´ 2.9 A

C_OUTA

»

= 72.5 mF

(20)

(21)

(22)

I_OUTA(Ripple)

1 A

V_OUTA(Ripple)

=

+ I_OUTA(Ripple)´ESR =

+1 A ´10 mW = 13.1mV

8´ f_SW´ C_OUTA

8´ 400 kHz ´100 mF

DI_OUTA

2.9 A

4´ 50 kHz ´100 mF

DV_OUTA

=

+ DI_OUTA´ESR =

+ 2.9 A ´10 mW = 174 mV

4´ f_C´ C_OUTA

Bandwidth of Buck Converter f_C

Use the following guidelines to set frequency poles, zeroes, and crossover values for the trade-off between

stability and transient response.

•

Crossover frequency f_Cbetween f_SW/ 6 and f_SW/ 10. Assume f_C= 50 kHz.

Select the zero f_z≈ f_C/ 10

Make the second pole f_P2≈ f_SW/ 2

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Selection of Components for Type II Compensation

V_OUT

F

Bx

R_ESR

C_OUT

R_L

COMP

Type 2A

Gm_BUCK

V_REF

R3

R0

C2

C1

Figure 26. Buck Compensation Components

2p´ f_C´ V_OUTA´ C_OUTA

Gm_BUCK´K_CFB´ V_REF

2p´ 50 kHz ´ 3.4 V ´100 mF

Gm_BUCK´K_CFB´ V_REF

R3 =

=

= 19 kW

Use standard value of R3 = 18 kΩ

where:

•

V_O= 3.4 V

C_O= 100 µF

Gm = 1 mS

V_REF= 0.8 V

K_CFB= 0.125 / R_SENSE= 6.9 (0.125 is an internal constant)

(23)

(24)

Use standard value of 1.8 nF.

C1

1.8 nF

C2 =

=

= 45 pF

f

400 kHz

2

æ

ç

ö

æ

ç

ö

SW

2p´18 kW ´1.8 nF

-1

2p´R3 ´ C1

-1

÷

2

è

ø

è

ø

(25)

Use standard value of 47 pF.

The resulting bandwidth of buck converter f_C

Gm_BUCK´R3´K_CFBV_REF

f_C=

´

2p´C_OUTA

V_OUT

1mS´18 kW´ 6.9 S´0.8 V

2p´100 μF´ 3.4 V

f_C=

= 46.5 kHz

(26)

(27)

f_Cis close to the target bandwidth of 50 kHz.

The resulting zero frequency f_Z1

1

f_Z1

=

2p´R3 ´ C1 2p´18 kW ´1.8 nF

= 4.9 kHz

= 188 kHz

f_Z1is close to the f_C/ 10 guideline of 5 kHz

The second pole frequency f_P2

1

f_P2

=

2p´R3 ´ C2 2p´18 kW ´ 47 pF

(28)

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f_P2is close to the f_SW/ 2 guideline of 200 kHz. Hence, all requirements for a good loop response are satisfied.

BuckB Component Selection

Using the same method as VBUCKA, the following parameters and components are realized in Equation 29.

V_OUTB

1.235 V

t_{ON min}

=

= 103 ns

V

_{IN max}´ f_SW30 V ´ 400 kHz

(29)

This t_ONminis on the edge of the minimum duty cycle specified (100 ns, typical); expect pulse-skipping at high V_IN.

60 mV

R_SENSE

=

= 30 mW

2A

30 mW

L = 200 ´

= 15 mH

400 kHz

choose 30 mΩ, 15 µH.

•

∆I_ripplecurrent ≈ 0.4 A (approx. 20% of I_{O max})

Select an output capacitance C_Oof 100 µF with low ESR in the range of 10 mΩ. This gives ∆V_O(ripple) ≈ 7.5 mV

and ∆V drop of ≈ 120 mV during a load step.

Assume f_C= 50 kHz.

2´ DI_OUTB

=

f_SW´ DV_OUTB400 kHz ´ 0.12 V

2´1.9 A

C_OUTB

»

= 46 mF

(30)

(31)

(32)

I_OUTB(Ripple)

0.4 A

V_OUTB(Ripple)

=

+ I_OUTB(Ripple)´ESR =

+ 0.4 A ´10 mW = 5.3 mV

8´ f_SW´ C_OUTB

8´ 400 kHz ´100 mF

DI_OUTB

1.9 A

DV_OUTB

=

+ DI_OUTB´ESR =

+1.9 A ´10 mW = 114 mV

4´ f_C´ C_OUTB

4´ 50 kHz ´100 mF

2p´ f_C´ V_OUTB´ C_OUTB

Gm_BUCK´K_CFB´ V_REF

R3 =

2p´ 50 kHz ´1.235 V ´100 mF

1mS

´

4.16S

´

0.8V

=

= 11.7 kW

(33)

(34)

Use standard value of R3 = 12 kΩ.

10

C1=

=

2p´R3 ´ f_C2p´12 kW ´ 50 kHz

= 2.7 nF,

choose 2.7nF

C1

C2 =

f

æ

ö

SW

2p´R3 ´ C1´

-1

ç

÷

2

è

ø

2.7 nF

=

= 68 pF, choose 68 pF

400 kHz

2

æ

ö

2p´12 kW ´ 2.7 nF ´

-1

ç

÷

è

Gm_BUCK´R3 ´K_CFBV_REF

ø

(35)

f_C=

´

2p´ C_OUTB

VO

1mS ´12 kW ´ 4.16 ´ 0.8

2p´100 mF´1.235 V

f_C=

= 51.5 kHz

(36)

29

f_Cis close to the target bandwidth of 50 kHz.

TPS43337-Q1

ZHCSBJ4A –AUGUST 2013–REVISED SEPTEMBER 2013

www.ti.com.cn

The resulting zero frequency f_Z1

1

f_Z1

=

2p´R3 ´ C1 2p´12 kW ´ 2.7 nF

= 4.9 kHz

f_Z1is close to the f_C/ 10 guideline of 5 kHz.

The second pole frequency f_P2

1

f_P2

=

2p´R3 ´ C2 2p´12kW ´ 68 pF

= 195 kHz

(37)

f_P2is close to the f_SW/ 2 guideline of 200 kHz.

Hence, all requirements for a good loop response are satisfied.

BuckX High-Side and Low-Side N-Channel MOSFETs

The gate-drive supply for these MOSFETs is supplied by an internal supply which is 5.8 V (typical) under normal

operating conditions. The output is a totem pole, allowing full voltage drive of V_REGto the gate with peak output

current of 1.2 A. The high-side MOSFET is referenced to a floating node at the phase terminal (PHx) and the

low-side MOSFET is referenced to the power ground (PGx) terminal. For a particular application, these

MOSFETs should be selected with consideration for the following parameters: r_ds(on), gate charge Qg, drain-to-

source breakdown voltage BVDSS, maximum dc current IDC(max), and thermal resistance for the package.

The times t_rand t_fdenote the rising and falling times of the switching node and are related to the gate-driver

strength of the TPS43337-Q1 and gate Miller capacitance of the MOSFET. The first term denotes the conduction

losses, which are minimized when the on-resistance of the MOSFET is low. The second term denotes the

transition losses, which arise due to the full application of the input voltage across the drain-source of the

MOSFET as it turns on or off. They are lower at low currents and when the switching time is low.

V ´I

æ

ö

= (I_OUT)²´r_DS(on)(1+ TC)´D +

´(t_r+ t_f)´ f_SW

IN

OUT

P

BuckTOPFET

ç

÷

2

è

ø

(38)

(39)

P

= (I_OUT)²´r_DS(on)(1+ TC)´(1-D) + V_F´I_OUT´(2´ t_d)´ f_SW

BuckLOWERFET

In addition, during the dead time t_dwhen both the MOSFETs are off, the body diode of the low-side MOSFET

conducts, increasing the losses which is denoted by the second term in the Equation 39. Using external Schottky

diodes in parallel to the low-side MOSFETs of the buck converters helps to reduce this loss.

Note that r_DS(on)has a positive temperature coefficient which is accounted for in the TC term for r_DS(on), TC = d ×

ΔT[°C]. The temperature coefficient, d, is available as a normalized value from MOSFET data sheets and can be

assumed to be 0.005 / ºC as a starting value.

30

TPS43337-Q1

www.ti.com.cn

ZHCSBJ4A –AUGUST 2013–REVISED SEPTEMBER 2013

Schematic

The following section summarizes the previously calculated example and gives a schematic and component

proposals.

Table 4. Application Example

PARAMETER

V_BUCKA

V_BUCKB

BOOST

V_IN= 6 to 30 V

12 V - typical

V_IN= 6 to 30 V

12 V - typical

V_BAT= 5 (cranking pulse

input) to 30 V

Input voltage

Output voltage, V_OUTx

3.396 V

3 A

1.235 V

2 A

10 V

2.5 A

Maximum output current, I_OUTx

Load-step output tolerance, ∆V_OUT+ ΔV_OUT(Ripple)

Current output load step, ∆I_OUTx

Converter switching frequency, f_SW

±0.2 V

±0.12 V

0.1 to 2 A

400 kHz

±0.5 V

0.1 to 3 A

400 kHz

0.1 to 2.5 A

200 kHz

5 V to 30 V

V_BAT

L1

D1

BOOST — 10V, 25W

3.9 µH

680 µF

C_OUT1

10µF

C_IN

220 µF

TOP-SW3

1kΩ

VBAT

DS

VIN

EXTSUP

DIV

BOT-SW3

0.025Ω

1.5 kΩ

1nF

GC1

GC2

VREG

CBB

CBA

TOP-SW2

L3

TOP-SW1

L2

0.1µF

0.1 µF

V_BuckA— 3.4 V, 10.2 W 0.018 Ω

V_BuckB— 1.235 V, 2 W

0.03 Ω

GA1

GB1

10 µH

15 µH

100µF

C_OUTA

100 µF

C_OUTB

PHA

PHB

BOT-SW2

BOT-SW1

GA2

GB2

PGNDA

SA1

PGNDB

SB1

TPS43337-Q1

SA2

SB2

FBA

FBB

COMPA

SSA

COMPB

SSB

47 pF

68 pF

1.8 nF

2.7 nF

12 kΩ

18 kΩ

PGA

ENA

PGB

5k Ω

500 nF

AGND

RT

ENB

COMPC

ENC

DLYAB

SYNC

220 pF

22 nF

1 nF

7.2 kΩ

Figure 27. Schematic - Application Example

Table 5. Application Example - Component Proposals

Name

Component Proposal

Value

3.9 µH

10 µH

15 µH

L1

L2

L3

D1

MSS1278T-392NL (Coilcraft)

MSS1278T-103ML (Coilcraft)

MSS1278T-153ML (Coilcraft)

SK103 (Micro Commercial Components)

IRF7416 (International Rectifier)

TOP_SW3

TOP_SW1, TOP_SW2 Si4840DY-T1-E3 (Vishay)

BOT_SW1, BOT_SW2 Si4840DY-T1-E3 (Vishay)

BOT_SW3

COUT1

IRFR3504ZTRPBF (International Rectifier)

EEVFK1J681M (Panasonic)

ECASD91A107M010K00 (Murata)

EEVFK1J221Q (Panasonic)

680 µF

100 µF

220 µF

C_OUTA, C_OUTB

C_IN

31

TPS43337-Q1

ZHCSBJ4A –AUGUST 2013–REVISED SEPTEMBER 2013

www.ti.com.cn

Power Dissipation Derating Profile, 38-Pin HTTSOP Package With PowerPAD Package

Figure 28. Power Dissipation Derating Profile Based on High-K JEDEC PCB

PCB Layout Guidelines

Grounding and PCB Circuit Layout Considerations

Boost Converter

1. The path formed from the input capacitor to the inductor and BOT_SW3 with the low-side current-sense

resistor should have short leads and PC trace lengths. The same applies for the trace from the inductor to

the Schottky diode D1 to the COUT1 capacitors. The negative terminal of the input capacitor and the

negative terminal of the sense resistor must be connected together with short trace lengths.

2. The overcurrent-sensing shunt resistor may require noise filtering, and this capacitor should be close to the

IC pin.

Buck Converter

1. Connect the drains of TOP_SW1 and TOP_SW2 together with the positive terminal of input capacitor

COUT1. The trace length between these terminals should be short.

2. Connect a local decoupling capacitor between the drain of TOP_SWx and the source of BOT_SWx.

3. The Kelvin-current sensing traces for the shunt resistor should have minimum trace spacing and be routed

parallel to each other. Any filtering capacitors for noise should be placed near the IC pins.

4. Connect the positive terminal of the respective output capacitor C_OUTAor C_OUTBto the respective feedback

input FBA or FBB. Do not connect these traces near any switching nodes or high-current traces.

Other Considerations

1. PGNDx and AGND should be shorted to the thermal pad. Use a star-ground configuration if connecting to a

non-ground-plane system. Use tie-ins for the EXTSUP capacitor, compensation-network ground, and

voltage-sense-feedback ground networks to this star ground.

2. Connect a compensation network between the compensation pins and IC signal ground. Connect the

oscillator resistor (frequency setting) between the RT pin and IC signal ground. These sensitive circuits

should not be located near nodes showing high dv/dt; these include the gate-drive outputs, phase pins, and

boost circuits (bootstrap).

3. Reduce the surface area of the high-current-carrying loops to a minimum, by ensuring optimal component

placement. Ensure the bypass capacitors are located as close as possible to their respective power and

ground pins.

32

TPS43337-Q1

www.ti.com.cn

ZHCSBJ4A –AUGUST 2013–REVISED SEPTEMBER 2013

PCB Layout

POWER

INPUT

Power L ines

Connection to GND P lane ofPCB through vias

Connection to top /bottom ofPCB through vias

Vo ltage Ra ilOutputs

V_BOOST

VBAT

DS

V IN

EXTSUP

D IV

GC1

GC2

CBA

VREG

CBB

GA1

PHA

GB1

PHB

GA2

PGNDA

SA1

GB2

PGNDB

SB1

SA2

SB2

FBA

FBB

COMPA

SSA

COMPB

SSB

PGA

ENA

PGB

AGND

RT

ENB

COMPC

ENC

DLYAB

SYNC

Exposed Pad

connected to GND

P lane

M icrocontro ller

33

TPS43337-Q1

ZHCSBJ4A –AUGUST 2013–REVISED SEPTEMBER 2013

www.ti.com.cn

REVISION HISTORY

Changes from Original (August 2013) to Revision A

Page

•

Changed 文档状态从产品预览改为生成数据 ........................................................................................................................ 1

34

PACKAGE MATERIALS INFORMATION

www.ti.com

15-Feb-2019

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0

B0

K0

P1

W

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

TPS43337QDAPRQ1 HTSSOP

DAP

38

2000

330.0

24.4

8.6

13.0

1.8

12.0

24.0

Q1

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

15-Feb-2019

*All dimensions are nominal

Device

Package Type Package Drawing Pins

HTSSOP DAP 38

SPQ

Length (mm) Width (mm) Height (mm)

350.0 350.0 43.0

TPS43337QDAPRQ1

2000

Pack Materials-Page 2

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型号：	TPS43337-Q1
厂家：	TEXAS INSTRUMENTS
描述：	汽车类 2V 至 40V 低 Iq 单路升压和双路固定输出电压同步降压控制器控制器
文件：	总41页 (文件大小：2032K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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