TPS65232A2 [TI]
采用 HTSSOP 封装的宽输入电压电源管理 IC (PMIC);
| 型号： | TPS65232A2 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 采用 HTSSOP 封装的宽输入电压电源管理 IC (PMIC) 集成电源管理电路 电源电路 |
| 文件： | 总31页 (文件大小：1861K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Not Recommended for New Designs
TPS65232
www.ti.com
SLVSA42 –FEBRUARY 2010
TRIPLE BUCK POWER MANAGEMENT IC
Check for Samples: TPS65232
1
FEATURES
•
Pull-Up Current Sources on Buck Enable Pins
for Accurate Start-Up Timing Control with
Preset Default
•
Wide Input Supply Voltage Range
(10.8 V - 22 V)
•
•
Over Current Protection on All Rails
•
One Adjustable PWM Buck Controller
Thermal Shutdown to Protect Device During
Excessive Power Dissipation
–
–
–
–
–
10.8-V - 22-V Input Voltage Range
3.3-V - 6.1-V Output Voltage Range
500-kHz Switching Frequency
Type III Compensation
•
Thermally Enhanced Package for Efficient
Heat Management (48-pin HTSSOP or
6-mm x 6-mm 40-Pin QFN)
Programmable Current Limit
•
Two Adjustable Step-Down Converter With
Integrated Switching FETs:
APPLICATIONS
•
•
•
xDSL and Cable Modems
Wireless Access Points
STB, DTV, DVD and Home Gateway
–
–
–
–
–
4.75-V - 5.5-V Input
0.9-V-3.3-V Output Voltage Range
3-A Output Current
1-MHz Switching Frequency
Type III Compensation
DESCRIPTION/ORDERING INFORMATION
The TPS65232 provides one PWM buck controller, two adjustable, synchronous buck regulators. The SMPS
have integrated switching FETs for optimized power efficiency and reduced external component count. All power
blocks have thermal and over current/short circuit protection. The TPS65232 startup timing can be controlled
through buck enable pins. The buck controller and buck converters have internal pole/zero pairs to help
stabilizing the system with minimum external components.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2010, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Not Recommended for New Designs
TPS65232
SLVSA42 –FEBRUARY 2010
www.ti.com
FUNCTIONAL BLOCK DIAGRAM
12-V DC Supply
Optional
VINB and VINBQ pins must be tied
togther on PC board
12V
HDRV
BST1
PH1
VIN
Vout BUCK1
EN_BCK1
EN_BCK2
EN_BCK3
from enable logic
from enable logic
from enable logic
BUCK1
LDRV
FB1
CMP1
BST2
PH2a
PH2b
FB2
REF
VINB2
Vout BUCK2
BUCK2
TRIM
TSD
OSC
CMP2
UVLO
V3p3
V6V
BST3
PH3a
PH3b
FB3
VINB3
INTERNAL
VOLTAGE RAILS
Vout BUCK3
BUCK3
CMP3
ORDERING INFORMATION(1)
TA
PACKAGE(2)
ORDERABLE PART NUMBER
TOP-SIDE MARKING
TPS65232
48-pin (HTSSOP) - DCA
40-pin (QFN) - RHA
Reel of 2000
Reel of 2500
TPS65232A2DCAR
0°C to 85°C
TPS65232A0RHAR
TPS65232
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
2
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Product Folder Link(s): TPS65232
Not Recommended for New Designs
TPS65232
www.ti.com
SLVSA42 –FEBRUARY 2010
PIN OUT (DCA)
DCA PACKAGE
(TOP VIEW)
BG
VINBQ
V6V
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
BST3
2
3
VIN
4
FB2
5
CMP2
EN_BCK2
PGND2
PGND2
PH2
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
VINB3
VINB3
PH3
PH2
VINB2
VINB2
BST2
DGND
LDRV
HDRV
PH1
PH3
PGND3
PGND3
EN_BCK3
CMP3
FB3
BST1
EN_BCK1
CMP1
FB1
AGND
AGND
AGND
AGND
AGND
V3P3
SS
TRIP
Copyright © 2010, Texas Instruments Incorporated
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Not Recommended for New Designs
TPS65232
SLVSA42 –FEBRUARY 2010
www.ti.com
TERMINAL FUNCTIONS (DCA)
NAME
BG
NO.
1
I/O
DESCRIPTION
I
I
I
I
I
I
I
Reference filter pin
VINBQ
V6V
2
Reference supply for BUCK2 and BUCK3
Filter pin for internal voltage regulator (6 V)
Input supply for BUCK1 and support circuitry
Feedback pin (BUCK2)
3
VIN
4
FB2
5
CMP2
EN_BCK2
PGND2
PH2
6
Regulator Compensation (BUCK2)
Enable pin for BUCK2, active high
Power ground BUCK2
7
8, 9
10, 11
12, 13
14
15
16
17
18
19
20
21
22
23
24
25
O
I
Switching pin (BUCK2)
VINB2
BST2
Input supply for BUCK2 (must be tied to VINB3, VINBQ)
Bootstrap input (BUCK2)
DGND
LDRV
HDRV
PH1
Digital ground
O
O
O
I
Low-side gate drive output (PWM controller)
High-side gate drive output (PWM controller)
Switching pin (BUCK1)
BST1
Bootstrap input (BUCK1)
EN_BCK1
CMP1
FB1
I
Enable pin for BUCK1, active high
Regulator compensation (PWM controller)
Feedback pin (PWM controller)
External capacitor for soft start
BUCK1 over current trip point set-up
Filter pin for internal voltage regulator (3.3 V)
Analog ground
I
I
SS
I
TRIP
I
V3P3
I
AGND
26, 27, 28, 29,
30, 41, 42, 43,
44, 45, 46, 47, 48
FB3
31
32
I
I
I
Feedback pin (BUCK3)
CMP3
EN_BCK3
PGND3
PH3
Regulator compensation (BUCK3)
Enable pin for BUCK3, active high
Power ground BUCK3
33
34, 35
36, 37
38, 39
40
O
I
Switching pin (BUCK3)
VINB3
BST3
Input supply for BUCK3 (must be tied to VINB2, VINBQ)
Bootstrap input (BUCK3)
I
4
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Product Folder Link(s): TPS65232
Not Recommended for New Designs
TPS65232
www.ti.com
SLVSA42 –FEBRUARY 2010
PIN OUT (RHA)
RHA PACKAGE
(TOP VIEW)
40 39 38 37 36 35 34 33 32 31
30
BST3
1
AGND
AGND
V3P3
TRIP
SS
29
28
AGND
AGND
AGND
BG
2
3
4
5
27
26
Thermal
Pad
25
FB1
VINBQ
V6V
6
7
CMP1
24
23
22
VIN
8
9
EN_BCK1
BST1
FB2
21
10
CMP2
PH1
11 12 13 14 15 16 17 18 19 20
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Not Recommended for New Designs
TPS65232
SLVSA42 –FEBRUARY 2010
www.ti.com
TERMINAL FUNCTIONS (RHA)
NAME
BG
NO.
5
I/O
DESCRIPTION
I
I
I
I
I
I
I
Reference filter pin
VINBQ
V6V
6
Reference supply for BUCK2 and BUCK3
Filter pin for internal voltage regulator (6 V)
Input supply for BUCK1 and support circuitry
Feedback pin (BUCK2)
7
VIN
8
FB2
9
CMP2
EN_BCK2
PGND2
PH2
10
11
12
13, 14
15, 16
17
18
19
20
21
22
23
24
25
26
27
28
Regulator compensation (BUCK2)
Enable pin for BUCK2, active high
Power ground BUCK2
O
I
Switching pin (BUCK2)
VINB2
BST2
Input supply for BUCK2 (must be tied to VINB3, VINBQ)
Bootstrap input (BUCK2)
DGND
LDRV
HDRV
PH1
Digital ground
O
O
O
I
Low-side gate drive output (PWM controller)
High-side gate drive output (PWM controller)
Switching pin (BUCK1)
BST1
Bootstrap input (BUCK1)
EN_BCK1
CMP1
FB1
I
Enable pin for BUCK1, active high
Regulator compensation (PWM controller)
Feedback pin (PWM controller)
External capacitor for soft start
BUCK1 over current trip point set-up
Filter pin for internal voltage regulator (3.3 V)
Analog ground
I
I
SS
I
TRIP
I
V3P3
I
AGND
2, 3, 4, 29, 30,
31, 32, 33
FB3
34
35
I
I
Feedback pin (BUCK3)
CMP3
EN_BCK3
PH3
Regulator Compensation (BUCK3)
Enable pin for BUCK3, active high
Switching pin (BUCK3)
36
I
37, 38
39, 40
1
O
I
VINB3
BST3
Input supply for BUCK3 (must be tied to VINB2, VINBQ)
Bootstrap input (BUCK3)
I
6
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Product Folder Link(s): TPS65232
Not Recommended for New Designs
TPS65232
www.ti.com
SLVSA42 –FEBRUARY 2010
ABSOLUTE MAXIMUM RATINGS(1) (2)
over operating free-air temperature range (unless otherwise noted)
Input voltage range at VIN
–0.3 to 25
–0.3 to 7.0
–0.3 to 3.6
–0.3 to 31
–0.3 to 24
–0.3 to 3.6
–0.3 to 7.0
–0.3 to 15
3.8
V
V
V
V
V
V
V
V
A
Input voltage range at VINB, VINBQ
Voltage range at EN_BCK1, EN_BCK2, EN_BCK3
Voltage on HDRV, BST1
Voltage on PH1
Voltage on FB1, CMP1, FB2, CMP2, FB3, CMP3
Voltage on PH2, PH3, LDRV
Voltage on BST2, BST3
Output current at BUCK2, BUCK3
Peak output current
Internally limited
2k
Human body model (HBM)
ESD rating
V
°C/W
W
Charged device model (CDM)
500
TSSOP
QFN
25
qJA
Thermal resistance – Junction to ambient(3)
18.1
Continuous total power dissipation 55°C(3) no thermal
warning
TSSOP
QFN
2.6
2.5
TJ
Operating virtual junction temperature range
Operating ambient temperature range
Storage temperature range
0 to 150
0 to 85
°C
°C
°C
TA
TSTG
–65 to 150
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to network ground terminal.
(3) Using JEDEC 51-5 (High K) board. This is based on standard 48DCA package, 4 layers, top/bottom layer: 2 oz Cu, inner layer: 1 oz Cu.
Board size: 114.3 x 76.2 mm (4.5 x 3 inches), board thickness: 1.6 mm (0.0629 inch).
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TPS65232
SLVSA42 –FEBRUARY 2010
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RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
MIN
10.8
4.75
0
NOM
MAX
22
UNIT
Input voltage range at VIN
12
V
Input voltage range at VINB
6.1
3.3
50
Voltage range, EN_BCK1, EN_BCK2, EN_BCK3
V
TA
Ambient operating temperature
0
°C
ELECTRICAL CHARACTERISTICS
VIN = 12 V ±5%, VINB2, VINB3 = 5 V ±5%, TJ = 0°C to 150°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
10.8
4.7
TYP
MAX UNIT
INPUT VOLTAGE
VIN
Input supply voltage
12
22
V
V
VIN rising
10.8
UVLO VIN
UVLO threshold – VIN (main supply)
VIN falling
VINB rising
VINB falling
4.75
4
UVLO threshold – VINB
(BUCK2/BUCK3 supply)
UVLO VINB
V
4.25
INPUT CURRENT
All regulators/USB switches
disabled
ICCQ
Input supply current
mA
BUCK ENABLE INPUTS (EN_BCK1,2,3)
VEN
VENHYS
IPULLUP
RD
Enable threshold
Enable voltage hysteresis
Pull-up current
1.2
100
6
V
mV
mA
kΩ
ms
tEN = 0.2 ms/nF
Power-up
Discharge resistor
Discharge time
1
tD
5
PWM CONTROLLER (BUCK1)
VOUT
VFB
Output voltage range(1)
3.3
6.1
2%
V
V
Feedback voltage
–2%
0.804
6
LDRV
HDRV
High and low side drive voltage
No load
V
R_ONLDRV
R_OFFLDRV
R_ONHDRV
R_OFFHDRV
d
Low side ON resistance
Low side OFF resistance
High side ON resistance
High side OFF resistance
Duty cycle(2)
8
1
Ω
Ω
Ω
Ω
%
20
1
20
80
AMOD
Modulator gain
12
fSW
Switching frequency
500
kHz
Current source for setting OCP trip
point
ITRIP
TA = 25°C
10
mA
TCTRIP
RTRIP
COUT
L
Temperature coefficient of ITRIP
Current-limit setting resistor
Output capacitance
3700
ppm/°C
kW
80
22(3)
250
mF
Nominal inductance
Recommended
4.7
mH
BUCK2
VOUT
VFB
Output voltage range(1)
Feedback voltage
0.9
3.3
2%
V
V
– 2%
0.804
(1) Output voltage range is limited by the minimum and maximum duty cycle. VOUT(min) ~ d(min) x VINPUT and VOUT(max) ~ d(max) x
VINPUT
.
(2) Performance outside these limits is not guaranteed.
(3) Absolute value. User should make allowances for tolerance and variations due to component selection.
8
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TPS65232
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SLVSA42 –FEBRUARY 2010
ELECTRICAL CHARACTERISTICS (continued)
VIN = 12 V ±5%, VINB2, VINB3 = 5 V ±5%, TJ = 0°C to 150°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
IOUT
Output current
3000
mA
%
h
Efficiency
IO = 2 A, VOUT = 3.3V
VIN12V = 12 V
95
32
36
5
Low-side MOSFET On resistance
High-side MOSFET On resistance
Switch current limit
RDS(ON)
ILIMIT
mΩ
A
Current limit accuracy
–30
30
1
%
Line regulation - DC
ΔVOUT/ΔVINB
VINB = 4.75 V - 6.1 V,
IOUT = 1 A
VLINEREG
VLOADREG
VOUTTOL
%
Load regulation - DC
ΔVOUT/ΔIOUT
IOUT = 10 – 90% IOUT,MAX
0.5
%/A
Feedback resistor tolerance
not included
DC set tolerance
–2
15
2
%
%
d
Duty cycle(2)
85
AMOD
fSW
Modulator gain
5
1
Switching frequency
Output capacitance
Capacitor ESR
MHz
mF
COUT
ESR
L
10(3)
47
50
mΩ
mH
Nominal inductance
2.2
BUCK3
VOUT
VFB
IOUT
h
Output voltage range(4)
Feedback voltage
0.9
3.3
2%
3
V
V
–2%
0.804
Output current
A
Efficiency
IO = 2 A, VOUT = 1.2 V
VIN12V = 12 V
86
32
36
5
%
Low-side MOSFET On resistance
High-side MOSFET On resistance
Switch current limit
RDS(ON)
ILIMIT
mΩ
A
Current limit accuracy
–30
30
1
%
Line regulation - DC
ΔVOUT/ΔVINB
VINB = 4.75 V - 6.1 V,
IOUT = 1000 mA
VLINEREG
VLOADREG
VOUTTOL
%
Load regulation - DC
ΔVOUT/ΔIOUT
IOUT = 10 – 90% IOUT,MAX
0.5
%/A
Feedback resistor tolerance
not included
DC Set Tolerance
–2
15
2
%
%
d
Duty cycle(5)
85
AMOD
fSW
COUT
ESR
L
Modulator gain
5
1
Switching frequency
Output capacitance
Capacitor ESR
MHz
mF
10
50
mΩ
mH
Nominal inductance
2.2
(4) Output voltage range is limited by the minimum and maximum duty cycle. VOUT(min) ~ d(min) x VINPUT and VOUT(max) ~ d(max) x
VINPUT
(5) Performance outside these limits is not guaranteed.
.
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TPS65232
SLVSA42 –FEBRUARY 2010
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ELECTRICAL CHARACTERISTICS (continued)
VIN = 12 V ±5%, VINB2, VINB3 = 5 V ±5%, TJ = 0°C to 150°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
SOFT START (BUCK1, 2, and 3)
ISS
Soft start current source
2
0.8
3.3
2.5
500
mA
VSS, MAX
CSS
Soft start ramp voltage
Soft start capacitor
Deglitch time
Ramp end
tSS = 0.4 ms/nF
V
2
4.7
nF
ms
ms
SSDONE_BK
SSDONE_DCH
SS discharge time
THERMAL SHUTDOWN
Thot
Ttrip
Thyst
Thermal warning
120
160
20
°C
°C
°C
Thermal s/d trip point
Thermal s/d hysteresis
POWER-UP SEQUENCING
ON/OFF control and power sequencing of the three buck regulators is controlled through EN_BCK1, EN_BCK2,
and EN_BCK3 enable pins. Each pin is internally connected to a 6-mA constant-current source and monitored by
a comparator with Schmitt trigger input with defined threshold. Connecting EN_BCKn pin to ground disables
BUCKn and connecting EN_BCKn to V3p3 will enable the respective buck without delay. If more than one buck
enable pin is connected to V3p3 the default startup sequence is BUCK1, BUCK2, BUCK3 and the minimum
startup delay between rails is the soft-start time (typical 1.5 ms) plus 1 ms.
To create a startup-sequence different from the default, capacitors are connected between the EN_BUCKn pins
and ground. At power-up the capacitors are first discharged and then charged to V3p3 level by internal current
sources (6 mA typical) creating a constant-slope voltage ramp. A regulator is enabled when its EN pin voltage
crosses the enable threshold (typical 1.2 V). A delay of 0.2 ms is generated for each 1-nF of capacitance
connected to the enable pin. If two enable pins are pulled high while the third regulator is starting up, the default
sequence will be applied to enable the remaining two regulators. To override default power-up sequence it is
recommended that delay times differ by more than the soft-start time (typical 1.3 ms) plus 1 ms.
V3p3
V3p3
Delay time = 0.2ms/nF
(1)
(2)
6uA
1.2V
EN_BCKx
Enable
Threshold
BUCK ENABLE
Time
BUCK A
Enable
BUCK C
Enable
BUCK B
Enable
(1) Connect EN_BCKx pin to V3P3 to follow the default power-up sequence or
(2) Connect a capacitor from EN_BCKx to GND to generate a custom power-up sequence.
Figure 1. Customizing the Power-Up Sequence
10
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SLVSA42 –FEBRUARY 2010
OVER CURRENT PROTECTION
Over current protection (OCP) for BUCK1 is achieved by comparing the drain-to-source voltage of the low-side
MOSFET to a set-point voltage, which is defined by both the internal current source, ITRIP, and the external
resistor connected between the TRIP pin and ground. Over current threshold is calculated as follows:
RTRIP · ITRIP
10 · RDS(ON)
ILIM
=
(1)
ITRIP has a typical value of 10 mA at 25°C and a temperature coefficient of 3700 ppm/°C to compensate the
temperature dependency of the MOS RDS(ON). The TPS65232 supports cycle-by-cycle over current limiting
control which means that the controller compares the drain-to-source voltage of the low-side FET to the set-point
voltage once per switching cycle and blanks out the next switching cycle if an over-current condition is detected.
If in the following cycle over current condition is detected again, the controller blanks out 2, then 4, 8, and up to
16 cycles before turning on the high-side driver again. In an over current condition the current to the load
exceeds the current to the output capacitor thus the output voltage will drop, and eventually cross the under
voltage protection threshold and shut down the BUCK controller. Buck 2 and 3 show a similar mode of operation.
All converters operate in “hiccup mode”: Once an over-current is sensed, the controller shuts off the converter for
a given time and then tries to start again. If the overload has been removed, the converter will ramp up and
operate normally. If this is not the case, the converter will see another over-current event and shuts down again
repeating the cycle until the failure is cleared.
SOFT START
Soft start for all three BUCKs is controlled by a single capacitor connected to the SS pin and an internal current
source. When one of the BUCKs is enabled, the SS capacitor is pre-charged to the output voltage divided by the
feed-back ratio before the internal SS current source starts charging the external capacitor. The output voltage of
the BUCK ramps up as the SS pin voltage increased from its pre-charged value to 0.8 V. The soft start time is
calculated from the SS supply current (ISS) and the capacitor value and has a typical value of 0.4 ms/nF or
1.3 ms for a 3.3-nF capacitor connected to the SS pin. Before the next rail is enabled, the SS cap is discharged
and the SS cycle starts over again.
UNDER VOLTAGE LOCKOUT (UVLO)
TPS65232 monitors VIN and VINB pin voltages and will disable one or more power paths depending on the
current use condition:
•
•
If VIN drops below 4.7 V, BUCK1, 2, and 3 are disabled.
If VINB drops below 4.25 V and either BUCK2 or BUCK3 are enabled, all three output rails are disabled.
UVLO state is not latched and the system recovers as soon as the input voltage rises above its respective
threshold. All three BUCK_ENx pins are discharged and remain discharged during UVLO to ensure proper power
sequencing when the system recovers.
THERMAL SHUTDOWN (TSD)
TPS65232 monitors junction temperature and will disable the power path (BUCK1-3) if junction temperature rises
above the specified trip point. All three BUCK_ENx pins are discharged and remain discharged during TSD to
ensure proper power sequencing when the system recovers.
LOOP COMPENSATION
All three BUCKs are voltage mode converters designed to be stable with ceramic capacitors. Refer to
Component Selection Procedure section for calculating feedback components.
3.3-V REGULATOR
The TPS65232 has a built-in 3.3-V regulator for powering internal circuitry. The 3.3-V rail can also be used for
enabling the BUCK regulators and/or the USB switches, but is not intended for supplying any other external
circuitry.
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SLVSA42 –FEBRUARY 2010
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6-V REGULATOR
The TPS65232 has a built-in 6-V regulator for powering internal circuitry.
THERMAL MANAGEMENT AND SAFE OPERATING AREA
Total power dissipation inside TPS65232 is limited not to exceed the maximum allowable junction temperature of
150°C. The maximum allowable power dissipation is a function of the thermal resistance of the package (qJA)
and ambient temperature. qJA itself is highly dependent on board layout. The maximum allowable power inside
the IC for operation at maximum ambient temperature without exceeding the temperature warning flag using the
JEDEC High-K board is calculated as follows.
DT = qJA · P
(2)
For TSSOP:
TMAX - Tambient
120°C - 55°C
25°C/W
PMAX
=
» 2.6 W
» 2.5 W
=
qJA
(3)
(4)
For QFN:
TMAX - Tambient
120°C - 75°C
18.1°C/W
PMAX
=
=
qJA
For different PCB layout arrangements the thermal resistance (qJA) will change as the following table shows.
BOARD TYPE
STACK-UP
qJA
1.5-oz Cu, 60% Cu coverage top layer, 80% Cu coverage bottom
layer, no airflow
8" x 10" FR4 PCB, four layers
29
0.5-oz 30% Cu coverage inner layers
1-oz Cu, 20% Cu coverage top layer, 90% Cu coverage bottom
layer, no airflow
8” x 10” FR4 PCB, two layers
44
A minimum of two layers of 1-oz Cu with 20% Cu coverage on the top and 90% coverage on the bottom and the
use of thermal vias to connect the thermal pad to the bottom layer is recommended. Note that the maximum
allowable power inside the device will depend on the board layout. For recommendations on board layout for
thermal management using TPS65232 consult your TI field application engineer.
In the example shown above the maximum allowable power dissipation for the IC has been calculated. This
figure includes all heat sources inside the device including the power dissipated in BUCK1, BUCK2, BUCK3 and
all supporting circuitry. Power dissipated in BUCK1 and all supporting circuitry is approximately 0.4 W and almost
independent of the application. Power dissipated in BUCK2 and BUCK3 depends on the output voltage, output
current, and efficiency of the switching converters. The following examples of safe operating area assume 90%
efficiency for BUCK2 and BUCK3, 3.3-V output from BUCK3 and 1.2-V, 1.8-V, and 2.5-V output from BUCK2,
respectively.
3.5
3.5
3.5
3
3
3
2.5
2.5
2.5
2
2
2
1.5
1.5
1.5
Safe Operating Area
Safe Operating Area
Safe Operating Area
1
1
1
0.5
0.5
0.5
0
0
0
0
0.5
1
1.5
2
2.5
3
3.5
0
0.5
1
1.5
2
2.5
3
3.5
0
0.5
1
1.5
2
2.5
3
3.5
Current from BUCK2 [A] @ 1.2V or less
Current from BUCK2 [A] @ 1.8V
Current from BUCK2 [A] @ 2.5V
For any voltage / current comination inside the shaded area, the dissipated power inside the chip is below the allowable
maximum. The examples assume Tambient < 60°C, h = 90% and qJA < 44°C/W.
Figure 2. Examples of Thermal Safe Operating Area for V(BUCK3) = 3.3 V and
V(BUCK1) = 1.2 V, 1.8 V and 2.5 V, Respectively
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COMPONENT SELECTION PROCEDURE
The following example illustrates the design procedure for selecting external components for the three buck
converters. The example focuses on BUCK1 but the procedure can be directly applied to BUCK2 and BUCK3 as
well. The design goal parameters are given in the table below. A list of symbol definitions is found at the end of
this section. For this example the schematic in Figure 3 will be used.
L3
2.2uH
V1
1.2V 3A V3
C32
0.1uF
C31
47uF
C33
22uF
C34
22uF
C36
1000pF
R33
20K
EN3
R31
22.1K
C37
100pF
C35
1000pF
C30
0.1uF
R32
44.2K
BST3
AGND
C5
1uF
AGND
AGND
AGND
BG
AGND
V3P3
V1
R14
210K
C1
1uF
TRIP
C2
1uF
C4
3.3nF
SS
TPS65232
FB1
C16
1000pF
C18
1000pF
R13
20K
VINBQ
V6V
FB1
C3
1uF
CMP1
EN_BCK1
BST1
PH1
VIN
EN1
12V
VIN
FB2
C12
100uF
VIN
FB2
C10
0.22uF
C17
100pF
CMP2
C11
100uF
L1
4.7uH
Q1A
5V 6A
V1
FDS6982
Q1B
EN2
V1
C13
22uF
C14
22uF
R23
20K
C20
0.1uF
L2
2.2uH
1.8V 3A
V2
C22
0.1uF
C27
100pF
R11
22.1K
C26
1000pF
C15
1000pF
C23
22uF
C24
22uF
C21
47uF
FB1
R12
R21
22.1K
4.22K
C25
1000pF
FB2
R22
17.8K
Figure 3. Sample Schematic for TPS65232
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BUCK1 DESIGN GUIDELINE
PARAMETER
www.ti.com
TEST CONDITIONS
MIN
10.8
TYP
MAX
13.2
UNIT
V
VIN
Input supply voltage
Input voltage ripple
Output voltage
12
VIN RIPPLE
VOUT
IOUT, BUCK1 = 6 A
75
mV
V
4.75
5
25
25
5.25
Line regulation
VIN = 10.8 V to 13.2 V
IOUT, BUCK1 = 0 A to 6 A
IOUT, BUCK1 = 6 A
mV
mV
mV
mV
A
Load regulation
Output ripple
VOUT RIPPLE
VTRANS
IOUT
75
6
Transient deviation
Output current
IOUT, BUCK1 = 1.5 A to 3 A
VIN = 10.8 V to 13.2 V
50
0
fSW
Switching frequency
500
kHz
INDUCTOR SELECTION (L1)
The inductor is typically sized for < 30% peak-to-peak ripple current (IRIPPLE). Given this target ripple current, the
required inductor size is calculated by Equation 5.
VIN(MAX) - VOUT
0.3 · IOUT
VOUT
VIN(MAX)
1
¾
·
fSW
·
L =
(5)
Solving Equation 5 with VIN(MAX) = 13.2 V, an inductor value of 3.5 mH is obtained. A standard value of 4.7 mH is
selected, resulting in 1.25-A peak-to-peak ripple. The RMS current through the inductor is approximated by
Equation 6.
2
2
2
(IOUT) +
2
1
12
1
12
IL(RMS)
=
¾
+
¾
(IL(avg)
Ö
(IRIPPLE
)
(IRIPPLE
)
) =
Ö
(6)
Using Equation 6, the maximum RMS current in the inductor is about 6.01 A.
OUTPUT CAPACITOR SELECTION (C13, C14)
The selection of the output capacitor is typically driven by the output load transient response requirement.
Equation 7 and Equation 8 estimate the output capacitance required for a given output voltage transient
deviation.
2
ITRAN(MAX) · L
when VIN(MIN) < 2 · VOUT
COUT(MIN)
=
(VIN(MIN) - VOUT) · VTRAN
(7)
(8)
2
ITRAN(MAX) · L
when VIN(MIN) > 2 · VOUT
COUT(MIN)
=
VOUT · VTRAN
For this example, Equation 8 is used in calculating the minimum output capacitance.
Based on a 1.5-A load transient with a maximum 50-mV deviation, a minimum of 42-mF output capacitance is
required. We choose two 22-mF capacitors in parallel for a total capacitance of 44 mF.
The output ripple is divided into two components. The first is the ripple generated by the inductor ripple current
flowing through the output capacitor’s capacitance, and the second is the voltage generated by the ripple current
flowing in the output capacitor’s ESR. The maximum allowable ESR is then determined by the maximum ripple
voltage and is approximated by Equation 9.
IRIPPLE
VRIPPLE(total)
-
(
)
VRIPPLE(total) - VRIPPLE(cap)
COUT · fSW
ESRMAX
=
=
IRIPPLE
IRIPPLE
(9)
Based on 44-mF of capacitance, 1.25-A ripple current, 500-kHz switching frequency and a design goal of 75-mV
ripple voltage, we calculate a capacitive ripple component of 56 mV and an maximum ESR of 15 mΩ. Two 1210,
47-mF, 10-V X5R ceramic capacitors are selected to provide significantly less than 15-mΩ of ESR.
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PEAK CURRENT RATING OF THE INDUCTOR
With output capacitance known, it is now possible to calculate the charging current during start-up and determine
the minimum saturation current rating of the inductor. The start-up charging current is approximated by
Equation 10.
VOUT · COUT
ICHARGE
=
TSS
(10)
Using the TPS65232’s recommended 1.3-ms soft-start time, COUT = 44 mF and VOUT = 5 V, ICHARGE is found to be
169 mA. The peak current rating of the inductor is now found by Equation 11.
1
¾
IL(PEAK) = IOUT(MAX)
+
I
RIPPLE + ICHARGE
2
(11)
For this example an inductor with a peak current rating of 6.79 A is required.
INPUT CAPACITOR SELECTION (C11, C12)
The input voltage ripple is divided between capacitance and ESR. For this design, VRIPPLE(CAP) = 50 mV and
VRIPPLE(ESR) = 25 mV. The minimum capacitance and maximum ESR are estimated by Equation 12 and
Equation 13.
ILOAD · VOUT
CIN(MIN)
=
VRIPPLE(cap) · VIN · fSW
(12)
VRIPPLE(ESR)
ESRMAX
=
1
¾
2
ILOAD
+
IRIPPLE
(13)
For this design, CIN > 100 mF and ESR < 3.7 mΩ. The RMS current in the output capacitors is estimated by
Equation 14.
2
2
1
12
VOUT · IOUT
VIN
· VOUT
)
VIN
IRMS(CIN) = IIN(RMS) - IIN(avg)
=
¾
((IOUT) + (IRIPPLE
)
¾
-
Ö
(14)
With VIN = VIN(MAX), the input capacitors must support a ripple current of 1.4-A RMS. The two 1210, 47-mF X5R
ceramic capacitors with about 5-mΩ ESR and 2-A RMS current rating are selected. It is important to check the
DC bias voltage de-rating curves to ensure the capacitors provide sufficient capacitance at the working voltage.
BOOTSTRAP CAPACITOR (C10)
To ensure proper charging of the high-side MOSFET gate, limit the ripple voltage on the bootstrap capacitor to
< 5% of the minimum gate drive voltage.
20 · QGS, HSD
VIN(MIN)
CBOOST
=
(15)
Based on the FDS6982 MOSFET with a maximum total gate charge of 12 nC, calculate a minimum of 22-nF of
capacitance. A standard value of 220 nF is selected.
SHORT CIRCUIT PROTECTION (R14, C18) (BUCK1 ONLY)
The TPS65232 uses the forward drop across the low-side MOSFET during the OFF time to measure the inductor
current. The voltage drop across the low-side MOSFET is given by Equation 16.
VDS = IL(PEAK) · RDSON, LSD
(16)
When VIN = 10.8 V to 13.2 V, IPEAK = 7.4 A. Using the FDS6982 MOSFET with a RDSON,MAX at TJ = 25°C of
20 mΩ we calculate the peak voltage drop to be 148 mV. Solving Equation 1 for RTRIP and using ITRIP = 10 mA:
R14 = RTRIP = RDS(ON) · ILIM · 106
(17)
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We calculate a trip resistor value of 210 kΩ. Place a 1-nF capacitor parallel to R14. Please note that typical FET
RDS(ON) is specified at 10 mΩ. Since we used RDSON,MAX, for setting the current limit, the actual current flowing
through the inductor with a nominal FET can be higher than the peak current of 7.4 A before the current limit
kicks in. Make sure that the chosen inductor has the correct peak current capabilities.
FEEDBACK LOOP DESIGN
TPS65232 loop compensation looks like a type-II compensation network because an internal zero-pole pair can
provide additional phase boost to stabilize this voltage mode control DC/DC controller. The internal zero is
located at 45 kHz and the pole is located at 240 kHz. Ideally, the best cross-over frequency is around 1/10th of
the switching frequency.
FEEDBACK DIVIDER (R11, R12)
Select R11 between 10 kΩ and 100 kΩ. For this design select 22.1 kΩ. Next, R12 Is selected to produce the
desired output voltage when VFB = 0.8 V using the following formula:
VFB · R11
R12 =
VOUT - VFB
(18)
VFB = 0.8 V and R11 = 22.1 KΩ for VOUT = 5.0 V, R12 = 4.22 kΩ.
Error Amplifier Pole-Zero Selection
The design guidelines for TPS65232 Buck1 loop compensation are as follows:
1. Place a compensation zero at 8 kHz to boost the phase margin at the anticipated cross-over frequency.
2. Set the value of R and C of this to zero: C16 = 1000 pF and R13 = 20 kΩ.
3. Add an additional pole by making C17 = 100 pF. This pole is used to attenuate high frequency noise.
4. If VIN is 20 V - 24 V, make C17 = 200 pF.
BUCK2 DESIGN GUIDELINE
PARAMETER
Input supply voltage
Input voltage ripple
Output voltage
TEST CONDITIONS
MIN
TYP
MAX
6
UNIT
V
VIN
4.75
5
VIN RIPPLE
VOUT
IOUT, BUCK1 = 3 A
75
mV
V
1.8
18
18
Line regulation
VIN = 3 V to 6 V
IOUT, BUCK1 = 0 A to 3 A
IOUT, BUCK1 = 3 A
mV
mV
mV
mV
A
Load regulation
Output ripple
VOUT RIPPLE
VTRANS
IOUT
36
3
Transient deviation
Output current
IOUT, BUCK1 = 1.5 A to 3 A
VIN = 3 V to 6 V
50
0
fSW
Switching frequency
1000
kHz
INDUCTOR SELECTION (L2)
The inductor is typically sized for < 30% peak-to-peak ripple current (IRIPPLE). Given this target ripple current, the
required inductor size is calculated by Equation 5.
VIN(MAX) - VOUT
0.3 · IOUT
VOUT
VIN(MAX)
1
¾
·
fSW
·
L =
(19)
Solving Equation 19 with VIN(MAX) = 6 V, an inductor value of 1.4 mH is obtained. A standard value of 2.2 mH is
selected, resulting in 0.37-A peak-to-peak ripple. The RMS current through the inductor is approximated by
Equation 6.
2
2
2
(IOUT) +
2
1
12
1
12
IL(RMS)
=
¾
+
¾
(IL(avg)
Ö
(IRIPPLE
)
(IRIPPLE
)
) =
Ö
(20)
Using Equation 20, the maximum RMS current in the inductor is about 3.002 A.
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OUTPUT CAPACITOR SELECTION (C23, C24)
The selection of the output capacitor is typically driven by the output load transient response requirement.
Equation 21 and Equation 22 estimate the output capacitance required for a given output voltage transient
deviation.
2
ITRAN(MAX) · L
when VIN(MIN) < 2 · VOUT
COUT(MIN)
=
(VIN(MIN) - VOUT) · VTRAN
(21)
(22)
2
ITRAN(MAX) · L
when VIN(MIN) > 2 · VOUT
COUT(MIN)
=
VOUT · VTRAN
For this example, Equation 22 is used in calculating the minimum output capacitance.
Based on a 1-A load transient with a maximum 54-mV deviation, a minimum of 26-mF output capacitance is
required. We choose two 22-mF capacitors in parallel for a total capacitance of 44 mF.
The output ripple is divided into two components. The first is the ripple generated by the inductor ripple current
flowing through the output capacitor’s capacitance, and the second is the voltage generated by the ripple current
flowing in the output capacitor’s ESR. The maximum allowable ESR is then determined by the maximum ripple
voltage and is approximated by Equation 23.
IRIPPLE
VRIPPLE(total)
-
(
)
VRIPPLE(total) - VRIPPLE(cap)
COUT · fSW
ESRMAX
=
=
IRIPPLE
IRIPPLE
(23)
Based on 44-mF of capacitance, 0.37-A ripple current, 1-MHz switching frequency and a design goal of 36-mV
ripple voltage, we calculate a maximum ESR of 76 mΩ. Two 1210, 22-mF, 10-V X5R ceramic capacitors are
selected to provide significantly less than 76-mΩ of ESR.
PEAK CURRENT RATING OF THE INDUCTOR
With output capacitance known, it is now possible to calculate the charging current during start-up and determine
the minimum saturation current rating of the inductor. The start-up charging current is approximated by
Equation 24.
VOUT · COUT
ICHARGE
=
TSS
(24)
Using the common start time (1 ms), COUT = 44 mF and VOUT = 1.8 V, ICHARGE is found to be 79 mA. The peak
current rating of the inductor is now found by Equation 25.
1
¾
IL(PEAK) = IOUT(MAX)
+
I
RIPPLE + ICHARGE
2
(25)
For this example an inductor with a peak current rating of 3.264 A is required.
INPUT CAPACITOR SELECTION (C21, C22)
The input voltage ripple is divided between capacitance and ESR. For this design, VRIPPLE(CAP) = 50 mV and
VRIPPLE(ESR) = 25 mV. The minimum capacitance and maximum ESR are estimated by Equation 26 and
Equation 27.
ILOAD · VOUT
CIN(MIN)
=
VRIPPLE(cap) · VIN · fSW
(26)
VRIPPLE(ESR)
ESRMAX
=
1
¾
2
ILOAD
+
IRIPPLE
(27)
For this design, CIN > 32 mF and ESR < 7.8 mΩ. The RMS current in the output capacitors is estimated by
Equation 28.
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2
2
1
12
VOUT · IOUT
VIN
· VOUT
)
VIN
IRMS(CIN) = IIN(RMS) - IIN(avg)
=
¾
((IOUT) + (IRIPPLE
)
¾
-
Ö
(28)
With VIN = VIN(TYP), the input capacitors must support a ripple current of 0.58-A RMS. The two 1210, 47-mF X5R
ceramic capacitors with about 5-mΩ ESR and 2-A RMS current rating are selected. It is important to check the
DC bias voltage de-rating curves to ensure the capacitors provide sufficient capacitance at the working voltage.
BOOTSTRAP CAPACITOR (C20)
A standard value of 100 nF is selected.
SHORT CIRCUIT PROTECTION
Current limits for BUCK2 are internally set to 5 A.
FEEDBACK LOOP DESIGN
TPS65232 loop compensation looks like a type-II compensation network because an internal zero-pole pair can
provide additional phase boost to stabilize this voltage mode control DC/DC controller. The internal zero is
located at 45 kHz and the pole is located at 240 kHz. Ideally, the best cross-over frequency is around 1/10th of
the switching frequency.
FEEDBACK DIVIDER (R21, R22)
Select R21 between 10 kΩ and 100 kΩ. For this design select 22.1 kΩ. Next, R22 Is selected to produce the
desired output voltage when VFB = 0.8 V using the following formula:
VFB · R21
R22 =
VOUT - VFB
(29)
VFB = 0.8 V and R21 = 22.1 KΩ for VOUT = 1.8 V, R22 = 17.8 kΩ.
Error Amplifier Pole-Zero Selection
The design guidelines for TPS65232 BUCK2 loop compensation are as follows:
1. Place a compensation zero at 8 kHz to boost the phase margin at the anticipated cross-over frequency.
2. Set the value of R and C of this to zero: C26 = 1000 pF and R23 = 20 kΩ.
3. Add an additional pole by making C27 = 100 pF. This pole is used to attenuate high frequency noise.
BUCK3 DESIGN GUIDELINE
Both BUCK2 and BUCK3 have the same internal structure. Thus, BUCK2’s design guideline can be applied to
BUCK3’s design directly.
OTHER COMPONENTS
A 1-µF ceramic capacitor should be connected as close as possible to the following pins:
•
•
•
•
BG: Bandgap reference
VIN: Bypass capacitor
V6V: Internal 6-V supply
V3P3: Internal 3.3-V supply
SIX RAIL POWER SYSTEM
The following example illustrates two TPS65232 ICs can provide six power rails and the low output voltage rail is
capable of delivering 10-A load current with high efficiency.
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L3
2.2uH
V1
1.2V 3A V3
C32
0.1uF
C31
47uF
C33
22uF
C34
22uF
C36
1000pF
R33
20K
EN3
R31
22.1K
C37
100pF
C35
1000pF
C30
0.1uF
R32
44.2K
BST3
AGND
C5
1uF
AGND
AGND
AGND
BG
AGND
V3P3
V1
R14
210K
C1
1uF
TRIP
C2
1uF
C4
3.3nF
SS
TPS65232
FB1
C16
1000pF
C18
1000pF
R13
20K
VINBQ
V6V
FB1
C3
1uF
CMP1
EN_BCK1
BST1
PH1
VIN
EN1
12V
VIN
FB2
C12
100uF
VIN
FB2
C10
0.22uF
C17
100pF
CMP2
C11
100uF
L1
4.7uH
Q1A
5V 6A
V1
FDS6982
Q1B
EN2
V1
C13
22uF
C14
22uF
R23
20K
C20
0.1uF
L2
2.2uH
1.8V 3A
V2
C22
0.1uF
C27
100pF
R11
22.1K
C26
1000pF
C15
1000pF
C23
22uF
C24
22uF
C21
47uF
FB1
R12
R21
22.1K
4.22K
C25
1000pF
FB2
R22
17.8K
Figure 4. Six Rail Power System Part I: 5 V, 1.8 V and 1.2 V
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L6
2.2uH
V1
1.5V 3A V6
C322
0.1uF
C312
47uF
C332
22uF
C342
22uF
C362
1000pF
R332
20K
EN6
R312
22.1K
C372
100pF
C352
1000pF
C302
0.1uF
R322
25.5K
BST3
AGND
AGND
V3P3
TRIP
SS
C52
1uF
AGND
AGND
AGND
BG
V1
R142
30.1K
C12
1uF
C22
1uF
C42
3.3nF
TPS65232
FB4
C162
1000pF
C182
1000pF
R132
20K
VINBQ
V6V
FB1
C32
1uF
CMP1
EN_BCK1
BST1
VIN
EN4
12V
C122
100uF
VIN
FB5
VIN
FB2
C102
0.22uF
C172
100pF
CMP2
PH1
C112
100uF
CSD16409
Q1
1.0V 10A
V4
L4
3.4uH
C142
22uF
EN5
V1
Q2
CSD16323
R232
20K
C202
0.1uF
C132
22uF
L5
2.2uH
3.3V 3A
V5
C222
0.1uF
C272
100pF
R112
22.1K
C262
1000pF
C152
1000pF
C232
22uF
C242
22uF
C212
47uF
FB4
R122
R212
22.1K
88.7K
C252
1000pF
FB5
R222
6.98K
Figure 5. Six Rail Power System Part II: 3.3 V, 1.5 V and 1 V
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FDS6982
5.0V 3A
Buck 1
L1
12V
C1
C2
1.8V 3A
5.0V
Buck 2
Buck 3
L2
L3
C3
C4
1.2V 3A
TPS65232
CSD16409
1.0V 10A
C5
Buck 1
L4
12V
CSD16323
3.3V 3A
1.5V 3A
Buck 2
Buck 3
L5
C6
C7
L6
TPS65232
Figure 6. Six Rail Power System Block Diagram
Copyright © 2010, Texas Instruments Incorporated
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Product Folder Link(s): TPS65232
PACKAGE OPTION ADDENDUM
www.ti.com
3-Aug-2012
PACKAGING INFORMATION
Status (1)
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
TPS65232A0RHA
TPS65232A0RHAR
TPS65232A2DCA
TPS65232A2DCAR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
VQFN
VQFN
RHA
RHA
DCA
DCA
40
40
48
48
50
2500
40
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
CU NIPDAU Level-3-260C-168 HR
CU NIPDAU Level-3-260C-168 HR
HTSSOP
HTSSOP
Green (RoHS
& no Sb/Br)
2000
Green (RoHS
& no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS65232A2DCAR
HTSSOP DCA
48
2000
330.0
24.4
8.6
15.8
1.8
12.0
24.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
*All dimensions are nominal
Device
Package Type Package Drawing Pins
HTSSOP DCA 48
SPQ
Length (mm) Width (mm) Height (mm)
367.0 367.0 45.0
TPS65232A2DCAR
2000
Pack Materials-Page 2
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