TPS65581PWPR [TI]
具有低侧栅极驱动器的 4.5V 至 20V 输入、3.3V 3A SWIFT™ 同步降压转换器 | PWP | 20 | -40 to 125;型号: | TPS65581PWPR |
厂家: | TEXAS INSTRUMENTS |
描述: | 具有低侧栅极驱动器的 4.5V 至 20V 输入、3.3V 3A SWIFT™ 同步降压转换器 | PWP | 20 | -40 to 125 栅极驱动 开关 光电二极管 驱动器 转换器 |
文件: | 总26页 (文件大小:1202K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
TPS65581
www.ti.com.cn
ZHCSBO1 –OCTOBER 2013
4.5V 至 18V 输入电压 1.5A,2.5A,1.5A 三路同步降压转换器
查询样品: TPS65581
1
特性
应用范围
23
•
高级 D-CAP2™ 控制模式
•
针对广泛应用的低功耗系统中的负载点调节
–
–
–
快速瞬态响应
–
–
–
–
–
数字电视电源
环路补偿无需外部部件
与陶瓷输出电容器兼容
网络互联家庭终端设备
数字机顶盒 (STB)
DVD 播放器,刻录机
游戏控制台和其它设备
•
•
•
宽输入电压范围:4.5V 至 18V
输出电压范围:0.76V 至 7V
针对低占空比应用对高效集成场效应晶体管 (FET)
进行了优化
说明
TPS65581 是一款三路、高级 D-CAP2™ 模式同步降
压转换器。 TPS65581 可帮助系统设计人员通过成本
有效性、低组件数量和低待机电流解决方案来完成多种
终端设备的电源总线调节器集。 TPS65581 的主控制
环路采用高级 D-CAP2™ 模式控制,无需外部补偿组
件即可提供快速的瞬态响应。 高级 D-CAP2™ 模式控
制支持较高负载条件下脉宽调制 (PWM) 模式与 Eco-
mode™ 之间的无缝转换,从而使得 TPS65581 能够
在轻负载期间保持高效率。 此器件能够适应诸如高分
子有机半导体固体电容器 (POSCAP) 或者高分子聚合
物电容器 (SP-CAP) 等低等效串联电阻 (ESR) 输出电
容器,以及超低 ESR,陶瓷电容器。 此器件在输入电
压为 4.5V 至 18V 之间时提供便捷且有效的运行。
–
–
对于 2.5A 电流为 160mΩ(高侧)和
130mΩ(低侧)
对于 1.5A 电流为 250mΩ(高侧)和
230mΩ(低侧)
•
•
•
•
•
•
•
高初始基准精度
低侧 RDS(on) 低损耗电流感测
固定 1.2ms 软启动
非吸入预偏置软启动
700kHz 开关频率
逐周期过流限制控制
过流限制 (OCL),过压 (OVP),欠压 (UVP),欠压
闭锁 (UVLO),热关断 (TSD) 保护
•
•
•
针对过载保护的断续定时器
电源正常 (PowerGood)
TPS65581 采用 4.4mm x 6.5mm 20 引脚 TSSOP
(PWP) 封装,额定环境温度范围为 -40°C 至 85°C。
带有集成式升压 P 通道金属氧化物半导体 (PMOS)
开关的自适应栅极驱动器
•
由于热补偿 RDS(on) 的值为 4000ppm/℃ ,过流保
护 (OCP) 恒定
•
•
20 引脚散热薄型小外形尺寸封装 (HTSSOP)
自动跳跃 Eco-mode ™ 为了在轻负载下实现高效
率
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
3
D-CAP2, Eco-mode are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2013, Texas Instruments Incorporated
English Data Sheet: SLVSC38
TPS65581
ZHCSBO1 –OCTOBER 2013
www.ti.com.cn
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
HTSSOP APPLICATION DIAGRAM
Input Voltage
20
19
18
17
VBST2
SW2
1
VIN
C32
L12
VO2
2
3
VIN
C22
C11
VBST1
PGND2
L11
C31
VO1
PGND
4
SW1
EN2
C21
5
6
PGND1
VREG5
PG
PGND3 16
TPS65581
PGND
L13
C4
PGND
C23
VO3
HTSSOP20
(PowerPAD)
15
14
SW3
C33
PGND
7
8
9
VBST3
EN1
13
EN3
R11
R13
R23
VFB1
VFB3 12
R21
R12
R22
11
VFB2
10 GND
SGND
SGND
SGND
SGND
ORDERING INFORMATION
ORDERING PART NUMBER
TPS65581PWPR
TA
–40℃ to 85℃
PACKAGE(1)
PINS
20
OUTPUT SUPPLY
Tape-and-Reel
Tube
PWP
TPS65581PWP
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com
2
Copyright © 2013, Texas Instruments Incorporated
TPS65581
www.ti.com.cn
ZHCSBO1 –OCTOBER 2013
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)(1)(2)
VALUE
UNIT
MIN
–0.3
–0.3
–0.3
–0.3
–0.3
–2
MAX
20
VIN, EN1, EN2, EN3
VBST1, VBST2, VBST3
26
VBST1, VBST2, VBST3 (10ns transient)
28
Input voltage range
VBST1–SW1, VBST2–SW2, VBST3–SW3
VFB1, VFB2, VFB3
6.5
6.5
20
V
V
SW1, SW2, SW3
SW1, SW2, SW3 (10ns transient)
VREG5, PG
–3
22
–0.3
–0.3
6.5
0.3
2
Output voltage range
Electrostatic discharge
PGND1, PGND2, PGND3
Human Body Model (HBM)
Charged Device Model (CDM)
kV
V
500
85
Operating ambient temperature range, TA
Storage temperature range, TSTG
Junction temperature range, TJ
–40
–55
–40
°C
°C
°C
150
150
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" are not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are with respect to IC GND terminal.
THERMAL INFORMATION
TPS65581
THERMAL METRIC(1)
UNITS
PWP (20) PINS
θJA
Junction-to-ambient thermal resistance
40.0
24.8
21.3
0.8
θJCtop
θJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
ψJB
21.1
1.7
θJCbot
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
VALUES
UNIT
MIN
4.5
MAX
18
Supply input voltage range
Input voltage range
VIN
V
VBST1, VBST2, VBST3
VBST1, VBST2, VBST3 (10ns transient)
VBST1–SW1, VBST2–SW2, VBST3–SW3
VFB1, VFB2, VFB3
–0.1
–0.1
–0.1
–0.1
–0.1
–1.0
–3
24
27
5.7
5.7
18
V
EN1, EN2, EN3
SW1, SW2, SW3
18
SW1, SW2, SW3 (10ns transient)
VREG5, PG
21
–0.1
–0.1
–40
–40
5.7
0.1
85
Output voltage range
V
PGND1, PGND2, PGND3
TA
TJ
Operating free-air temperature
Operating Junction Temperature
°C
°C
150
Copyright © 2013, Texas Instruments Incorporated
3
TPS65581
ZHCSBO1 –OCTOBER 2013
www.ti.com.cn
ELECTRICAL CHARACTERISTICS
over recommended free-air temperature range, VIN = 12 V (unless otherwise noted)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY CURRENT
TA = 25°C, EN1 = EN2 = EN3 = 5 V,
IIN
VIN supply current
2.9
1.8
3.6
3
mA
µA
VFB1 = VFB2 = VFB3 = 1 V, non-
switching
IVINSDN
VIN shutdown current
TA = 25°C, EN1 = EN2 = EN3 = 0 V
VFB VOLTAGE
TA = 25°C, CH1 = 3.3 V, CH2 = 1.2 V,
CH3 = 1.5 V
On the basis of 25°C(2)
(1)
VVFBTHL
VFBx threshold voltage
Temperature coefficient
752
764
776
180
mV
TCVFBx
VREG5 OUTPUT
–180
ppm/℃
VREG5 Rising
4
0.3
5.5
VUVREG5
VREG5 UVLO Threshold
V
Hysteresis
VVREG5
VREG5 output voltage
Output current
TA = 25°C, VIN = 12 V, IVREG = 5 mA
VIN = 6 V, TA = 25°C
V
IVREG5
20
mA
MOSFETs
rDS(on)H2
rDS(on)H2
High side switch resistance for 2.5A
Low side switch resistance for 2.5A
TA = 25℃, VBST2-SW2 = 5.5 V (2) , CH2
TA = 25℃ (2), CH2
160
130
mΩ
mΩ
TA = 25℃, VBSTx-SWx = 5.5 V (2) , CH1,
CH3
TA = 25℃ (2), CH1, CH3
rDS(on)Hx
rDS(on)Lx
High side switch resistance for 1.5A
Low side switch resistance for 1.5A
250
230
mΩ
mΩ
MIN ON/OFF TIME and SW frequency
tONminx
tOFFminx
Fsw
Min On Time
Minoff time
TA = 25℃, VOUTx = 0.8V(2)
TA = 25℃, VFBx = 0.7 V
TA = 25℃
80
ns
ns
220
700
SW-frequency
kHz
SOFT START
TSS
Soft-start time
Internal soft-start time
1.2
ms
(1) x means either 1 or 2 or 3, that is, VFBx means VFB1, VFB2 or VFB3.
(2) Specified by design. Not production tested.
4
Copyright © 2013, Texas Instruments Incorporated
TPS65581
www.ti.com.cn
ZHCSBO1 –OCTOBER 2013
ELECTRICAL CHARACTERISTICS (continued)
over recommended free-air temperature range, VIN = 12 V (unless otherwise noted)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
POWER GOOD
VPGTH
PG from lower VOx (going high)
PG from higher VOx (going low)
VPG = 0.5 V
84%
116%
85
PG threshold
RPG
PG pull-down resistance
PG delay time
50
130
Ω
Delay for PG going high
Delay for PG going low
1.5
ms
µs
TPGDLY
2
TPGCOMPSS
PGOOD comparator start-up delay
PG comparator wake-up delay
2.8
ms
LOGIC THRESHOLD
VENH
ENx H-level threshold voltage
2
V
V
VENL
ENx L-level threshold voltage
ENx input resistance
0.4
RENx_IN
ENx = 12 V
225
400
900
kΩ
CURRENT LIMIT
IOCL1
LOUT = 3.3 µH(3), VOUT1 = 3.3 V
LOUT = 2.2 µH(3) VOUT2 = 1.2 V
LOUT = 2.2 µH(3) VOUT3 = 1.5 V
1.7
2.9
1.8
2.0
3.5
2.2
3.4
4.9
3.6
A
A
A
IOCL2
Current limit
IOCL3
UNDER VOLTAGE PROTECTION
VUVP
Output UVP trip threshold
Output UVP delay time
Output UVP enable delay
measured on VFBx
UVP Enable Delay
63%
68%
0.5
73%
TUVPDEL
TUVPEN
ms
ms
2.8
THERMAL SHUTDOWN
Shutdown temperature(3)
Hysteresis(3)
155
30
TSD
Thermal shutdown threshold
°C
(3) Specified by design. Not production tested.
Copyright © 2013, Texas Instruments Incorporated
5
TPS65581
ZHCSBO1 –OCTOBER 2013
www.ti.com.cn
DEVICE INFORMATION
HTSSOP PACKAGE
(TOP VIEW)
20
19
18
17
16
15
VBST2
VIN
1
SW2
2
3
VIN
VBST1
PGND2
4
SW1
EN2
5
6
PGND1
VREG5
PG
PGND3
SW3
TPS65581
HTSSOP 20
(PowerPAD)
7
8
9
14
13
VBST3
EN1
EN3
VFB1
VFB3 12
11
VFB2
10 GND
PIN FUNCTIONS(1)
PIN
I/O
DESCRIPTION
NAME
HTSSOP20
VIN
1,2
I
I
Power input and connects to both high side NFET drains. Supply Input for 5.5V linear regulator.
VBST1, VBST2,
VBST3
Supply input for high-side NFET gate drive circuit. Connect 0.1µF ceramic capacitor between
VBSTx and SWx pins. An internal diode is connected between VREG5 and VBSTx
3, 14, 20
SW1, SW2,
SW3
Switch node connections for both the high-side NFETs and low–side NFETs. Input of current
comparator.
4,15,19
5,16,18
6
I/O
I/O
O
PGND1,
PGND2,
PGND3
Ground returns for low-side MOSFETs. Input of current comparator.
Output of 5.5V linear regulator. Bypass to GND with a high-quality ceramic capacitor of at least
1.0µF. VREG5 is active when ENx is high level.
VREG5
PG
7
O
I
Open drain power good output. Low means the output voltage is out of regulation.
Enable. Pull High to according converter.
EN1, EN2, EN3
8,13,17
VFB1, VFB2,
VFB3
9,11,12
10
I
Advanced D-CAP2 feedback inputs. Connect to output voltage with resistor divider.
Signal GND. Connect sensitive VFBx returns to GND at a single point.
GND
I/O
I/O
Exposed
Thermal Pad
Thermal pad of the package. Must be soldered to achieve appropriate dissipation. Must be
connected to GND.
Back side
(1) x means either 1, 2 or 3, VFBx means VFB1, VFB2 or VFB3.
6
Copyright © 2013, Texas Instruments Incorporated
TPS65581
www.ti.com.cn
ZHCSBO1 –OCTOBER 2013
FUNCTIONAL BLOCK DIAGRAM
VIN
Circuitry for single channel, x = 1,2 or 3
VIN
-32
UVx
VBSTx
.
OVx
+20
VOx
SWx
Err
Refx
Comp
SSx
PGND
PGNDx
VFBx
+16%
PGx
/
Ref_OCL
PGND
-16%
SWx
SWx
OCPx
ZCx
CHx Min-off timer
Common Circuitry
ENx
EN
Logic
ENintx
ENSSx
Control
VIN
and
Protection
Logic
OVx
UVx
VREG5
GND
PG
VREG5
SSx
UVLO
TSD
Fixed
SoftStart
.
ENSSx
VBG
Refx
Bandgap
UVLO
TSD
UVLO
TSD
PG1
PG2
PG3
Copyright © 2013, Texas Instruments Incorporated
7
TPS65581
ZHCSBO1 –OCTOBER 2013
www.ti.com.cn
OVERVIEW
The TPS65581 is a 1.5A, 2.5A, 1.5A triple synchronous step-down (buck) converter with two integrated N-
channel MOSFETs for each channel. It operates using Advanced D-CAP2™ control mode. The fast transient
response of Advanced D-CAP2™ control reduces the required output capacitance to meet a specific level of
performance. Proprietary internal circuitry allows the use of low ESR output capacitors including ceramic and
special polymer types.
DETAILED DESCRIPTION
PWM Operation
The main control loop of the TPS65581 is a fixed switching frequency pulse width modulation (PWM) controller
that supports a proprietary advanced D-CAP2™ mode control. Advanced D-CAP2™ mode control combines
constant switching frequency with an internal compensation circuit and low external component count
configuration with both low ESR and ceramic output capacitors. It is stable even with virtually no ripple at the
output.
Auto-Skip Eco-mode™ Control
The TPS65581 is designed with Auto-Skip Eco-mode™ to increase light load efficiency. As the output current
decreases from heavy load condition, the inductor current is also reduced and eventually comes to point that its
rippled valley touches zero level, which is the boundary between continuous conduction and discontinuous
conduction modes. The rectifying MOSFET is turned off when its zero inductor current is detected. As the load
current further decreases the converter run into discontinuous conduction mode. The transition point to the light
load operation IOUT(LL) current can be calculated in Equation 1.
V
IN - VOUT ´ V
)
(
1
OUT
IOUT(LL)
=
´
2´L ´ fSW
V
IN
(1)
PWM Frequency and Adaptive On-Time Control
TPS65581 uses a advanced D-CAP2 mode control scheme and have a dedicated on board oscillator. The
device runs with fixed frequency of 700 kHz.
Soft Start and Pre-Biased Soft Start
The TPS65581 has an internal, 1.2 ms, soft-start for each channel. When the ENx pin becomes high, an internal
DAC begins ramping up the reference voltage to the PWM comparator. Smooth control of the output voltage is
maintained during start up.
The device contains a unique circuit to prevent current from being pulled from the output during startup if the
output is pre-biased. When the soft-start commands a voltage higher than the pre-bias level (internal soft start
becomes greater than internal feedback voltage VFB), the controller slowly activates synchronous rectification by
starting the first low side FET gate driver pulses with a narrow on-time. It then increments that on-time on a
cycle-by-cycle basis until it coincides with the time dictated by (1-D), where D is the duty cycle of the converter.
This scheme prevents the initial sinking of the pre-biased output, and ensures that the output voltage (VOx)
starts and ramps up smoothly into regulation from pre-biased startup to normal mode operation.
Current Protection
The output overcurrent protection (OCP) is implemented using a cycle-by-cycle valley detect control circuit and
using HICCUP mode overcurrent protection. The switch current is monitored by measuring the low-side FET
switch voltage between the SWx pin and PGNDx. This voltage is proportional to the switch current and the on-
resistance of the FET. To improve accuracy, the voltage sensing is temperature compensated.
During the on time of the high-side FET switch, the switch current increases at a linear rate determined by VIN,
VOUT, the on-time and the output inductor value. During the on time of the low-side FET switch, this current
decreases linearly. The average value of the switch current is the load current IOX. If the sensed voltage on the
low side FET is above the voltage proportional to the current limit, the converter keeps the low-side switch on
until the measured voltage falls below the voltage corresponding to the current limit and a new switching cycle
begins. In subsequent switching cycles, the on-time is set to the value determined for CCM and the current is
monitored in the same manner.
8
Copyright © 2013, Texas Instruments Incorporated
TPS65581
www.ti.com.cn
ZHCSBO1 –OCTOBER 2013
Following are some important considerations for this type of overcurrent protection. The load current one half of
the peak-to-peak inductor current higher than the overcurrent threshold. Also when the current is being limited,
the output voltage tends to fall as the demanded load current may be higher than the current available from the
converter. When the over current condition is removed, the output voltage returns to the regulated value. This
protection is non-latching.
Lower than 1.5 A load current for CH1 and CH3 is required at the VOUT setting in high on-duty because the
overcurrent limit function causes the degradation of load transient response.
Hiccup Mode
Hiccup mode of operation protects the power supply from being damaged during an ove-current fault condition.
The operation of hiccup is as follows. If the OCL comparator circuit detects an over-current event the output
voltage falls. When the feedback voltage falls below 68% of the reference voltage, the UVP comparator output
goes high and an internal UVP delay counter begins counting. After counting UVP delay time, the TPS65581
shuts off the power supply for a given time (7x UVP Enable Delay Time) and then tries to re-start the power
supply. If the over-load condition has been removed, the power supply starts and operates normally; otherwise,
the TPS65581 detects another overcurrent event and shuts off the power supply again, repeating the previous
cycle. Excess heat due to overload lasts for only a short duration in the hiccup cycle, therefore the junction
temperature of the power devices is much lower.
POWERGOOD
The TPS65581 has power-good output that are measured on VFBx. The power-good function is activated after
the soft-start has finished. If the all output voltages of 3 channels are within 16% of the target voltage, the
internal comparator detects the power good state and the power good signal becomes high after 1.5ms delay.
During start-up, this internal delay starts after 1.5ms of the UVP Enable delay time to avoid a glitch of power-
good signal. Even if at least one of the feedback voltages of 3 channels goes outside of ±16% of target value,
the power-good signal becomes low after 2 µs.
<Start up>
Figure 1. Start up
Copyright © 2013, Texas Instruments Incorporated
9
TPS65581
ZHCSBO1 –OCTOBER 2013
www.ti.com.cn
<Vout Transient>
Figure 2. VOUT Transient
<Power Down>
Figure 3. Power Down
UVLO Protection
Under voltage lock out protection (UVLO) monitors the voltage of the VREG5 pin. When the VREG5 voltage is
lower than UVLO threshold voltage, the TPS65581 is shut down. As soon as the voltage increases above the
UVLO threshold, the converter starts again.
Thermal Shutdown
TPS65581 monitors its temperature of itself. If the temperature exceeds the threshold value (typically 155°C), the
device is shut down. When the temperature falls below the threshold, the IC starts again.
When VIN starts up and VREG5 output voltage is below its nominal value, the thermal shutdown threshold is
lower than 155℃. As long as VIN and VREG5 rise, TJ must be kept below 110℃.
10
Copyright © 2013, Texas Instruments Incorporated
TPS65581
www.ti.com.cn
ZHCSBO1 –OCTOBER 2013
TYPICAL CHARACTERISTICS
VIN = 12 V, TA = 25°C (unless otherwise noted)
30.0
25.0
20.0
15.0
10.0
5.0
5.0
VIN = 12 V
VIN = 12 V
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
0.0
-50
0
50
100
150
-50
0
50
100
150
C001
C002
TJ Junction Temperature (C)
TJ Junction Temperature (C)
Figure 4. VIN Current vs Junction Temperature
(VIN Current at All CHs Switching with IO = 0 A)
Figure 5. VIN Current vs Junction Temperature
(VIN Current at All CHs Non-switching, EN = H)
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
60
50
40
30
20
10
0
EN1
EN2
EN3
VIN = 12 V
0
50
100
150
0
5
10
15
20
±50
C003
TJ Junction Temperature (C)
EN Input Voltage (V)
C019
Figure 6. VIN Shutdown Current vs Junction Temperature
Figure 7. EN Current vs EN Voltage
1.25
1.24
1.23
1.22
1.21
1.2
3.40
VIN = 6 V
3.38
VIN = 12 V
3.36
3.34
3.32
3.30
3.28
3.26
3.24
3.22
3.20
VIN = 18 V
1.19
1.18
1.17
1.16
1.15
VIN = 5 V
VIN = 12 V
VIN = 18 V
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
0.0
0.5
1.0
1.5
2.0
2.5
C004
C005
IOUT - Output Current (A)
IOUT - Output Current (A)
Figure 8. VOUT1 = 3.3 V Output Voltage vs Output Current
Figure 9. VOUT2 = 1.2 V Output Voltage vs Output Current
Copyright © 2013, Texas Instruments Incorporated
11
TPS65581
ZHCSBO1 –OCTOBER 2013
www.ti.com.cn
TYPICAL CHARACTERISTICS (continued)
VIN = 12 V, TA = 25°C (unless otherwise noted)
1.55
3.4
3.38
3.36
3.34
3.32
3.3
1.54
1.53
1.52
1.51
1.5
1.49
1.48
1.47
1.46
1.45
3.28
3.26
3.24
3.22
3.2
VIN = 5 V
VIN = 12 V
VIN = 18 V
IOUT = 10 mA
IOUT = 1 A
16 18
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
0
2
4
6
8
10
12
14
20
C006
IOUT - Output Current (A)
C007
VIN - Input Voltage (V)
Figure 10. VOUT3 = 1.5 V Output Voltage vs Output Voltage
Figure 11. VOUT1 = 3.3 V Output Voltage vs Input Voltage
1.25
1.24
1.23
1.22
1.21
1.2
1.55
1.54
1.53
1.52
1.51
1.5
1.19
1.18
1.17
1.49
1.48
1.47
IOUT = 10 mA
IOUT = 1 A
16 18
IOUT = 10 mA
IOUT = 1 A
16 18
1.16
1.15
1.46
1.45
0
2
4
6
8
10
12
14
20
0
2
4
6
8
10
12
14
20
C008
C009
VIN - Input Voltage (V)
VIN - Input Voltage (V)
Figure 12. VOUT2 = 1.2 V Output Voltage vs Input Voltage
Figure 13. VOUT3 = 1.5 V Output Voltage vs Input Voltage
V
= 3.3V
O
V
O
= 1.2V
V
OUT
(50mV/div)
V
OUT
(50mV/div)
I 2 (1A/div)
OUT
I 1 (1A/div)
OUT
100 Ps/div
Figure 14. VOUT1 = 3.3V, 0A to 1.5A Load Transient
100 Ps/div
Figure 15. VOUT2 = 1 .2V, 0A to 2.5A Load Transient
Response
Response
12
Copyright © 2013, Texas Instruments Incorporated
TPS65581
www.ti.com.cn
ZHCSBO1 –OCTOBER 2013
TYPICAL CHARACTERISTICS (continued)
VIN = 12 V, TA = 25°C (unless otherwise noted)
100
90
80
70
60
50
40
30
20
10
0
V
O
= 1.5V
V
(50mV/div)
OUT
I
3 (1A/div)
OUT
VIN = 6 V
VIN = 12 V
VIN = 18 V
0.001
0.01
0.1
1
10
C010
IOUT - Output Current (A)
100 Ps/div
Figure 16. VOUT3 = 1.5V, 0A to 1.5A Load Transient
Response
Figure 17. VOUT1 = 3.3V Light Load Efficiency vs Output
Current
100
100
90
80
70
60
50
40
30
90
80
70
60
50
40
30
20
10
0
VIN = 5 V
VIN = 5 V
VIN = 12 V
VIN = 18 V
20
10
0
VIN=12V
V
= 18 V
IN
0.001
0.01
0.1
1
10
0.001
0.01
0.1
1
10
C011
C012
IOUT - Output Current (A)
IOUT - Output Current (A)
Figure 18. VOUT2 = 1.2V Light Load Efficiency vs Output
Current
Figure 19. VOUT3=1.5V, Light Load Efficiency vs Output
Current
900
900
IOUT = 1 A
IOUT = 1 A
850
850
800
750
700
650
600
550
500
450
400
800
750
700
650
600
550
500
450
400
0
5
10
15
20
0
5
10
15
20
C013
C014
VIN - Input Voltage (V)
VIN - Input Voltage (V)
Figure 20. VOUT1 = 3.3V Switching Frequency vs Input
Voltage
Figure 21. VOUT2 = 1.2V Switching Frequency vs Input
Voltage
Copyright © 2013, Texas Instruments Incorporated
13
TPS65581
ZHCSBO1 –OCTOBER 2013
www.ti.com.cn
TYPICAL CHARACTERISTICS (continued)
VIN = 12 V, TA = 25°C (unless otherwise noted)
900
850
800
750
700
650
600
550
500
450
400
800
700
600
500
400
300
200
100
0
IOUT = 1 A
VIN = 12 V
0
5
10
15
20
0.01
0.1
1
10
C015
C016
VIN - Input Voltage (V)
IO - Output Current (A)
Figure 22. VOUT3 = 1.5V Switching Frequency vs Input
Voltage
Figure 23. VOUT1 = 3.3V Switching Frequency vs Output
Current
800
800
VIN = 12 V
VIN = 12 V
700
600
500
400
300
200
100
0
700
600
500
400
300
200
100
0
0.01
0.1
1
10
0.01
0.1
1
10
C017
C018
IO - Output Current (A)
IO - Output Current (A)
Figure 24. VOUT2 = 1.2V, Switching Frequency vs Output
Current
Figure 25. VOUT3 = 1.5V, Switching Frequency vs Output
Current
V 2 (10mV/div)
O
V 1 (10mV/div)
O
V
O
= 1.2V
V
O
= 3.3V
SW1 (5V/div)
SW2 (5V/div)
400 ns/div
400 ns/div
Figure 27. VOUT2 = 1.2V, Ripple Voltage at IOUT1 = 2.5A
Figure 26. VOUT1 = 3.3V, Ripple Voltage at IOUT1 = 1.5A
14
Copyright © 2013, Texas Instruments Incorporated
TPS65581
www.ti.com.cn
ZHCSBO1 –OCTOBER 2013
TYPICAL CHARACTERISTICS (continued)
VIN = 12 V, TA = 25°C (unless otherwise noted)
V 3 (10mV/div)
O
V
IN
(50mV/div)
V
O
= 1.5V
V = 3.3V
O
SW3 (5V/div)
SW1(5V/div)
400 ns/div
400ns/div
Figure 29. VOUT1 = 3.3V, VIN Ripple Voltage at IOUT1 =
1.5A
Figure 28. VOUT3 = 1.2V, Ripple Voltage at IOUT1 = 1.5A
V
IN
(50mV/div)
V
IN
(50mV/div)
V
O
= 1.2V
V = 1.5V
O
SW3 (5V/div)
SW2(5V/div)
400ns/div
400ns/div
Figure 30. VOUT2 = 1.2V VIN Ripple at IOUT2 = 2.5A
Figure 31. VOUT3 = 1.5V VIN Ripple at IOUT3 = 1.5A
EN2 (10V/div)
EN1 (10V/div)
VREG5 (5V/div)
VREG5 (5V/div)
V 2 (0.5V/div)
OUT
V 1 (1V/div)
OUT
PG (5V/div)
PG (5V/div)
1 ms/div
Figure 32. VOUT1 = 3.3V Soft-Start IOUT1 = 1.5A
1 ms/div
Figure 33. VOUT2 = 1.2V Soft-Start IOUT2 = 2.5A
Copyright © 2013, Texas Instruments Incorporated
15
TPS65581
ZHCSBO1 –OCTOBER 2013
www.ti.com.cn
TYPICAL CHARACTERISTICS (continued)
VIN = 12 V, TA = 25°C (unless otherwise noted)
EN3 (10V/div)
VREG5 (5V/div)
V 3 (0.5V/div)
OUT
PG (5V/div)
1 ms/div
Figure 34. VOUT3 = 1.5V Soft-Start IOUT3 = 1.5A
16
Copyright © 2013, Texas Instruments Incorporated
TPS65581
www.ti.com.cn
ZHCSBO1 –OCTOBER 2013
DESIGN GUIDE
Step By Step Design Procedure
To begin the design process, you must know a few application parameters:
•
•
•
Input voltage range
Output voltage
Output current
Input Voltage
VBST2
SW2
20
19
18
1
2
3
4
5
6
VIN
C32
L12
VO2
VIN
C22
C11
VBST1
PGND2
L11
C31
VO1
PGND
SW1
EN2
17
16
C21
PGND1
PGND3
PGND
TPS65581
L13
C4
PGND
C23
VO3
HTSSOP20
(PowerPAD)
VREG5
PG
SW3 15
C33
PGND
7
14
VBST3
EN1
8
9
EN3 13
R11
R13
R23
VFB1
12
11
VFB3
VFB2
R21
R12
R22
10
GND
SGND
SGND
SGND
SGND
Figure 35. Schematic Diagram for the Design Example at VIN = 12V
Output Voltage Resistors Selection
The output voltage is set with a resistor divider from the output node to the VFBx pin. It is recommended to use
1% tolerance or better divider resistors. Start by using Equation 2 to calculate VOx
.
To improve the efficiency at very light loads consider using larger value resistors, but too high resistance values
will be more susceptible to noise and voltage errors due to the VFBx input current will be more noticeable.
R1x
æ
ö
VOX = 0.764´ 1+
ç
÷
R2x
è
ø
(2)
(3)
Output Filter Selection
The output filter used with the TPS65581 is an LC circuit. This LC filter has double pole at:
1
F =
P
2p L1X ´ C2X
Copyright © 2013, Texas Instruments Incorporated
17
TPS65581
ZHCSBO1 –OCTOBER 2013
www.ti.com.cn
At low frequencies, the overall loop gain is set by the output set-point resistor divider network and the internal
gain of the TPS65581. The low frequency phase is 180 degrees. At the output filter pole frequency, the gain rolls
off at a –40 dB per decade rate and the phase drops rapidly. Advanced D-CAP2™ introduces a high frequency
zero that reduces the gain roll off to –20 dB per decade and increases the phase to 90 degrees one decade
above the zero frequency. The inductor and capacitor selected for the output filter must be selected so that the
double pole of Equation 3 is located below the high frequency zero but close enough that the phase boost
provided by the high frequency zero provides adequate phase margin for a stable circuit. To meet this
requirement, use the values recommended in Table 1.
Table 1. Recommended Component Values
OUTPUT VOLTAGE (V)
R1x (kΩ)
0.68
R2x (kΩ)
2.2
L1x (µH)
1.5 to 3.3
1.5 to 3.3
1.5 to 3.3
1.5 to 3.3
1.5 to 3.3
2.2 to 4.7
2.2 to 4.7
2.2 to 4.7
2.2 to 4.7
C2x (µF)
22 - 68
22 - 68
22 - 68
22 - 68
22 - 68
22 - 68
22 - 68
22 - 68
22 - 68
1
1.05
1.2
1.5
1.8
2.5
3.3
5
0.82
2.2
1.27
2.2
2.15
2.2
3.00
2.2
4.98
2.2
7.36
2.2
12.4
2.2
6.5
16.5
2.2
The inductor peak-to-peak ripple current, peak current and RMS current are calculated using Equation 4,
Equation 5 and Equation 6. The inductor saturation current rating must be greater than the calculated peak
current and the RMS or heating current rating must be greater than the calculated RMS current.
For the calculations, use 700 kHz as the switching frequency, fSW. Make sure the chosen inductor is rated for the
peak current of Equation 5 and the RMS current of Equation 6.
V
- VOX
VOX
IN(MAX)
DIL1X
=
´
V
L1x ´ ƒSW
IN(MAX)
(4)
(5)
DIL1X
IL1XPEAK = IOX
+
2
1
+
12
2
2
IL1X(RMS)
=
IOX
DIL1X
(6)
For the above design example, the calculated peak current is 2.46 A and the calculated RMS current is 2.02 A.
for Vo1. The inductor used is a TDK CLF7045-1R5N with a rated current of 7.3 A based on the inductance
change and of 4.9A based on the temperature rise.
The capacitor value and ESR determines the amount of output voltage ripple. The TPS65581 is intended for use
with ceramic or other low ESR capacitors. Recommended values range from 22µF to 68µF. Use Equation 7 to
determine the required RMS current rating for the output capacitor(s).
VOX ´ VIN - VOX
(
)
12 ´ V ´LIX ´ ƒSW
IC2X(RMS)
=
IN
(7)
For this design two TDK C3216X5R0J226M 22 µF output capacitors are used. The typical ESR is 2 mΩ each.
The calculated RMS current is 0.19A and each output capacitor is rated for 4 A.
Input Capacitor Selection
The TPS65581 requires an input decoupling capacitor and a bulk capacitor is needed depending on the
application. A ceramic capacitor over 10µF x 2 is recommended for the decoupling capacitor. Accordingly, 0.1 µF
ceramic capacitors from pin 1 to ground is recommended to improve the stability and reduce the SWx node
overshoots. The capacitor voltage rating needs to be greater than the maximum input voltage.
18
Copyright © 2013, Texas Instruments Incorporated
TPS65581
www.ti.com.cn
ZHCSBO1 –OCTOBER 2013
Bootstrap Capacitor Selection
A 0.1 µF ceramic capacitors must be connected between the VBSTx and SWx pins for proper operation. It is
recommended to use ceramic capacitors with a dielectric of X5R or better.
VREG5 Capacitor Selection
A 1 µF ceramic capacitor must be connected between the VREG5 and GND pins for proper operation. It is
recommended to use a ceramic capacitor with a dielectric of X5R or better.
Thermal Information
This 20-pin PWP package incorporates an exposed thermal pad that is designed to be directly to an external
heartsick. The thermal pad must be soldered directly to the printed board (PCB). After soldering, the PCB can be
used as a heartsick. In addition, through the use of thermal vias, the thermal pad can be attached directly to the
appropriate copper plane shown in the electrical schematic for the device, or alternatively, can be attached to a
special heartsick structure designed into the PCB. This design optimizes the heat transfer from the integrated
circuit (IC).
For additional information on the exposed thermal pad and how to use the advantage of its heat dissipating
abilities, refer to the Technical Brief, PowerPAD™ Thermally Enhanced Package, Texas Instruments Literature
No. SLMA002 and Application Brief, PowerPAD™ Made Easy, Texas Instruments Literature No. SLMA004.
The exposed thermal pad dimensions for this package are shown in the following illustration.
Figure 36. Thermal Pad Dimensions
Copyright © 2013, Texas Instruments Incorporated
19
TPS65581
ZHCSBO1 –OCTOBER 2013
www.ti.com.cn
Layout Considerations
1. Keep the input current loop as small as possible. And avoid the input switching current through the thermal
pad.
2. Keep the SW node as physically small and short as possible to minimize parasitic capacitance and
inductance and to minimize radiated emissions. Kelvin connections should be brought from the output to the
feedback pin of the device.
3. Keep analog and non-switching components away from switching components.
4. Make a single point connection from the signal ground to power ground.
5. Do not allow switching currents to flow under the device.
6. Keep the pattern lines for VIN and PGND broad.
7. Exposed pad of device must be connected to PGND with solder.
8. VREG5 capacitor should be placed near the device, and connected to PGND.
9. Output capacitors should be connected with a broad pattern to the PGND.
10. Voltage feedback loops should be as short as possible, and preferably with ground shield.
11. Kelvin connections should be brought from the output to the feedback pin of the device.
12. Providing sufficient vias is preferable for VIN, SW and PGND connection.
13. PCB pattern for VIN, SW, and PGND should be as broad as possible.
14. VIN Capacitor should be placed as near as possible to the device.
Recommend to keep
VIN INPUT
BYPASS
distance more than 3-4mm.
VIN
(to avoid noise scattering,
CAPACITOR
10mF x 2
especially GND plane.)
VIN HIGH
FREQUENCY
BYPASS
CAPACITOR
~0.1mF
Break Line * Flow of
switching noise.
Switching noise
flows through IC
and Cin.
OUTPUT
FILTER
CAPACITOR
1
2
3
20
19
VBST2
SW2
VIN
VO2
OUTPUT
INDUCTOR
VIN
OUTPUT
FILTER
CAPACITOR
BOOST
CAPACITOR
VBST1
SW1
18
VO1
PGND2
GND PLANE
OUTPUT
INDUCTOR
TO ENABLE
CONTROL
4
5
17
16
15
EN2
PGND1
VREG5
PG
PGND3
SW3
GND PLANE
6
7
OUTPUT
INDUCTOR
VO3
14
VBST3
OUTPUT
FILTER
CAPACITOR
TO ENABLE
CONTROL
8
9
EN1
13 EN3
Feedback
resisters
12
VFB1
VFB3
Feedback
resisters
10
VFB2
11
GND
Feedback
resisters
VO3
GND
Keep
distance more
than 1 inch
PLANE
2,3 or bottom
layer
VO2
VO1
Figure 37. TPS65581 Layout
20
Copyright © 2013, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS65581PWP
ACTIVE
ACTIVE
HTSSOP
HTSSOP
PWP
PWP
20
20
70
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
TPS65581
TPS65581
TPS65581PWPR
2000 RoHS & Green
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
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