TPS65631DPDR [TI]
双路输出有源矩阵有机发光二极管 (AMOLED) 显示屏电源 | DPD | 12 | -40 to 85;
| 型号： | TPS65631DPDR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 双路输出有源矩阵有机发光二极管 (AMOLED) 显示屏电源 | DPD | 12 | -40 to 85 驱动 光电二极管 接口集成电路 |
| 文件： | 总24页 (文件大小：867K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TPS65631
ZHCSCJ0E –SEPTEMBER 2012–REVISED MAY 2014
TPS65631 双输出有源矩阵有机发光二极管 (AMOLED) 显示屏电源
1 特性
3 说明
1
•
2.9V 至 4.5V 输入电压范围
4.6V 固定正输出电压
TPS65631 被设计用于驱动需要正负电源轨的
AMOLED（有源矩阵有机发光二极管）显示屏。 此器
件集成了一个针对 VPOS 的升压转换器和一个针对
•
•
•
•
25ºC 至 85ºC 温度范围内，VPOS 精度 0.5%
单独的 VPOS 输出感测引脚
VNEG 的反相降压升压转换器，非常适合于电池供电类
产品。 数字控制引脚 (CTRL) 允许用数字步长设定负
输出电压。 TPS65631 使用能够实现出色线路瞬态性
能的创新技术。
-1.4V 至 -4.4V 的数字可编程负输出电压（缺省值 -
4V）
•
•
•
•
•
支持的输出电流高达 250mA
出色的线路瞬态稳压
短路保护功能
器件信息(1)
产品型号
封装
封装尺寸（标称值）
热关断
TPS65631
QFN (12)
3.00mm x 3.00mm
采用 3.00mm x 3.00mm 12 引脚四方扁平无引线
(QFN) 封装
(1) 要了解所有可用封装，请见数据表末尾的可订购产品附录。
空白
空白
空白
空白
空白
2 应用范围
AMOLED 显示屏
4 简化电路原理图
L1
4.7 µH
效率与输出电流间的关系
100
90
80
70
60
50
40
30
20
VI
PVIN
AVIN
SWP
OUTP
FBS
2.9 V to 4.5 V
VPOS
4.6 V, 300 mA
C1
2×10 µF
C2
10 µF
TPS65631
EN / Program VNEG
CTRL
C4
100 nF
VNEG
±4.0 V, 300 mA
OUTN
SWN
CT
C3
2×10 µF
PGND
AGND
GND
L2
4.7 µH
VPOS = 4.6 V
10
VNEG = –4.0 V
50
VI = 3.7 V
250 300
0
0
100
150
200
Output Current (mA)
G000
1
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
English Data Sheet: SLVSBK1
TPS65631
ZHCSCJ0E –SEPTEMBER 2012–REVISED MAY 2014
www.ti.com.cn
目录
8.2 Functional Block Diagram ......................................... 8
8.3 Feature Description................................................... 8
8.4 Device Functional Modes........................................ 12
Applications and Implementation ...................... 12
9.1 Application Information............................................ 12
9.2 Typical Application .................................................. 12
1
2
3
4
5
6
7
特性.......................................................................... 1
应用范围................................................................... 1
说明.......................................................................... 1
简化电路原理图........................................................ 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
7.1 Absolute Maximum Ratings ..................................... 4
7.2 Handling Ratings....................................................... 4
7.3 Recommended Operating Conditions....................... 4
7.4 Thermal Information.................................................. 4
7.5 Electrical Characteristics........................................... 5
7.6 Timing Requirements................................................ 6
7.7 Typical Characteristics.............................................. 7
Detailed Description .............................................. 8
8.1 Overview ................................................................... 8
9
10 Power Supply Recommendations ..................... 16
11 Layout................................................................... 17
11.1 Layout Guidelines ................................................. 17
11.2 Layout Example .................................................... 17
12 器件和文档支持 ..................................................... 18
12.1 器件支持................................................................ 18
12.2 Trademarks........................................................... 18
12.3 Electrostatic Discharge Caution............................ 18
12.4 Glossary................................................................ 18
13 机械封装和可订购信息 .......................................... 18
8
5 修订历史记录
日期
修订版本
注释
2014 年 5 月
E
没有针对修订版本 E 的之前修订历史记录 - 首次公开发布
2
Copyright © 2012–2014, Texas Instruments Incorporated
TPS65631
www.ti.com.cn
ZHCSCJ0E –SEPTEMBER 2012–REVISED MAY 2014
6 Pin Configuration and Functions
DPD PACKAGE
(TOP VIEW)
SWP
PGND
OUTP
FBS
1
12 PVIN
2
3
4
5
6
11 AVIN
10 SWN
9
8
7
OUTN
CT
AGND
GND
CTRL
DPD PACKAGE
(BOTTOM VIEW)
PVIN 12
AVIN 11
SWN 10
1
2
3
4
5
6
SWP
PGND
OUTP
FBS
OUTN
CT
9
8
7
AGND
GND
CTRL
Pin Functions
NAME
AGND
AVIN
CT
NO.
5
I/O
—
DESCRIPTION
Analog ground.
11
8
—
Input supply voltage for internal analog circuits (both converters).
I/O
Timing capacitor pin. Connect a capacitor between this pin and ground to
control the time it takes for the output of the inverting buck-boost converter to
ramp from one value of VNEG to another.
CTRL
7
I
Control pin. Combined device enable and inverting buck-boost converter output
voltage programming pin.
FBS
4
6
I
Feedback sense pin of the boost converter output voltage.
GND
—
Ground. (Note: it is possible to leave this pin floating without affecting device
performance.)
PGND
PVIN
2
12
10
1
—
—
O
Power ground of the boost converter.
Input supply voltage pin for the inverting buck-boost converter.
Switch pin of the inverting buck-boost converter.
Switch pin of the boost converter.
SWN
SWP
O
OUTN
OUTP
9
O
Rectifier pin of the inverting buck-boost converter.
Rectifier pin of the boost converter.
3
O
Exposed Thermal
Pad
13
—
Connect this pad to AGND and PGND.
Copyright © 2012–2014, Texas Instruments Incorporated
3
TPS65631
ZHCSCJ0E –SEPTEMBER 2012–REVISED MAY 2014
www.ti.com.cn
7 Specifications
(1)
7.1 Absolute Maximum Ratings
(1)
over operating free-air temperature range (unless otherwise noted)
MIN
–0.3
–0.3
–6
MAX
6
UNIT
V
SWP, OUTP, FBS, PVIN, AVIN
OUTN
–6
V
(2)
Input voltage
SWN
CTRL
CT
6
V
–0.3
–0.3
–40
5.5
3.6
150
V
V
Operating junction temperature range, TJ
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) With respect to GND pin.
7.2 Handling Ratings
MIN
MAX
UNIT
TSTG
Storage temperature range
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001,
–65
150
°C
–2
2
kV
(1)
all pins
VESD
Electrostatic discharge Charged device model (CDM), per JEDEC specification
–500
–200
500
200
V
V
(2)
JESD22-C101, all pins
Machine model (MM) ESD stress voltage
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process..
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
PARAMETER
MIN
NOM
3.7
MAX UNIT
VI
Input supply voltage range
Output voltage range
2.9
4.5
V
VPOS
VNEG
IPOS
4.6
VO
V
–4.4
–4
–1.4
300
300
85
IO
Output current range
mA
INEG
TA
TJ
Operating ambient temperature
Operating junction temperature
–40
–40
25
85
°C
°C
125
7.4 Thermal Information
PD
THERMAL METRIC(1)
UNIT
12 PINS
51.5
47.1
25.0
0.5
RθJA
Junction-to-ambient thermal resistance
RθJCtop
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
ψJB
25.2
4.4
RθJCbot
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
4
Copyright © 2012–2014, Texas Instruments Incorporated
TPS65631
www.ti.com.cn
ZHCSCJ0E –SEPTEMBER 2012–REVISED MAY 2014
7.5 Electrical Characteristics
VI = 3.7 V, V(CTRL) = 3.7 V, VPOS = 4.6 V, VNEG = –4.0 V, TJ = –40°C to 125°C, typical values are at TA = 25°C (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY
II
Shutdown current into AVIN and
PVIN
CTRL pin connected to ground.
0.1
µA
VI rising.
VI falling.
2.4
2.1
VUVLO
Undervoltage lockout threshold
V
V
BOOST CONVERTER
Output voltage
4.6
VO
25°C ≤ TA ≤ 85°C, no load
–40°C ≤ TA < 85°C, no load
I(SWP) = 200 mA
–0.5%
–0.8%
0.5%
0.8%
Output voltage tolerance
Switch (low-side) on-resistance
Rectifier (high-side) on-resistance
Switching frequency
200
350
1.7
1
rDS(ON)
mΩ
I(SWP) = 200 mA
IO = 200 mA
MHz
A
Switch current limit
Inductor valley current
0.8
Short-circuit threshold voltage in
operation
VO falling
4.1
3
V
Short-circuit detection time during
operation
ms
mV
Output sense threshold voltage
using OUTP
V(OUTP) - V(FBS) increasing
300
Output sense threshold voltage
using FBS
V(OUTP) - V(FBS) decreasing
Between FBS pin and ground
200
4
mV
MΩ
Ω
Input resistance of FBS
CTRL pin connected to ground,
IO = 1 mA
Discharge resistance
30
Line regulation
Load regulation
IO = 200 mA
0.002
0.01
%/V
%/A
INVERTING BUCK-BOOST CONVERTER
Output voltage default
–4.0
VO
Output voltage range
–4.4
–1.4
0.05
V
Output voltage tolerance
Switch (high-side) on-resistance
Rectifier (low-side) on-resistance
Switching frequency
–0.05
I(SWN) = 200 mA
I(SWN) = 200 mA
IO = 10 mA
200
300
1.7
rDS(ON)
mΩ
MHz
A
Switch current limit
VI = 2.9 V
1.5
2.2
Short-circuit threshold voltage during
operation
Voltage drop from nominal VO
500
200
10
mV
Short-circuit threshold voltage during
start-up
180
230
Short-circuit detection time during
start-up
tSCP
ms
ms
Ω
Short-circuit detection time during
operation
3
CTRL pin connected to ground,
IO = 1 mA
Discharge resistance
150
Line regulation
Load regulation
IO = 200 mA
0.006
0.31
%/V
%/A
CTRL
High-level threshold voltage
Low-level threshold voltage
1.2
V
V
0.4
Copyright © 2012–2014, Texas Instruments Incorporated
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TPS65631
ZHCSCJ0E –SEPTEMBER 2012–REVISED MAY 2014
www.ti.com.cn
Electrical Characteristics (continued)
VI = 3.7 V, V(CTRL) = 3.7 V, VPOS = 4.6 V, VNEG = –4.0 V, TJ = –40°C to 125°C, typical values are at TA = 25°C (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Pull-down resistance
150
400
860
kΩ
OTHER
R(CT)
tINIT
CT pin output resistance
Initialization time
150
300
300
500
400
80
kΩ
µs
µs
µs
°C
tOFF
Shut-down time
30
30
tSTORE
TSD
Data storage time
80
Thermal shutdown temperature
145
7.6 Timing Requirements
MIN
TYP
MAX
UNIT
CTRL Interface
tHIGH
tLOW
High-level pulse duration
Low-level pulse duration
2
2
10
10
25
25
µs
µs
6
Copyright © 2012–2014, Texas Instruments Incorporated
TPS65631
www.ti.com.cn
ZHCSCJ0E –SEPTEMBER 2012–REVISED MAY 2014
7.7 Typical Characteristics
At TA = 25°C, unless otherwise noted.
4.0
3.5
0.50
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0.00
3.0
2.5
2.0
1.5
1.0
0.5
0.0
−0.5
−1.0
−50
−25
0
25
50
75
100
125
−50
−25
0
25
50
75
100
125
Junction Temperature (°C)
Junction Temperature (°C)
G001
G002
Figure 1. Shutdown Current into AVIN and PVIN
Figure 2. Boost Converter Switch rDS(ON)
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
0.50
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0.00
−50
−25
0
25
50
75
100
125
−50
−25
0
25
50
75
100
125
Junction Temperature (°C)
Junction Temperature (°C)
G003
G004
Figure 3. Boost Converter Rectifier rDS(ON)
Figure 4. Inverting Buck-Boost Converter Switch rDS(ON)
0.50
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0.00
−50
−25
0
25
50
75
100
125
Junction Temperature (°C)
G005
Figure 5. Inverting Buck-Boost Converter Rectifier rDS(ON)
Copyright © 2012–2014, Texas Instruments Incorporated
7
TPS65631
ZHCSCJ0E –SEPTEMBER 2012–REVISED MAY 2014
www.ti.com.cn
8 Detailed Description
8.1 Overview
The TPS65631 consists of a boost converter and an inverting buck boost converter. The VPOS output is fixed at
4.6 V and VNEG output is programmable via a digital interface in the range of -1.4 V ~ -4.4 V, the default is -4 V.
The transition time of VNEG output is adjustable by the CT pin capacitor.
8.2 Functional Block Diagram
SWP
OUTP
1
3
4
VPOS
DCHG
Short-Circuit
Protection
Gate Driver
FBS
Output Sense
Control
AVIN
PGND
±
VI
11
+
PWM Control
Oscillator
VREF
SWP
CTRL
Short-Circuit
Protection
±
CT
+
CT
Control
8
+
±
50 mV
Constant Off-Time
Controller
Gate
Drive
Digital
DCHG
Interface
PVIN
OUTN
12
9
VNEG
6
5
10
7
2
GND
AGND
SWN
CTRL
PGND
8.3 Feature Description
8.3.1 Boost Converter
The boost converter uses a fixed-frequency current-mode topology, and its output voltage (VPOS) is fixed at 4.6 V
For the highest output voltage accuracy, connect the output sense pin (FBS) directly to the positive pin of the
output capacitor. If not used, the FBS pin can be left floating or connected to ground. If the FBS pin is not used,
the boost converter senses its output voltage using the OUTP pin.
8
Copyright © 2012–2014, Texas Instruments Incorporated
TPS65631
www.ti.com.cn
ZHCSCJ0E –SEPTEMBER 2012–REVISED MAY 2014
Feature Description (continued)
8.3.2 Inverting Buck-Boost Converter
The inverting buck-boost converter uses a constant-off-time peak-current mode topology. The converter's default
output voltage (VNEG) is –4 V, but it can be programmed to any voltage in the range –1.4 V to –4.4 V (see
Programming VNEG).
8.3.2.1 Programming VNEG
The output voltage of the inverting buck-boost converter (VNEG) can be programmed using the CTRL pin. If
output voltage programming is not required, the CTRL pin can be used as a standard enable pin (see Enable
(CTRL)).
ttINIT
tLOW
t
ttHIGH
ttSTORE
ttOFF
CTRL
VPOS
VNEG
4.6 V
ttSCP
t
ttSET
±4.0 V
±4.2 V
Figure 6. Programming VNEG Using the CTRL Pin
When the CTRL pin is pulled high, the inverting buck-boost converter starts up with its default voltage of –4V.
The device now counts the rising edges applied to the CTRL pin and sets the output voltage (VNEG) according to
Table 1. For the timing diagram shown in Figure 6, VNEG is programmed to –4.2 V, since three rising edges are
detected.
The CTRL interface is designed to work with pulses whose duration is between 2 µs and 25 µs. Pulses shorter
than 2 µs or longer than 25 µs are not ensured to be recognized.
Table 1. Programming Table for VNEG
Number of Rising Edges
VNEG
Number of Rising Edges
VNEG
0 / no pulses
–4 V
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
–2.9 V
–2.8 V
–2.7 V
–2.6 V
–2.5 V
–2.4 V
–2.3 V
–2.2 V
–2.1 V
–2.0 V
–1.9 V
–1.8 V
–1.7 V
–1.6 V
–1.5 V
–1.4 V
1
2
–4.4 V
–4.3 V
–4.2 V
–4.1 V
–4.0 V
–3.9 V
–3.8 V
–3.7 V
–3.6 V
–3.5 V
–3.4 V
–3.3 V
–3.2 V
–3.1 V
–3.0 V
3
4
5
6
7
8
9
10
11
12
13
14
15
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TPS65631
ZHCSCJ0E –SEPTEMBER 2012–REVISED MAY 2014
www.ti.com.cn
8.3.2.2 Controlling the VNEG Transition Time
The transition time (tset) is the time required to move VNEG from one voltage level to the next. Users can control
the transition time by connecting a capacitor between the CT pin and ground. When the CT pin is left open or is
connected to ground, the transition time is as short as possible. When a capacitor is connected to the CT pin, the
transition time is determined by the time constant (τ) of the external capacitor (C(CT)) and the internal resistance
of the CT pin (R(CT)). The output voltage VNEG reaches 70% of its programmed value after 1τ.
An example is given below for the case when using 100 nF for C(CT)
.
τ ≈ tset(70%) = R(CT) × C(CT) = 300 kΩ × 100 nF = 30 ms
(1)
The output voltage VNEG reaches its programmed value after approximately 3τ.
The external capacitor connected to the CT pin has no effect on the first programming of VNEG, when the
inverting buck-boost converter ramps its output to the default voltage as fast as possible. Figure 7 shows the
detail of programming of the VNEG transition time with the CT pin during start-up.
CTRL
4.6 V
VPOS
t10 mst
±3.8 V
VNEG
±4.0 V (Default)
±4.1 V (Initial)
tNot programmable
tby CT capacitor
tProgrammable by
tCT capacitor (3×Tau)
tNot programmable
tby CT capacitor
Figure 7. Programming the Transition Time of VNEG
8.3.3 Soft-Start and Start-Up Sequence
The TPS65631 features a soft-start function to limit inrush current. When the device is enabled by a high-level
signal applied to the CTRL pin, the boost converter starts switching with a reduced switch current limit. Ten
milliseconds after the CTRL pin goes high, the inverting buck-boost converter starts with a default value of –4 V.
A typical start-up sequence is shown in Figure 8.
CTRL
VPOS
10 ms (typ.)
VNEG
Figure 8. Typical Start-Up Sequence
10
Copyright © 2012–2014, Texas Instruments Incorporated
TPS65631
www.ti.com.cn
ZHCSCJ0E –SEPTEMBER 2012–REVISED MAY 2014
8.3.4 Enable (CTRL)
The CTRL pin serves two functions. One is to enable and disable the device, and the other is to program the
output voltage (VNEG) of the inverting buck-boost converter (see Programming VNEG). If the digital interface is not
required, the CTRL pin can be used as a standard enable pin for the device, which will come up with its default
value on VNEG of –4 V. When CTRL is pulled high, the device is enabled. The device is shut down with CTRL
low.
8.3.5 Undervoltage Lockout
The TPS65631 features an undervoltage lockout function that disables the device when the input supply voltage
is too low for normal operation.
8.3.6 Short Circuit Protection
The TPS65631 is protected against short-circuits of VPOS and VNEG to ground and to each other.
8.3.6.1 Short-Circuits During Normal Operation
During normal operation an error condition is detected if VPOS falls below 4.1 V for more than 3 ms or VNEG is
pulled above the programmed nominal output by 500 mV for longer than 3 ms. In either case the device enters
shutdown mode: the converters are disabled and their outputs are disconnected from the input. To resume
normal operation either cycle the input supply voltage or toggle the CTRL pin low and then high again.
8.3.6.2 Short-Circuits During Start-Up
During start up an error condition is detected if:
•
•
•
VPOS is not in regulation 10 ms after a high-level is applied to the CTRL pin.
VNEG is higher than threshold level 10 ms after a high-level is applied to the CTRL pin.
VNEG is not in regulation 20 ms after a high-level is applied to the CTRL pin.
To resume normal operation either cycle the input supply voltage or toggle the CTRL pin low and then high
again.
8.3.7 Output Discharge During Shutdown
The TPS65631 actively discharges its outputs during shutdown. Figure 9 shows the output discharge control.
VI
CTRL
VPOS
tVUVLO
tVUVLO
Discharge
Discharge
Discharge
Discharge
Discharge
Discharge
VNEG
t10 ms (typ.)
t10 ms (typ.)
Figure 9. Active Discharge of VPOS and VNEG During Shutdown
8.3.8 Thermal Shutdown
The TPS65631 enters thermal shutdown mode if its junction temperature exceeds 145°C (typical). During
thermal shutdown mode none of the device functions are available. To resume normal operation, either cycle the
input supply voltage or toggle the CTRL pin low and then high again.
Copyright © 2012–2014, Texas Instruments Incorporated
11
TPS65631
ZHCSCJ0E –SEPTEMBER 2012–REVISED MAY 2014
www.ti.com.cn
8.4 Device Functional Modes
8.4.1 Operation with VI < 2.9 V
The recommended minimum input supply voltage for full performance is 2.9 V. The device continues to operate
with input supply voltages below 2.9 V; however, full performance is not guaranteed. The device does not
operate with input supply voltages below the UVLO threshold.
8.4.2 Operation with VI ≈ VPOS (Diode Mode)
The TPS65631 features a "diode" mode that enables it to regulate its output voltage even when the input supply
voltage is close to VPOS (that is, too high for normal boost operation). When operating in diode mode the
converter's high-side switch stops switching and its body diode is used as the rectifier. Boost converter efficiency
is reduced when operating in diode mode. At low output currents (≈2 mA and below), the boost converter
automatically transitions from pulse-width modulation to pulse-skip mode. This ensures that VPOS stays in
regulation but increases the output voltage ripple on VPOS
.
8.4.3 Operation with CTRL
When a low-level signal is applied to the CTRL pin the device is disabled and switching is inhibited. When the
input supply voltage is above the UVLO threshold and a high-level signal is applied to the CTRL pin the device is
enabled and its start-up sequence begins.
9 Applications and Implementation
9.1 Application Information
Figure 10 shows a typical application circuit suitable for supplying AMOLED displays in smartphone applications.
The circuit is designed to operate from a single-cell Li-Ion battery and generates a positive output voltage VPOS of
4.6 V and a negative output voltage of –4 V. Both outputs are capable of supplying up to 300 mA of output
current.
9.2 Typical Application
L1
4.7 µH
VI
PVIN
AVIN
SWP
OUTP
FBS
2.9 V to 4.5 V
VPOS
4.6 V, 300 mA
C1
2×10 µF
C2
10 µF
TPS65631
EN / Program VNEG
CTRL
C4
100 nF
VNEG
±4.0 V, 300 mA
OUTN
SWN
CT
C3
2×10 µF
PGND
AGND
GND
L2
4.7 µH
Figure 10. Typical Application Schematic
12
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Typical Application (continued)
9.2.1 Design Requirements
For this design example, use the following input parameters.
Table 2. Design Parameters
DESIGN PARAMETER
Input voltage range
Output voltage
EXAMPLE
2.9 V to 4.5 V
VPOS = 4.6V, VNEG = –4 V
1.7 MHz
Switching frequency
9.2.2 Detailed Design Procedure
In order to maximize performance, the TPS65631 has been optimized for use with a relatively narrow range of
component values, and customers are strongly recommended to use the application circuit shown in Figure 10
with the components listed in Table 3 and Table 4.
9.2.2.1 Inductor Selection
The boost converter and inverting buck-boost converter have been optimized for use with 4.7 µH inductors, and it
is recommended that this value be used in all applications. Customers using other values of inductor are strongly
recommended to characterize circuit performance on a case-by-case basis.
Table 3. Inductor Selection
PARAMETER
VALUE
MANUFACTURER
Coilmaster
Toko
PART NUMBER
MMPP252012-4R7N
1239AS-H-4R7M
LPP252012-4R7N
XFL4020-4R7ML
L1, L2
4.7 µH
ABCO
Coilcraft
9.2.2.2 Capacitor Selection
The recommended capacitor values are shown in Table 4. Applications using less than the recommended
capacitance (e.g. to save PCB area) may experience increased voltage ripple. In general, the lower the output
power, the lower the necessary capacitance.
Table 4. Capacitor Selection
PARAMETER
VALUE
2 × 10 µF
10 µF
MANUFACTURER
Murata
PART NUMBER
C1
C2
C3
C4
GRM21BR71A106KE51
GRM21BR71A106KE51
GRM21BR71A106KE51
GRM21BR71E104KA01
Murata
2 × 10 µF
100 nF
Murata
Murata
9.2.2.3 Stability
Applications using component values that differ significantly from those recommended in Table 3 and Table 4
should be checked for stability over the full range of operating conditions.
Copyright © 2012–2014, Texas Instruments Incorporated
13
TPS65631
ZHCSCJ0E –SEPTEMBER 2012–REVISED MAY 2014
www.ti.com.cn
9.2.3 Application Curves
The performance shown in the following graphs was obtained using the circuit shown in Figure 10 and the
external components shown in Table 3 and Table 4. The output voltage settings for these measurements were
VPOS = 4.6 V and VNEG = –4 V.
100
V
(CTRL)
90
80
70
V
POS
60
50
40
V
NEG
30
VI = 4.3 V
VI = 3.7 V
VI = 3.2 V
VI = 2.9 V
20
10
0
L1 = L2 = Coilcraft XFL4020−4R7ML
50 100 150 200
I
IN
0
250
300
Output Current (mA)
G000
Time = 2 ms/div
Figure 12. Start-Up Waveforms
Figure 11. Efficiency vs. Output Current
V
POS
V
V
POS
(SWP)
V
(SWP)
I
(L3)
I
(L3)
Time = 400 ns/div
Time = 400 ns/div
Figure 14. VPOS Switch Voltage, Inductor Current and
Output Voltage Ripple (IO = 300 mA)
Figure 13. VPOS Switch Voltage, Inductor Current and
Output Voltage Ripple (IO = 100 mA)
V
V
NEG
NEG
V
(SWN)
V
(SWN)
I
(L1)
I
(L1)
Time = 400 ns/div
Time = 400 ns/div
Figure 15. VNEG Switch Voltage, Inductor Current and
Output Voltage Ripple (IO = 100 mA)
Figure 16. VNEG Switch Voltage, Inductor Current and
Output Voltage Ripple (IO = 300 mA)
14
Copyright © 2012–2014, Texas Instruments Incorporated
TPS65631
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ZHCSCJ0E –SEPTEMBER 2012–REVISED MAY 2014
4.610
−4.390
−4.395
−4.400
−4.405
−4.410
−4.415
−4.420
4.605
4.600
4.595
4.590
4.585
TJ = –40°C
TJ = 25°C
TJ = 85°C
TJ = –40°C
TJ = 25°C
IOUT = 100 mA
IOUT = 100 mA
3.1 3.3
TJ = 85°C
4.580
2.9
3.1
3.3
3.5
3.7
3.9
4.1
4.3
4.5
2.9
3.5
3.7
3.9
4.1
4.3 4.5
Input Voltage (V)
Input Voltage (V)
G000
G000
Figure 17. Boost Converter Line Regulation
Figure 18. Inverting Buck-Boost Converter Line Regulation
4.610
4.605
4.600
4.595
4.590
4.585
−4.390
−4.395
−4.400
−4.405
−4.410
TJ = –40°C
TJ = 25°C
TJ = 85°C
TJ = –40°C
TJ = 25°C
TJ = 85°C
−4.415
VI = 3.7 V
50
VI = 3.7 V
50
4.580
0
−4.420
100
150
200
250
300
0
100
150
200
250 300
Output Current (mA)
Output Current (mA)
G000
G000
Figure 19. Boost Converter Load Regulation
Figure 20. Inverting Buck-Boost Converter Load
Regulation
VI
IPOS
VPOS
VPOS
VNEG
Time = 40 µs/div
Time = 200 µs/div
Figure 22. Boost Converter Load Transient Response
Figure 21. Line Transient Response
Copyright © 2012–2014, Texas Instruments Incorporated
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TPS65631
ZHCSCJ0E –SEPTEMBER 2012–REVISED MAY 2014
www.ti.com.cn
INEG
VNEG
Time = 400 µs/div
Figure 23. Inverting Buck-Boost Converter Load Transient Response
10 Power Supply Recommendations
The TPS65631 is designed to operate from an input voltage supply range between 2.9 V and 4.5 V. If the input
supply is located more than a few centimeters from the TPS65631 additional bulk capacitance may be required.
The 2×10 µF shown in the schematics in this data sheet are a typical choice for this function.
16
Copyright © 2012–2014, Texas Instruments Incorporated
TPS65631
www.ti.com.cn
ZHCSCJ0E –SEPTEMBER 2012–REVISED MAY 2014
11 Layout
11.1 Layout Guidelines
No PCB layout is perfect, and compromises are always necessary. However, following the basic principles listed
below (in order of importance) should go a long way to achieving good performance:
•
Route switching currents on the top layer using short, wide traces. Do not route these signals through vias,
which have relatively high parasitic inductance and resistance.
•
•
•
•
•
•
•
Place C1 as close as possible to pin 12.
Place C2 as close as possible to pin 3.
Place C3 as close as possible to pin 9.
Place L1 as close as possible to pin 1.
Place L2 as close as possible to pin 10.
Use the thermal pad to join GND, AGND and PGND.
Connect the FBS pin directly to the positive pin of C2, that is, keep this connection separate from the
connection between OUTP and C2.
•
Use a copper pour on layer 2 as a thermal spreader and connect the thermal pad to it using a number of
thermal vias.
Figure 24 illustrates how a PCB layout following the above principles may be realized in practice.
11.2 Layout Example
Figure 24 shows the above principles implemented for the circuit of Figure 10.
L1
C1
C2
SWP
PGND
OUTP
FBS
1
2
3
4
5
6
12 PVIN
11 AVIN
10 SWN
L2
9
8
7
OUTN
CT
C3
C4
AGND
GND
CTRL
Via to signal layer on internal or bottom layer.
Thermal via to copper pour on internal or bottom layer.
Figure 24. PCB Layout Example
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www.ti.com.cn
12 器件和文档支持
12.1 器件支持
12.1.1 第三方产品免责声明
TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此类
产品或服务单独或与任何 TI 产品或服务一起的表示或认可。
12.2 Trademarks
All trademarks are the property of their respective owners.
12.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms and definitions.
13 机械封装和可订购信息
以下页中包括机械封装和可订购信息。 这些信息是针对指定器件可提供的最新数据。 这些数据会在无通知且不对
本文档进行修订的情况下发生改变。 欲获得该数据表的浏览器版本，请查阅左侧的导航栏。
18
Copyright © 2012–2014, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS65631DPDR
ACTIVE
WSON
DPD
12
3000 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
SDS
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Apr-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS65631DPDR
WSON
DPD
12
3000
330.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Apr-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
WSON DPD 12
SPQ
Length (mm) Width (mm) Height (mm)
346.0 346.0 33.0
TPS65631DPDR
3000
Pack Materials-Page 2
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