TPS79533DCQR [TI]
ULTRALOW-NOISE, HIGH PSRR, FAST RF 500-mA LOW-DROPOUT LINEAR REGULATORS; 超低噪声，高PSRR ，快速射频500 mA低压降线性稳压器
| 型号： | TPS79533DCQR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | ULTRALOW-NOISE, HIGH PSRR, FAST RF 500-mA LOW-DROPOUT LINEAR REGULATORS |
| 文件： | 总15页 (文件大小：422K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS79501, TPS79516
TPS79518, TPS79525
TPS79530, TPS79533
www.ti.com
SLVS350C–OCTOBER 2002–REVISED JANUARY 2005
ULTRALOW-NOISE, HIGH PSRR, FAST RF 500-mA
LOW-DROPOUT LINEAR REGULATORS
FEATURES
DESCRIPTION
•
500-mA Low-Dropout Regulator With Enable
The TPS795xx family of low-dropout (LDO)
low-power linear voltage regulators features high
power-supply rejection ratio (PSRR), ultralow noise,
fast start-up, and excellent line and load transient
responses in a small outline, SOT223-6, package.
Each device in the family is stable with a small 1-µF
ceramic capacitor on the output. The family uses an
advanced, proprietary BiCMOS fabrication process to
yield extremely low dropout voltages (for example,
110 mV at 500 mA). Each device achieves fast
start-up times (approximately 50 µs with a 0.001-µF
bypass capacitor) while consuming very low quiesc-
ent current (265 µA typical). Moreover, when the
device is placed in standby mode, the supply current
is reduced to less than 1 µA. The TPS79530 exhibits
approximately 33 µVRMS of output voltage noise at
3.0 V output with a 0.1-µF bypass capacitor. Appli-
cations with analog components that are noise sensi-
tive, such as portable RF electronics, benefit from the
high PSRR and low noise features, as well as the fast
response time.
•
Available in 1.6-V, 1.8-V, 2.5-V, 3-V, 3.3-V, and
Adjustable (1.2-V to 5.5-V)
•
•
•
•
•
•
High PSRR (50 dB at 10 kHz)
Ultralow Noise (33 µVRMS, TPS79530)
Fast Start-Up Time (50 µs)
Stable With a 1-µF Ceramic Capacitor
Excellent Load/Line Transient Response
Very Low Dropout Voltage (110 mV at Full
Load, TPS79530)
•
6-Pin SOT223-6 Package
APPLICATIONS
•
•
•
•
•
RF: VCOs, Receivers, ADCs
Audio
Bluetooth™, Wireless LAN
Cellular and Cordless Telephones
Handheld Organizers, PDAs
TPS79530
TPS79530
RIPPLE REJECTION
vs
OUTPUT SPECTRAL NOISE DENSITY
vs
FREQUENCY
FREQUENCY
80
0.5
V
C
C
= 4 V
= 10 µF
IN
V
= 5.5 V
IN
DCQ PACKAGE
SOT223-6
(TOP VIEW)
70
OUT
C
C
= 2.2 µF
OUT
= 0.1 µF
= 0.01 µF
NR
I
= 1 mA
0.4
0.3
OUT
NR
60
1
2
3
4
5
50
40
30
EN
IN
GND
OUT
NR/FB
I
= 1 mA
OUT
6
GND
I
= 500 mA
OUT
0.2
20
10
0
I
= 0.5 A
OUT
0.1
0
1
10
100
1 k 10 k 100 k 1 M 10 M
100
1 k
Frequency (Hz)
10 k
100 k
Frequency (Hz)
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Bluetooth is a trademark of Bluetooth SIG, Inc.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2002–2005, Texas Instruments Incorporated
TPS79501, TPS79516
TPS79518, TPS79525
TPS79530, TPS79533
www.ti.com
SLVS350C–OCTOBER 2002–REVISED JANUARY 2005
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated
circuits be handled with appropriate precautions. Failure to observe proper handling and installation
procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision
integrated circuits may be more susceptible to damage because very small parametric changes could
cause the device not to meet its published specifications.
AVAILABLE OPTIONS
TRANSPORT MEDIA,
PRODUCT
VOLTAGE
PACKAGE
TJ
SYMBOL
PART NUMBER
QUANTITY
TPS79501DCQ
TPS79501DCQR
TPS79516DCQ
TPS79516DCQR
TPS79518DCQ
TPS79518DCQR
TPS79525DCQ
TPS79525DCQR
TPS79530DCQ
TPS79530DCQR
TPS79533DCQ
TPS79533DCQR
Tube, 78
TPS79501
1.2 to 5.5 V
PS79501
Tape and Reel, 2500
Tube, 78
TPS79516
TPS79518
TPS79525
TPS79530
TPS79533
1.6 V
1.8 V
2.5 V
3 V
PS79516
PS79518
PS79525
PS79530
PS79533
Tape and Reel, 2500
Tube, 78
Tape and Reel, 2500
Tube, 78
SOT223-6
-40°C to 125°C
Tape and Reel, 2500
Tube, 78
Tape and Reel, 2500
Tube, 78
3.3 V
Tape and Reel, 2500
ABSOLUTE MAXIMUM RATINGS
over operating temperature (unless otherwise noted)(1)
UNIT
-0.3 V to 6 V
-0.3 V to VIN + 0.3 V
6 V
VIN range
VEN range
VOUT range
Peak output current
ESD rating, HBM
Internally limited
2 kV
ESD rating, CDM
500 V
Continuous total power dissipation
Junction temperature range, TJ
Storage temperature range, Tstg
See Dissipation Rating Table
-40°C to 150°C
-65°C to 150°C
(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not implied.
DISSIPATION RATING TABLE
PACKAGE
BOARD
RΘJC
RΘJA
SOT223
Low K(1)
15°C/W
53°C/W
(1) The JEDEC low-K (1s) board design used to derive this data was a 3-inch × 3-inch (7.5 cm × 7.5cm), two-layer board with 2-ounce
copper traces on top of the board.
2
TPS79501, TPS79516
TPS79518, TPS79525
TPS79530, TPS79533
www.ti.com
SLVS350C–OCTOBER 2002–REVISED JANUARY 2005
ELECTRICAL CHARACTERISTICS
Over recommended operating temperature range (TJ = -40°C to 125°C), VEN = VIN, VIN = VOUT(nom) + 1 V, IOUT = 1mA,
COUT = 10µF, CNR = 0.01 µF, unless otherwise noted. Typical values are at 25°C.
PARAMETER
TEST CONDITIONS
MIN TYP
MAX
5.5
UNIT
V
(1)
Input voltage, VIN
2.7
0
Continuous output current, IOUT
Output voltage
500
mA
TPS79516
TPS79518
TPS79525
TPS79530
TPS79533
0 µA< IOUT < 500 mA,
2.6 V < VIN < 5.5 V
2.8 V < VIN < 5.5 V
3.5 V < VIN < 5.5 V
4 V < VIN < 5.5 V
4.3 V < VIN < 5.5 V
1.568
1.6
1.8
1.632
1.836
2.55
3.06
3.366
0.12
0 µA< IOUT < 500 mA,
0 µA< IOUT < 500 mA,
0 µA< IOUT < 500 mA,
0 µA< IOUT < 500 mA,
VOUT + 1 V < VIN ≤ 5.5 V
0 µA < IOUT < 500 mA,
IOUT = 500 mA
1.764
2.45
2.5
V
2.94
3.0
3.234
3.3
(1)
Output voltage line regulation (∆VOUT%/∆VIN
)
0.05
3
%/V
mV
Load regulation (∆VOUT%/∆IOUT
)
TJ = 25°C
Dropout voltage(2)
VIN = VOUT(nom) - 0.1 V
TPS79530
TPS79533
110
105
2.8
170
160
4.2
385
1
mV
IOUT = 500 mA
Output current limit
Ground pin current
Shutdown current(3)
FB pin current
VOUT = 0 V
2.4
A
0 µA< IOUT < 500 mA
VEN = 0 V,
265
0.07
µA
µA
µA
2.7 V < VIN < 5.5 V
VFB = 1.8 V
1
f = 100 Hz,
IOUT = 10 mA
59
58
50
39
46
41
35
33
50
75
110
f = 100 Hz,
IOUT = 500 mA
IOUT = 500 mA
IOUT = 500 mA
CNR = 0.001 µF
CNR = 0.0047 µF
CNR = 0.01 µF
CNR = 0.1 µF
Power supply ripple rejection TPS79530
dB
f = 10 kHz,
f = 100 kHz,
BW = 100 Hz to 100 kHz,
IOUT = 500 mA
Output noise voltage (TPS79530)
Time, start-up (TPS79530)
µVRMS
CNR = 0.001 µF
CNR = 0.0047 µF
CNR = 0.01 µF
RL = 6 Ω, COUT = 1 µF
µs
High-level enable input voltage
Low-level enable input voltage
EN pin current
2.7 V < VIN < 5.5 V
2.7 V < VIN < 5.5 V
VEN = 0 V
1.7
VIN
0.7
1
V
V
1
µA
V
UVLO threshold
VCC rising
2.25
2.65
UVLO hysteresis
100
mV
(1) Minimum VIN is 2.7 V or VOUT + VDO, whichever is greater.
(2) Dropout is not measured for the TPS79501 and TPS79525 since minimum VIN = 2.7 V.
(3) For adjustable version, this applies only after VIN is applied; then VEN transitions high to low.
3
TPS79501, TPS79516
TPS79518, TPS79525
TPS79530, TPS79533
www.ti.com
SLVS350C–OCTOBER 2002–REVISED JANUARY 2005
FUNCTIONAL BLOCK DIAGRAM—ADJUSTABLE VERSION
IN
OUT
Current
Sense
UVLO
SHUTDOWN
ILIM
R
1
_
GND
EN
+
FB
UVLO
R
2
Thermal
Shutdown
Quickstart
External to
the Device
Bandgap
Reference
1.225 V
250 kΩ
V
REF
V
IN
FUNCTIONAL BLOCK DIAGRAM—FIXED VERSION
IN
OUT
UVLO
Current
Sense
GND
EN
SHUTDOWN
ILIM
R
1
_
+
UVLO
Thermal
Shutdown
R
2
Quickstart
R = 40k
2
Bandgap
Reference
1.225 V
250 kΩ
V
REF
V
IN
NR
Table 1. Terminal Functions
TERMINAL
ADJ
DESCRIPTION
NAME
FIXED
NR
N/A
5
Connecting an external capacitor to this pin bypasses noise generated by the internal bandgap. This
improves power-supply rejection and reduces output noise.
EN
1
1
Driving the enable pin (EN) high turns on the regulator. Driving this pin low puts the regulator into shutdown
mode. EN can be connected to IN if not used.
FB
5
N/A
This terminal is the feedback input voltage for the adjustable device.
GND
IN
3, TAB
3, TAB Regulator ground
2
4
2
4
Unregulated input to the device.
Output of the regulator.
OUT
4
TPS79501, TPS79516
TPS79518, TPS79525
TPS79530, TPS79533
www.ti.com
SLVS350C–OCTOBER 2002–REVISED JANUARY 2005
TYPICAL CHARACTERISTICS
TPS79530
OUTPUT VOLTAGE
vs
TPS79530
OUTPUT VOLTAGE
vs
TPS79530
GROUND CURRENT
vs
OUTPUT CURRENT
JUNCTION TEMPERATURE
JUNCTION TEMPERATURE
3.005
3.02
3.01
276
V
C
= 4 V
V
= 4 V
IN
IN
274
272
270
268
266
264
= 10 µF
C
OUT
= 10 µF
OUT
3
I
= 1 mA
OUT
2.995
I
= 1 mA
OUT
2.99
2.985
2.98
3
I
= 0.5 A
OUT
I
= 0.5 A
OUT
2.99
2.98
2.975
2.97
262
260
0
0.1
0.2
0.3
(mA)
0.4
0.5
−40 −25 −10 5 20 35 50 65 80 95 110 125
(°C)
−40 −25−10 5 20 35 50 65 80 95 110 125
I
T
J
(°C)
OUT
T
J
Figure 1.
Figure 2.
Figure 3.
TPS79530
TPS79530
TPS79530
OUTPUT SPECTRAL NOISE DEN-
OUTPUT SPECTRAL NOISE DEN-
OUTPUT SPECTRAL NOISE DEN-
SITY
vs
FREQUENCY
SITY
vs
FREQUENCY
SITY
vs
FREQUENCY
2.5
2
0.6
0.5
0.4
0.3
V
= 5.5 V
= 500 mA
IN
V
C
C
= 5.5 V
V
C
C
= 5.5 V
IN
IN
I
OUT
= 2.2 µF
= 10 µF
OUT
= 0.1 µF
OUT
= 0.1 µF
0.5
0.4
0.3
0.2
0.1
0
C
= 10 µF
OUT
NR
NR
C
NR
= 0.001 µF
I
= 1 mA
OUT
C
NR
= 0.0047 µF
I
= 1 mA
OUT
1.5
1
C
NR
= 0.01 µF
0.2
C
= 0.1 µF
NR
I
= 0.5 A
OUT
I
= 0.5 A
OUT
0.5
0
0.1
0
100
1 k
10 k
100 k
100
1 k
10 k
100 k
100
1 k
10 k
100 k
Frequency (Hz)
Frequency (Hz)
Frequency (Hz)
Figure 4.
Figure 5.
Figure 6.
5
TPS79501, TPS79516
TPS79518, TPS79525
TPS79530, TPS79533
www.ti.com
SLVS350C–OCTOBER 2002–REVISED JANUARY 2005
TYPICAL CHARACTERISTICS (continued)
TPS79530
TPS79530
DROPOUT VOLTAGE
vs
ROOT MEAN SQUARED OUTPUT NOISE
vs
CNR
JUNCTION TEMPERATURE
50
175
150
125
100
75
V
C
= 2.9 V
= 10 µF
OUT
= 500 mA
IN
I
C
= 500 mA
OUT
= 10 µF
OUT
I
OUT
40
30
20
50
10
0
25
0
BW = 100 Hz to 100 kHz
−40−25−10
5
20 35 50 65 80 95 110 125
(°C)
0.001
0.01
0.1
0.0047
T
J
C
NR
(µF)
Figure 7.
Figure 8.
TPS79530
TPS79530
RIPPLE REJECTION
vs
TPS79530
RIPPLE REJECTION
vs
RIPPLE REJECTION
vs
FREQUENCY
FREQUENCY
FREQUENCY
80
70
60
50
40
30
20
80
80
70
60
50
40
30
20
V
C
C
= 4 V
V
C
C
= 4 V
V
C
C
= 4 V
IN
IN
IN
= 2.2 µF
= 10 µF
= 10 µF
OUT
= 0.01 µF
70
OUT
= 0.1 µF
OUT
= 0.01 µF
NR
NR
NR
I
= 1 mA
OUT
I
= 1 mA
OUT
I
= 1 mA
60
50
40
30
OUT
I
= 500 mA
I
= 500 mA
OUT
OUT
I
= 500 mA
OUT
20
10
0
10
0
10
0
1
10
100 1 k 10 k 100 k 1 M 10 M
1
10
100 1 k 10 k 100 k 1 M 10 M
1
10
100
1 k 10 k 100 k 1 M 10 M
Frequency (Hz)
Frequency (Hz)
Frequency (Hz)
Figure 9.
Figure 10.
Figure 11.
TPS79530
RIPPLE REJECTION
vs
TPS79530
START-UP TIME
TPS79518
LINE TRANSIENT RESPONSE
FREQUENCY
80
70
60
50
40
30
20
10
0
3
20
C
= 0.001 µF
V
C
C
= 4 V
NR
IN
2.75
2.50
2.25
2
= 2.2 µF
OUT
= 0.1 µF
10
0
NR
C
= 0.0047 µF
NR
I
= 1 mA
OUT
C
= 0.01 µF
NR
Enable
1.75
1.50
1.25
1
−10
−20
4
C
I
= 10 µF, C = 0.01 µF,
NR
OUT
= 0.5 A, dv/dt = 1 V/µs
OUT
I
= 500 mA
OUT
0.75
0.50
0.25
0
V
= 4 V
= 10 µF
= 0.5 A
IN
3
2
C
OUT
I
OUT
0
100
200
300
400
500 600
0
50
100
150
200
1
10
100 1 k 10 k 100 k 1 M 10 M
Frequency (Hz)
t (µs)
t (µs)
Figure 12.
Figure 13.
Figure 14.
6
TPS79501, TPS79516
TPS79518, TPS79525
TPS79530, TPS79533
www.ti.com
SLVS350C–OCTOBER 2002–REVISED JANUARY 2005
TYPICAL CHARACTERISTICS (continued)
TPS79530
LINE TRANSIENT RESPONSE
TPS79530
LOAD TRANSIENT RESPONSE
TPS79525
POWER UP/POWER DOWN
4.5
30
20
10
0
60
40
20
V
R
= 2.5 V,
OUT
= 10 Ω
4
L
3.5
V
IN
3
0
−20
−40
−60
2.5
−10
−20
5
2
1.5
C
I
= 10 µF, C = 0.01 µF,
NR
OUT
= 0.5 A, dv/dt = 1 V/µs
C
L
= 10 µF, C = 0.01 µF,
NR
V
OUT
= 3.8 V, dv/dt = 0.5 A/µs
OUT
1
OUT
V
0.5
0.5
4
3
0
0
−0.5
−0.5
0
200
400
t (µs)
600
800
1000
0
1
2
3
4
5
6
7
8
9
10
0
50
100
t (µs)
150
200
200 µs/Div
Figure 15.
Figure 16.
Figure 17.
TPS79530
TYPICAL REGIONS OF STABILITY
TPS79530
TPS79501
EQUIVALENT SERIES RESISTANCE
DROPOUT VOLTAGE
vs
DROPOUT VOLTAGE
vs
(ESR)
vs
OUTPUT CURRENT
OUTPUT CURRENT
INPUT VOLTAGE
180
160
140
120
100
80
200
150
100
100
C
OUT
= 1 µF
C
C
= 10 µF,
= 0.01 µF,
= 50 mA
OUT
NR
I
OUT
Region of
Instability
10
1
T
= 125°C
J
T
J
= 125°C
T
J
= 25°C
T
= 25°C
J
60
Region of Stability
T
= −40°C
J
0.1
50
0
T
J
= −40°C
40
20
0.01
0
0
100
200 300
I (mA)
OUT
400
500
2.5
3
3.5
4
4.5
5
0
100
200
300
400
500
V
(V)
IN
I
(mA)
OUT
Figure 18.
Figure 19.
Figure 20.
7
TPS79501, TPS79516
TPS79518, TPS79525
TPS79530, TPS79533
www.ti.com
SLVS350C–OCTOBER 2002–REVISED JANUARY 2005
TYPICAL CHARACTERISTICS (continued)
TPS79530
TYPICAL REGIONS OF STABILITY
EQUIVALENT SERIES RESISTANCE
(ESR)
TPS79530
TYPICAL REGIONS OF STABILITY
EQUIVALENT SERIES RESISTANCE
(ESR)
vs
vs
OUTPUT CURRENT
OUTPUT CURRENT
100
100
C
OUT
= 10 µF
C
OUT
= 2.2 µF
Region of
Instability
10
10
1
Region of
Instability
1
Region of Stability
Region of Stability
0.1
0.1
0.01
0.01
0
100
200
300
(A)
400
500
1
10
100
1000
I
I
(mA)
OUT
OUT
Figure 21.
Figure 22.
8
TPS79501, TPS79516
TPS79518, TPS79525
TPS79530, TPS79533
www.ti.com
SLVS350C–OCTOBER 2002–REVISED JANUARY 2005
APPLICATION INFORMATION
because any leakage current creates an IR drop
across the internal resistor thus creating an output
error. Therefore, the bypass capacitor must have
minimal leakage current. The bypass capacitor
should be no more than 0.1-µF in order to ensure that
it is fully charged during the quickstart time provided
by the internal switch shown in the functional block
diagram.
The TPS795xx family of low-dropout (LDO) regulators
has been optimized for use in noise-sensitive equip-
ment. The device features extremely low dropout
voltages, high PSRR, ultralow output noise, low
quiescent current (265 µA typically), and enable input
to reduce supply currents to less than 1 µA when the
regulator is turned off.
A typical application circuit is shown in Figure 23.
For example, the TPS79530 exhibits only 33 µVRMS
of output voltage noise using a 0.1-µF ceramic
bypass capacitor and a 10-µF ceramic output capaci-
tor. Note that the output starts up slower as the
bypass capacitance increases due to the RC time
constant at the bypass pin that is created by the
internal 250-kΩ resistor and external capacitor.
VIN
VOUT
IN
OUT
TPS795xx
GND
µ
1 µF
2.2 F
EN
NR
µ
0.01 F
Figure 23. Typical Application Circuit
Board Layout Recommendation to Improve
PSRR and Noise Performance
External Capacitor Requirements
To improve ac measurements like PSRR, output
noise, and transient response, it is recommended that
the board be designed with separate ground planes
for VIN and VOUT, with each ground plane connected
only at the ground pin of the device. In addition, the
ground connection for the bypass capacitor should
connect directly to the ground pin of the device.
A 1-µF or larger ceramic input bypass capacitor,
connected between IN and GND and located close to
the TPS795xx, is required for stability and improves
transient response, noise rejection, and ripple rejec-
tion. A higher-value input capacitor may be necessary
if large, fast-rise-time load transients are anticipated
and the device is located several inches from the
power source.
Regulator Mounting
Like most low dropout regulators, the TPS795xx
requires an output capacitor connected between OUT
and GND to stabilize the internal control loop. The
minimum recommended capacitance is 1 µF. Any
1 µF or larger ceramic capacitor is suitable.
The tab of the SOT223-6 package is electrically
connected to ground. For best thermal performance,
the tab of the surface-mount version should be
soldered directly to a circuit-board copper area.
Increasing the copper area improves heat dissipation.
The internal voltage reference is a key source of
noise in an LDO regulator. The TPS795xx has an NR
pin which is connected to the voltage reference
through a 250-kΩ internal resistor. The 250-kΩ
internal resistor, in conjunction with an external by-
pass capacitor connected to the NR pin, creates a
low pass filter to reduce the voltage reference noise
and, therefore, the noise at the regulator output. In
order for the regulator to operate properly, the current
flow out of the NR pin must be at a minimum,
Solder pad footprint recommendations for the devices
are presented in an application bulletin Solder Pad
Recommendations for Surface-Mount Devices, litera-
ture number AB-132, available from the TI web site
(www.ti.com).
9
TPS79501, TPS79516
TPS79518, TPS79525
TPS79530, TPS79533
www.ti.com
SLVS350C–OCTOBER 2002–REVISED JANUARY 2005
–7
(3 x 10 ) x (R1 ) R2)
Programming the TPS79501 Adjustable LDO
Regulator
C1 +
(R1 x R2)
(3)
The output voltage of the TPS79501 adjustable
regulator is programmed using an external resistor
divider as shown in Figure 24. The output voltage is
calculated using Equation 1:
The suggested value of this capacitor for several
resistor ratios is shown in the table below. If this
capacitor is not used (such as in a unity-gain con-
figuration) then the minimum recommended output
capacitor is 2.2 µF instead of 1 µF.
R1
R2
ǒ1 ) Ǔ
VOUT + VREF
(1)
Regulator Protection
where:
The TPS795xx PMOS-pass transistor has a built-in
back diode that conducts reverse current when the
input voltage drops below the output voltage (e.g.,
during power down). Current is conducted from the
output to the input and is not internally limited. If
extended reverse voltage operation is anticipated,
external limiting might be appropriate.
•
VREF = 1.2246 V typ (the internal reference
voltage)
Resistors R1 and R2 should be chosen for approxi-
mately 40-µA divider current. Lower value resistors
can be used for improved noise performance, but the
device wastes more power. Higher values should be
avoided, as leakage current at FB increases the
output voltage error. The recommended design pro-
cedure is to choose R2 = 30.1 kΩ to set the divider
current at 40 µA, C1 = 15 pF for stability, and then
calculate R1 using Equation 2:
The TPS795xx features internal current limiting and
thermal protection. During normal operation, the
TPS795xx limits output current to approximately 2.8
A. When current limiting engages, the output voltage
scales back linearly until the overcurrent condition
ends. While current limiting is designed to prevent
gross device failure, care should be taken not to
exceed the power dissipation ratings of the package.
If the temperature of the device exceeds approxi-
mately 165°C, thermal-protection circuitry shuts it
down. Once the device has cooled down to below
approximately 140°C, regulator operation resumes.
VOUT
R1 + ǒ Ǔ
In order to improve the stability of the adjustable
version, it is suggested that a small compensation
capacitor be placed between OUT and FB. The
approximate value of this capacitor can be calculated
as Equation 3:
* 1 R2
VREF
(2)
OUTPUT VOLTAGE
PROGRAMMING GUIDE
VIN
VOUT
IN
OUT
TPS79501
R1
R2
µ
C1
OUTPUT
VOLTAGE
1
F
EN
NR
1 µF
R1
R2
C1
GND
F
FB
1.8 V
3.6V
14.0 kΩ 30.1 kΩ 22 pF
61.9 kΩ 30.1 kΩ 15 pF
µ
0.01
Figure 24. TPS79501 Adjustable LDO Regulator Programming
10
TPS79501, TPS79516
TPS79518, TPS79525
TPS79530, TPS79533
www.ti.com
SLVS350C–OCTOBER 2002–REVISED JANUARY 2005
THERMAL INFORMATION
T
A
The amount of heat that an LDO linear regulator
generates is directly proportional to the amount of
power it dissipates during operation. All integrated
circuits have a maximum allowable junction tempera-
ture (TJ(max)) above which normal operation is not
J
R
θ
JC
CIRCUIT BOARD COPPER AREA
C
T
C
B
assured.
A
system designer must design the
B
R
θ
θ
CS
operating environment so that the operating junction
temperature (TJ) does not exceed the maximum
junction temperature (TJ(max)). The two main environ-
mental variables that a designer can use to improve
thermal performance are air flow and external
heatsinks. The purpose of this information is to aid
the designer in determining the proper operating
environment for a linear regulator that is operating at
a specific power level.
A
C
R
SA
SOT223 Package
(a)
T
A
Figure 25. Thermal Resistances
In general, the maximum expected power (PD(max)
)
consumed by a linear regulator is computed as
Equation 4:
Equation 5 summarizes the computation:
ǒ
Ǔ
TJ + TA ) PD max RθJC ) RθCS ) RθSA
(5)
ǒ
Ǔ
PD max + VIN(avg) * VOUT(avg) IOUT(avg) ) VI(avg) I(Q)
The RΘJC is specific to each regulator as determined
by its package, lead frame, and die size provided in
the regulator's data sheet. The RΘSA is a function of
the type and size of heatsink. For example, black
body radiator type heatsinks can have RΘCS values
ranging from 5°C/W for very large heatsinks to
50°C/W for very small heatsinks. The RΘCS is a
function of how the package is attached to the
heatsink. For example, if a thermal compound is used
to attach a heatsink to a SOT223 package, RΘCS of
1°C/W is reasonable.
(4)
where:
•
•
•
•
VIN(avg) is the average input voltage
VOUT(avg) is the average output voltage
IOUT(avg) is the average output current
I(Q) is the quiescent current
For most TI LDO regulators, the quiescent current is
insignificant compared to the average output current;
therefore, the term VIN(avg) x I(Q) can be neglected.
The operating junction temperature is computed by
adding the ambient temperature (TA) and the in-
crease in temperature due to the regulator's power
dissipation. The temperature rise is computed by
multiplying the maximum expected power dissipation
by the sum of the thermal resistances between the
junction and the case (RΘJC), the case to heatsink
(RΘCS), and the heatsink to ambient (RΘSA). Thermal
resistances are measures of how effectively an object
dissipates heat. Typically, the larger the device, the
more surface area available for power dissipation and
the lower the object's thermal resistance.
Even if no external black body radiator type heatsink
is attached to the package, the board on which the
regulator is mounted provides some heatsinking
through the pin solder connections. Some packages,
like the DDPAK and SOT223 packages, use a copper
plane underneath the package or the circuit board's
ground plane for additional heatsinking to improve
their thermal performance. Computer aided thermal
modeling can be used to compute very accurate
approximations of an integrated circuit's thermal per-
formance in different operating environments (e.g.,
different types of circuit boards, different types and
sizes of heatsinks, and different air flows, etc.). Using
these models, the three thermal resistances can be
combined into one thermal resistance between junc-
tion and ambient (RΘJA). This RΘJA is valid only for the
specific operating environment used in the computer
model.
Figure 25 illustrates these thermal resistances for (a)
a SOT223 package mounted in a JEDEC low-K
board.
11
TPS79501, TPS79516
TPS79518, TPS79525
TPS79530, TPS79533
www.ti.com
SLVS350C–OCTOBER 2002–REVISED JANUARY 2005
Equation 5 simplifies into Equation 6:
TJ + TA ) PD max RθJA
180
160
(6)
(7)
No Air Flow
Rearranging Equation 6 gives Equation 7:
TJ TA
PD max
140
120
100
RθJA
+
Using Equation 6 and the computer model generated
curves shown in Figure 26, a designer can quickly
compute the required heatsink thermal resist-
ance/board area for a given ambient temperature,
power dissipation, and operating environment.
80
60
40
SOT223 Power Dissipation
The SOT223 package provides an effective means of
managing power dissipation in surface mount appli-
cations. The SOT223 package dimensions are pro-
vided in the Mechanical Data section at the end of
the data sheet. The addition of a copper plane
directly underneath the SOT223 package enhances
the thermal performance of the package.
20
0
0.1
1
10
2
PCB Copper Area - in
Figure 26. SOT223 Thermal Resistance vs PCB
Copper Area
To illustrate, the TPS79525 in a SOT223 package
was chosen. For this example, the average input
voltage is 3.3 V, the output voltage is 2.5 V, the
average output current is 1 A, the ambient tempera-
ture 55°C, no air flow is present, and the operating
environment is the same as documented below.
Neglecting the quiescent current, the maximum aver-
age power is Equation 8:
From the data in Figure 26 and rearranging equation
6, the maximum power dissipation for a different
ground plane area and a specific ambient tempera-
ture can be computed (see Figure 27).
6
T
A
= 25°C
(
)
PD max
3.3
2.5 V
1A
800mW
(8)
5
4
Substituting TJmax for TJ into Equation 4 gives
Equation 9:
R
θJA max + (125 * 55)°Cń800mW + 87.5°CńW
(9)
2
4 in PCB Area
3
2
From Figure 26, RΘJA vs PCB Copper Area, the
ground plane needs to be 0.55 in2 for the part to
dissipate 800 mW. The operating environment used
to construct Figure 26 consisted of a board with 1 oz.
copper planes. The package is soldered to a 1 oz.
copper pad on the top of the board. The pad is tied
through thermal vias to the 1 oz. ground plane.
2
0.5 in PCB Area
1
0
0
25
50
75
100
125
150
T
A
(°C)
Figure 27. SOT223 Maximum Power Dissipation
vs Ambient Temperature
12
PACKAGE OPTION ADDENDUM
www.ti.com
11-Jan-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
SOP
SOP
SOP
SOP
SOP
SOP
SOP
SOP
SOP
SOP
SOP
SOP
Drawing
DCQ
DCQ
DCQ
DCQ
DCQ
DCQ
DCQ
DCQ
DCQ
DCQ
DCQ
DCQ
TPS79501DCQ
TPS79501DCQR
TPS79516DCQ
TPS79516DCQR
TPS79518DCQ
TPS79518DCQR
TPS79525DCQ
TPS79525DCQR
TPS79530DCQ
TPS79530DCQR
TPS79533DCQ
TPS79533DCQR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
6
6
6
6
6
6
6
6
6
6
6
6
78
2500
78
None
None
None
None
None
None
None
None
None
None
None
None
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Level-3-235C-168 HR
Level-3-235C-168 HR
Level-3-235C-168 HR
Level-3-235C-168 HR
Level-3-235C-168 HR
Level-3-235C-168 HR
Level-3-235C-168 HR
Level-3-235C-168 HR
Level-3-235C-168 HR
Level-3-235C-168 HR
2500
78
2500
78
2500
78
2500
78
2500
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional
product content details.
None: Not yet available Lead (Pb-Free).
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens,
including bromine (Br) or antimony (Sb) above 0.1% of total product weight.
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
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In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
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Addendum-Page 1
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