TPS7H1210MRGWTSEP [TI]

采用增强型航天塑料的耐辐射、-3V 至 -16.5V 输入、1A 负电压线性稳压器 | RGW | 20 | -55 to 125;


型号：	TPS7H1210MRGWTSEP
厂家：	TEXAS INSTRUMENTS
描述：	采用增强型航天塑料的耐辐射、-3V 至 -16.5V 输入、1A 负电压线性稳压器 \| RGW \| 20 \| -55 to 125 稳压器
文件：	总29页 (文件大小：2610K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TPS7H1210-SEP

ZHCSNP8 –NOVEMBER 2021

采用空间增强型塑料的TPS7H1210-SEP –16.5-V、1A 负线性稳压器

1 特性

3 说明

• 提供供应商项目图，VID V62/21616

• 电离辐射总剂量(TID) 为30krad(Si)

TPS7H1210-SEP 是一款低噪音、高 PSRR 负电压线

性稳压器，可提供最大1A 的负载。

– 每个晶圆批次的TID RLAT（辐射批次验收测

试）：20krad (Si)

• 确定了单粒子效应(SEE)

该稳压器装有一个 CMOS 逻辑电平兼容使能引脚

(EN)，此引脚允许用户定制电源管理方案。其他特性

包括内置电流值限制和热关断以在故障情况下保护此器

件和系统。

– 单粒子锁定(SEL)、单粒子烧毁(SEB) 和单粒子

栅穿(SEGR) 对于线性能量传递(LET) 的抗扰度

= 43MeV-cm²/mg

– 单粒子功能中断(SEFI) 和单粒子瞬变(SET) 对

于LET 的额定值= 43MeV-cm²/mg

由于在设计中主要使用双极技术，TPS7H1210-SEP

器件适合于高准确度、低噪声应用，在此类应用中，为

了获得更高的系统性能，清洁的电压轨很关键。因此，

它非常适合为运算放大器、ADC、DAC 和其他高性能

模拟电路供电。

• 低噪声：13.7μV_RMS典型值（10Hz 至100kHz）

• 高电源抑制比，PSRR（V_IN= –6V、V_OUT= –

5V、I_OUT= 1A 下的典型值）：

此外，TPS7H1210-SEP 器件适用于后置直流/直流转

换器稳压。通过滤除直流/直流开关转换所固有的输出

电压纹波，可确保在敏感器件和射频应用中尽可能提高

系统性能。

– 100Hz 时为61dB

– 100 kHz 时为61dB

– 1 MHz 时为41dB

• 输入电压范围：-3 V 至-16.5 V

• 可调输出：-1.2 V 至-15.5 V

• 输出电流高达1A

• 与电容值≥10μF 的陶瓷电容一起工作时保持稳定

• 内置电流限制和热关断保护

• 增强型航天塑料(SEP)

器件信息

器件型号⁽¹⁾

封装⁽²⁾

VQFN (20)

5.00mm × 5.00mm

等级

特征值为

20krad(Si)

RLAT、30krad(Si) 质量= 83.6mg

TPS7H1210MRGWSEP

TPS7H1210EVM

EVM

评估板

– 受控基线

– 金键合线

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

– NiPdAu 铅涂层

(2) 尺寸和质量为标称值。

– 一个组装和测试基地

– 一个制造基地

– 军用级（-55°C 到125°C）温度范围

– 延长了产品生命周期

– 延长了产品变更通知(PCN)

– 产品可追溯性

TPS7H1210-SEP

-3 V t -íòXñ V

-1.2 V t -íñXñ V @ 1 A

OUT

R_{EN_TOP}

R_{FB_TOP}

C_IN

C_OUT

– 采用增强型模塑化合物实现低释气

2 应用

R_{EN_BOT}

R_{FB_BOT}

NR_SS

GND

• 支持近地轨道(LEO) 航天应用

• 卫星电力系统(EPS)

• 模拟电路电源

C_{NR_SS}

– 数据转换器：ADC 和DAC（模数转换器和数模

转换器）

– 运算放大器

典型应用原理图

– 图像传感器

• 后置直流/直流转换器稳压和纹波滤除

• 用于空间受限区域的耐辐射超洁净模拟电源

本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问

www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SBVS414

TPS7H1210-SEP

ZHCSNP8 –NOVEMBER 2021

www.ti.com.cn

Table of Contents

8.1 Application Information............................................. 15

8.2 Typical Application.................................................... 18

8.3 Do's and Don’ts......................................................19

9 Power Supply Recommendations................................20

10 Layout...........................................................................20

10.1 Layout Guidelines................................................... 20

10.2 Layout Example...................................................... 21

10.3 Thermal Performance............................................. 21

11 Device and Documentation Support..........................22

11.1 Device Support........................................................22

11.2 Documentation Support.......................................... 22

11.3 接收文档更新通知................................................... 22

11.4 支持资源..................................................................22

11.5 Trademarks............................................................. 22

11.6 Electrostatic Discharge Caution..............................22

11.7 术语表..................................................................... 22

12 Mechanical, Packaging, and Orderable

1 特性................................................................................... 1

2 应用................................................................................... 1

3 说明................................................................................... 1

4 Revision History.............................................................. 2

5 Pin Configuration and Functions...................................3

6 Specifications.................................................................. 4

6.1 Absolute Maximum Ratings........................................ 4

6.2 ESD Ratings............................................................... 4

6.3 Recommended Operating Conditions.........................5

6.4 Thermal Information....................................................5

6.5 Electrical Characteristics.............................................6

6.6 Typical Characteristics................................................7

7 Detailed Description......................................................12

7.1 Overview...................................................................12

7.2 Functional Block Diagram.........................................12

7.3 Feature Description...................................................12

7.4 Device Functional Modes..........................................14

8 Application and Implementation..................................15

Information.................................................................... 22

4 Revision History

注：以前版本的页码可能与当前版本的页码不同

DATE

REVISION

NOTES

November 2021

Initial Release

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5 Pin Configuration and Functions

OUT

NR_SS

Thermal Pad

12 NC

图5-1. RGW Package, 20-Pin VQFN (Top View)

表5-1. Pin Functions

I/O⁽¹⁾

DESCRIPTION

NAME

NO.

Enable. This dual-polarity pin turns the regulator on when |V_EN| ≥2 V. The EN pin can be

connected to IN if not used. If V_ENis negative polarity, then keep |V_EN| ≤|V_IN|.

Feedback. This pin is the input to the control-loop error amplifier. It is used to set the output

voltage of the device and is normally equal to V_REF(–1.182 V, typical) during operation.

GND

Ground.

—

Input supply. It is recommended to connect a 10-µF capacitor from IN to GND (as close to the

device as possible).

15, 16

No connect. This pin is not internally connected. It is recommended to connect these pins to

GND to prevent charge buildup; however, these pins can also be left open or tied to any voltage

between GND and V_IN.

2, 4–6, 8–

12, 17–19

—

Noise reduction and soft start. A capacitor connected from this pin to GND controls the soft-start

function and allows RMS noise to be reduced to very low levels. TI recommends connecting a

100-nF capacitor from NR_SS to GND (as close to the device as possible) to filter the noise

generated by the internal band gap and maximize AC performance.

NR_SS

OUT

Output of the regulator. A capacitor greater than or equal to 10 µF must be tied from this pin to

ground to ensure stability. TI recommends connecting a 47-µF ceramic capacitor from OUT to

GND (as close to the device as possible) to maximize AC performance.

1, 20

Thermal

Pad

Connect the thermal pad to a large-area ground plane. The thermal pad is not internally

grounded and it must be externally tied to GND for proper operation.

—

(1) I = Input, O = Output, —= Other

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6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

–35

–2

MAX

UNIT

IN to GND

FB to GND

0.3

FB to IN

–0.3

–35

–0.3

–2

Input voltage

EN to GND

NR_SS to IN

NR_SS to GND

0.3

OUT to GND

–33

–0.3

Output voltage

OUT to IN

Output current

Peak output

Internally limited

Operating virtual junction temperature

Storage temperature

T_J

150

°C

–55

–65

T_stg

(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply

functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If

used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully

functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.

6.2 ESD Ratings

VALUE UNIT

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins⁽¹⁾

Charged device model (CDM), per JEDEC specification JESD22-C101, all pins⁽²⁾±500

±1000

V_(ESD)Electrostatic discharge

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

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6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

–16.5

V_IN

NOM

MAX

–3

UNIT

Input voltage

Output voltage

Output current

OUT⁽¹⁾

OUT⁽²⁾

V_REF

–15.5

R_{FB_BOT}is the lower feedback

resistor

(3)

R_{FB_BOT}

240

kΩ

Input capacitance

Output capacitance

C_IN

µF

C_OUT

Noise reduction and soft start

capacitor

C_{NR_SS}

100

°C

Operating junction temperature

T_J

125

–55

(1) The minimum dropout voltage must also be met.

(2) To ensure stability at no load conditions, a current from the feedback resistive network greater than or equal to 5 µA is required.

(3) This condition helps ensure stability at no load.

6.4 Thermal Information

TPS7H1210-SEP

THERMAL METRIC⁽¹⁾

RQW (VQFN)

UNIT

20 PINS

32.7

R_θJA

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

°C/W

R_θJC(top)

R_θJB

11.8

0.3

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

Ψ_JT

11.7

3.6

Ψ_JB

R_θJC(bot)

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

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6.5 Electrical Characteristics

Over |V_IN| = 3 V, I_OUT= 1 mA, C_IN= 20 µF, C_OUT= 20 µF, C_{NR_SS}= 0 nF, FB tied to OUT, EN tied to IN, over operating

temperature range (T_J= –55°C to 125°C), unless otherwise noted.⁽¹⁾

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

POWER SUPPLIES AND CURRENTS

V_UVLO

Undervoltage lockout threshold

–2

224

363

I_OUT= 0.5 A

325

V_IN= –4.6 V, V_OUT(set)= –5

|V_DO| = |V_IN–

V_{OUT(measured)}|,

C_IN= 30 µF

I_OUT= 1 A

500

|V_DO

Dropout voltage

I_OUT= 1 A,

T_J= 25°C

363

2.9

450

V_IN= –6 V, V_OUT(SET)= –5 V,

V_OUT(forced)= –4.5 V

I_CL

Current limit

I_Q

Quiescent current

Ground current⁽²⁾

V_EN= 3 V, I_OUT= 0 A

V_EN= 3 V, I_OUT= 0.5 A

V_EN= 0.4 V

210

350

µA

I_GND

|I_SHDN

Shutdown current

µA

V_EN= –0.4 V

I_FB(LKG)

Feedback leakage current⁽³⁾

ACCURACY

–

V_REF

Reference voltage

V_FB= V_REF

1.199 1.182 1.164

±1%

|V_IN| = 3 V, 1 mA ≤I_OUT≤1 A

–2%

|V_IN| = 16.5 V, 1 mA ≤I_OUT≤100 mA

V_ACC

Output voltage accuracy

|V_IN| = 16.5 V, |V_OUT| = 15.5 V,

I_OUT= 1 A

±1%

–2%

Line regulation

Load regulation

V_OUT/V

V_OUT/A

ΔV_OUT/ΔV_IN

ΔV_OUT/ΔI_OUT

ENABLE

V_EN(+HI)

3 V ≤|V_IN| ≤16.5 V

1 mA ≤I_OUT≤1 A

–0.007%

–0.5%

Enable turn-on (positive logic)

Enable turn-on (negative logic)

Enable turn-off (positive logic)

Enable turn-off (negative logic)

V_IN

-2

0.4

V_EN(–HI)

V_IN= –16.5 V

V_EN(+LO)

V_EN(–LO)

–0.4

0.48

0.51

0.5

V_IN= V_EN= –3 V

|I_EN

Enable current

µA

°C

V_IN= V_EN= –16.5 V

V_IN= –16.5 V, V_EN= 10 V

T_SD(enter)

T_SD(exit)

NOISE AND PSRR

Thermal shutdown enter temperature

178

152

Thermal shutdown exit temperature

f = 100 Hz

V_IN= –6 V, V_OUT= –5 V,

PSRR

V_N

Power-supply rejection ratio

f = 100 kHz

f = 1 MHz

C_OUT= 50.11 µF, I_OUT= 1 A,

C_{NR_SS}= 100 nF⁽⁴⁾

Output noise rms voltage (bandwidth

from 10 Hz to 100 kHz)

V_IN= –3 V, V_OUT(nom)= V_REF, C_IN= 11.1 µF,

C_OUT= 50.11 µF, C_{NR_SS}= 100 nF, I_OUT= 1 A

13.7

µV_RMS

(1) At operating conditions, V_IN≤0 V, V_OUT(nom)≤V_REF≤0 V; at regulation, V_IN≤V_OUT(nom)–|V_DO|; I_OUT> 0 flows from OUT to IN.

(2) I_GND= I_IN–I_OUT

(3) I_FB> 0 flows into the device.

(4) C_INis removed as part of PSRR testing. During normal operation, follow the recommended operating condition of C_IN≥10 µF.

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6.6 Typical Characteristics

Over |V_IN| = 3 V, I_OUT= 1 mA, C_IN= 20 µF, C_OUT= 20 µF, C_{NR_SS}= 0 nF, FB tied to OUT, EN tied to IN, T_A= 25°C, unless

otherwise noted.

-1.1780

-1.1785

-1.1790

-1.1795

-1.1800

-1.1805

-1.1810

-1.1815

-55°C

-40°C

0°C

25°C

85°C

125°C

V_IN= -3 V

V_IN= -5 V

V_IN= -12 V

V_IN= -16.5 V

-55

-18

-16

-14

-12

-10

V_IN(V)

-8

-6

-4

-2

-35

-15

105 125

Temperature (°C)

I_FB> 0 flows into the device

图6-1. Reference Voltage vs Input Voltage

图6-2. Feedback Leakage Current vs Temperature

Across Temperature

Across Input Voltage

I_OUT= 1 mA

I_OUT= 500 mA

I_OUT= 1000 mA

-18

-16

-14

-12

-10

-8

-6

-4

-2

V_IN(V)

I_OUT= 500 mA

图6-4. Ground Current vs Input Voltage

图6-3. Ground Current vs Input Voltage

Across Temperature

Across Output Current

580

-55°C

-40°C

0°C

25°C

85°C

125°C

-55°C

-40°C

0°C

25°C

85°C

125°C

570

560

550

540

530

520

510

500

490

480

470

460

-18

-16

-14

-12

-10

-8

-6

-4

-2

100 200 300 400 500 600 700 800 900 1000

I_OUT(mA)

V_EN(V)

图6-6. Enable Current vs Enable Voltage

图6-5. Ground Current vs Output Current

Across Temperature

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6.6 Typical Characteristics (continued)

Over |V_IN| = 3 V, I_OUT= 1 mA, C_IN= 20 µF, C_OUT= 20 µF, C_{NR_SS}= 0 nF, FB tied to OUT, EN tied to IN, T_A= 25°C, unless

otherwise noted.

280

270

260

250

240

230

220

210

200

190

180

170

160

2.7

2.6

2.5

2.4

2.3

2.2

2.1

-55°C

-40°C

0°C

25°C

85°C

125°C

-55°C

-40°C

25°C

85°C

125°C

1.9

1.8

1.7

1.6

-18

-16

-14

-12

-10

V_IN(V)

-8

-6

-4

-2

-18

-16

-14

-12

-10

V_IN(V)

-8

-6

-4

-2

I_OUT= 0 mA

V_EN= 0.4 V

图6-7. Quiescent Current vs Input Voltage

图6-8. Shutdown Current vs Input Voltage

Across Temperature

270

260

250

240

230

220

210

200

450

400

350

300

250

200

150

100

-55°C

-40°C

0°C

25°C

85°C

125°C

-55°C

-40°C

0°C

25°C

85°C

125°C

100 200 300 400 500 600 700 800 900 1000

I_OUT(mA)

-15 -14 -13 -12 -11 -10 -9

V_IN(V)

-8

-7

-6

-5

-4

V_IN= –4.6 V

V_OUT(SET)= –5 V

C_IN= 30 μF

I_OUT= 500 mA

C_IN= 30 μF

图6-10. Dropout Voltage vs Output Current

图6-9. Dropout Voltage vs Input Voltage

Across Temperature

420

400

380

360

340

320

300

280

260

240

220

200

2.5

Iout = 500 mA

Iout = 1000 mA

Enable Threshold Positive

1.5

0.5

OFF

-0.5

-1

-1.5

-2

Enable Threshold Negative

-2.5

-55

-35

-15

105 125

-55

-35

-15

105 125

Temperature (°C)

V_IN= –4.6 V

V_OUT(SET)= –5 V

C_IN= 30 μF

图6-12. Enable Threshold Voltage vs Temperature

图6-11. Dropout Voltage vs Temperature

Across Output Current

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6.6 Typical Characteristics (continued)

Over |V_IN| = 3 V, I_OUT= 1 mA, C_IN= 20 µF, C_OUT= 20 µF, C_{NR_SS}= 0 nF, FB tied to OUT, EN tied to IN, T_A= 25°C, unless

otherwise noted.

-0.001%

-0.002%

-0.003%

-0.004%

-0.005%

-0.006%

-0.007%

-0.008%

0.2%

0.1%

0.0

-55°C

-40°C

0°C

25°C

85°C

125°C

-55°C

-40°C

0°C

25°C

85°C

125°C

-0.1%

-0.2%

-0.3%

-0.4%

-0.5%

-0.6%

-2

-4

-6

-8

-10

V_IN(V)

-12

-14

-16

-18

100 200 300 400 500 600 700 800 900 1000

I_OUT(mA)

Each individual curve is normalized to 0% at V_IN= –3 V

Each individual curve is normalized to 0% at I_OUT= 0 mA

图6-13. Line Regulation vs Input Voltage

图6-14. Load Regulation vs Output Current

Across Temperature

100

C_OUT= 20 µF

C_OUT= 50 µF

C_OUT= 97 µF

C_{NR_SS}= 0 nF

C_{NR_SS}= 10 nF

C_{NR_SS}= 100 nF

C_{NR_SS}= 1 µF

100

10k

100k

10M

100

10k

100k

10M

Frequency (Hz)

C_IN= 0 μF^(A)

C_OUT= 50.11 μF

C_IN= 0 μF^(A)

C_{NR_SS}= 100 nF

I_OUT= 1 A

All curves have 100-nF and 10-nF capacitor on V_OUT

图6-15. Power-Supply Rejection Ratio vs Frequency Across

图6-16. Power-Supply Rejection Ratio vs Frequency Across

C_OUT

C_{NR_SS}

100

I_OUT= 10 mA

I_OUT= 200 mA

I_OUT= 500 mA

I_OUT= 1000 mA

V_OUT= V_FB

V_OUT= -5 V

V_OUT= -12 V

V_OUT= -15.5 V

100

10k

100k

10M

100

10k

100k

10M

Frequency (Hz)

C_IN= 0 μF^(A)

C_OUT= 50.11 μF

C_IN= 0 μF^(A)

C_{NR_SS}= 100 nF

|V_IN| = |V_OUT+ 1 V|, 3-V minimum

C_OUT= 50.11 μF

I_OUT= 1 A

图6-17. Power-Supply Rejection Ratio vs Frequency Across

图6-18. Power-Supply Rejection Ratio vs Frequency Across

Output Current

Output Voltage

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6.6 Typical Characteristics (continued)

Over |V_IN| = 3 V, I_OUT= 1 mA, C_IN= 20 µF, C_OUT= 20 µF, C_{NR_SS}= 0 nF, FB tied to OUT, EN tied to IN, T_A= 25°C, unless

otherwise noted.

100

10000

1000

100

V_DO= 800 mV

V_DO= 1000 mV

I_OUT= 1 mA, V_N= 7.2 µV_RMS

I_OUT= 200 mA, V_N= 13.3 µV_RMS

I_OUT= 500 mA, V_N= 13.4 µV_RMS

I_OUT= 1000 mA, V_N= 13.7 µV_RMS

0.1

100

10k

100k

10M

100

10k

100k

10M

Frequency (Hz)

C_IN= 0 μF^(A)

C_{NR_SS}= 100 nF

C_OUT= 50.11 μF

C_{NR_SS}= 100 nF

C_OUT= 50.11 μF

C_IN= 11.1 μF

I_OUT= 1 A

V_OUT= –5 V

V_N= output noise RMS voltage (10-Hz to 100-kHz bandwidth)

|V_IN| = |V_OUT+ V_DO|, 3-V minimum

图6-19. Power-Supply Rejection Ratio vs Frequency Across

图6-20. Output Noise vs Frequency Across Output Current

Dropout Voltage

(Noise Spectral Density)

10000

C_{NR_SS}= 0 nF, V_N= 14.3 µV_RMS

C_{NR_SS}= 10 nF, V_N= 14.3 µV_RMS

C_{NR_SS}= 100 nF, V_N= 13.7 µV_RMS

C_{NR_SS}= 1 µF, V_N= 13.4 µV_RMS

1000

100

0.1

100

10k

100k

10M

Frequency (Hz)

I_OUT= 1 A

I_OUT= 1 mA

C_OUT= 50.11 μF

C_IN= 11.1 μF

C_OUT= 50.11 μF

C_IN= 11.1 μF

V_N= output noise RMS voltage (10-Hz to 100-kHz bandwidth)

图6-21. Output Noise vs Frequency Across C_{NR_SS}

图6-22. Output Noise vs Frequency Across C_{NR_SS}

(Noise Spectral Density)

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6.6 Typical Characteristics (continued)

Over |V_IN| = 3 V, I_OUT= 1 mA, C_IN= 20 µF, C_OUT= 20 µF, C_{NR_SS}= 0 nF, FB tied to OUT, EN tied to IN, T_A= 25°C, unless

otherwise noted.

10000

1000

V_OUT(50 mV/div) (AC coupled)

100

V_OUT= V_FB, V_N= 13.7 µV_RMS

V_OUT= -5 V, V_N= 27.2 µV_RMS

V_OUT= -12 V, V_N= 44.3 µV_RMS

V_OUT= -15.5 V, V_N= 51.4 µV_RMS

I_OUT(500 mA/div)

0.1

100

10k

100k

10M

Frequency (Hz)

Time (100 µs/div)

V_OUT= –12 V

C_OUT= 50 μF

I_OUT= 1 A

|V_IN| = |V_OUT+ V_DO|, 3-V minimum

C_OUT= 50.11 μF

C_IN= 11.1 μF

I_{OUT (slew)}= 1 A / 10

μs

V_IN= –15 V

V_N= output noise RMS voltage (10-Hz to 100-kHz bandwidth)

C_{NR_SS}= 100 nF

C_IN= 11.1 μF

图6-23. Output Noise vs Frequency Across Output Voltage

(Noise Spectral Density)

图6-24. Load Step: 1 mA to 500 mA

V_OUT(50 mV/div) (AC coupled)

I_OUT(500 mA/div)

V_IN(5 V/div)

V_OUT(5 V/div)

Time (100 µs/div)

I_{OUT (slew)}= 1 A / 10

Time (50 ms/div)

V_IN(SET)= –15 V

C_OUT= 50 μF

V_OUT(SET)= –12 V C_IN= 11.1 μF

V_IN= –15 V

V_OUT= –12 V

μs

C_{NR_SS}= 100 nF

C_IN= 11.1 μF

C_OUT= 50 μF

图6-26. Start-up with Soft-Start

图6-25. Load Step: 500 mA to 1 mA

A. C_INis removed as part of PSRR testing. During normal operation, follow the recommended operating condition of C_IN≥10 μF.

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7 Detailed Description

7.1 Overview

The TPS7H1210-SEP negative voltage linear regulator uses a bipolar process to achieve very low noise and

very high PSRR levels at a wide input voltage and current range. These features, plus its radiation tolerance,

make this device ideal for high-performance analog applications in satellites.

7.2 Functional Block Diagram

GND

Control

Logic

OUT

1.2V V_REF

NR_SS

Thermal

Shutdown

Current

Limit

IN IN

7.3 Feature Description

7.3.1 Internal Current Limit

The fixed internal current limit of the TPS7H1210-SEP device helps protect the regulator during fault conditions.

The maximum amount of current the device can source is the current limit (2.9 A, typical), and it is largely

independent of output voltage. For reliable operation, do not operate the device in current limit for extended

periods of time.

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7.3.2 Enable Pin Operation

The TPS7H1210-SEP provides a dual-polarity enable pin (EN) that turns on the regulator when |V_EN| > 2 V,

whether the voltage is positive or negative, as shown in 图7-1. Specifically, if V_EN≥V_EN(+HI)or V_EN≤V_EN(–HI)

the regulator is enabled. If V_EN(+LO)≥V_EN≥V_EN(–LO), the regulator is disabled.

This functionality allows for different system power management topologies; for example:

• Connecting the EN pin directly to a negative voltage, such as V_IN.

• Connecting the EN pin directly to a positive voltage, such as the output of digital logic circuitry.

• Connecting the EN pin to a resistor divider from V_INto GND to turn-on at a specific input voltage level

(programmable turn-on voltage).

V_OUT

V_EN

V_IN

Time (20ms/div)

图7-1. Enable Pin Positive and Negative Threshold

7.3.3 Programmable Soft-Start

The NR_SS capacitor acts as a noise reduction capacitor and a soft-start capacitor to slow down the rise time of

the output. The output rise time, when using an NR_SS capacitor, is approximated by 方程式1.

t_SS(ms) = 1.2 × C_{NR_SS}(nF)

(1)

In 方程式 1, t_SSis the soft-start time in milliseconds and C_{NR_SS}is the capacitance at the NR_SS pin in

nanofarads.

图7-2 shows the start-up voltage waveforms versus C_{NR_SS}

C_{NR_SS}= 10 nF

C_{NR_SS}= 100 nF

C_{NR_SS}= 1 µF

-2

-4

-6

-8

-10

-12

-14

-100

100

300

500

Time (ms)

700

900

图7-2. Start-Up Waveforms vs C_{NR_SS}

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7.3.4 Thermal Protection

Thermal protection disables the output when the junction temperature rises to approximately 178°C, allowing the

device to cool. When the junction temperature cools to approximately 152°C, the output circuitry is enabled.

Depending on power dissipation, thermal resistance, and ambient temperature, the thermal protection circuit

may cycle on and off. This cycling limits the dissipation of the regulator, mitigating damage as a result of

overheating.

Any tendency to activate the thermal protection circuit indicates excessive power dissipation or an inadequate

heat sink. For reliable operation, limit the junction temperature to a maximum of 125°C.

The internal protection circuitry of the TPS7H1210-SEP has been designed to protect against overload

conditions. It was not intended to replace proper thermal management. Continuously running the TPS7H1210-

SEP into thermal shutdown degrades device reliability.

7.4 Device Functional Modes

7.4.1 Normal Operation

The device regulates to the nominal output voltage under all of the following conditions:

• The input voltage magnitude has previously exceeded the UVLO rising voltage magnitude and has not

decreased below the UVLO falling threshold magnitude.

• The input voltage magnitude is greater than the nominal output voltage magnitude added to the dropout

voltage magnitude.

• |V_EN| > |V_(HI)

• The output current is less than the current limit.

• The device junction temperature is less than the maximum specified recommended operating conditions

junction temperature.

7.4.2 Dropout Operation

If the input voltage magnitude is lower than the magnitude of the nominal output voltage plus the specified

dropout voltage, but all other conditions are met for normal operation, the device operates in dropout mode. In

this condition, the output voltage is the same as the input voltage minus the dropout voltage. The transient

performance of the device is significantly degraded because the pass device (as a bipolar junction transistor, or

BJT) is in saturation and no longer controls the current through the LDO. Line or load transients in dropout can

result in large output voltage deviations.

7.4.3 Disabled

The device is disabled under any of the following conditions:

• |V_EN| < |V_(HI)

• The device junction temperature is greater than the thermal shutdown temperature.

表7-1 shows the conditions that lead to the different modes of operation.

表7-1. Device Functional Mode Comparison

PARAMETER

OPERATING MODE

V_IN

V_EN

I_OUT

I_OUT< I_CL

—

T_J

Normal mode

Dropout mode

|V_IN| > { |V_OUT(nom)| + |V_DO|, |V_IN(min)| }

|V_EN| > |V_(HI)

T_J< 125°C

|V_IN(min)| < |V_IN| < |V_OUT(nom)| + |V_DO

|V_EN| > |V_(HI)

Disabled mode

(any true condition disables the

device)

|V_EN| < |V_(HI)

T_J> ~178°C

|V_IN| ≤|V_UVLO

—

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8 Application and Implementation

备注

Information in the following applications sections is not part of the TI component specification, and TI

does not warrant its accuracy or completeness. TI’s customers are responsible for determining

suitability of components for their purposes, as well as validating and testing their design

implementation to confirm system functionality.

8.1 Application Information

8.1.1 Adjustable Operation

The TPS7H1210-SEP has an output voltage range of V_REFto –15.5 V. The nominal output voltage of the device

is set by two external resistors, as shown in 图8-2.

R_{FB_TOP}and R_{FB_BOT}can be calculated for any output voltage range using 方程式 2. To ensure stability under

no-load conditions at |V_OUT| > |V_REF|, this resistive network must provide a current equal to or greater than 5

μA.

REF

OUT

= R

FB_BOT

− 1 , where

> 5 µA

(2)

FB_TOP

REF

FB_BOT

表 8-1 shows the resistor combinations to achieve a few of the most common rails using commercially available,

1%-tolerance resistors. If greater voltage accuracy is required, consider the output voltage offset contributions

because of the feedback pin current and use 0.1%-tolerance resistors.

表8-1. Example 1% Tolerance Resistors for Common Voltage Rails

R_{FB_TOP}

(kΩ)

R_{FB_BOT}

(kΩ)

V_OUT

(V)

RESISTOR NETWORK

BIAS CURRENT (µA)

RESISTOR ERROR

CONTRIBUTION⁽¹⁾

N/A

84.4

N/A

–1.182

–1.8

–2.5

–3.3

–5

∞

7.32

11.3

19.1

+0.001%

+0.341%

–0.245%

–0.189%

+0.066%

–0.086%

+0.187%

–0.627%

10.2

10.7

10.5

17.4

15.4

115.9

110.5

112.6

67.9

115

445

137

133

–9

76.8

–10

–12

–15

78.8

11.3

104.6

(1) This is the error contribution due to the mismatch between the ideal resistor ratio and the actual resistor ratio (using the indicated

resistor values). It does not include the error contribution due to the resistor tolerance itself. More accurate ratios are possible by using

0.1% tolerance resistors.

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8.1.2 Capacitor Recommendations

It is recommended to use low equivalent series resistance (ESR) capacitors for the input, output, noise

reduction, and bypass capacitors. Ceramic capacitors with an X7R dielectric is preferred. This dielectric offers

stable characteristics over temperature.

备注

High-ESR capacitors may degrade PSRR and affect stability.

The TPS7H1210-SEP negative linear regulator achieves stability with a minimum input and output capacitance

of 10 μF. TI recommends using a 10-μF capacitor at the input. A larger capacitor is recommended at the

output. Specifically, TI recommends using a 47-μF capacitor (or multiple capacitors to reach ~47 μF) at the

output to improve single event transient (SET) performance.

8.1.3 Noise Reduction and Feed-Forward Capacitor Requirements

Although the noise-reduction (C_{NR_SS}) capacitor is not needed to achieve stability, TI highly recommends using a

100-nF noise-reduction capacitor to minimize noise and maximize AC performance. The noise-reduction

capacitor is especially important at low currents as shown in 图6-22.

It is generally recommended to not use a feed-forward capacitor. While a feed-forward capacitor can provide

some improvements in PSRR at certain frequencies, it also has additional risks. See Pros and Cons of Using a

Feed-Forward Capacitor with a Low Dropout Regulator for additional information.

CAUTION

Using a feed-forward capacitor with the TPS7H1210-SEP can cause the FB pin to go too positive

during shutdown, thus damaging the device.

图 8-1 shows the different PSRR performance of the device with and without a feed-forward capacitor with V_IN

–13 V, V_OUT= –12 V, I_OUT= 1 A, C_{NR_SS}= 100 nF, and C_OUT= 50 μF.

100

C_FF= 0 nF

C_FF= 10 nF

100

10k

100k

10M

Frequency (Hz)

图8-1. Power-Supply Rejection Ratio vs Frequency Across C_FF

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8.1.4 Power-Supply Rejection Ratio (PSRR)

Using a noise-reduction capacitor (C_{NR_SS}) of at least 10-nF greatly improves TPS7H1210-SEP power-supply

rejection ratio. If the C_{NR_SS}capacitor is omitted, the PSRR can be 10 dB lower or worse across a wide range of

frequencies. A 100-nF capacitor is generally recommended.

Additionally, TI recommends using at least a 47-μF output capacitor for both single event transient (SET) and to

achieve great AC performance. A 10-μF input capacitor is generally sufficient for good device performance;

however, a 47-μF input capacitor or larger may be ideal if the input rail is extremely noisy.

The high power-supply rejection of the TPS7H1210-SEP makes it a good choice for powering high-performance

analog circuitry.

8.1.5 Output Noise

The TPS7H1210-SEP provides low output noise when a noise-reduction capacitor (C_{NR_SS}) is used.

The noise-reduction capacitor serves as a filter for the internal reference. By using at a 100-nF noise reduction

capacitor (C_{NR_SS}), the output noise can be reduced by approximately 80% (from 35.7 μV_RMSto 7.1 μV_RMS).

See 图6-22 for additional information. The benefit is less pronounced at higher currents (see 图6-21).

The TPS7H1210-SEP low output voltage noise makes it an ideal solution for powering noise-sensitive circuitry.

8.1.6 Transient Response

As with any regulator, increasing the size of the output capacitor reduces overshoot and undershoot magnitude,

but increases duration of the transient response.

8.1.7 Post DC-DC Converter Filtering

Most of the time, the voltage rails available in a system do not match the voltage specifications demanded by

one or more of its circuits; these rails must be stepped up or down, depending on specific voltage requirements.

DC-DC converters are generally the preferred solution to stepping up or down a voltage rail when current

consumption is not negligible. These devices offer high efficiency with minimum heat generation, but they have

one primary disadvantage: they introduce a high-frequency component, and the associated harmonics, on top of

the DC output signal.

If not filtered properly, this high-frequency component degrades analog circuitry performance, and reduces

overall system accuracy and precision.

The TPS7H1210-SEP offers a wide-bandwidth, very-high power-supply rejection ratio (PSRR). This specification

makes it ideal for post DC-DC converter filtering. TI recommends using a schematic like the one shown in 图8-2

for high performance. Also, verify that the TPS7H1210-SEP regulator PSRR is still high within the fundamental

frequency (and its first harmonic, if possible) of the switching regulator.

8.1.8 Power for Precision Analog

One of the primary TPS7H1210-SEP applications is to provide very low noise voltage rails to high-performance

analog circuitry in order to maximize system accuracy and precision. This includes powering operational

amplifiers, ADCs, DACs, and RF amplifiers.

Because of the low noise levels at high voltages, the TPS7H1210-SP can directly power high performance

analog circuitry with high-voltage input supply requriements.

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8.2 Typical Application

TPS7H1210-SEP

V_OUT= -5 V

V_IN

OUT

R_{EN_TOP}

102 kΩ

R_{FB_TOP}

34 kΩ

C_IN

11.1 µF

C_OUT

50.11 µF

R_{EN_BOT}

68 kΩ

R_{FB_BOT}

10.5 kΩ

NR_SS

GND

C_{NR_SS}

100 nF

图8-2. Adjustable Operation for Optimized AC and Radiation Performance

8.2.1 Design Requirements

The design goals for this example are V_IN= –6 V, V_OUT= –5 V, and I_OUT= 1-A maximum. The design must

optimize transient response, and the input supply comes from a supply on the same printed-circuit board (PCB).

8.2.2 Detailed Design Procedure

The design consists of C_IN, C_OUT, C_{NR_SS}, R_{FB_TOP}, R_{FB_BOT}, R_{EN_TOP}, R_{EN_BOT}, and the circuit shown in 图8-2.

The first step when designing with a linear regulator is to examine the maximum load current along with the input

and output voltage requirements to determine if the device thermal and dropout voltage requirements can be

met. At 1 A, the input dropout voltage of the TPS7H1210-SEP device is a maximum of 500 mV over

temperature; thus, the dropout headroom is sufficient for operation over both input and output voltage accuracy.

Keep in mind that operating an LDO close to the dropout limit reduces AC performance, but has the benefit of

reducing the power dissipation across the LDO.

The maximum power dissipated in the linear regulator is the maximum voltage drop across the pass element

from the input to the output multiplied by the maximum load current (plus a small amount of quiescent power). In

this example, the maximum voltage drop across in the pass element is (–6 V) – (–5 V), giving us a V_DROP= 1

V. The power dissipated in the pass element is calculated by taking this voltage drop multiplied by the maximum

load current. For this example, the maximum power dissipated in the linear regulator is approximately 1 W.

To ensure an accurate output voltage, R_{FB_TOP}and R_{FB_BOT}must also be found, and the current through these

resistors must be greater than 5 µA to ensure stability. For this design, R_{FB_TOP}is set to 34 kΩ, to achieve

reasonable leakage current leakage while continuing to hold it well above 5 µA. Then 方程式 3 is used to

calculate the proper value for R_{FB_BOT}

× V

REF

FB_TOP

REF

= 10.5 kΩ and I

= 112.6 µA

(3)

FB_BOT

DIVIDER

− V

OUT

REF

FB_BOT

Next, for C_INa 10 µF, 1 µF, and 0.1-µF ceramic capacitor are selected. This provides margin over the 10-µF

minimum input capacitance and reduces the impedance across a wider range of frequencies than a single 10-µF

capacitor.

For C_OUT, 5 × 10-µF, 1 × 100-nF, and 1 × 10-nF ceramic capacitors are selected. The multiple ceramic

capacitors reduce ESR (equivalent series resistance) and ESL (equivalent series inductance) to aid in good AC

performance. Additionally, better SET (single-event-transient) performance is generally achieved by choosing a

larger output capacitance than the minimum of 10 µF.

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Next, C_{NR_SS}is set at 100 nF for optimal noise performance along with maximized AC performance while

keeping reasonable soft-start times.

To have a configurable turn-on voltage, feed the EN pin by a resistor divider from V_INto GND. Since the

TPS7H1210-SEP is commanded to turn-on when EN is less than –2 V (see V_EN(-HI)in 节 6.5), 方程式 4 can be

used to determine the resistors to select for a desired turn-on voltage, V_IN(turn-on)

× 2 V

EN_TOP

IN turn−on

(4)

EN_BOT

− 2 V

For this design R_{EN_TOP}= 102 kΩand R_{EN_BOT}= 68 kΩ, which results in V_IN(turn-on)= –5 V. This means that as

V_INis ramping from 0 V to its final value of –6 V during start-up, the regulator will turn-on when V_INreaches –5

8.2.3 Application Curves

图 8-3 and 图 8-4 show a 1-mA to 500-mA load step and 500-mA to 1-mA load step respectively using the

values described within this section.

V_OUT(50 mV/div) (AC coupled)

I_OUT(500 mA/div)

Time (200 µs/div)

V_OUT= –5 V

Time (200 µs/div)

V_OUT= –5 V

I_{OUT (slew)}= 1 A / 10

μs

I_{OUT (slew)}= 1 A / 10

μs

V_IN= –6 V

C_{NR_SS}= 100 nF

C_IN= 11.1 μF

C_OUT= 50.11 μF

C_IN= 11.1 μF

C_OUT= 50.11 μF

图8-3. Load Step: 1 mA to 500 mA

图8-4. Load Step: 500 mA to 1 mA

8.3 Do's and Don’ts

Place at least one low ESR 10-µF capacitor as close as possible to both the IN and OUT terminals of the

regulator to the GND pin.

Provide adequate thermal paths away from the device.

Do not place the input or output capacitor more than 10 mm away from the regulator.

Do not exceed the absolute maximum ratings.

Do not float the EN pin.

Do not resistively or inductively load the NR_SS pin.

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9 Power Supply Recommendations

The input supply for the LDO must be within its recommended operating conditions, of –16.5 V to –3 V. The

input voltage must provide adequate headroom for the device to have a regulated output. If the input supply is

noisy, additional input capacitors with low ESR can help improve the output noise performance.

10 Layout

Layout is a critical part of good power-supply design. Several signal paths that conduct fast-changing currents or

voltages can interact with stray inductance or parasitic capacitance to generate noise or degrade the power-

supply performance. To help eliminate these problems, bypass the IN pin to ground with a low ESR ceramic

bypass capacitor with an X7R dielectric.

10.1 Layout Guidelines

10.1.1 Improve PSRR and Noise Performance

To improve AC performance such as PSRR, output noise, and transient response, TI recommends designing the

board with separate planes for IN, OUT, and GND. The IN and OUT planes should be isolated from each other

by a GND plane section. In addition, the ground connection for the output capacitor should connect directly to

the GND pin of the device.

Equivalent series inductance (ESL) and equivalent series resistance (ESR) must be minimized in order to

maximize performance and ensure stability. Every capacitor (C_IN, C_OUT, C_{NR_SS}, and C_FFif used) must be placed

as close as possible to the device and on the same side of the PCB as the regulator itself.

Do not place any of the capacitors on the opposite side of the PCB from where the regulator is installed. The use

of vias and long traces is strongly discouraged because they may impact system performance negatively and

even cause instability.

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10.2 Layout Example

It may be possible to obtain acceptable performance with alternative PCB layouts.

R_{FB_TOP}

R_{FB_BOT}

Sense Line

Output Power Plane

C_OUT

GND

20 OUT

Input GND Plane and Thermal Relief

18 NC

17 NC

Thermal Pad

Output GND Plane

14 15

C_NR

Input Power Plane

C_IN

图10-1. TPS7H1210-SEP Layout Guideline

10.3 Thermal Performance

The high-current and high-voltage characteristics of the TPS7H1210-SEP means that, often enough, high power

(heat) is dissipated from the device itself. This heat, if dissipated into the PCB, creates a temperature gradient in

the surrounding area that causes nearby components to react to this temperature change (drift). In high-

performance systems, such drift may degrade overall system accuracy and precision.

The heat generated by the device is a result of the power dissipation, which depends on input voltage and load

conditions. Power dissipation (P_D) can be approximated by calculating the product of the output current times the

voltage drop across the output pass element, as shown in 方程式5:

= V − V

× I

OUT

(5)

OUT

Be sure the PCB is able to effectively dissipate the heat resulting from the power dissipation.

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11 Device and Documentation Support

11.1 Device Support

11.1.1 Development Support

11.1.1.1 Spice Models

Computer simulation of circuit performance using SPICE is often useful when analyzing the performance of

analog circuits and systems. A PSpice model for the TPS7H1210-SEP is available through the product folder

under the Design & Development section.

11.2 Documentation Support

11.2.1 Related Documentation

For related documentation see the following:

• Texas Instrument, TPS7H1210-SEP Total Ionizing Dose (TID) radiation report

• Texas Instrument, TPS7H1210-SEP Single-Event Effects (SEE) radiation report

• Texas Instrument, TPS7H1210-SEP Evaluation Module (EVM) user's guide

• Texas Instrument, Pros and Cons of Using a Feedforward Capacitor with a Low-Dropout Regulator

application report

• Vendor item drawing available, VID V62/21616

11.3 接收文档更新通知

要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新进行注册，即可每周接收产品信息更

改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

11.4 支持资源

TI E2E^™支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解

答或提出自己的问题可获得所需的快速设计帮助。

链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅

TI 的《使用条款》。

11.5 Trademarks

TI E2E^™is a trademark of Texas Instruments.

所有商标均为其各自所有者的财产。

11.6 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled

with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric changes could cause the device not to meet its published

specifications.

11.7 术语表

TI 术语表

本术语表列出并解释了术语、首字母缩略词和定义。

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

Submit Document Feedback

Product Folder Links: TPS7H1210-SEP

PACKAGE OPTION ADDENDUM

www.ti.com

26-Mar-2023

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

TPS7H1210MRGWSEP

TPS7H1210MRGWTSEP

V62/21616-01XE

ACTIVE

VQFN

RGW

250

RoHS & Green

NIPDAU

Level-3-260C-168 HR

-55 to 125

7H1210

Samples

NIPDAU

7H1210

V62/21616-01XE-T

250

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

26-Mar-2023

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2

GENERIC PACKAGE VIEW

RGW 20

5 x 5, 0.65 mm pitch

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

This image is a representation of the package family, actual package may vary.

Refer to the product data sheet for package details.

4227157/A

www.ti.com

PACKAGE OUTLINE

VQFN - 1 mm max height

RGW0020A

PLASTIC QUAD FLATPACK-NO LEAD

5.1

4.9

PIN 1 INDEX AREA

5.1

4.9

1 MAX

SEATING PLANE

0.08 C

0.05

0.00

3.15±0.1

2X 2.6

(0.1) TYP

16X 0.65

SYMM

2.6

0.36

0.26

20X

PIN1 ID

(OPTIONAL)

0.1

C A B

0.05

SYMM

0.65

0.45

20X

4219039/A 06/2018

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.

www.ti.com

EXAMPLE BOARD LAYOUT

VQFN - 1 mm max height

RGW0020A

PLASTIC QUAD FLATPACK-NO LEAD

(4.65)

3.15)

(2.6)

(

16X (0.65)

(1.325)

SYMM

(4.65) (2.6)

(R0.05) TYP

20X (0.31)

20X (0.75)

(Ø0.2) VIA

TYP

(1.325)

SYMM

LAND PATTERN EXAMPLE

SCALE: 15X

0.07 MAX

ALL AROUND

0.07 MIN

ALL AROUND

SOLDER MASK

OPENING

EXPOSED METAL

METAL

EXPOSED METAL

METAL UNDER

SOLDER MASK

OPENING

NON SOLDER MASK

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4219039/A 06/2018

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

www.ti.com

EXAMPLE STENCIL DESIGN

VQFN - 1 mm max height

RGW0020A

PLASTIC QUAD FLATPACK-NO LEAD

(4.65)

4X ( 1.37)

2X (0.785)

16X (0.65)

2X (0.785)

SYMM

(4.65) (2.6)

(R0.05) TYP

20X (0.31)

20X (0.75)

METAL

TYP

SYMM

(2.6)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD

75% PRINTED COVERAGE BY AREA

SCALE: 15X

4219039/A 06/2018

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

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邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

TPS7H1210MRGWTSEP [TI]

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