TPS7H2211HKR/EM [TI]
耐辐射 QMLV、4.5V 至 14V 输入、3.5A 负载开关/电子保险丝 | HKR | 16 | 25 to 25;
| 型号： | TPS7H2211HKR/EM |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 耐辐射 QMLV、4.5V 至 14V 输入、3.5A 负载开关/电子保险丝 | HKR | 16 | 25 to 25 电子 开关 |
| 文件： | 总43页 (文件大小：2200K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS7H2211-SP
ZHCSOS3B –AUGUST 2021 –REVISED MAY 2022
TPS7H2211-SP 耐辐射保证(RHA) 14V、3.5A 电子保险丝
开关由可与低压控制信号直接连接的打开和关闭输入
(EN) 控制。过压保护和软启动可通过OVP 和SS 引脚
使用很少的外部组件进行编程。TPS7H2211-SP 采用
陶瓷封装，带有外露散热垫，可提高散热性能。
1 特性
• 电离辐射总剂量(TID) 为100krad(Si)
– 抗辐射加固保障为100krad(Si)
• 确定了单粒子效应(SEE)
器件信息
等级(2)
可订购器件型号(1)
– 单粒子锁定(SEL)、单粒子烧毁(SEB) 和单粒子
栅穿(SEGR) 对于线性能量传递(LET) 的抗扰度
= 75MeV-cm2/mg*
封装
飞行等级QMLV-
RHA 100krad(Si)
5962R1822001VXC
16 引脚CFP
11.00mm ×
9.60mm 质量=
1.56g(4)
– 单粒子功能中断(SEFI) 和单粒子瞬变(SET) 对
于LET 的额定值= 75MeV-cm2/mg*
• 集成式单通道eFuse
• 输入电压范围：4.5 V 至14 V
• 低导通电阻(RON)，在温度为25°C 和输入电压为
12V 时具有60mΩ的最大值
• 3.5A 最大持续开关电流
• 低控制输入阈值支持使用
1.2V、1.8V、2.5V 和3.3V 逻辑电平
• 可配置上升时间（软启动）
• 反向电流保护(RCP)
5962-1822001VXC
TPS7H2211HKR/EM
飞行等级QMLV
工程样品(3)
飞行等级QMLV-
RHA KGD
5962R1822001V9A
已知合格芯片
3.66mm × 5.75mm
工程样品(3)
TPS7H2211Y/EM
TPS7H2211EVM-CVAL
评估模块
评估板
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
(2) 有关器件等级的其他信息，请查看SLYB235。
(3) 这些器件仅适用于工程评估。器件按照不合规的流程进行加工
处理。这些器件不适用于质检、生产、辐射测试或飞行用途。
这些零器件无法在–55°C 至125°C 的完整MIL 额定温度范围
内或运行寿命中保证其性能。
• 过压保护(OVP)
• 内部电流限制（快速跳变）
• 热关断
• 带散热垫的陶瓷封装
(4) 质量误差在±10% 以内。
• 支持军用（–55°C 至125°C）温度范围
VIN
VOUT
VIN
VOUT
SS
*请参阅TPS7H2211-SP SEE 辐射报告，了解测试条件和完整
信息
CSS
RTOP_EN
2 应用
RTOP_OVP
TPS7H2211-SP
• 卫星电力系统(EPS)
• 冷备用电源（冗余）
• 电源时序
• 命令和数据处理
• 通信负载
• 耐辐射电源树
EN
RBOT_EN
OVP
GND
RBOT_OVP
3 说明
TPS7H2211-SP 是一个单通道 eFuse（具有附加功能
的集成 FET 负载开关），可提供反向电流保护、过压
保护和可配置的上升时间，以更大限度减少浪涌电流
（软启动）。此器件包含一个可在 4.5V 至14V 输入电
压范围内运行的P 沟道MOSFET，并且支持最大3.5A
的持续电流。
简化版原理图
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLVSEW6
TPS7H2211-SP
ZHCSOS3B –AUGUST 2021 –REVISED MAY 2022
www.ti.com.cn
Table of Contents
9.3 Feature Description...................................................18
9.4 Device Functional Modes..........................................23
10 Application and Implementation................................25
10.1 Application Information........................................... 25
10.2 Typical Applications................................................ 25
11 Power Supply Recommendations..............................35
12 Layout...........................................................................35
12.1 Layout Guidelines................................................... 35
12.2 Layout Example...................................................... 35
13 Device and Documentation Support..........................36
13.1 Device Support....................................................... 36
13.2 Documentation Support.......................................... 36
13.3 Receiving Notification of Documentation Updates..36
13.4 支持资源..................................................................36
13.5 Trademarks.............................................................36
13.6 Electrostatic Discharge Caution..............................36
13.7 术语表..................................................................... 36
14 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Related Products.............................................................2
6 Pin Configuration and Functions...................................3
7 Specifications.................................................................. 7
7.1 Absolute Maximum Ratings........................................ 7
7.2 ESD Ratings............................................................... 7
7.3 Recommended Operating Conditions.........................8
7.4 Thermal Information....................................................8
7.5 Electrical Characteristics.............................................9
7.6 Switching Characteristics..........................................11
7.7 Quality Conformance Inspection...............................11
7.8 Typical Characteristics..............................................12
8 Parameter Measurement Information..........................15
9 Detailed Description......................................................17
9.1 Overview...................................................................17
9.2 Functional Block Diagram.........................................17
Information.................................................................... 37
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision A (November 2021) to Revision B (May 2022)
Page
• 发布了器件的裸片版本（5962R1822001V9A 和TPS7H2211Y/EM）................................................................1
Changes from Revision * (August 2021) to Revision A (November 2021)
Page
• 发布了5962R1822001VXC 器件........................................................................................................................1
• 将器件分类从“负载开关”更改为“eFuse”，并更新了整个文档中的相关措辞...............................................1
• Added additional information about the NC pins and added a default recommendation....................................3
5 Related Products
PROGRAMMABLE
CURRENT LIMIT
DEVICE
VIN RANGE
MAXIMUM OUTPUT CURRENT
CURRENT SENSE
TPS7H2211-SP
TPS7H2201-SP
4.5 V to 14 V
1.5 V to 7 V
3.5 A
6 A
No
No
Yes
Yes
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6 Pin Configuration and Functions
1
16
15
14
13
VOUT
VOUT
VOUT
VOUT
SS
VIN
2
VIN
3
4
VIN
VIN
NC
Thermal Pad
5
6
12
11
NC
EN
7
8
10
9
NC
OVP
GND
NC
图6-1. HKR Package
16-Pin CFP With Thermal Pad
(Top View)
表6-1. Pin Functions
PIN
I/O
DESCRIPTION
NO.
1
NAME
2
VIN
I
Switch input. An input bypass capacitor is recommended for minimizing VIN dip.
Active high switch control input. Do not float this pin.
3
4
6
EN
OVP
GND
SS
I
I
Overvoltage protection. Set using an external resistor divider. If no OVP is desired, connect
this pin to GND. Do not float this pin.
7
8
Device ground.
—
Soft start (switch slew rate control). If this functionality is not desired, the SS pin must be left
disconnected (floating). In all cases be sure to follow the requirements of 节9.3.3.
12
I/O
13
14
15
16
5
VOUT
NC
O
Switch output. A minimum 10-µF output capacitor is recommended.
NC —No connect. These pins are not internally connected. It is recommended to connect
these pins to GND to prevent charge buildup; however, these pins can also be left open or
tied to any voltage between GND and VIN.
9
—
10
11
Thermal pad (exposed center pad) for heat dissipation purposes. The thermal pad is
internally connected to the seal ring and GND.
Thermal Pad
Metal Lid
—
—
—
—
The lid is internally connected to the thermal pad and GND through the seal ring.
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表6-2. Bare Die Information
BACKSIDE
POTENTIAL
BOND PAD METALLIZATION
DIE THICKNESS
BACKSIDE FINISH
BOND PAD THICKNESS
COMPOSITION
15 mils
Silicon with backgrind
Ground
AlCu
1050 nm
2
5
3
6
4
7
1
8
61 60 59 58
57 56 55 54
9
10 11 12
53 52 51 50
49 48 47 46
13 14 15 16
45 44 43 42
41 40 39 38
17 18 19 20
21 22 23 24
25
26
27
37
36
28
29
35
30
31
32 33
34
0
0
3510
3662
76
1. All dimensions in microns (μm).
2. The inner rectangle is the die and the outer rectangle is the die plus scribe lines.
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表6-3. Bond Pad Coordinates in Microns (μm)
DESCRIPTION
PAD NUMBER
X MIN
725.8
169.3
354.8
540.3
169.3
354.8
540.3
725.8
169.3
354.8
540.3
725.8
169.3
354.8
540.3
725.8
169.3
354.8
540.3
725.8
169.3
354.8
540.3
725.8
61.1
Y MIN
5485.5
5485.5
5485.5
5485.5
5300
X MAX
881.3
Y MAX
5641
VIN
VIN
1
2
324.8
5641
VIN
3
510.3
5641
VIN
4
695.8
5641
VIN
5
324.8
5455.5
5455.5
5455.5
5455.5
5243.45
5243.45
5243.45
5243.45
5057.95
5057.95
5057.95
5057.95
4103.4
4103.4
4103.4
4103.4
3917.9
3917.9
3917.9
3917.9
2181.15
1991.65
1800.8
1531.85
1236.25
801.4
VIN
6
5300
510.3
VIN
7
5300
695.8
VIN
8
5300
881.3
VIN
9
5087.95
5087.95
5087.95
5087.95
4902.45
4902.45
4902.45
4902.45
3947.9
3947.9
3947.9
3947.9
3762.4
3762.4
3762.4
3762.4
2025.65
1836.15
1645.3
1376.35
1080.75
645.9
324.8
VIN
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
510.3
VIN
695.8
VIN
881.3
VIN
324.8
VIN
510.3
VIN
695.8
VIN
881.3
VIN
324.8
VIN
510.3
VIN
695.8
VIN
881.3
VIN
324.8
VIN
510.3
VIN
695.8
VIN
881.3
VINA(1)
VINA(1)
NC
216.6
61.1
216.6
61.1
216.6
NC
61.1
216.6
EN
61.1
216.6
NC
61.1
216.6
OVP
GND
GND
NC
61.1
451.4
216.6
606.9
452.45
641.95
3103.2
3683.4
3683.4
3683.4
3575.15
3389.65
3204.15
3018.65
3575.15
3389.65
3204.15
3018.65
61.1
607.95
797.45
3258.7
3838.9
3838.9
3838.9
3730.65
3545.15
3359.65
3174.15
3730.65
3545.15
3359.65
3174.15
216.6
61.1
216.6
61.1
216.6
NC
652.7
808.2
NC
1221.4
1715.65
3762.4
3762.4
3762.4
3762.4
3947.9
3947.9
3947.9
3947.9
1376.9
1871.15
3917.9
3917.9
3917.9
3917.9
4103.4
4103.4
4103.4
4103.4
SS
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
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表6-3. Bond Pad Coordinates in Microns (μm) (continued)
DESCRIPTION
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
PAD NUMBER
X MIN
Y MIN
4902.45
4902.45
4902.45
4902.45
5087.95
5087.95
5087.95
5087.95
5300
X MAX
3730.65
3545.15
3359.65
3174.15
3730.65
3545.15
3359.65
3174.15
3730.65
3545.15
3359.65
3174.15
3730.65
3545.15
3359.65
3174.15
Y MAX
5057.95
5057.95
5057.95
5057.95
5243.45
5243.45
5243.45
5243.45
5455.5
5455.5
5455.5
5455.5
5641
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
3575.15
3389.65
3204.15
3018.65
3575.15
3389.65
3204.15
3018.65
3575.15
3389.65
3204.15
3018.65
3575.15
3389.65
3204.15
3018.65
5300
5300
5300
5485.5
5485.5
5485.5
5485.5
5641
5641
5641
(1) VINA supplies internal circuitry. Connect VINA to VIN in a single point manner.
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted); all voltages referenced to GND(1)
MIN
–0.5
–0.5
–0.3
–0.3
MAX UNIT
VIN
Input voltage pins
16
16
V
V
VOUT
SS
Output voltage pins
Soft start pin
16
V
EN, OVP
IIN, IOUT
IIN_PLS, IOUT_PLS
TJ
Enable and over voltage protection pins
Continuous switch current
Pulsed switch current (t ≤5 µs)
Junction temperature
7.5
5.4
30
V
A
A
150
150
°C
°C
–55
–65
Tstg
Storage temperature
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If
used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
7.2 ESD Ratings
VALUE
±2000
±500
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
V(ESD)
Electrostatic discharge
V
Charged-device model (CDM), per ANSI/ESDA/JEDEC specification JS-002(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 500-V HBM is possible with the necessary precautions.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 250-V CDM is possible with the necessary precautions.
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7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted); all voltages referenced to GND
MIN
4.5
0
MAX
14
UNIT
V
VIN
Input voltage pins
VOUT
EN, OVP
VINSR
IIN, IOUT
TJ
Output voltage pins
14(1)
7
V
Enable and overvoltage pins
Input voltage slew rate
Continuous switch current
Operating junction temperature(2)
0
V
0.015
3.5
V/µs
A
125
°C
–55
(1) This maximum VOUT voltage is only applicable when the device is disabled (EN = Low). When the device is enabled (EN = High), the
maximum VOUT voltage is the input voltage, VIN.
(2) In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature
may have to be derated. Maximum ambient temperature [TA(max)] is dependent on the maximum operating junction temperature
[TJ(max)], the maximum power dissipation of the device in the application [PD(max)], and the junction-to-ambient thermal resistance of the
part/package in the application (θJA), as given by the equation: TA (max) = TJ(max) –(θJA × PD(max)
)
7.4 Thermal Information
TPS7H2211-SP
THERMAL METRIC(1)
HKR (CFP)
16 PINS
23
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
5.4
7.7
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
1.3
ψθJT
7.4
ψθJB
RθJC(bot)
0.33
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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7.5 Electrical Characteristics
over operating ambient temperature range TA = –55°C to 125°C, VIN = 4.5 to 14 V, COUT = 10 µF, and all voltages
referenced to GND (unless otherwise noted); includes group E radiation testing at TA = 25°C for RHA devices(1)
SUB-
PARAMETER
TEST CONDITIONS
GROUP
MIN
TYP
MAX UNIT
(2)
POWER SUPPLIES AND CURRENTS
VINUVLOR
VINUVLOF
Internal VIN UVLO rising
Internal VIN UVLO falling
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1
3.2
2.6
3.4
2.9
0.55
5
3.8
3.2
V
V
V
HYSTVIN-UVLO Internal VIN UVLO hysteresis
0.75
IQ
Quiescent current
IOUT = 0 mA, EN = 7 V
10 mA
1.3
VIN = 14 V
VIN = 12 V
VIN = 9 V
1
0.65
0.15
0.04
6.9
5.9
4.4
3.7
390
363
264
249
208
247
44
0.94
VIN to VOUT forward leakage
current
EN = 0 V, VOUT = 0 V, measured
VOUT current
IF
mA
mA
0.49
0.23
10
VIN = 4.5 V
VIN = 14 V
VIN = 12 V
VIN = 9 V
9.5
8
EN = 0 V, VOUT = 0 V, measured
VIN current
ISD VIN
VIN off-state supply current
VIN = 4.5 V
VIN = 4.5 V
VIN = 14 V
VIN = 4.5 V
VIN = 14 V
VIN = 4.5 V
VIN = 14 V
7
Reverse current protection enter
voltage(3)
VRCP_ENTER
VRCP_EXIT
tRCP
mV
mV
µs
EN = 7 V, see 图8-1
EN = 7 V, see 图8-2
EN = 7 V, see 图8-1
1
1
Reverse current protection exit
voltage(3)
1
9
Reverse current protection
response time
9
EN = 0 V, VOUT = 0 to 14 V and VOUT > VIN
EN = 7 V, VIN = 0 V, VOUT = 0 to 14 V
1, 2, 3
1, 2, 3
250
240
Reverse current protection leakage
current
IRCP
µA
37
SOFT START
ISS
Soft start charge current
1, 2, 3
65
83 µA
ENABLE (EN) INPUT
VIHEN
EN threshold voltage, rising
1, 2, 3
1, 2, 3
1, 2, 3
9, 10, 11
1, 2, 3
1, 2, 3
0.60
0.50
94
0.63
0.52
109
0.68
0.57
V
V
VILEN
EN threshold voltage, falling
EN hysteresis voltage
HYSTEN
tLOW_OFF
VINEN
IEN
139 mV
µs
EN signal low time during cycling
VIN percentage for enable (4)
EN pin input leakage current
20
VOUT falls to < 90%, see 图8-3
75%
EN = 7 V, VIN = 14 V
2
12
nA
OVERVOLTAGE PROTECTION (OVP)
VOVPR
VOVPF
HYSTOVP
IOVP
OVP threshold voltage, rising
OVP threshold voltage, falling
OVP hysteresis voltage
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1.11
1.09
5
1.15
1.14
14
1.18
1.17
V
V
4.6 V < VIN < 14 V
OVP = 7 V
40 mV
OVP pin input leakage current
1.5
12
nA
CURRENT LIMIT(5)
IL_trip
IL_peak
tftr
Internal current limit trip point
VIN = 12 V, CSS = 2 nF
1
1
9
9
8
25
A
A
Fast trip off current limit peak
Fast trip off response time
Fast trip off off-time
VIN = 12 V, 10 Ω to 10 mΩ short in 1 µs,
switch inductance = 270 nH
2.3
51
µs
µs
tfto
VIN = 12 V, CSS = 2 nF
THERMAL SHUTDOWN
Thermal shutdown
155
20
°C
°C
Thermal shutdown hysteresis
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7.5 Electrical Characteristics (continued)
over operating ambient temperature range TA = –55°C to 125°C, VIN = 4.5 to 14 V, COUT = 10 µF, and all voltages
referenced to GND (unless otherwise noted); includes group E radiation testing at TA = 25°C for RHA devices(1)
SUB-
PARAMETER
TEST CONDITIONS
GROUP
MIN
TYP
MAX UNIT
(2)
RESISTANCE CHARACTERISTICS
3
41
43
54
65
72
41
43
54
65
72
41
43
54
65
72
41
43
54
65
72
44
47
59
71
79
45
46
60
71
79
45
46
60
71
79
45
46
–55°C
–40°C
25°C
VIN = 14 V, IOUT = 3.5 A
1
85°C
125°C
–55°C
–40°C
25°C
2
3
VIN = 12 V, IOUT = 3.5 A
VIN = 9 V, IOUT = 3.5 A
VIN = 6 V, IOUT = 3.5 A
VIN = 4.5 V, IOUT = 3.5 A
1
85°C
125°C
–55°C
–40°C
25°C
2
3
On-state resistance,
RON
mΩ
1
61
71
79
45
47
61
71
79
48
50
65
76
84
lead length ≈2.5 mm
85°C
125°C
–55°C
–40°C
25°C
2
3
1
85°C
125°C
–55°C
–40°C
25°C
2
3
1
2
85°C
125°C
(1) See the 5962-18220 SMD (standard microcircuit drawing) for additional information on the RHA devices.
(2) For subgroup definitions, see the Quality Conformance Inspection table
(3) This parameter is not referenced to GND; it is referenced from VOUT to VIN.
(4) VIN must be ≥75% of its final value before EN is asserted only if VINSR > VOUTSR
.
(5) See 节9.3.2 for additional information on current limits and how the associated parameters are defined.
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7.6 Switching Characteristics
over operating ambient temperature TA = 25°C, COUT = 10 µF, CSS = 2 nF, RLOAD = 10 Ω(unless otherwise noted); all
voltages referenced to GND
PARAMETER
TEST CONDITIONS
SUBGROUP(1)
MIN
TYP
MAX
UNIT
VIN = 5 V
tON
Turn-on time
107
56
167
8
µs
µs
µs
µs
µs
tOFF
Turn-off time
9
9
See 图8-4
See 图8-5
tF
VOUT fall time
OVP assert time
OVP deassert time
tASSERT
tDEASSERT
VIN = 12 V
tON
41
Turn-on time
220
41
139
6
µs
µs
µs
µs
µs
tOFF
Turn-off time
9
9
See 图8-4
See 图8-5
tF
VOUT fall time
OVP assert time
OVP deassert time
tASSERT
tDEASSERT
63
(1) For subgroup definitions, see the Quality Conformance Inspection table
7.7 Quality Conformance Inspection
MIL-STD-883, Method 5005 - Group A
SUBGROUP
DESCRIPTION
Static tests at
TEMPERATURE (°C)
1
2
25
125
–55
25
Static tests at
3
Static tests at
4
Dynamic tests at
Dynamic tests at
Dynamic tests at
5
125
–55
25
6
7
Functional tests at
Functional tests at
Functional tests at
Switching tests at
Switching tests at
Switching tests at
8A
8B
9
125
–55
25
10
11
125
–55
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7.8 Typical Characteristics
6.5
1.3
1.2
1.1
1
VIN = 4.5 V
VIN = 9 V
VIN = 12 V
VIN = 14 V
VIN = 4.5 V
VIN = 9 V
VIN = 12 V
VIN = 14 V
6
5.5
5
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
4.5
4
3.5
-55
-35
-15
5
25
45
65
85
105 125
-55
-35
-15
5
25
45
65
85
105 125
Temperature (°C)
Temperature (°C)
图7-1. IQ vs Temperature Across VIN
图7-2. IF vs Temperature Across VIN
9
8.5
8
100
80
60
40
20
0
VIN = 4.5 V
VIN = 9 V
VIN = 12 V
VIN = 14 V
VOUT = 4.5 V
VOUT = 9 V
VOUT = 12 V
7.5
7
6.5
6
5.5
5
4.5
4
3.5
3
-55
-35
-15
5
25
45
65
85
105 125
-55
-35
-15
5
25
45
65
85
105 125
Temperature (°C)
Temperature (°C)
VIN = 0 V
图7-3. ISD vs Temperature Across VIN
图7-4. IRCP vs Temperature Across VOUT With EN
= 7 V
140
68
VOUT = 4.5 V
VOUT = 9 V
VOUT = 12 V
VOUT = 14 V
VIN = 4.5 V
VIN = 9 V
VIN = 12 V
VIN = 14 V
67.5
120
100
80
60
40
20
0
67
66.5
66
65.5
65
64.5
64
63.5
63
62.5
62
-55
-35
-15
5
25
45
65
85
105 125
-55
-35
-15
5
25
45
65
85
105 125
Temperature (°C)
Temperature (°C)
VIN = 0 V
图7-5. IRCP vs Temperature Across VOUT With EN
图7-6. ISS vs Temperature Across VIN
= 0 V
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0.641
0.528
0.527
0.526
0.525
0.524
0.523
VIN = 4.5 V, 9 V, 12 V, 14 V
VIN = 4.5 V, 9 V, 12 V, 14 V
0.639
0.637
0.635
0.633
0.631
0.629
0.627
-55
-35
-15
5
25
45
65
85
105 125
-55
-35
-15
5
25
45
65
85
105 125
Temperature (°C)
Temperature (°C)
There was no observed VIN dependency across these
measured values
There was no observed VIN dependency across these
measured values
图7-7. VIHEN vs Temperature Across VIN
图7-8. VILEN vs Temperature Across VIN
1.155
1.135
VIN = 4.5 V, 9 V, 12 V, 14 V
VIN = 4.5 V, 9 V, 12 V, 14 V
1.153
1.133
1.151
1.149
1.147
1.145
1.143
1.141
1.139
1.137
1.135
1.131
1.129
1.127
1.125
1.123
1.121
1.119
1.117
1.115
-55
-35
-15
5
25
45
65
85
105 125
-55
-35
-15
5
25
45
65
85
105 125
Temperature (°C)
Temperature (°C)
There was no observed VIN dependency across these
measured values
There was no observed VIN dependency across these
measured values
图7-9. VOVPR vs Temperature Across VIN
图7-10. VOVPF vs Temperature Across VIN
80
80
IOUT = 1 A
IOUT = 1 A
76
72
68
64
60
56
52
48
44
40
76
72
68
64
60
56
52
48
44
40
IOUT = 3 A
IOUT = 3.5 A
IOUT = 3 A
IOUT = 3.5 A
-55
-35
-15
5
25
45
65
85
105 125
-55
-35
-15
5
25
45
65
85
105 125
Temperature (°C)
Temperature (°C)
图7-11. On-Resistance vs Temperature Across
图7-12. On-Resistance vs Temperature Across
Loads at VIN = 4.5 V
Loads at VIN = 6 V
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80
80
76
72
68
64
60
56
52
48
44
40
IOUT = 1 A
IOUT = 3 A
IOUT = 3.5 A
IOUT = 1 A
IOUT = 3 A
IOUT = 3.5 A
76
72
68
64
60
56
52
48
44
40
-55
-35
-15
5
25
45
65
85
105 125
-55
-35
-15
5
25
45
65
85
105 125
Temperature (°C)
Temperature (°C)
图7-13. On-Resistance vs Temperature Across
图7-14. On-Resistance vs Temperature Across
Loads at VIN = 9 V
Loads at VIN = 12 V
80
IOUT = 1 A
76
72
68
64
60
56
52
48
44
40
IOUT = 3 A
IOUT = 3.5 A
-55
-35
-15
5
25
45
65
85
105 125
Temperature (°C)
图7-15. On-Resistance vs Temperature Across Loads at VIN = 14 V
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8 Parameter Measurement Information
VIN + 0.7 V
VOUT
VIN t ìXí V
0.7 V
VRCP_ENTER
VOUT - VIN
-0.1 V
IOUT
0 A
IRCP
tRCP
A. VIN is held constant during the test.
B. VRCP_ENTER is referenced from VOUT to VIN. It is the threshold that, when reached, will turn-off the main switch FETs to prevent reverse
current flow.
图8-1. Reverse Current Protection Enter (VRCP_ENTER) Test Waveforms
VIN + 0.7 V
VOUT
VIN t ìXí V
0.7 V
VRCP_EXIT
-0.1 V
VOUT - VIN
IOUT
IRCP
0 A
A. VIN is held constant during the test.
B. VRCP_EXIT is referenced from VOUT to VIN. It is the threshold that, when reached, will turn-off the reverse current protection feature.
图8-2. Reverse Current Protection Exit (VRCP_EXIT) Test Waveforms
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90% × VIN
IOUT
tLOW_OFF
EN
VIHEN
VIHEN
VILEN
VILEN
t < tLOW_OFF
t ≥ tLOW_OFF
图8-3. EN Signal Low Time to Restart Device (tLOW_OFF
)
50%
EN
tF
tOFF
90%
tON
50%
50%
VOUT
10%
图8-4. Turn-On Time (tON), Turn-Off Time (tOFF), and VOUT Fall Time (tF) Waveforms
1.25 V
1.00 V
1.25 V
1.00 V
VOVPR(MAX)
VOVPR(MIN)
VOVPF(MAX)
VOVPF(MIN)
(OVP Rising
Threshold)
(OVP Falling
Threshold)
OVP
tASSERT
VOUT
tDEASSERT
90% × VOUT
10% × VOUT
A. The OVP test signal uses a typical rise time and fall time of 30 ns.
图8-5. OVP Assert (tASSERT) and OVP Deassert (tDEASSERT) Waveforms
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9 Detailed Description
9.1 Overview
The TPS7H2211-SP device is a single channel, 3.5-A eFuse with a programmable turn-on slew rate (soft start)
and overvoltage protection (OVP). Additionally, the TPS7H2211-SP features reverse current protection capability
for power distribution applications. It is available as a radiation hardness assured device to 100 krad(Si).
9.2 Functional Block Diagram
VIN
Linear
regulator
AVDD
Current
Sense
Overcurrent
Protection
6 V regulator
AVDD
EN
+
VIHEN
VILEN
-
CONTROL
LOGIC
Driver
AVDD
+
OVP
VOVPR
VOVPF
-
VOUT
SS
Thermal
Shutdown
RAMP
CONTROL
GND
ISS
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9.3 Feature Description
9.3.1 Enable and Overvoltage Protection
图 9-1 shows how resistor dividers from VIN connected to the EN and OVP pins can be used to set the enable
and overvoltage trip points.
TPS7H2211-SP
VIN
RTOP_OVP
EN
RTOP_EN
EN
ON
+
OFF
VIHEN
VILEN
-
OVP
OVP
+
VOVPR
VOVPF
-
RBOT_EN
RBOT_OVP
GND
图9-1. Enable and OVP Thresholds Set by Resistor Dividers
The EN pin turns on or turns off the internal switch FETs. An EN voltage greater than VIHEN turns on the switch,
and a voltage less than VILEN turns off the switch. The external resistor divider allows the enable threshold to be
configured for a different enable rising voltage (VINEN_RISE) and a disable falling voltage (VINEN_FALL) based on
the VIHEN and VILEN specifications respectively. Generally, applications are optimized to configure the enable
rising voltage. However, if desired the falling voltage can be configured to use the EN pin as an under voltage
protection (UVP) feature.
Typically RTOP_EN is set to 100 kΩand a value for RBOT_EN is calculated. 节10.2.2.2.2 shows how these resistor
values could be calculated. The enable rising and falling threshold parameters are shown in 图 9-2, and
equations to calculate the resulting rising and falling voltages are shown in 方程式 1 and 方程式 2 respectively.
These equations do not take into account the small EN leakage current which has minimal effect on the results.
Additionally, ensure EN is not asserted before VIN is ≥ 75% of its final value as indicated in the electrical
characteristics footnote (see 节 7.5). This is only required if VINSR > VOUTSR. This requirement is to prevent a
false overcurrent trigger event.
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VINEN_RISE(MAX)
VINEN_RISE(MIN)
VINEN_FALL(MAX)
VINEN_FALL(MIN)
VIN
VIHEN(MAX)
VIHEN(MIN)
VILEN(MAX)
VILEN(MIN)
图9-2. Enable Rising and Falling Thresholds
RTOP _EN + RBOT _EN
VINEN_RISE = V
IHEN
RBOT _EN
(1)
(2)
RTOP _EN + RBOT _EN
VINEN_FALL = V
ILEN
RBOT _EN
Similarly, the overvoltage protection (OVP) feature can be configured using a resistor divider from VIN connected
to the OVP pin. A voltage at the OVP pin greater than VOVPR will turn off the switch FETs, and a voltage less
than VOVPF will keep the switch FETs on. If this feature is not desired, the OVP pin must be grounded.
The OVP feature is intended to protect downstream devices from an overvoltage condition (by turning off the
eFuse if the OVP threshold is reached). The OVP feature does not protect the TPS7H2211-SP eFuse itself from
higher values of VIN. Follow the 14-V maximum VIN value and the 7-V maximum OVP value in the
recommended operating conditions.
Typically RTOP_OVP is set to 100 kΩ and a value for RBOT_OVP is calculated. 节 10.2.1.2.3 shows how these
resistor values could be calculated. The OVP rising and falling threshold parameters are shown in 图 9-3, and
equations to calculate the resulting rising and falling voltages are shown in 方程式 3 and 方程式 4 respectively.
These equations do not take into account the small OVP leakage current which has minimal effect on the results.
VINOVP_RISE(MAX)
VINOVP_RISE(MIN)
VINOVP_FALL(MAX)
VINOVP_FALL(MIN)
VIN
VOVPR(MAX)
VOVPR(MIN)
VOVPF(MAX)
VOVPF(MIN)
图9-3. OVP Rising and Falling Thresholds
RTOP _ OVP + RBOT _ OVP
VINOVP _RISE = VOVPR
RBOT _ OVP
(3)
RTOP _ OVP + RBOT _ OVP
VINOVP _FALL = VOVPF
RBOT _ OVP
(4)
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9.3.2 Current Limit
There is an internal current limit intended to protect the TPS7H2211-SP against hard short circuit conditions. 图
9-4 shows a short circuit condition followed by an immediate recovery. The TPS7H2211-SP internal short circuit
protection trips at IL_trip. It takes time tftr, for the internal circuitry to respond to the short circuit condition. Before
the current limit circuitry responds, the current through the switch will continue to rise to a peak value, IL_peak. At
this point the current limit circuitry responds and quickly turns off the switch. As there is no active discharge on
VOUT, the rate of discharge will depend on external factors such as the short condition and COUT. The switch
will stay off for time tfto, before turning-on again.
tftr
tSS
IL_peak
tfto
IL_trip
TIME
Normal operation
Fast trip mode
Normal Operation
Startup
Fault is no longer present
TIME
Startup
Normal operation
Fast trip mode
Normal Operation
A. The following values were measured at VIN = 12 V, a parasitic switch inductance nominal value of 270 nH, and ROUT changing from 10
Ωto 10 mΩin 1 μs:
•
•
•
•
IL_trip(typ) = 8.5 A
tftr(typ) = 2.3 μs
IL_peak(typ) = 25 A
tfto(typ) = 51 μs
图9-4. Single Hard Short and Recovery
As shown in 图 9-4, the TPS7H2211-SP is designed to quickly respond to a hard fault condition to minimize the
current peak. IL_trip and tftr are highly dependent upon the actual fault conditions.
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While 图 9-4 shows a hard short condition that immediately recovers, 图 9-5 shows a hard short condition that
does not immediately recover. Instead, the device twice enters the fast trip mode before the fault is removed.
CAUTION
A short will repeat indefinitely until the short is removed or until the device is disabled. The
TPS7H2211-SP is not intended to remain in this mode indefinitely.
tftr
tSS
IL_peak
Fault is still
present
tfto
tfto
IL_trip
TIME
Normal operation
Fast trip mode
Fast trip mode
Normal Operation
Startup
Startup
Fault is no longer present
TIME
Normal operation
Fast trip mode
Fast trip mode
Startup
Normal Operation
Startup
图9-5. Two Hard Shorts and Recovery
9.3.3 Soft Start (Adjustable Rise Time)
An external capacitor, CSS, connected between the VOUT and SS pins, sets tSS, the soft start time. tSS is defined
as the time it takes VOUT to rise from 10% to 90% of its final value. 方程式 5 calculates the needed CSS
capacitor where ISS is the soft start current (typically 65 μA) and VOUT is the final output voltage reached (for
example, 12 V).
tSS × ISS
Css
=
VOUT × 0.8
(5)
In order to avoid false trips due to the internal current limit being triggered during startup, the slew rate VOUTSR
,
must satisfy 方程式 6 where IL_trip is the internal current limit trip point (typically 8.5 A), IOUT is the final output
current (max of 3.5 A), and COUT is the output capacitance. In the Application and Implementation Soft Start
Time section, a suggested derated value for IL_TRIP is shown.
If external current limit circuitry is used, it is recommended to replace the IL_trip value with the minimum trip-point
value of the external current limit (assuming this trip-point is less than IL_trip). This is in order to ensure the
external current limit circuitry isn't tripped during startup.
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IL_trip F IOUT
VOUTSR
<
COUT
(6)
The output slew rate of the eFuse, VOUTSR, can be calculated as shown in 方程式 7. To determine the worst
case slew rate, it is recommended to use the maximum value of ISS, 83 μA, and the minimum value of the
selected capacitor. These worst case conditions may also be used to calculate the worst case (fastest) tSS time.
ISS
VOUT × 0.8
tSS
VOUTSR
=
=
CSS
(7)
9.3.4 Parallel Operation
The TPS7H2211-SP can be configured in parallel operation either to increase the current capability, up to nearly
7 A, or to reduce the on-state resistance. In this case, all pins are shared as shown in 图9-6.
Since the SS pin sinks current, the combined pins result in a doubled current sink value; consequently the
calculated capacitance values must be doubled. The EN and OVP pins have no additional changes from the
non-parallel case as they are high impedance inputs.
VIN
VOUT
COUT
VIN
VOUT
SS
RTOP_EN
RTOP_OVP
CSS
EN
EN
SS
TPS7H2211-SP
OVP
OVP
RBOT_EN
RBOT_OVP
GND
VIN
EN
VOUT
SS
EN
SS
OVP
OVP
TPS7H2211-SP
GND
图9-6. Parallel Configuration to Reduce Resistance or Increase Current Capability
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9.3.5 Reverse Current Protection
The TPS72211-SP eFuse features back to back FETs to prevent current flow from VIN to VOUT and from VOUT
to VIN when the switch is disabled (excluding leakage currents). This supports cold sparing (redundancy)
applications. For example, VOUT may be up to 14 V while VIN is between 0 V and 14 V. In all cases, only small
leakage current will result.
Additionally, the eFuse features active reverse current protection when the switch is enabled. This protection
feature is activated when VOUT rises above VIN by VRCP_ENTER (typically 363 mV at VIN = 14 V) which causes
the switch to turn-off. After VRCP_ENTER is reached, it will take time, tRCP (typically 247 μs at VIN = 14 V) for the
switch to turn off. Until the switch responds and turns off, there may be high reverse current through the switch.
After this time, only a small amount of leakage current, IRCP, will result from VOUT to VIN (typically 40 μA). The
switch will again be enabled after VOUT –VIN falls to less than or equal to VRCP_EXIT (typically 249 mV at VIN =
14 V).
The test waveforms for VRCP_ENTER and VRCP_EXIT can be found in 图8-1 and 图8-2 respectively.
9.3.6 Forward Leakage Current
When VIN is powered but the TPS7H2211-SP is disabled (EN is low), the internal FETs are disabled, creating a
high impedance path from VIN to VOUT. However, there are parasitic leakage paths that could cause VOUT to
slowly charge. The forward leakage current, IF, indicates how much current flows from VIN to VOUT during this
situation. This is typically 0.65 mA at VIN = 12 V but could be a maximum of 1.3 mA at 14 V.
Some applications may tolerate these leakage mechanisms while some applications may need to pay particular
attention to this behavior. It is particularly relevant when VOUT is a high impedance node (and therefore the
leakage current goes entirely to charging VOUT instead of being dissipated). By using the basic capacitor
equation shown in 方程式8, the time for the voltage to rise to a given value can be theoretically calculated.
Δt = ΔVOUT × COUT / IF
(8)
where
• Δt = time to charge to final value
• ΔVOUT = change in output voltage; for a 0 V starting voltage, use VIN
For example, with a 12-V input voltage and a 220-µF output capacitance, VOUT will typically charge to 12 V in
4.1 seconds (using IF = 0.65 mA, ΔVOUT = 12 V, COUT = 220 µF).
If the output voltage must remain below a certain value, a pull-down resistor can be utilized with a value as
calculated by 方程式9.
VOUTLKG_MAX = IF × RPULL_DOWN
(9)
where
• VOUTLKG_MAX = maximum output voltage due to leakage current, IF
• RPULL_DOWN = external pull-down resistor from VOUT to GND
For example, placing a 1-kΩ resistor between VOUT and ground will ensure VOUT does not rise above 0.65-V
typically or 1.3-V worse case due to the IF current. It is recommended to ensure the resistor can handle the worst
case power dissipation when the switch is enabled and VOUT ≈VIN.
9.4 Device Functional Modes
表9-1 lists the state of the eFuse for a given EN input voltage.
表9-1.
EN PIN
SWITCH STATUS
VEN < VILEN
OFF: VOUT = Open
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表9-1. (continued)
EN PIN
SWITCH STATUS
VEN > VIHEN
ON: VOUT ≈VIN
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10 Application and Implementation
备注
以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。
10.1 Application Information
The TPS7H2211-SP device is a single channel, 3.5-A eFuse with configurable features such as overvoltage
protection, soft start, and enable. Additionally, the TPS7H2211-SP features reverse current protection for power
distribution applications.
10.2 Typical Applications
The following list shows just a few of the multiple applications for the TPS7H2211-SP eFuse. The first two are
discussed in further detail.
• Cold sparing (redundancy) for primary and secondary (redundant) voltage rails (common in satellites)
• Protection of loads from upstream latch-up sensitive converters
• Power rail sequencing
• Power multiplexing
• Power system ORing
10.2.1 Application 1: Cold Sparing
In applications where a primary and secondary (redundant) power rails are present, the TPS7H2211-SP readily
implements cold sparing because of its reverse current blocking capability. Generally, the primary eFuse will be
enabled. If there is a reason to switch to the secondary rail, the primary eFuse will be turned-off and the
secondary eFuse will be turned-on. In this cold sparing application, since the eFuse is placed at the input of the
point of load regulator, the on-resistance of the switch is not highly critical.
5 V
12 V
12 V Primary
VIN
EN
VOUT
SS
TPS7A4501-SP
CSS
COUT
CIN
EN
Primary
TPS7H2211-SP
RTOP_OVP
OVP
GND
RBOT_OVP
12 V Secondary
CIN
VIN
EN
VOUT
SS
COUT
CSS
EN
Secondary
TPS7H2211-SP
RTOP_OVP
OVP
GND
RBOT_OVP
图10-1. Cold Sparing Example Using the TPS7H2211-SP
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10.2.1.1 Design Requirements
表10-1 shows the design parameters used for this example.
表10-1. Design Parameters
DESIGN PARAMETER
REQUIREMENT
VIN, input voltage
12 V ± 5%
Not applicable - will control EN pin from central
controller
VINEN, turn-on voltage
VINOVP_RISE, overvoltage protection set point
IOUT, switch current
13.5 V
3 A
tSS, VOUT soft start time
10 ms
10.2.1.2 Detailed Design Procedure
10.2.1.2.1 Capacitance
At least a 10-µF output capacitor is recommended on VOUT. Additionally, a capacitor on VIN is recommended in
order to keep the input stable. However, it is generally advisable to use higher capacitance values to align with
the TI EVM (evaluation module) and the radiation testing configuration (mostly relevant for SETs on VOUT as a
higher capacitance generally reduces the SETs). A good higher capacitance value is 170.1 µF–specifically, 1 ×
150-μF tantalum, 2 × 10-μF ceramic, and 1 × 0.1-μF ceramic capacitors. This is what is selected for this
design for both the input and output capacitance.
10.2.1.2.2 Enable Control
The EN pin controls the state of the eFuse. Bringing EN high turns on the switch and bringing EN low turns off
the switch. In a cold sparing application, only one of the switches is to be enabled at a given time. This EN signal
can be controlled from external circuitry. For example, a microcontroller or FPGA may interface to the eFuses
through two GPIO pins. The TPS7H2211-SP is compatible with a variety of logic levels such as 1.1-V logic.
When the primary 12-V rail is to be used, EN of the primary eFuse is set high while the EN of the secondary
eFuse remains low. If there is an issue with the primary rail, the secondary rail can instead be used. To make this
change, first deassert the EN pin of the primary eFuse. Then assert the EN pin of the secondary eFuse. If both
pins are enabled at the same time, reverse current flow in one of the eFuses may result. While there is internal
reverse current protection circuitry in the eFuses, it is simple to avoid this problem through proper EN
sequencing.
10.2.1.2.3 Overvoltage Protection
The overvoltage protection is set by configuring the RBOT_OVP and RTOP_OVP resistors. The overvoltage
protection feature turns off the switch if the input voltage exceeds a predetermined value as described in 节
9.3.1. For this design, the goal is to have the overvoltage protection activate at a nominal voltage of 13.5 V. First
set RTOP_OVP = 100 kΩ with a 0.1% tolerance resistor, then use 方程式 10 to calculate the nominal value of
R
BOT_OVP. A nominal 9.31-kΩ0.1% tolerance resistor best satisfies the equation.
VOVPR TYP ìRTOP _ OVP
(
)
RBOT _ OVP
=
VINOVP _RISE - VOVPR TYP
(10)
where
• VOVPR(TYP) = 1.15 V
• RTOP_OVP = 100 kΩ
• VINOVP_RISE = 13.5 V
In order to ensure the selected RBOT_OVP value is acceptable for both the minimum and maximum OVP rising
threshold, use 方程式 11. VINOVP_RISE(MIN) is selected as the highest possible value that VIN will reach during
nominal operation (to prevent false OVP trips). VINOVP_RISE(MAX) may be selected by the user as long as it is
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within the VIN Recommended Operating Conditions. These selections result in an allowable value of RBOT_OVP
between 9.214 kΩ and 9.650 kΩ. The selected 9.31-kΩ 0.1% tolerance resistor satisfies these constraints,
even when taking into account its tolerance.
VOVPR MAX ìRTOP _OVP ì 1+ R
VOVPR MIN ìRTOP _OVP ì 1-R
tolerance
(
)
(
)
tolerance
(
)
(
)
Ç RBOT _OVP
Ç
VINOVP _RISE MAX - VOVPR MAX
VINOVP _RISE MIN - VOVPR MIN
(
)
(
)
(
)
(
)
(11)
where
• VOVPR(MAX) = 1.18 V
• RTOP_OVP = 100 kΩ
• Rtolerance = 0.01% = 0.001
• VINOVP_RISE(MAX) = 14 V
• VOVPR(MIN) = 1.11 V
• VINOVP_RISE(MIN) = VIN × (1 + tolerance) = 12.6 V
Since the OVP pin has hysteresis, the OVP falling threshold will be different than the rising threshold. Therefore,
in order to ensure the selected RBOT_OVP value is acceptable for the OVP falling threshold, use 方程式 12.
VINOVP_FALL(MIN) and VINOVP_FALL(MAX) values may be selected using the same method as for VINOVP_RISE(MIN)
and VINOVP_RISE(MAX). These selections results in an allowable RBOT_OVP value between of 9.129 kΩ and 9.460
kΩ. The selected 9.31-kΩ 0.1% tolerance resistor also satisfies these constraints, even when taking into
account its tolerance.
VOVPF MAX ìRTOP _ OVP ì 1+ R
VOVPF MIN ìRTOP _ OVP ì 1-R
tolerance
(
)
(
)
tolerance
(
)
(
)
Ç RBOT _ OVP
Ç
VINOVP _FALL MAX - VOVPF MAX
VINOVP _FALL MIN - VOVPF MIN
(12)
where
• VOVPF(MAX) = 1.17 V
• RTOP_OVP = 100 kΩ
• Rtolerance = 0.001
• VINOVP_FALL(MAX) = 14 V
• VOVPF(MIN) = 1.09 V
• VINOVP_FALL(MIN) = VIN × (1 + tolerance) = 12.6 V
To summarize, using 方程式 3 and 方程式 4 with RTOP_OVP = 100 kΩ and RBOT_OVP = 9.31 kΩ, the eFuse will
nominally go into overvoltage protection mode at 13.50 V and exit at 13.38 V. Taking into account the minimum
and maximum OVP pin threshold and resistor tolerances, the switch will enter over voltage protection mode
between 13.01 V and 13.88 V and exit between 12.77 V and 13.76 V.
CAUTION
The eFuse input voltage must remain within the recommended operating conditions (which contain a
maximum VIN of 14 V). If OVP is configured above 14 V, then the OVP mode should only be used
as a last resort feature. The eFuse is not intended to be above 14 V.
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10.2.1.2.4 Soft Start Time
The desired 10-ms soft start time is achieved following the procedure in 节 9.3.3. The procedure is replicated
below for convenience.
First, use 方程式 13 to determine the needed value of CSS. This results in a calculated CSS value of 67.7 nF. A
68-nF ±10% capacitor is selected.
tSS × ISS
Css
=
VOUT × 0.8
(13)
where
• tSS = 10 ms = 10 × 10–3 s
• ISS(TYP) = 65 μA = 65 × 10–6 A
• VOUT(NOM) = 12 V
Next determine the resulting slew rate using 方程式 14. Using the minimum value for the 10% tolerance CSS and
the maximum value for ISS results in the worst case (fastest) slew rate of 1,356 V/s.
ISS
VOUT × 0.8
tSS
VOUTSR
=
=
CSS
(14)
where
• ISS(MAX) = 83 μA = 83 × 10–6 A
• CSS = 68 nF × (1 –10%) = 61.2 × 10–9 F
Finally, determine if the resulting slew rate is less than the maximum allowed by 方程式 15. IL_trip is typically 8.5
A, but in order to select a conservative value it is suggested to let IL_trip = 5.4 A (which is also the absolute
maximum rating for continuous switch current). The 1,356-V/s slew rate is less than the maximum acceptable
slew rate of 14,109 V/s. Therefore, this soft start capacitor is acceptable.
IL_trip F IOUT
VOUTSR
<
COUT
(15)
where
• IL_trip = 5.4 A
• IOUT(NOM) = 3.0 A
• COUT = 170.1 μF = 170.1 × 10–6 F
While it is typically trivial to meet the slew rate restrictions, note that for space applications a large output
capacitor is often utilized. This results in a lower maximum acceptable slew rate and additional care must be
taken in order to ensure the expected slew rate is not too fast.
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10.2.1.2.5 Summary
The final component values are shown in 图10-2.
12 V Primary
12 V
5 V
VIN
VOUT
SS
2x0.1µF 2x10µF
TPS7A4501-SP
150µF
150µF 2x10µF 2x0.1µF
68nF
EN
Primary
EN
TPS7H2211-SP
100kQ
OVP
GND
9.31kQ
12 V Secondary
VIN
VOUT
SS
2x0.1µF 2x10µF
150µF
150µF 2x10µF 2x0.1µF
68nF
EN
Secondary
EN
TPS7H2211-SP
100kQ
OVP
GND
9.31kQ
图10-2. Cold Sparing Example With Calculated Component Values
10.2.1.3 Application Curve
图10-3 shows the first eFuse being enabled. 图10-4 shows the first eFuse being powered down and the second
device being powered up (switch from primary to secondary power). The less time both switches are turned-off,
the less droop on VOUT.
图10-3. Power-Up Behavior of Primary TPS7H2211-
图10-4. Switch From Primary to Secondary
SP in a Cold Sparing Application
TPS7H2211-SP in a Cold Sparing Application
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10.2.2 Application 2: Protection
The TPS7H2211-SP can be used to protect a load from an upstream latchup sensitive regulator. The eFuse will
provide overvoltage protection (OVP) and under-voltage protection (by using the EN pin). If the upstream
regulator fails, the eFuse will disconnect the load from the regulator. The load could then be powered by a
redundant supply (see the Application 1: Cold Sparing section).
In this configuration, the on-resistance of the switch is more important as it is placed after the point of load
regulator. Two eFuses can be placed in parallel to further reduce the on-resistance. In the design example
shown here, it was determined only one eFuse was needed.
12 V
5 V
5 V
VIN
VIN
VOUT
SS
Latchup
Sensitive
Regulator
CSS
Load
RTOP_EN
RTOP_OVP
TPS7H2211-SP
EN
RBOT_EN
OVP
GND
RBOT_OVP
图10-5. Protection Example Using the TPS7H2211-SP
10.2.2.1 Design Requirements
表10-2 shows the design parameters used for this example.
表10-2. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
VIN, input voltage
5 V ± 2%
4.5 V
5.4 V
3 A
VINEN, turn-on voltage
VINOVP_RISE, overvoltage protection set point
IOUT, switch current
tSS, VOUT soft start time
1 ms
10.2.2.2 Detailed Design Procedure
10.2.2.2.1 Capacitance
Similarly to 节 10.2.1.2.1, 170.1 µF of input and output capacitance is selected–specifically, 1 × 150-μF
tantalum, 2 × 10-μF ceramic, and 1 × 0.1-μF ceramic capacitors.
10.2.2.2.2 Enable Control
The enable threshold is set by configuring the RBOT_EN and RTOP_EN resistors in order to turn on the switch at the
desired input voltage as described in 节 9.3.1. For this design, the goal is to turn on the switch when VIN
reaches 4.5 V. First we set RTOP_EN = 100 kΩ with a 0.1% tolerance resistor, and then use 方程式 16 to
calculate the nominal RBOT_EN. A 16.2-kΩ0.1% tolerance resistor is found to best satisfy the equation.
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V
) ìRTOP _EN
IHEN TYP
(
RBOT _EN
=
VINEN_RISE - V
IHEN TYP
(16)
where
• VIHEN(TYP) = 0.63 V
• RTOP_EN = 100 kΩ
• VINEN_RISE = 4.5 V
Additionally, it should be ensured the worst case minimum and maximum turn-on voltages are acceptable. The
minimum turn-on voltage would ideally be above 4.5 V (the minimum operating voltage). However, in this case
that is not possible to achieve, and it is acceptable to allow the minimum turn-on voltage to be lower than 4.5 V
(such as 4.2 V). Note however that the device will not be fully operational until at least 4.5 V is reached. This is
okay in this case since the VIN voltage will quickly rise to above 4.5 V which puts the device in a fully operational
state. The eFuse maximum turn-on voltage must be less than the minimum final VIN value (which is 4.9 V as
determined by the 2% tolerance on the 5-V rail). The maximum turn-on voltage can be calculated using 方程式
17. It is determined that VINEN_RISE(MAX) = 4.89 V which is under 4.9 V.
:
;
:
RTOP _EN × 1 + Rtolerance + RBOT _EN × 1 F Rtolerance
;
VINEN_RISE (MAX ) = V
×
IHEN (MAX )
:
RBOT _EN × 1 F Rtolerance
;
(17)
where
• VIHEN(MAX) = 0.68 V
• RTOP_EN = 100 kΩ
• RBOT_EN = 16.2 kΩ
• Rtolerance = 0.1% = 0.001
An alternative method to ensure the selected RBOT_EN value is acceptable for both the minimum and maximum
enable thresholds is to select minimum and maximum values for VINEN_RISE and VINEN_FALL and ensure 方程式
18 and 方程式19 are satisfied.
V
ìRTOP _EN ì 1+ R
V
ìRTOP _EN ì 1-R
(
)
(
)
tolerance
tolerance
VINEN_RISE MIN - V
IHEN MIN
IHEN MAX
(
IHEN MIN
)
(
)
Ç RBOT _EN
Ç
VINEN_RISE MAX - V
IHEN MAX
(18)
V
ìRTOP _EN ì 1+ R
V
ìRTOP _EN ì 1-R
(
)
(
)
tolerance
tolerance
VINEN_FALL MIN - V
ILEN MIN
ILEN MAX
(
ILEN MIN
)
(
)
Ç RBOT _EN
Ç
VINEN_FALL MAX - V
IHLN MAX
(19)
To summarize, using 方程式 1 and 方程式 2 with RTOP_EN = 100 kΩ and RBOT_EN = 16.2 kΩ, shows the eFuse
will nominally turn on at 4.52 V and turn off at 3.73 V. The turn-off voltage is different due to the enable pin
hysteresis. Taking into account the maximum and minimum EN pin thresholds and resistor tolerances the switch
will turn on between 4.30 V and 4.89 V and turn off between 3.58 V and 4.10 V. To change the turn-off levels
requires changing the turn-on levels. The turn-off level will act as an under voltage protection (UVP) feature to
protect the downstream circuitry from receiving a sustained voltage under 3.58 V (which could potentially put the
circuit in an undefined state).
Additionally, as the turn-on voltage minimum is 4.30 V, this is greater than 75% of the final VIN value (4.30 V >
4.9 V × 0.75 = 3.68 V). Therefore, there is no EN and slew rate related requirements as indicated in the electrical
characteristics footnote (see 节 7.5). If the device was enabled under 3.68 V (not advised; this is less than the
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recommended operating VIN voltage of 4.5 V), the output voltage slew rate must be less than the input voltage
slew rate or a false overcurrent trigger may occur.
10.2.2.2.3 Overvoltage Protection
The TPS7H2211-SP eFuse is exceptionally well suited to provide overvoltage protection in this application. This
is because even if the upstream regulator fails in a manner that shorts its input to output (12 V), the TPS7H2211-
SP eFuse is able to handle up to 14 V at the input with full data sheet specified performance.
The overvoltage protection is set by configuring the RBOT_OVP and RTOP_OVP resistors similarly to 节 10.2.1.2.3.
The overvoltage protection feature turns off the switch if the input voltage exceeds a predetermined value. For
this design, the goal is to have the overvoltage protection activate at a nominal voltage of 5.4 V. First set
RTOP_OVP = 100 kΩ with a 0.1% tolerance resistor, then use 方程式 20 to calculate the nominal value of
RBOT_OVP. A nominal 27-kΩ0.1% tolerance resistor best satisfies the equation.
VOVPR TYP ìRTOP _ OVP
(
)
RBOT _ OVP
=
VINOVP _RISE - VOVPR TYP
(20)
where
• VOVPR(TYP) = 1.15 V
• RTOP_OVP = 100 kΩ
• VINOVP_RISE = 5.4 V
In order to ensure the selected RBOT_OVP value is acceptable for both the minimum and maximum OVP rising
threshold, use 方程式 21. VINOVP_RISE(MIN) is selected as the highest possible value that VIN will reach during
nominal operation. VINOVP_RISE(MAX) may be selected by the user as long as it is within the VIN Recommended
Operating Conditions. These selections result in an allowable value of RBOT_OVP between 9.214 kΩ and 27.791
kΩ. The selected 27 kΩ-0.1% tolerance resistor satisfies these constraints, even when taking into account its
tolerance.
VOVPR MAX ìRTOP _OVP ì 1+ R
VOVPR MIN ìRTOP _OVP ì 1-R
tolerance
(
)
(
)
tolerance
(
)
(
)
Ç RBOT _OVP
Ç
VINOVP _RISE MAX - VOVPR MAX
VINOVP _RISE MIN - VOVPR MIN
(
)
(
)
(
)
(
)
(21)
where
• VOVPR(MAX) = 1.18 V
• RTOP_OVP = 100 kΩ
• Rtolerance = 0.01% = 0.001
• VINOVP_RISE(MAX) = 14 V
• VOVPR(MIN) = 1.11 V
• VINOVP_RISE(MIN) = VIN × (1 + tolerance) = 5.1 V
Since the OVP pin has hysteresis, the OVP falling threshold will be different than the rising threshold. Therefore,
in order to ensure the selected RBOT_OVP value is acceptable for the OVP falling threshold, use 方程式 22.
VINOVP_FALL(MIN) and VINOVP_FALL(MAX) values may be selected using the same method as for VINOVP_RISE(MIN)
and VINOVP_RISE(MAX). These selections results in an allowable RBOT_OVP value between of 9.128 kΩ and
27.154 kΩ. The selected 27 kΩ-0.1% tolerance resistor also satisfies these constraints, even when taking into
account its tolerance.
VOVPF MAX ìRTOP _ OVP ì 1+ R
VOVPF MIN ìRTOP _ OVP ì 1-R
tolerance
(
)
(
)
tolerance
(
)
(
)
Ç RBOT _ OVP
Ç
VINOVP _FALL MAX - VOVPF MAX
VINOVP _FALL MIN - VOVPF MIN
(22)
where
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• VOVPF(MAX) = 1.17 V
• RTOP_OVP = 100 kΩ
• Rtolerance = 0.001
• VINOVP_FALL(MAX) = 14 V
• VOVPF(MIN) = 1.09 V
• VINOVP_FALL(MIN) = VIN × (1 + tolerance) = 5.1 V
To summarize, using 方程式 3 and 方程式 4 with RTOP_OVP = 100 kΩ and RBOT_OVP = 27 kΩ, the eFuse will
nominally go into overvoltage protection mode at 5.41 V and exit at 5.36 V. Taking into account the minimum and
maximum OVP pin threshold and resistor tolerances, the switch will enter overvoltage protection mode between
5.21 V and 5.56 V and exit between 5.12 V and 5.51 V.
10.2.2.2.4 Soft Start Time
The desired 1-ms soft start time is achieved following the procedure in 节 9.3.3. The procedure is replicated
below for convenience.
First, use 方程式 23 to determine the needed value of CSS. This results in a calculated CSS value of 16.3 nF. A
22-nF ±10% capacitor is selected.
tSS × ISS
Css
=
VOUT × 0.8
(23)
where
• tSS = 1 ms = 1 × 10–3 s
• ISS(TYP) = 65 μA = 65 × 10–6 A
• VOUT(NOM) = 5 V
Next determine the resulting slew rate using 方程式 24. Using the minimum value for the 10% tolerance CSS and
the maximum value for ISS results in the worst case (fastest) slew rate of 4,192 V/s.
ISS
VOUT × 0.8
tSS
VOUTSR
=
=
CSS
(24)
where
• ISS(MAX) = 83 μA = 83 × 10–6 A
• CSS = 22 nF × (1 –10%) = 19.8 × 10–9 F
Finally, determine if the resulting slew rate is less than the maximum allowed by 方程式 25. IL_trip is typically 8.5
A, but in order to select a conservative value it is suggested to let IL_trip = 5.4 A (which is also the absolute
maximum rating for continuous switch current). The 2,955-V/s slew rate is less than the maximum acceptable
slew rate of 4,192 V/s. Therefore, this soft start capacitor is acceptable.
IL_trip F IOUT
VOUTSR
<
COUT
(25)
where
• IL_trip = 5.4 A
• IOUT(NOM) = 3.0 A
• COUT = 170.1 μF = 170.1 × 10–6 F
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While it is typically trivial to meet the slew rate restrictions (as demonstrated here by selecting a relatively fast
soft start time), note that for space applications a large output capacitor is often utilized. This results in a lower
maximum acceptable slew rate and additional care must be taken in order to ensure the expected slew rate is
not too fast.
10.2.2.2.5 Summary
The final calculated values are shown in 图10-6.
12 V
5 V
22nF
5 V
VIN
VIN
VOUT
SS
2x0.1µF 2x10µF
150µF
150µF 2x10µF 2x0.1µF
Latchup
Sensitive
Regulator
Load
100kQ
16.2kQ
100kQ
TPS7H2211-SP
EN
OVP
GND
27kQ
图10-6. Final Schematic With Component Values for the Protection Application
10.2.2.3 Application Curve
图 10-7 shows how a 12 V overvoltage event trips the overvoltage protection (OVP) circuitry to protect the
downstream load. 图10-8 shows how the switch will turn-off if the voltage falls too far.
图10-7. Overvoltage Protection of TPS7H2211-SP
图10-8. Undervoltage Turn-Off of TPS7H2211-SP in
in Protection Application
Protection Application
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11 Power Supply Recommendations
The TPS7H2211-SP is designed to operate from a wide input voltage supply range between 4.5 V to 14 V. This
supply voltage must be well regulated and proper local bypass capacitors must be used for proper electrical
performance from VIN to GND. Due to stringent requirements for space applications, typically numerous input
bypass capacitors are used and the total capacitance is much larger than for commercial applications. The
TPS7H2211-SP evaluation module uses 1 × 150-µF tantalum capacitor in parallel with 2 × 10-µF ceramic
capacitors and 1 × 0.1-µF ceramic capacitor.
12 Layout
12.1 Layout Guidelines
For best performance, make all traces as short as possible. Place the input and output capacitors close to the
device to minimize the effects that parasitic trace inductances may have on normal operation. Use wide traces
for VIN, VOUT, and GND to help minimize the parasitic electrical effects. Pay particular attention to minimizing
the length of the CSS capacitor connection between VOUT and SS in order to minimize stray inductance.
Use thermal vias for the thermal pad to ensure the device remains at allowable temperatures, especially during
fault conditions (such as a short at VOUT). As the thermal pad is internally connected to GND, TI recommends
the vias be connected to a large GND plane on the printed circuit board.
12.2 Layout Example
16
15
14
13
1
2
3
4
VOUT
VOUT
VOUT
VOUT
SS
VIN
VIN
VIN
VIN
NC
As close to the
device as possible
TPS7H2211-SP
12
11
5
6
NC
EN
10
9
7
8
NC
OVP
GND
NC
Thermal vias
图12-1. Layout Recommendation
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13 Device and Documentation Support
13.1 Device Support
13.2 Documentation Support
13.2.1 Related Documentation
For related documentation see the following:
• Texas Instruments, TPS7H2211-SP Total Ionizing Dose (TID) radiation report
• Texas Instruments, TPS7H2211-SP Single-Event Effects (SEE) radiation report
• Texas Instruments, TPS7H2211EVM-CVAL Evaluation Module user's guide
• Texas Instruments, Basics of Load Switches application report
• Texas Instruments, Basics of eFuses application report
13.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
13.4 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
13.5 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
13.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
13.7 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
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14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Jun-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
5962-1822001VXC
ACTIVE
CFP
HKR
16
1
RoHS-Exempt
& Green
NIAU
N / A for Pkg Type
-55 to 125
5962-1822001VXC
TPS7H2211MHKRV
Samples
5962R1822001V9A
5962R1822001VXC
ACTIVE
ACTIVE
XCEPT
CFP
KGD
HKR
0
25
1
RoHS & Green
Call TI
NIAU
N / A for Pkg Type
N / A for Pkg Type
-55 to 125
-55 to 125
Samples
Samples
16
RoHS-Exempt
& Green
5962R1822001VXC
TPS7H2211MHKRV
TPS7H2211HKR/EM
TPS7H2211Y/EM
ACTIVE
ACTIVE
CFP
HKR
KGD
16
0
1
5
RoHS-Exempt
& Green
NIAU
N / A for Pkg Type
N / A for Pkg Type
25 to 25
25 to 25
TPS7H2211HKR/EM
EVAL ONLY
Samples
Samples
XCEPT
RoHS & Green
Call TI
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Jun-2022
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Feb-2022
TUBE
*All dimensions are nominal
Device
Package Name Package Type
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
5962-1822001VXC
5962R1822001VXC
TPS7H2211HKR/EM
HKR
HKR
HKR
CFP
CFP
CFP
16
16
16
1
1
1
506.98
506.98
506.98
26.16
26.16
26.16
6220
6220
6220
NA
NA
NA
Pack Materials-Page 1
PACKAGE OUTLINE
HKR0016A
CFP - 2.416 mm max height
S
C
A
L
E
0
.
7
0
0
CERAMIC DUAL FLATPACK
9.88
9.38
B
METAL LID
A
PIN 1 ID
14X 1.27
16
1
11.26
10.76
(10.41)
2X 8.89
8
9
0.482
16X
0.382
(9.14)
0.2
C A B
METAL LID
C
2.416
1.850
0.177
0.097
(6.59)
1.04
0.84
25.142
24.642
HEATSINK
8
9
8.95
8.65
16
1
6.74
6.44
PIN 1 ID
4226020/C 08/2022
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This package is hermetically sealed with a metal lid. Lid is connected to Heatsink.
4. The terminals are gold plated.
5. Falls within MIL-STD-1835 CDFP-F11A.
www.ti.com
EXAMPLE BOARD LAYOUT
HKR0016A
CFP - 2.416 mm max height
CERAMIC DUAL FLATPACK
(6.59)
(1.2) TYP
(0.6)
(1.2) TYP
(0.6)
(8.8)
PKG
(
0.2) TYP
(R0.05) TYP
PKG
HEATSINK LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:10X
4226020/C 08/2022
www.ti.com
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相关型号：
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