TPS92643QPWPRQ1 [TI]
汽车类 3A 同步降压 LED 驱动器 | PWP | 16 | -40 to 125;
| 型号： | TPS92643QPWPRQ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 汽车类 3A 同步降压 LED 驱动器 | PWP | 16 | -40 to 125 驱动 驱动器 |
| 文件： | 总39页 (文件大小：2789K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS92643-Q1
ZHCSQK6 –MAY 2022
TPS92643-Q1 汽车3A 同步降压LED 驱动器
TPS92643-Q1 采用 6.6mm × 5.1mm 热增强型 16 引
脚HTSSOP 封装，引线间距为0.65mm。
1 特性
• 符合面向汽车应用的AEC-Q100 标准
器件信息
封装(1)
– 1 级：–40°C 至125°C 的工作环境温度范围
– 器件HBM 分类等级H1C
– 器件CDM 分类等级C5
封装尺寸（标称值）
器件型号
TPS92643-Q1
HTSSOP (16)
6.60mm × 5.10mm
(1) 如需了解所有可用封装，请参阅产品说明书末尾的可订购产品
附录。
• 输入电压范围：5.5 V 至36 V
– 启动后工作电压低至5.15V
• 高达3A 的连续电流，精度为4%
• 自适应导通时间电流控制
– 低失调高侧电流检测放大器
– 与陶瓷和铝电容器等任意电容器组合搭配使用时
均可保持稳定
RCS
L
LED+
COUT
1
2
16
SW
SW
PGND
GND
VIN
CIN1
15
14
RBST
CBST
VIN
VIN
3
• 可编程开关频率范围为100kHz 至2.2MHz
• 高级调光操作
BST
CVCC
4
5
VCC
IADJ
RON
RUV2
RUV1
– 1000:1 高精度PWM 调光
– 15:1 高精度模拟调光
– 1.4kHz 内部模拟输入至PWM 占空比的转换
• 开关逐周期过流保护
• 开漏故障指示灯输出
13
12
11
10
9
RON
UDIM
CSP
CSN
FLT
CCOMP
6
7
COMP
AGND
PWM
RPWM1
RNTC
8
APWM
– LED 短路、开路和电缆线束故障指示
• 热关断保护
典型降压LED 驱动器应用示意图
2 应用
96
94
92
90
88
86
84
82
80
78
76
74
72
• 前照灯
• 前雾灯LED 驱动器模块
3 说明
TPS92643-Q1 是一款单片同步降压 LED 驱动器，具
有 5.5V 至 36V 宽工作输入电压范围和 40V 容差，支
持 400ms 时长的负载突降。TPS92643-Q1 基于电感
器谷值电流检测实现自适应导通时间平均电流模式控
制。自适应导通时间控制功能可提供近乎恒定的开关频
率，频率设置范围为 100kHz 至 2.2MHz。电感器电流
检测和闭环反馈功能可在宽输入、输出和环境温度范围
内实现±4% 以上的精度。
1 LED
2 LEDs
3 LEDs
0
0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7
LED Current (A)
3
典型效率
高性能 LED 驱动器可使用模拟调光或 PWM 调光技术
来单独调制 LED 电流。通过设置 IADJ 电压可获得超
过 15:1 范围的线性模拟调光范围。通过使用所需占空
比直接调制 UDIM 输入引脚，或设置 APWM 的模拟电
压以启用内部模拟至 PWM 转换，可实现 LED 电流的
PWM 调光。。内部 PWM 发生器通过将外部模拟电压
与内部 1.4kHz 斜坡信号进行比较来实现外部模拟电压
的转换。
TPS92643-Q1 包含高级诊断和故障保护功能：逐周期
开关电流限制、自举欠压保护、LED 开路保护、LED
短路保护和热关断保护。
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLUSCV5
TPS92643-Q1
ZHCSQK6 –MAY 2022
www.ti.com.cn
Table of Contents
7.4 Device Functional Modes..........................................21
8 Application and Implementation..................................22
8.1 Application Information............................................. 22
8.2 Typical Application.................................................... 26
9 Power Supply Recommendations................................30
10 Layout...........................................................................31
10.1 Layout Guidelines................................................... 31
10.2 Layout Example...................................................... 32
11 Device and Documentation Support..........................33
11.1 接收文档更新通知................................................... 33
11.2 支持资源..................................................................33
11.3 Trademarks............................................................. 33
11.4 Electrostatic Discharge Caution..............................33
11.5 术语表..................................................................... 33
12 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................4
6.4 Thermal Information....................................................5
6.5 Electrical Characteristics.............................................5
6.6 Typical Characteristics................................................8
7 Detailed Description......................................................10
7.1 Overview...................................................................10
7.2 Functional Block Diagram......................................... 11
7.3 Feature Description...................................................12
Information.................................................................... 33
4 Revision History
DATE
REVISION
NOTES
May 2022
*
Initial release.
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5 Pin Configuration and Functions
SW
SW
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
PGND
VIN
BST
VIN
VCC
RON
UDIM
CSP
CSN
FLT
IADJ
COMP
AGND
APWM
图5-1. PWP Package, 16-Pin HTSSOP with PowerPAD, Top View
表5-1. Pin Functions
PIN
I/O
DESCRIPTION
NO.
NAME
AGND
Analog ground. Return for the internal voltage reference and analog circuit. Connect to circuit ground,
GND, to complete return path.
7
—
I
Supply input for high-side MOSFET gate drive circuit. Connect a ceramic capacitor between BST and
SW pins. An internal diode is connected between VCC and BST pins.
3
6
BST
Output of internal transconductance error amplifier. Connect an integral compensation network to
ensure stability.
COMP
CSN
O
Negative input (–) of internal rail-to-rail transconductance error amplifier. Connect directly to the
10
I
negative node of the LED current sense resistor, RCS
Positive input (+) of internal rail-to-rail transconductance error amplifier. Connect directly to the positive
node of the LED current sense resistor, RCS
.
11
9
CSP
FLT
I
.
O
Open-drain fault indicator. Connect to VCC with a resistor to create an active low fault signal output.
Analog adjust input. Input below 100 mV disables the output. The analog input can be varied between
140 mV to 2.4 V to set current reference from 10 mV to 175 mV. Connect a 0.1-μF capacitor from pin
to AGND.
5
16
8
IADJ
I
PGND
APWM
Ground returns for low-side MOSFETs
—
External analog to PWM dimming command. The external analog dimming command between 1 V and
2.45 V is compared to the internal 1.5-kHz triangle waveform to set LED current duty cycle between
0% and 100%.
I
On-time programming pin. Connect a resistor to VIN based on the desired pseudo-fixed switching
frequency.
13
RON
SW
I
I
Switching output of the regulator. Internally connected to both power MOSFETs. Connect to the power
inductor.
1,2
Undervoltage lockout and external PWM dimming input. Connect to VIN through a resistor divider to
implement input undervoltage protection. Diode couple external PWM signal to enable dimming. Do
not float.
12
4
UDIM
VCC
VIN
I
O
I
VCC bias supply pin. Locally decouple to AGND using a 2.2-μF to 4.7-μF ceramic capacitor located
close to the controller.
Power input and connection to high-side MOSFET drain node. Connect to the power supply and
bypass capacitors CIN. The path from the VIN pin to the high frequency bypass capacitor and PGND
must be as short as possible.
14,15
PowerPAD
The AGND and PGND pin must be connected to the exposed PowerPAD for proper operation. This
PowerPAD must be connected to PCB ground plane using multiple vias for good thermal performance.
—
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
36
UNIT
V
VIN
Input Voltage
–0.3
VIN (< 400 ms)
40
V
Bias supply
VVCC
5.5
V
–0.3
voltage, VCC
BST to SW
5.5
41.5
36
V
V
–0.3
–0.3
–0.5
–0.5
–3.5
–0.5
–0.1
Boot voltage,
BST
BST to GND
VSW to GND
V
Switch node
voltage
VSW to GND (< 400 ms)
40
V
VSW to GND (< 10 ns)
40
V
CSP, CSN
RON
36
V
36
V
IRON
500
0.3
VVIN
5.5
5.5
20
µA
mV
V
V(CSP-CSN)
Inputs
–0.3
–0.3
–0.1
–0.3
–0.3
–0.5
–3.5
–40
UDIM to GND
IADJ
V
COMP, APWM
FLT
V
Outputs
Ground
V
PGND to AGND
PGND to AGND (< 10 ns)
Junction temperature
Storage temperature
0.5
3.5
150
150
V
V
TJ
°C
°C
Tstg
–40
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If
used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
6.2 ESD Ratings
VALUE UNIT
Human body model (HBM), per AEC Q100-002(1)
±2000
±750
±500
Corner pins (SW, APWM, FLT and
V(ESD) Electrostatic discharge
V
Charged device model (CDM), per
AEC Q100-011
PGND)
Other pins
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
5.5
8
NOM
MAX
UNIT
V
VVIN
Input Voltage
36
V(CSP-CSN) Sensed inductor current ripple voltage
mV
V/µs
A
dVCSP/dt
ILED
CSP slew-rate
10
3
LED Current (Continuous)
Analog PWM Input
VAPWM
3
–0.3
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6.3 Recommended Operating Conditions (continued)
over operating free-air temperature range (unless otherwise noted)
MIN
–0.3
–0.3
400
NOM
MAX
VVIN
18
UNIT
VUDIM
FLT
fSW
TA
Digital PWM Input
Fault Output
Switching Frequency
Ambient temperature
Junction temperature
2200
125
150
kHz
°C
–40
–40
TJ
°C
6.4 Thermal Information
DEVICE
THERMAL METRIC(1)
PKG (HTSSOP)
UNIT
PINS
38.9
24.3
19.9
0.7
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
ΨJT
19.7
1.7
ΨJB
RθJC(bot)
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics
–40°C < TJ < 150°C, VIN = 14V, VUDIM = 5V, VIADJ = 2.1V, CVCC = 2.2μF, CBST = 1nF, CCOMP = 1nF, RCS = 100mΩ, RON
401kΩ, VAPWM = 5V, fSW = 200 kHz
=
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
INPUT VOLTAGE (VIN)
VDO
ISW
IOP
LDO dropout voltage
Input switching current
Input operating current
IVCC = 20 mA, VVIN = 5 V
315
10
2
mV
mA
mA
17.6
4
Not switching, VIADJ = VVCC
BIAS SUPPLY (VCC)
VCC(UVLO-RISE) Rising threshold
VCC(UVLO-FALL) Falling threshold
VCC(UVLO-HYS)
VCC rising threshold, VVIN = 8 V
VCC falling threshold, VVIN = 8 V
Hysteresis
4.40
4.2
4.58
V
V
3.9
200
5.00
56
mV
V
VCC(REG)
ICC(LIMIT)
Regulation voltage
Supply current Limit
No Load
4.75
45
5.25
76
VVCC = 0 V
mA
HIGH-SIDE FET (SW, BOOT)
RDS(ON-HS)
VBST(UV)
VBST(HYS)
IQ(BST)
High-side MOSFET on resistance
ILED = 100 mA
65
3.2
130
3.47
240
325
mΩ
V
Bootstrap gate drive UVLO
V(BST-SW) rising
2.95
175
197
Bootstrap gate drive UVLO hysteresis
Bootstrap pin quiescent current
Hysteresis
207
265
mV
µA
VSW = 0V, VUDIM = 0 V, VBOOT = 5 V
LOW-SIDE FET (SW)
RDS(ON-LS)
Low-side MOSFET on resistance
ILED = 100 mA
67
130
mΩ
HIGH SIDE FET CURRENT LIMIT
ILIM(HS)
High-side current limit threshold
High-side current sense blanking period
3.75
35
4.80
60
5.85
80
A
t(HS-BLANK)
ns
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6.5 Electrical Characteristics (continued)
–40°C < TJ < 150°C, VIN = 14V, VUDIM = 5V, VIADJ = 2.1V, CVCC = 2.2μF, CBST = 1nF, CCOMP = 1nF, RCS = 100mΩ, RON
401kΩ, VAPWM = 5V, fSW = 200 kHz
=
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
LOW SIDE FET CURRENT LIMIT
ISINK(LS)
tBLANK
Sinking current limit
Blanking time
2.0
3.2
71
4.3
A
ns
ERROR AMPLIFIER (CSP, CSN, COMP)
VIADJ = VCC, VCSP = 3 V, ICOMP = 0 V
VIADJ = 2.1 V, VCSP = 3 V, ICOMP = 0 V
168
175
150
450
200
140
2.45
440
3
182
mV
mV
µA/V
µA
V(CSP-CSN)
Current sense threshold
gM
Transconductance
ICOMP(SRC)
ICOMP(SINK)
VCOMP(RISE)
COMP current source capacity
COMP current sink capacity
COMP startup threshold
VIADJ = 2.5 V, V(CSP-CSN) = 0 V
VIADJ = 150 mV, V(CSP-CSN) = 300 mV
Rising
µA
V
VCOMP(HYS
EA(BW)
)
COMP startup comparator hysteresis
Bandwidth
mV
MHz
nA
Unity gain bandwidth
VUDIM = 0 V
ICOMP(LKG)
Comp leakage current
2.5
VCOMP(RST)
RCOMP(DCH)
VCOMP(OV)
COMP pin reset voltage
VVCC dropping from 5 V to 0 V
100
230
3.2
mV
COMP discharge FET resistance
COMP overvoltage protection threshold
Ω
2.9
V
COMP overvoltage protection
hysteresis
VCOMP(OV-HYS)
60
mV
Falling
Rising
1.5
1.6
V
V
VCSP(SHORT)
Output short circuit detection threshold
ANALOG ADJUST INPUT (IADJ)
VIADJ(CLAMP) IADJ internal clamp voltage
VIADJ(DIS)
2.45
133
100
V
Disable threshold voltage
Disable threshold voltage
Rising
Falling
mV
mV
VIADJ(DIS)
VALLEY CURRENT COMPARATOR
gM(LV) Level shift amplifier transconductance
tDEL V(CSP-CSN) falling to gate rising delay
ON-TIME GENERATOR (RON)
50
65
µA/V
ns
80
tON(MIN)
Minimum on-time
81
96
150
336
0.95
3.55
111
ns
ns
ns
µs
µs
VVIN = 14 V, VCSP = 5 V, RON = 35 kΩ
VVIN = 10 V, VCSP = 8 V, RON = 35 kΩ
VVIN = 14 V, VCSP = 3 V, RON = 400 kΩ
VVIN = 10 V, VCSP = 8 V, RON = 400 kΩ
tON
Programmed on-time
MINIMUM OFF-TIME
tOFF(MIN) Minimum off-time
V(CSP-CSN) = 0 V, VCOMP = 2.5 V
76
6.5
91
106
ns
PWM DIMMING and PROGRAMMABLE UVLO INPUT (UDIM)
IUDIM(DO) UDIM source current (UVLO hysteresis) VUDIM > 2.45 V
10
2.44
2.34
1.22
1.120
245
13
µA
V
VUDIM(DO,RISE) Dropout detection rising threshold
VUDIM(DO,FALL) Dropout detection falling threshold
VUDIM(EN,RISE) Undervoltage lockout rising threshold
VUDIM(EN,FALL) Undervoltage lockout falling threshold
VUDIM rising
VUDIM falling
VUDIM rising
VUDIM falling
2.54
2.24
1.075
V
1.27
V
V
tUDIM(RISE)
tUDIM(FALL)
UDIM to SW pin rising delay
UDIM pin SW pin falling delay
ns
ns
105
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6.5 Electrical Characteristics (continued)
–40°C < TJ < 150°C, VIN = 14V, VUDIM = 5V, VIADJ = 2.1V, CVCC = 2.2μF, CBST = 1nF, CCOMP = 1nF, RCS = 100mΩ, RON
401kΩ, VAPWM = 5V, fSW = 200 kHz
=
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
ANALOG TO PWM GENERATOR (APWM)
fRAMP
Internal ramp generator frequency
Internal ramp high threshold
Internal ramp low threshold
VUDIM = 5 V
1.0
1.5
2.45
1.00
1
1.9
kHz
V
VRAMP(HIGH)
VRAMP(LOW)
VUDIM = 5 V
VUDIM = 5 V
VUDIM = 0 V
2.60
0.95
V
VRAMP(CLAMP) Internal ramp clamp
V
tAPWM(RISE)
tAPWM(FALL)
VAPWM(HYS)
APWM to SW pin rising delay
200
80
ns
ns
mV
APWM to SW pin falling delay
Analog to PWM comparator hysteresis
5
FAULT INDICATION (nFLT)
R(FLT)
Fault pin pull-down resistance
IFLT = 20 mA
2.5
5.5
20
7
Ω
ms
µs
TOC
Hiccup retry delay time
TUC(BLANK)
IFLT(LKG)
Undercurrent reporting blanking period
Fault pin leakage current
100
nA
THERMAL SHUTDOWN
TSD
Thermal shutdown threshold
Thermal shutdown hysteresis
175
15
°C
°C
TSD(HYS)
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6.6 Typical Characteristics
–40°C < TJ < 150°C, VIN = 14 V, VUDIM = 5 V, VIADJ = 2.1V , CVCC = 2.2 μF, CBST = 1 nF, CCOMP = 1 nF, RCS = 100 mΩ,
RON = 401 kΩ, VAPWM = 5 V, fSW = 200 kHz
5.01
5.008
5.006
5.004
5.002
5
120
110
100
90
80
4.998
4.996
4.994
4.992
4.99
70
60
50
40
-40 -20
0
20
40
60
80 100 120 140 160
-40 -20
0
20
40
60
80 100 120 140 160
Temperature (C)
Temperature (C)
图6-1. VCC Regulation Voltage vs Temperature
图6-2. High-Side MOSFET On Resistance vs Temperature
5.2
5.1
5
120
110
100
90
4.9
4.8
4.7
4.6
4.5
4.4
4.3
4.2
4.1
4
80
70
60
50
40
-40 -20
0
20
40
60
80 100 120 140 160
-40 -20
0
20
40
60
80 100 120 140 160
Temperature (C)
Temperature (C)
图6-4. Low-Side MOSFET On Resistance vs Temperature
图6-3. High-Side Current Limit Threshold vs Temperature
3.375
3.325
3.275
3.225
3.175
3.125
3.075
3.025
2.975
2.925
2.451
2.4505
2.45
2.4495
2.449
2.4485
2.448
-40 -20
0
20
40
60
80 100 120 140 160
-40 -20
0
20
40
60
80 100 120 140 160
Temperature (C)
Temperature (C)
图6-6. IADJ Internal Clamp Voltage vs Temperature
图6-5. Low-Side Sinking Current Limit vs Temperature
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6.6 Typical Characteristics (continued)
–40°C < TJ < 150°C, VIN = 14 V, VUDIM = 5 V, VIADJ = 2.1V , CVCC = 2.2 μF, CBST = 1 nF, CCOMP = 1 nF, RCS = 100 mΩ,
RON = 401 kΩ, VAPWM = 5 V, fSW = 200 kHz
6
4
2
0
-2
-4
-6
0.25 0.5 0.75
1
1.25 1.5 1.75
VIADJ (V)
2
2.25 2.5 2.75
图6-7. V(CSP--CSN) Sense Threshold vs Temperature
图6-8. V(CSP--CSN) Sense Error vs IADJ Setpoint
1.65
1.6
1.55
1.5
1.45
1.4
-40 -20
0
20
40
60
80 100 120 140 160
Temperature (C)
图6-9. Internal Ramp Generator Frequency vs Temperature
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7 Detailed Description
7.1 Overview
The TPS92643-Q1 is a wide input, synchronous buck LED driver. The device can deliver up to 3 A of continuous
current and power a single string of one to 10 series-connected LEDs. The device implements an adaptive on-
time current regulation control technique to achieve fast transient response. This architecture uses a comparator
and a one-shot on-timer that varies inversely with input and output voltage to maintain a near-constant
frequency. The integrated low offset rail-to-rail error amplifier enables closed-loop regulation of LED current and
ensures better than 4% accuracy over a wide input, output, and temperature range. The LED current reference
is set by the IADJ pin and is programmed by a voltage divider to achieve over a 15:1 linear analog dimming
range. The high impedance IADJ input simplifies LED current binning and thermal protection.
The TPS92643-Q1 device incorporates an internal ramp generator to control LED current through pulse width
modulation (PWM) dimming. The PWM duty cycle can be varied from 0% to 100% by modulating the analog
voltage on APWM from VRAMP(LOW) to VRAMP(HIGH). The PWM dimming frequency is internally set to typical value
of 1.5 kHz. In addition, an external PWM input can control current by driving UDIM input. When both UDIM and
APWM inputs are present, the internal PWM control command is derived by ANDing the two pulse width
modulated signals. The APWM input can be tied to VCC to enable only external PWM control. Alternatively,
APWM input can be biased using NTC to scale average LED current and enable temperature foldback protection
of LEDs. This device optimizes the inductor current response and is capable of achieving over a 1000:1 PWM
dimming ratio.
The device incorporates enhanced programmable fault features, including the following:
• Cycle-by-cycle switch overcurrent limit
• Input undervoltage protection
• Boot undervoltage protection
• Comp overvoltage warning
• Thermal warning
• LED short-circuit indication
In addition, thermal shutdown (TSD) protection is implemented to limit the junction temperature at 175°C
(typical).
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7.2 Functional Block Diagram
5V LDO
VIN
VCC
Regulator
2.45 V
1.22 V
Internal
References
Thermal
Limit
UVLO
Standby
BST
VIN
+
BST UVLO
On-time
Min on-time
Min off-time
RON
On-Time
Generator
VIN
VCSP
LEB
10
A
Current
Limit
HS Limit
UDIM
+
–
PWM(DIM)
Circuit
UVLO and
PWM detection
VBST(UV)
SW
Current
Limit
Circuit
LS Limit
COMP
100 mV
Fault
VCC
LEB
Reset
Logic
Logic
+
CompUV
CompOV
PGND
FLT
VCOMP(RISE)
+
VCOMP(OV)
+
Short
VCSP(SHORT)
Valley Current
CompOV and Short Fault
VCC
Control
CSP
R
Internal
Ramp
Generator
R
+
CSN
IADJ
Error Amplifier
VRAMP(HIGH)
Int. PWM
+
VRAMP(LOW)
14R
VIADJ(CLAMP)
PWM(APWM)
+
APWM
AGND
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7.3 Feature Description
7.3.1 Internal Regulator
The TPS92643-Q1 incorporates a 36-V input voltage rated linear regulator to generate the 5-V (typical) VCC bias
supply and other internal reference voltages. The device monitors the VCC output to implement UVLO protection.
Operation is enabled when VCC exceeds the VCC(UVLO) rising threshold and is disabled when VCC drops below
VCC(UVLO) falling threshold. The comparator provides 200 mV of hysteresis to avoid chatter during transitions.
The VCC UVLO thresholds are internally fixed and cannot be adjusted. An internal current limit circuit is
implemented to protect the device during VCC pin short-circuit conditions. The VCC supply powers the internal
circuitry, the low-side gate driver and the bootstrap supply for high-side gate driver. Place a bypass capacitor in
the range of 4.7 μF to 10 μF close to the device, across the VCC pin to AGND. The capacitor from VCC must
be five times larger than the bootstrap capacitor, CBST to support proper operation. The regulator operates in
dropout when input voltage, VIN falls below 5 V, forcing VCC to be lower than VIN by VDO for a 20-mA supply
current. The VCC is a regulated output of the internal regulator and is not recommended to be driven from an
external power supply.
7.3.2 Buck Converter Switching Operation
The following operating description of the TPS92643-Q1 refers to the Functional Block Diagram and the
waveforms in 图 7-1. The main control loop of the TPS92643-Q1 is based on an adaptive on-time pulse width
modulation (PWM) technique that combines a constant on-time control with an inductor valley current sense
circuit for pseudo-fixed frequency operation. This proprietary control technique enables closed-loop regulation of
LED current and fast dynamic response necessary to meet the requirements for dimming animation and fault
protection.
V(CSP-CSN)
IL × RCS
VVAL
t
VSW
VIN
0
t
tON
tOFF
tSW
图7-1. Adaptive On-Time Buck Converter Waveforms
In steady state, the high-side MOSFET is turned on at the beginning of each cycle. The on-time duration of this
MOSFET is controlled by an internal one-shot timer and the high-side MOSFET is turned off after the timer
expires. The one-shot timer duration is set by the output voltage measured at the CSP pin, VCSP, and the input
voltage measured at the VIN pin, VIN, to maintain a pseudo-fixed frequency. During the on-time interval, the
inductor current increases with a slope proportional to the voltage applied across its terminals (VIN –VCSP).
The low-side MOSFET is turned on after a fixed dead time and the inductor current then decreases with the
constant slope proportional to the output voltage, VCSP. Inductor current measured by the external sense resistor
is compared to the valley threshold, VVAL, by an internal high-speed comparator. This MOSFET is turned off and
the one-shot timer is initiated when the sensed inductor current falls below the valley threshold voltage. The
high-side MOSFET is turned on again after a fixed dead time.
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The internal rail-to-rail error amplifier sets the valley threshold voltage and regulates the average inductor current
based on a reference value set by VIADJ pin. A simple integral loop compensation circuit consisting of a capacitor
connected from the COMP pin to GND provides a stable and high-bandwidth response. As the inductor current
is directly sensed by an external resistor, the device operation is not sensitive to the ESR of the output
capacitors and is compatible with common multilayered ceramic capacitors (MLCC).
7.3.3 Bootstrap Supply
The TPS92643-Q1 contains both high-side and low-side N-channel MOSFETs. The high-side gate driver works
in conjunction with an internal bootstrap diode and an external bootstrap capacitor, CBST. During the on-time of
the low-side MOSFET, the SW pin voltage is approximately 0 V and CBST is charged from the VCC supply
through the internal diode and external RBST resistor. TI recommends a 0.1-µF to 2.2-µF capacitor and 2.2-Ω to
10-Ωresistor connected in series between the BST and SW pins.
VCC
BST
+
BST UVLO
VIN
RBST
LEB
CBST
Current
Limit
Circuit
HS Limit
+
–
VBST(UV)
SW
图7-2. Bootstrap Network
A larger capacitor is required to prevent a bootstrap undervoltage fault when operating at low PWM dimming
frequencies. Noise due to stored charge is reduced by the RBST. In addition, the RBST resistor allows
optimization of EMI with respect to efficiency. A larger RBST resistor results in lower SW node rise time and
allows energy in SW node harmonics to roll off near 100-MHz frequency. Switching with slower slew rate also
decreases the efficiency.
7.3.4 Switching Frequency and Adaptive On-Time Control
The TPS92643-Q1 uses an adaptive on-time control scheme and does not have a dedicated on-board oscillator.
The one-shot timer is programmed by the RON resistor. The on-time is calculated internally using 方程式 1 and is
inversely proportional to the measured input voltage, VIN, and directly proportional to the measured CSP voltage,
VCSP
.
V
−12
CSP
t
= 10 × 10
× R
×
(1)
ON
ON
V
IN
Given the duty ratio of the buck converter is VCSP/VIN, the switching period, TSW, remains nearly constant over
different operating points. Use 方程式2 to calculate the switching period.
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V
CSP
−12
T
= t
×
= 10 × 10
× R
ON
(2)
SW
ON
V
IN
The switching frequency is calculated internally using 方程式3.
1
−12
f
=
(3)
SW
10 × 10
× R
ON
The minimum or maximum duty cycle is limited to finite minimum on-time, TON(MIN) and minimum off-time,
TOFF(MIN), respectively. As on-time is constant, the frequency is also a dependent on the efficiency of the device,
ηREG, excluding inductor and sense resistor losses.
1
f
=
(4)
SW
−12
10 × 10
× R
ON
× η
REG
TI recommends a switching frequency setting between 100 kHz and 2.2 MHz.
7.3.5 Minimum On-Time, Off-Time, and Inductor Ripple
Buck converter operation is impacted by minimum on-time, minimum off-time, and minimum peak-to-peak
inductor ripple limitations. The converter reaches the minimum on-time of 96 ns (typical) when operating with
high input voltage and low-output voltage. In this control scheme, the off-time continues to increase and the
switching frequency reduces to regulate the inductor current and LED current to the desired value.
V
OUT MIN
f
=
; t = t
ON MIN
(5)
SW MIN
ON
T
× V
ON MIN
IN MAX
The converter reaches the minimum off-time of 91 ns (typical) when operating in dropout (low input voltage and
high output voltage). As the on-time and off-time are fixed, the duty cycle is constant and the buck converter
operates in open-loop mode. The inductor current and LED current are not in regulation.
The behavior and response of valley comparator is dependent on sensed peak-to-peak voltage ripple,
ΔV(CSP-CSN), and is a function of current sense resistor, RCS, and peak-to-peak inductor current ripple,
ΔiL(PK-PK). To ensure periodic switching, the sensed peak-to-peak ripple must exceed the minimum value. At
high (near 100%) or low (near 0%) duty cycles, the inductor current ripple may not be sufficient to ensure
periodic switching. Under such operating conditions, the converter transitions from periodic switching to a burst
sequence, forcing multiple on-time and off-time cycles at a rate higher than the programmed frequency. Although
the converter may not operate in a periodic manner, the closed-loop control continues regulating the average
LED current with a larger ripple value corresponding to higher peak-to-peak inductor ripple. TI recommends
choosing an inductor, output capacitor, and switching frequency to ensure minimum sensed peak-to-peak ripple
voltage under nominal operating condition is greater than 8 mV. The Application and Implementation section
summarizes the detailed design procedure.
7.3.6 LED Current Regulation and Error Amplifier
The reference voltage, VIADJ, set by the VIADJ and is internally scaled by a gain factor of 1/14 through a resistor
network. An internal rail-to-rail error amplifier generates an error signal proportional to the difference between the
scaled reference voltage (VIADJ / 14) and the inductor current measured by the differential voltage drop between
CSP and CSN, V(CSP-CSN). This error drives the COMP pin voltage, VCOMP, and directly controls the valley
threshold of the inductor current. Zero average DC error and closed-loop regulation is achieved by implementing
an integral compensation network consisting of a capacitor connected from the output of the error amplifier to
GND. As a good starting point, TI recommends a capacitor value between 1 nF and 10 nF between the COMP
pin and GND. The choice of compensation network must ensure a minimum of 60° of phase margin and 10 dB
of gain margin.
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CSP1
CSN1
Current Sense Amplifier
500 uS
Valley Current
Control
10k
10k
+
COMP1
2.45 V
Division by 14
V-I Converter
+
VIADJ
DAC
IADJ1
0 V to 2.45 V
140k
图7-3. Closed-Loop LED Current Regulation
LED current is dependent on the current sense resistor, RCS. Use 方程式15 to calculate the LED current.
LED current accuracy is a function of the tolerance of the external sense resistor, RCS, and the variation in the
sense threshold, V(CSP-CSN), caused by internal mismatch and temperature dependency of the analog
components. The TPS92643-Q1 incorporates low offset rail-to-rail amplifiers, and is capable of achieving LED
current accuracy of ±4% over common-mode range and a junction temperature range of –40°C to 150°C.
7.3.7 Start-Up Sequence
The start-up circuit allows the COMP pin voltage to gradually increase, thus reducing the LED current overshoot
and current surges. The switching operation is initiated after the COMP pin voltage exceeds 2.45 V. A 440-mV
hysteresis window allows the device to operate when COMP voltage is within the expected operating range of
2.2 V to 2.7 V. Switching is disabled on detection of low COMP voltage to avoid excessive negative inductor
current.
The duration of soft start, tss, depends on the size of the compensation capacitor and the error amplifier source
current, ICOMP(SRC)
.
2.45 × C
I
COMP
t
=
(6)
SS
COMP SRC
The source current, ICOMP(SRC) is a function of the transconductance, gM, of the error amplifier and error
generated between the reference and the current sensed voltage.
V
IADJ
14
I
= g
×
− V
CSP − CSN
(7)
COMP SRC
M
With no current flowing through the LEDs, the soft start duration depends on the choice of compensation
capacitor, CCOMP, and the reference voltage, VIADJ
.
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VIADJ
0.1
VUDIM
2.45
0
VCOMP
2.45
440 mV
t
VSW
VIN
0
t
ILED
t
图7-4. Soft-Start Sequence
The open drain fault indicator, FLT, is set low when the COMP voltage deviates from the nominal range and
exceeds VCOMP(OV) threshold. This setting indicates a fault condition where the converter is operating in open-
loop and the LED current is out of regulation. The device can be disabled by setting IADJ input below 100 mV or
controlling the UDIM input.
7.3.8 Analog Dimming and Forced Continuous Conduction Mode
Analog dimming is accomplished by the voltage on IADJ pin, VIADJ. The TPS92643-Q1 improves the linear
range of analog dimming by supporting forced continuous conduction mode of operation. With synchronous
MOSFETs, the inductor current is allowed to go negative for part of the switching cycle, thus enabling linear
dimming with over 15:1 dimming range. TI recommends a 10-nF capacitor from IADJ pin to AGND pin to
improve noise sensitivity.
7.3.9 External PWM Dimming and Input Undervoltage Lockout (UVLO)
The UDIM pin is a multifunction input that features an accurate input voltage detection based on band-gap
thresholds with programmable hysteresis as shown in 图 7-5. This pin functions as the external PWM dimming
input for the LEDs and monitors VIN to detect dropout and undervoltage conditions. When the rising pin voltage
exceeds the 2.45-V threshold, 10 µA (typical) of current is driven out of the UDIM pin into the resistor divider
providing programmable hysteresis. TI recommends a bypass capacitor value of 1 nF between the UDIM pin and
GND to improve noise immunity.
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100 mV
+
VIN
VBG
PWM and
Dropout
PWM
Standard
PWM
Dropout
Detecꢀon
V5A
RUV2
2VBG
10
A
+
DDIM
RUVH
10 k
UDIM
RUV1
CUDIM
Inverted
QDIM
PWM
图7-5. External PWM Dimming
The brightness of LEDs can be varied by modulating the duty cycle of the signal directly connected to the UDIM
input. In addition, either an n-channel MOSFET or a Schottky diode can be used to couple an external PWM
signal when using UDIM input in conjunction with UVLO functionality. With an n-channel MOSFET, the
brightness is proportional to the negative duty cycle of the external PWM signal. With a Schottky diode, the
brightness is proportional to the positive duty cycle of the external PWM signal.
Dropout and input undervoltage protection is achieved by connecting the resistor divider network from VIN to
UDIM pin and UDIM pin to GND. Dropout protection is activated when UDIM pin voltage drops below
VUDIM(DO, FALL) threshold but is held above VUDIM(EN) threshold. In dropout protection mode, the device disables
the error amplifier and disconnects the COMP pin to maintain charge on the compensation network. The device
continues switching, ensuring fast response with minimum led current overshoot as the converter recovers from
dropout condition. The minimum input voltage, below which drop protection is activated is programmed using 方
程式8.
3
R
+ 10 × 10 × R
+ R
UV1 UV2
UVH
V
= V
− I
×
R +
UV2
(8)
IN DO, FALL
IN DO, RISE
UDIM DO
R
UV1
方程式 9 shows the input voltage rising threshold. When VIN exceeds the rising threshold, the error amplifier is
enabled, the COMP pin is connected to the compensation network. The control loop now regulates the LED
current regulation.
R
+ R
UV1
R
UV2
V
= V
×
UDIM DO, RISE
(9)
IN DO, RISE
UV1
Additional hysteresis to internal 100 mV is programmed by connecting an external resistor, RUVH in series with
UDIM pin. This connection allows the standard resistor divider to have smaller values, minimizing PWM delays.
Input undervoltage protection is triggered when UDIM pin voltage drops below VUDIM(EN) thresholds. The device
responds to very low VIN voltage or to the external PWM input signal by disabling the error amplifier,
disconnecting the COMP pin and tri-stating the switch node. With switch disabled, inductor current and the LED
current drops to zero and the charge on the compensation network is maintained. On rising edge of PWM or
when VIN exceeds the internal hysteresis of 100 mV, the converter resumes switching operation. The inductor
current quickly ramps to the previous steady-state value.
方程式10 defines the VIN UVLO rising threshold.
R
+ R
UV1
R
UV2
V
= V
×
UDIM EN,RISE
(10)
IN UVLO,RISE
UV1
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Use 方程式11 to determine the VIN UVLO falling threshold.
R
+ R
UV1
R
UV2
V
= V
×
UDIM EN, FALL
(11)
IN UVLO, FALL
UV1
7.3.10 Analog Pulse Width Modulator Circuit
The TPS92643-Q1 features analog circuitry to generate an internal PWM dimming signal. The frequency of the
internal PWM signal is fixed to 1.5 kHz and the duty cycle is proportional to the applied voltage to APWM pin,
VAPWM, according to 方程式12:
V
− 1
APWM
1.45
D
=
× 100
(12)
PWM INT
2.45 V
APWM
1 V
DPWM(INT)
图7-6. APWM Waveform
The internal PWM signal is ANDed with the external PWM signal applied to UDIM pin. Hence, if this pin is
unused it should be tied to VCC pin. The TPS92643-Q1 stops switching if VAPWM falls below 1.0 V. Pulse width
modulated thermal fold-back can be implemented by connecting a NTC resistor, in conjunction with a voltage
divider network, to APWM pin. TI recommends a bypass capacitor of 10 nF between APWM pin and GND to
improve noise immunity.
7.3.11 Output Short and Open-Circuit Faults
The TPS92643-Q1 monitors the CSN voltage to detect output short circuit faults. A short failure is indicated by
open drain FLT output when the CSN voltage drops below 1.5 V (typical). The device continues to regulate
current and operate without interruption in case of short circuit. A short-circuit fault does not impact the device
behavior. The device continues to operate and regulate current without interruption.
An LED open-circuit fault ultimately causes the output voltage to increase and settle close to the input voltage.
When this event occurs, the TPS92643-Q1 switching operation is then controlled by the fixed on-time and
minimum off-time resulting in a duty cycle close to 100%. The COMP pin voltage exceeds the COMP
overvoltage threshold, VCOMP(OV), and the fault in indicated by FLT output. However, during open circuit, the
dynamic behavior of the device and buck converter is influenced by the input voltage, VIN, and the output
capacitor, COUT, value. The device response to open circuit can be categorized into the following two distinct
cases.
Case 1: For a Buck converter design with a small output capacitor, the switching operation in open load
condition exits the tank resonance forcing the output voltage to oscillate. The frequency and amplitude of the
oscillation are based on the resonant frequency and Q-factor of the second order tank network.
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VCSN
VIN
t
VCOMP
tOC
VCOMP(OV)
t
图7-7. Open-Circuit Condition with Output Voltage Oscillation
Case 2: For a buck converter design with large output capacitor the inductor Q-factor and resonant frequency
are much lower than the switching frequency. In this case, output voltage rises to input voltage and the converter
continues to switch with minimum off-time.
VCSN
VIN
t
图7-8. Open-Circuit Condition with Minimum Off-Time Operation
The voltage transient imposed on CSP and CSN inputs during short circuit and open circuit is dependent on the
output capacitance and is influenced by the cable harness impedance. The inductance associated with a long
cable harness resonates with the charge stored on the output capacitor and forces CSP and CSN voltage to ring
above VIN and below ground. The magnitude of the voltage overshoot above VIN and below ground are
dependent on the parasitic cable harness inductance and resistance.
CSN
CSP
VIN
LPAR
tOC(+)
RCS
LED+
SW
tSH
COUT
LED
LPAR
tOC(
)
PGND
图7-9. Cable Harness Parasitic Inductance
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When using a long cable harness, TI recommends diodes to clamp the voltage across CSP and CSN input, as
shown in 图 7-10. TI recommends a low forward voltage Schottky diode or a fast recovery silicon diode with
reverse blocking voltage rating greater than the maximum output voltage. The diode is required to be placed
close to the output capacitor.
VIN
DFP
LED+
SW
COUT
DRP
PGND
LED
图7-10. Transient Protection Using an External Diode
7.3.12 Overcurrent Protection
The device is protected from overcurrent conditions with cycle-by-cycle current limiting on both the high-side and
the low-side MOSFETs.
The device turns off the high-side MOSFET and discharges the COMP capacitor when the drain current exceeds
4.8-A typical. The low-side switch is turned on to discharge the inductor current and output capacitor.
When the low-side switch is turned on, the switch current is also sensed and monitored. The device turns off
both high-side and low-side MOSFETs and discharges the COMP capacitor when the drain current (from drain to
PGND) exceeds 3.2-A typical.
IL
4.8
ILIM(HS)
iL
tON
tOFF
0.0
(t)
-3.2
ISINK(LS)
图7-11. Overcurrent Protection Thresholds
The device employs hiccup mode overcurrent protection. In hiccup mode, the device shuts itself down and
attempts to start after TOC. Hiccup mode helps reduce the device power dissipation under severe overcurrent
conditions.
7.3.13 Thermal Shutdown
Thermal shutdown prevents the device from extreme junction temperatures by turning off the internal switches
when the IC junction temperature exceeds 175℃ (typical). Thermal shutdown does not trigger below 158℃.
After thermal shutdown occurs, hysteresis prevents the device from switching until the junction temperature
drops to approximately 160℃. When the junction temperature falls below 160℃ (typical), the device attempts to
start up.
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7.3.14 Fault Indicator and Diagnostics Summary
表7-1 summarizes the device behavior under fault conditions.
表7-1. Fault Description
FAULT
DETECTION
DESCRIPTION
The thermal protection is activated in the event the maximum MOSFET temperature
exceeds the typical value of 175°C. This feature is designed to prevent overheating
and damage to the internal switching MOSFETs.
Thermal protection
TJ > 175°C
VCC(RISE) < 4.4 V
VCC(FALL) < 4.2 V
VCC undervoltage
lockout
The device enters the Undervoltage Lockout (UVLO). The switching operation is
disabled, the COMP capacitor is discharged.
The device disables error amplifier and disconnects the compensation network for the
corresponding channel. Error amplifier is enabled and compensation network is
internally connected when the input voltage rises above the dropout rising threshold,
VIN dropout
protection
VUDIM < 2.34 V
VIN(DO,RISE)
The device disables switching operation for the corresponding channel. Switching is
enabled when the input voltage rises above the turn-on threshold, VIN(UVLO,RISE)
.
VIN undervoltage
lockout
VUDIM < 1.12 V
.
VBST(RISE) < 3.2 V
VBST(FALL) < 2.93 V
The device turns off the high-side MOSFET and turns on the low-side MOSFET for the
corresponding channel. Normal switching operation is resumed after the bootstrap
voltage exceeds 3.2 V.
BST undervoltage
lockout
The FLT flag is set low to indicate that the COMP voltage exceeded the normal
operating range. This condition indicates output open-circuit fault.
COMP overvoltage
Short output
VCOMP > 3.2 V
VCSN < 1.5 V
IHS > 4.8 A
The FLT flag is set low to indicate an output short-circuit condition based on sensed
CSN voltage.
High-side switch
current limit
The device turns off the high-side MOSFET, turns on low-side MOSFET and
discharges the COMP capacitor. The device attempts to restart after a delay of 5.5 ms.
Low-side switch
current limit
The device turns off both high-side and low-side MOSFETs and discharges the COMP
capacitor. The device attempts to restart after a delay of 5.5 ms.
ILS > 3.2 A
Output open and short circuit faults force the FLT pin low when biased through an external resistor and
connected to a 5-V supply. The FLT output can be used in conjunction with a microcontroller or system basis
chip (SBC) as an interrupt and aid in fault diagnostics.
7.4 Device Functional Modes
This device has no additional functional modes.
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8 Application and Implementation
备注
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
8.1 Application Information
图8-1 shows a schematic of a typical application for the TPS92643-Q1.
RCS
L
LED+
D1
COUT
1
2
16
SW
SW
PGND
GND
D2
CIN1
15
14
RBST
CBST
VIN
VIN
3
4
BST
VCC
VIN
RON
RUV2
RUV1
CIADJ
13
12
11
10
9
5
RON
UDIM
CSP
CSN
FLT
IADJ
RPWM1
RIADJ2
CCOMP
6
7
COMP
AGND
PWM
CVCC
CUDIM
RIADJ1
RNTC
CAPWM
8
APWM
图8-1. Typical Application Schematic
The TPS92643-Q1 controller is suitable for implementation of step-down LED driver topology. Use the following
design procedure to select component values for the TPS92643-Q1 device. This section presents a simplified
discussion of the design process for the Buck converter.
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8.1.1 Duty Cycle Considerations
The switch duty cycle, D, defines the converter operation and is a function of the input and output voltages. In
steady state, the duty cycle is defined using 方程式13:
V
CSN
D =
(13)
V
IN
The buck converter maximum operating duty cycle, DMAX, at minimum input voltage, VIN,MIN and maximum LED
voltage, VCSN,MAX
.
V
CSN, MAX
D
=
(14)
MAX
V
IN, MIN
There is no limitation for small duty cycles, because at low duty cycles, the switching frequency is reduced as
needed to always ensure current regulation. The maximum duty cycle attainable is limited by the minimum off-
time duration and is a function of switching frequency.
8.1.2 Switching Frequency Selection
Nominal switching frequency is set by programming the RON resistor. The switching varies slightly over operating
range and temperature based on converter efficiency. 表 8-1 shows common switching frequencies and
corresponding RON resistor values.
表8-1. Center Switching Frequency Setting
SWITCHING FREQUENCY (kHz)
RON (kΩ)
267
243
221
50
400
435
480
2000
2200
44.2
8.1.3 LED Current Programming
The LED current is set by the external current sense resistor, RCS, and the analog adjust voltage, VIADJ. The
LED current can be programmed by varying VIADJ between 140 mV to 2.3 V. The LED current can be calculated
using 方程式15:
V
IADJ
I
=
(15)
LED
14 × R
CS
The LED current can be programmed by varying VIADJ between 140 mV and 2.3 V. TI recommends a 10-nF
capacitor from IADJ pin to AGND pin to filter high frequency switching noise.
8.1.4 Inductor Selection
The inductor is sized to meet the ripple specification at maximum operating duty cycle. TI recommends a
minimum sensed peak-to-peak voltage ripple (ΔV(CSP-CSN)) of 8 mV to ensure periodic switching operation
under.
∆ V
= ∆ i × R
CS
(16)
CSP − CSN
L
Use 方程式17 to calculate the inductor value.
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V
− V
V
CSN, MAX
IN, MIN
CSN, MAX
SW
L =
×
(17)
V
∆ i × f
IN, MIN
L
The maximum inductor current ripple occurs at 50% duty cycle. Use 方程式 18 to calculate the maximum peak-
to-peak inductor current ripple, ΔiL(MAX)
.
V
IN TYP
∆ i
=
(18)
L MAX
4 × L × f
SW
Use 方程式 19 and 方程式 20 to calculate the RMS and peak currents through the inductor. Make sure that the
inductor is rated to handle these currents.
2
ΔI
L MAX
12
2
i
=
I
+
(19)
(20)
L RMS
L PK
LED MAX
Δi
L MAX
2
i
= I
+
LED MAX
8.1.5 Output Capacitor Selection
The output capacitor value depends on the total series resistance of the LED string, rD, and the switching
frequency, fSW. The capacitance required for the target LED ripple current, ΔiLED, is calculated using 方程式21.
Δi
L MAX
× r × Δi
D LED
C
=
(21)
OUT
8 × f
SW
When choosing the output capacitors, consider the ESR and ESL characteristics because they directly impact
the LED current ripple. Ceramic capacitors are the best choice due to the following:
• Low ESR
• High ripple current rating
• Long lifetime
• Good temperature performance
With ceramic capacitor technology, consider the derating factors associated with higher temperature and DC
bias operating conditions. TI recommends an X7R dielectric with a voltage rating greater than maximum LED
stack voltage.
8.1.6 Input Capacitor Selection
The input capacitor buffers the input voltage for transient events and decouples the converter from the supply. TI
recommends a 10-µF input capacitor across the VIN pin and PGND placed close to the device, and connected
using wide traces. X7R-rated ceramic capacitors are the best choice due to the low ESR, high ripple current
rating, and good temperature performance.
In addition, a small case size 100-nF ceramic capacitor must be used across VIN to PGND, immediately
adjacent to the device. This usage provides a high-frequency bypass for the control circuits internal to the
device. These capacitors also suppress SW node ringing, which reduces the maximum voltage present on the
SW node and EMI.
The capacitance can be increased to further limit the input voltage deviation during PWM dimming operation.
8.1.7 Bootstrap Capacitor Selection
The bootstrap capacitor biases the high-side gate driver during the high-side FET on-time. The required
capacitance depends on the PWM dimming frequency, PWMFREQ, and is sized to avoid boot undervoltage and
fault during PWM dimming operation. The bootstrap capacitance, CBST, is calculated using 方程式22:
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I
Q BST,MAX
C
=
(22)
BST
V
+ V
− V
× PWM
FREQ
CC
BST HYS
BST UV
表8-2 summarizes the TI recommended bootstrap capacitor value for different PWM dimming frequencies.
表8-2. Bootstrap Capacitor Value
PWM DIMMING FREQUENCY (Hz)
BOOTSTRAP CAPACITOR (µF)
1500
1300
1000
800
0.1
0.15
0.22
0.22
0.33
0.47
1
600
400
200
100
2.2
8.1.8 Bootstrap Resistor Selection
A resistor can be connected between the CBST capacitor and BST pin. A 4.7 resistor between the pins eliminates
overshoot. Even with 2.2 Ω, overshoot and ringing are minimal, less than 4 V if input capacitors are placed
correctly. A resistor value above 10 Ω is undesirable because the resulting incremental improvement in EMI is
not enough to justify further decreased efficiency.
8.1.9 Compensation Capacitor Selection
TI recommends a simple integral compensator to achieve stable operation across the wide operating range. The
buck converter behaves as a single pole system with additional phase lag caused by the switching behavior. The
gain and phase margin are, consequently determined by the choice of the switching frequency and are
independent of other design parameters. TI recommends a 1-nF to 10-nF capacitor to achieve bandwidth
between 4 kHz and 40 kHz. The choice of compensation capacitor impacts the transient response and PWM
dimming performance. TI recommends a larger compensation capacitor (lower bandwidth) to limit the LED
current overshoot on the rising edge of internal or external PWM signal.
表8-3. Compensation Capacitor Value
BANDWIDTH (kHz)
BOOTSTRAP CAPACITOR (nF)
40
18
12
8.5
5.8
4.8
4
1
2.2
3.3
4.7
6.8
8.2
10
8.1.10 Input Dropout and Undervoltage Protection
图 8-1 shows that the undervoltage protection threshold is programmed using a resistor divider, RUV1 and RUV2
,
from the input voltage, VIN to PGND. Use 方程式23 and 方程式24 to calculate the resistor values.
2 × V
I
V
IN DO, FALL
IN UVLO, RISE
UDIM DO
3
R
R
=
=
−
− 10 × 10
(23)
(24)
UV2
I
UDIM DO
V
UDIM EN, RISE
× R
UV1
UV2
V
− V
IN UVLO, RISE
UDIM EN, RISE
A capacitor of 1 nF from UDIM pin to GND is placed close to device to improve noise immunity.
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8.1.11 APWM Input and Thermal Protection
图 8-1 shows APWM input can be used in conjunction with NTC resistor to implement thermal foldback
protection. TI recommends a network of 10-kΩ resistor and a 100-kΩ NTC with β-value (25/50°C) of 4250 K to
implement thermal fold back from 80°C to 125°C.
8.1.12 Protection Diodes
External Schottky diodes are required to protect the CSP / CSN node by clamping the voltage during short circuit
and open-circuit transients. The Schottky diode must be selected based on the length of the cable harness and
the choice of output capacitor. TI recommends a Schottky diode with low forward voltage drop at room-
temperature and non-repetitive peak surge current rating of 10 A for duration of 5 µs. The diodes from CSN to
VIN and GND to CSN must be located close to the pin.
8.2 Typical Application
L2
R14
15uH
LED+
0.065
C15
50V
4.7uF
D4
CSP
U2
CSN
D5
GND
VIN
C16
100nF
50V
C17
10µF
50V
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
SW
PGND
GND
SW
VIN
VIN
C18 16V
R15
R16
267k
VCC
R17
100k
BST
4.7
1µF
C19 16V
VCC
RON
PWM
IADJ
COMP
AGND
APWM
UDIM
CSP
R18
57.6k
C20 16V
D6
R19
10k
10nF
CSP
CSN
R20
37.4k
4700pF
CSN
C22
1000pF
16V
C21 16V
10nF
C23
10µF
FLT
16V
R21
48.4k
17
R22
PowerPAD
GND
GND
100k
TPS92643QPWPRQ1
VCC
IADJ
GND
R23
GND
100k
nFLT
APWM
GND
图8-2. Application Schematic
8.2.1 Design Requirements
表8-4. Design Parameters
PARAMETER
CONDITIONS
MIN
TYP
13.5
2
MAX
UNIT
VIN
Input voltage
8
36
V
NS
Number of LEDs
VFLED
rD
VCSN
ILED
LED forward voltage drop
LED string series resistance
Output voltage
2.6
200
5.2
3
3.4
500
6.8
V
mΩ
V
N × rD(LED)
Ns × VFLED
6
LED current continuous
100
2500
mA
mA
LED current ripple
80
ΔiLED
ΔiL
Defined as percentage peak-to-peak at
maximum LED current
Inductor current ripple
6.2
%
VIN(DO,RISE)
VIN(DO,FALL)
Start input voltage
Stop input voltage
Input voltage rising
Input voltage falling
9
V
V
7.9
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表8-4. Design Parameters (continued)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
Hz
fPWM
DPWM
fSW
PWM frequency
200
PWM dimming duty cycle
Switching frequency
Ambient temperature
4
100
%
400
25
kHz
°C
TA
8.2.2 Detailed Design Procedure
8.2.2.1 Calculating Duty Cycle
Solve for duty cycle D, DMAX, and DMIN
:
V
CSN MAX
6.8
8
D
=
=
= 0.85
(25)
MAX
V
IN MIN
V
CSN MIN
5.2
D
=
=
= 0.144
36
(26)
MIN
V
IN MAX
8.2.2.2 Calculating Minimum On-Time and Off-Time
Solve for minimum on-time, tON(DMIN) at minimum duty cycle and minimum off-time, tOFF(DMAX) at maximum duty
cycle:
V
CSN MAX
1
6.8
8
1
t
t
=
=
×
=
×
= 2125 ns
= 360 ns
3
(27)
(28)
ON DMAX
ON DMIN
V
3
f
IN MIN
sw
400 × 10
V
CSN MIN
1
5.2
1
×
=
×
36
V
f
IN MAX
sw
400 × 10
8.2.2.3 Minimum Switching Frequency
Confirm minimum switching frequency at tON(DMIN), fSW(MIN)
:
V
CSN MIN
5.2
−9
f
(29)
sw MIN =
=
= 401.2 kHz
t
ON DMIN × V
360 × 10
× 36
IN MAX
For the design specification, tON(DMIN) > tON(MIN) and fSW(MIN) = fSW
.
8.2.2.4 LED Current Set Point
Solve for sense resistor, RCS
:
V
IADJ MAX
2.3
14 × 2.5
R
=
=
= 0.0657
(30)
CS
14 × I
LED MAX
A standard resistor of 65 mΩ with tolerance better than 1 % and low temperature coefficient is selected. The
power dissipated in RCS is calculated:
2
2
P
= R × I
= 0.065 × 2.5 = 0.406 W
(31)
sense
CS
LED MAX
A resistor with rated power of 500 mW and above must be selected.
A resistor divider network, with standard values 57.6 kΩ and 48.4 kΩ, from VCC pin to GND sets the maximum
LED current reference voltage of 2.3 V. A 10-nF capacitor from IADJ pin to AGND pin is included to filter high
frequency switching noise.
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8.2.2.5 Inductor Selection
The inductor is selected to meet the recommended peak-to-peak voltage ripple, ΔV(CSP-CSN)
:
V
− V
V
CSN, MAX
IN, MIN
CSN, MAX
SW
8 − 6.8
−3
6.8
8
−6
L =
×
=
×
3
= 16.45 × 10
(32)
V
∆ i × f
IN, MIN
L
155 × 10
× 400 × 10
The closest standard capacitor is 15 µH.
• Lower inductor values increase the peak-to-peak inductor current, which minimizes size and cost at the
expense of reduced efficiency and larger output capacitor.
• Higher inductance values decrease the peak-to-peak inductor current, which increases efficiency but reduces
the operating range based on minimum sense voltage ripple, ΔV(CSP-CSN) specification.
8.2.2.6 Output Capacitor Selection
The minimum output capacitance is selected to meet the LED current ripple specification:
∆ i
L MAX
× ∆ i
D MAX LED
0.5625
−6
C
=
=
= 4.4 × 10
(33)
OUT
3
−3
8 × f
× r
SW
8 × 400 × 10 × 0.5 × 80 × 10
A standard 4.7-µF, 50-V X7R capacitor is selected.
8.2.2.7 Bootstrap Capacitor Selection
Referring to 表8-2 , a standard 1-µF, 16-V X7R capacitor is selected to support PWM frequency of 200 Hz.
8.2.2.8 Bootstrap Resistor Selection
A standard 4.7-Ω bootstrap resistor is selected to limit ringing and mitigate EMI.
8.2.2.9 Compensation Capacitor Selection
A compensation capacitor of 4.7 nF is selected to achieve balanced transient response between PWM dimming
and shunt FET dimming.
8.2.2.10 VIN Dropout Protection and PWM Dimming
The resistor divider, RUV1 and RUV2, is set to meet VIN(UVLO,RISE) and VIN(DO,FALL) thresholds.
2 × 4.5
7.9
3
3
R
=
−
− 10 × 10 = 100 × 10
(34)
(35)
UV2
UV1
−6
−6
10 × 10
10 × 10
1.22
4.5 − 1.22
3
3
R
=
× 100 × 10 = 37.2 × 10
A standard value resistors of 100 kΩ and 37.4 kΩ are selected for RUV2 and RUV1, respectively.
The external PWM signal is achieved by controlling UDIM input. The device modulates the LED current based
on the PWM duty cycle of the external signal, coupled through external diode.
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8.2.3 Application Curves
Ch1: SW voltage (4 V/div); Ch2: Output voltage (1 V/div); Ch3:
Inductor current (500 mA/div); Ch4: VIN voltage (4 V/div);
Time: 2 ms/div
Ch1: SW voltage (4 V/div); Ch2: Output voltage (1 V/div); Ch3:
LED current (500 mA/div); Time: 4 µs/div
图8-4. Normal Operation
图8-3. Start-up Transient
Ch1: SW voltage (4 V/div); Ch2: Output voltage (1 V/div); Ch3:
Inductor current (500 mA/div); Time: 5 µs/div
Ch1: SW voltage (4 V/div); Ch2: Output voltage (1 V/div); Ch3:
Inductor current (500 mA/div); Time: 4 µs/div
图8-6. PWM Dimming (Rising Edge)
图8-5. Normal Operation
Ch1: SW voltage (4 V/div); Ch2: Output voltage (1 V/div); Ch3:
Inductor current (500 mA/div); Time: 5 µs/div
Ch1: SW voltage (4 V/div); Ch2: Output voltage (1 V/div); Ch3:
LED current (500 mA/div); Ch4: VIN voltage (4 V/div); Time:
50 ms/div
图8-7. PWM Dimming (Falling Edge)
图8-8. Input Dropout Transient
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Ch2: Output voltage (1 V/div); Ch3:
LED current (500 mA/div); Ch4: FLT
voltage (1 V/div); Time: 20 ms/div
Ch2: Output voltage (1 V/div); Ch3: LED current (500 mA/div);
Ch4: FLT voltage (1 V/div); Time: 20 ms/div
图8-9. Output Short-Circuit Fault
图8-10. Output Open-Circuit Fault
9 Power Supply Recommendations
The characteristics of the input supply must be compatible with Absolute Maximum Ratings and Recommended
Operating Conditions in this data sheet. In addition, the input supply must be capable of delivering the required
input current to the loaded converter.
If the converter is connected to the input supply through long wires or PCB traces, special care is required to
achieve good performance. The parasitic inductance and resistance of the input cables can have an adverse
effect on the operation of the converter. The parasitic inductance, in combination with the low-ESR, ceramic
input capacitors, can form an under-damped resonant circuit, resulting in overvoltage transients at the input to
the converter or tripping UVLO. Additional bulk capacitance or an input filter can be required in addition to the
ceramic bypass capacitors to address converter stability, noise, and EMI concerns.
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10 Layout
10.1 Layout Guidelines
The performance of any switching converter depends as much on the layout of the PCB as the component
selection. The following guidelines can help design a PCB with the best power converter performance.
• Place ceramic high-frequency bypass capacitors as close as possible to the TPS92643-Q1 VIN and PGND
pins. Grounding for both the input and output capacitors must consist of localized top side planes that
connect to the PGND pin.
• Place bypass capacitors for VCC close to the pins and ground the capacitors to device ground.
• Use wide traces for the CBST capacitor and RBST resistor. Place RBST and CBST network as close as possible
to BST pin and SW pin.
• Differentially route the CSP and CSN pins to sense resistor. Route the traces away from noisy nodes,
preferably through a layer on the other side of a shielding/ground layer.
• Use ground plane in one of the middle layers for noise shielding.
• Make VIN and ground connection as wide as possible. This action reduces any voltage drops on the input of
the converter and maximizes efficiency.
• Keep switch area small. Keep the copper area connecting the SW pin to the inductor as short and wide as
possible. At the same time, the total area of this node must be minimized to help reduce radiated EMI.
10.1.1 Compact Layout for EMI Reduction
Radiated EMI is generated by the high di/dt from pulsing currents in switching converters. The larger the area
covered by the path of a pulsing current, the more electromagnetic emission is generated. The key to minimize
radiated EMI is to identify the pulsing current path and minimize the area of the path. In buck converters, the
pulsing current path is from the VIN side of the input capacitors through the HS switch, through the LS switch,
and then returns to the ground of the input capacitor.
High-frequency ceramic bypass capacitors at the input side provide primary path for the high di/dt components of
the pulsing current. Placing ceramic capacitors as close as possible to the VIN and PGND pins is the key to EMI
reduction.
The PCB copper connection of the SW pin to the inductor must be as short as possible and just wide enough to
carry the LED current without excessive heating. Short, thick traces or, copper pours (shapes), must be used for
high current conduction path to minimize parasitic resistance. Place the output capacitor close to the CSN pin
and grounded closely to the PGND pin.
10.1.1.1 Ground Plane
TI recommends using one of the middle layers as a solid ground plane. The ground plane provides shielding for
sensitive circuits and traces. the ground plane also provides a quiet reference potential for the control circuitry.
Connect the GND, AGND and PGND pins to the ground plane using via right next to the bypass capacitors.
PGND pins are connected to the source of the internal LS switch. They must be connected directly to the
grounds of the input and output capacitors. The PGND net contains noise at the switching frequency and can
bounce due to load variations.
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10.2 Layout Example
SW
PGND
VIN
1
2
3
4
5
6
7
8
32
31
30
29
28
27
26
25
SW
BST
VIN
VCC
IADJ
COMP
AGND
APWM
RON
UDIM
CSP
CSN
FLT
GND
图10-1. TPS92643-Q1 Layout Example
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11 Device and Documentation Support
11.1 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
11.2 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
11.3 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
11.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.5 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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12-Jun-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS92643QPWPRQ1
ACTIVE
HTSSOP
PWP
16
2000 RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
92643Q
Samples
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OUTLINE
PWP0016G
PowerPAD TM TSSOP - 1.2 mm max height
S
C
A
L
E
2
.
4
0
0
PLASTIC SMALL OUTLINE
C
6.6
6.2
TYP
SEATING PLANE
PIN 1 ID
AREA
A
0.1 C
14X 0.65
16
1
2X
5.1
4.9
4.55
NOTE 3
8
9
0.30
0.19
4.5
4.3
NOTE 4
16X
B
1.2 MAX
0.1
C A
B
0.18
0.12
TYP
SEE DETAIL A
2X 0.24 MAX
NOTE 6
2X 0.56 MAX
NOTE 6
THERMAL
PAD
0.25
GAGE PLANE
3.29
2.71
0.15
0.05
0 - 8
0.75
0.50
DETAIL A
TYPICAL
(1)
2.41
1.77
4218975/B 01/2016
PowerPAD is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.
6. Features may not present.
www.ti.com
EXAMPLE BOARD LAYOUT
PWP0016G
PowerPAD TM TSSOP - 1.2 mm max height
PLASTIC SMALL OUTLINE
(3.4)
NOTE 10
(2.41)
SOLDER MASK
OPENING
SOLDER MASK
DEFINED PAD
SEE DETAILS
16X (1.5)
SYMM
1
16
16X (0.45)
(0.95)
TYP
(5)
SYMM
(3.29)
SOLDER MASK
OPENING
14X (0.65)
9
8
(0.95) TYP
METAL COVERED
BY SOLDER MASK
(
0.2) TYP
VIA
(5.8)
LAND PATTERN EXAMPLE
SCALE:10X
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
0.05 MIN
ALL AROUND
0.05 MAX
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
PADS 1-16
4218975/B 01/2016
NOTES: (continued)
7. Publication IPC-7351 may have alternate designs.
8. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
9. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).
10. Size of metal pad may vary due to creepage requirement.
www.ti.com
EXAMPLE STENCIL DESIGN
PWP0016G
PowerPAD TM TSSOP - 1.2 mm max height
PLASTIC SMALL OUTLINE
(2.41)
BASED ON
0.127 THICK
STENCIL
16X (1.5)
1
16
16X (0.45)
(3.29)
SYMM
BASED ON
0.127 THICK
STENCIL
14X (0.65)
(R0.05)
9
8
SYMM
(5.8)
SEE TABLE FOR
METAL COVERED
BY SOLDER MASK
DIFFERENT OPENINGS
FOR OTHER STENCIL
THICKNESSES
SOLDER PASTE EXAMPLE
EXPOSED PAD
100% PRINTED SOLDER COVERAGE BY AREA
SCALE:10X
STENCIL
THICKNESS
SOLDER STENCIL
OPENING
0.1
2.69 X 3.68
2.41 X 3.29 (SHOWN)
2.20 X 3.00
0.127
0.152
0.178
2.04 X 2.78
4218975/B 01/2016
NOTES: (continued)
11. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
12. Board assembly site may have different recommendations for stencil design.
www.ti.com
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