TPS92660PWPR/NOPB [TI]
具有 I2C/EPROM 电流微调功能的 TPS92660 两串 LED 驱动器 | PWP | 20 | -40 to 125;
| 型号： | TPS92660PWPR/NOPB |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有 I2C/EPROM 电流微调功能的 TPS92660 两串 LED 驱动器 | PWP | 20 | -40 to 125 可编程只读存储器 电动程控只读存储器 驱动 光电二极管 接口集成电路 驱动器 |
| 文件： | 总28页 (文件大小：842K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS92660
www.ti.com.cn
ZHCSB27 –APRIL 2013
具有 I2C 一次性可编程 (OTP) ROM 电流调整的两灯串发光二级管 (LED)
查询样品: TPS92660
1
特性
应用范围
2
•
输入电压：高达 80V
•
•
•
专业照明
•
•
两输出 LED 电流控制器
通过带有 I2C 接口的一次性可编程 (OTP) ROM 来
调整 LED 电流
工业用和商用照明
通用照明
说明
•
针对每个 LED 灯串脉宽调制 (PWM) 调光的可调
SADJ 和 LADJ 引脚
TPS92660 是一款双输出 LED 驱动器，此驱动器具有
用于 LED 电流调整的一次性可编程 (OTP) ROM 和
I2C 接口。 此电流调整为 LED 灯具制造商提供了一个
生产 LED 照明灯具的方法，这个方法可在不对 LED
灯进行颜色分级的情况下保持恒定的流明输出。
•
•
•
•
•
•
输入欠压闭锁和输出过压保护
使能接通/关闭
精确的 3.0V 基准电压
效率大于 95%
热关断保护
此器件的一个输出是非同步降压控制器，此控制器被用
来调节较高功率白光 LED 的电流。 此器件的另外一个
输出是线性稳压器控制器，此控制器被用来调节较低功
率红光 LED 的电流。 通过将白光 LED 与红光 LED 混
用，TPS92660 被用于受控 CCT（相关色温）LED 灯
应用。
20 引脚薄型小尺寸 (TSSOP) 外露垫封装
此器件采用 20 引脚，TSSOP 外露垫封装。
典型应用
VOUT1
VIN
EN/UVLO
VOUT2
LED2+
AC/DC
Front End
VCC
GATE
LED1+
RON
VO
LED1+
LED2+
SW
TPS92660
GND
BOOT
CS
VCC
REF
SVDD
SCL
COMP
GND
LNG
I2C
Interface
SDA
SADJ
LADJ
Dimming
Signal
LNCS
UDG-12217
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2013, Texas Instruments Incorporated
English Data Sheet: SLUSBC2
TPS92660
ZHCSB27 –APRIL 2013
www.ti.com.cn
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION(1) (2)
ORDERABLE
DEVICE NUMBER
MINIMUM ORDER
QUANTITY
TJ
PACKAGE
PINS
OUTPUTꢀSUPPLY
TPS92660PWP
Tube
73
–40°C to 125°C
TSSOP exposed pad
20
TPS92660PWPR
Tape and Reel
2500
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or visit the TI
website at www.ti.com.
(2) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
ABSOLUTE MAXIMUM RATINGS(1)
over operating free-air temperature range (unless otherwise noted)
VALUE
UNIT
MIN
–0.3
–0.3
–0.3
–0.3
–2.0
–0.3
–0.3
MAX
14
Supply voltage
VCC
VIN, UVLO/EN
80
BOOT to SW
14
SADJ, LADJ, RON, VO, COMP, CS, LNCS
6
V
Input voltage range(2)
SW
80
BOOT
90
SVDD, SCL, SDA
5.5
2000
750
165
150
260
Human body model (HBM) QSS 009-105 (JESD22-A114A)
V
Electrostatic discharge
Charged device model (CDM) QSS 009-147 (JESD22-C101B.01)
(3)
Junction temperature range, TJ
°C
Storage temperature range, Tstg
Lead temperature range, soldering, 10 s
–55
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to the network ground terminal unless otherwise noted.
(3) Maximum junction temperature is internally limited
2
Copyright © 2013, Texas Instruments Incorporated
TPS92660
www.ti.com.cn
ZHCSB27 –APRIL 2013
THERMAL INFORMATION
TPS92660
TSSOP exposed
pad (PWP)
THERMAL METRIC(1)
UNITS
20 PINS
36.9
22.7
18.6
0.6
θJA
Junction-to-ambient thermal resistance(2)
Junction-to-case (top) thermal resistance(3)
Junction-to-board thermal resistance(4)
Junction-to-top characterization parameter(5)
Junction-to-board characterization parameter(6)
Junction-to-case (bottom) thermal resistance(7)
θJCtop
θJB
°C/W
ψJT
ψJB
18.4
1.9
θJCbot
(1) 有关传统和新的热 度量的更多信息，请参阅IC 封装热度量应用报告， SPRA953。
(2) 在 JESD51-2a 描述的环境中，按照 JESD51-7 的指定，在一个 JEDEC 标准高 K 电路板上进行仿真，从而获得自然 对流条件下的结至环
境热阻。
(3) 通过在封装顶部模拟一个冷板测试来获得结至芯片外壳（顶部）的热阻。 不存在特定的 JEDEC 标准测试，但 可在 ANSI SEMI 标准 G30-
88 中能找到内容接近的说明。
(4) 按照 JESD51-8 中的说明，通过 在配有用于控制 PCB 温度的环形冷板夹具的环境中进行仿真，以获得结板热阻。
(5) 结至顶部特征参数， ψJT，估算真实系统中器件的结温，并使用 JESD51-2a（第 6 章和第 7 章）中 描述的程序从仿真数据中 提取出该参
数以便获得 θJA
(6) 结至电路板特征参数， ψJB，估算真实系统中器件的结温，并使用 JESD51-2a（第 6 章和第 7 章）中 描述的程序从仿真数据中 提取出该
参数以便获得 θJA
。
。
(7) 通过在外露（电源）焊盘上进行冷板测试仿真来获得 结至芯片外壳（底部）热阻。 不存在特定的 JEDEC 标准 测试，但可在 ANSI SEMI
标准 G30-88 中能找到内容接近的说明。
空白
.
.
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
MIN
8.6
2.7
0
MAX
80
UNIT
V
VVIN
Input Voltage
I2C VDD
VSVDD
VVO
5.5
2.5
5.5
5.5
5.5
5.5
125
V
Output voltage sense for control and protection
Enable/Under Voltage lock-out
V
VUVLO/EN
VSADJ
VLADJ
VRON
TJ
0
V
Switching regulator analog or PWM LED current adjust
Linear regulator analog or PWM LED current adjust
Resistor and capacitor sets switching frequency of device
Operating junction temperature
0
V
0
V
0
V
–40
°C
Copyright © 2013, Texas Instruments Incorporated
3
TPS92660
ZHCSB27 –APRIL 2013
www.ti.com.cn
MAX UNITS
ELECTRICAL CHARACTERISTICS
Unless otherwise specified VIN = 48 V, –40°C <TA = TJ< 125°C .
PARAMETER
VCC REGULATOR (VCC)
CONDITIONS
MIN
TYP
VCC
IVCC
VCC Voltage
7.75
14
8.2
20
8.55
27
V
VCC current limit
Rising threshold
Falling threshold
Quiescent current
VCC = 0
mA
6.4
6.1
2.2
VCCUVLO
IQ
V
VIN = 80 V
VEN increasing
VEN = 0
mA
UVLO/DEVICE ENABLE (EN/UV)
VEN
Device enable voltage threshold
1.14
2.4
1.2
20
10
1.26
V
VEN_HYS
IEN
Enable input hysteresis
Enable source current
mV
µA
ON/OFF TIMER/OVER VOLTAGE PROTECTION (RON, VO)
RPD_RON
VOV
RON pull-down resistance
VO pin overvoltage threshold
VO pin overvoltage hysteresis
RON pin to GATE delay
Minimum off-time
60
2.5
0.1
58
83
Ω
V
2.6
VOV_HYS
tON_DLY
tOFF(min)
tON(min)
V
ns
ns
ns
VCS = 0 V
200
80
255
120
340
180
Minimum on-time
I2C LOGIC INTERFACE (SCL, SDA) (2.7V ≤ VSVDD ≤ 5.5V)
VIL
VIH
IL
Low-level input voltage
High-level input voltage
Logic input current
0.2 × VSVDD
V
V
0.8 × VSVDD
–1
0
100
0.2
1
200
0.38
1
µA
kHz
V
fSCL
VOL
IL
SCL input frequency
Low-level output voltage
Output leakage current
ISDA = 3 mA
VSDA = 5 V
µA
SWITCHER LED CURRENT SENSE (CS, COMP)
Switcher LED current reference
VSW_REF
voltage
Non-programmed
196
202
209
1
mV
mV
Switcher LED current reference
∆ VSW_REF
±40
–40
voltage adjust range
ICS
CS bias current
µA
µA/V
V
gM
CS amplifier transconductance
CS to COMP offset voltage
COMP source current
COMP sink current
600
1.8
75
VCS_COMP
µA
ICOMP
75
µA
HIGH SIDE SWITCH CURRENT LIMIT (VIN, SW)
High side switch current limit
VSW_LIM
232
275
280
200
329
mV
µS
nS
(referenced from VIN)
tLIM_OFF
tLEB
Current limit OFF time
Switch current sense leading edge
blank time
4
Copyright © 2013, Texas Instruments Incorporated
TPS92660
www.ti.com.cn
ZHCSB27 –APRIL 2013
ELECTRICAL CHARACTERISTICS (continued)
Unless otherwise specified VIN = 48 V, –40°C <TA = TJ< 125°C .
PARAMETER
CONDITIONS
MIN
TYP
MAX UNITS
LINEAR LED CURRENT SENSE (LNCS)
VLN_REF
∆VLN_REF
ILNCS
Linear LED current reference voltage Non-programmed
190
200
209
1
mV
mV
µA
LinearLED current reference voltage
adjust range
+44
–50
LNCS Input bias current
SWITCHING GATE DRIVER (GATE, BOOT, SW)
RSRC_GATE
RSNK_GATE
VBOOT
Gate sourcing resistance
Gate sinking resistance
BOOT UVLO threshold
BOOT UVLO threshold
SW node pull down current
GATE = High
GATE = Low
2
2
Ω
Ω
BOOT-SW rising
4.2
5.6
750
60
7.0
5.5
V
VBOOT_HYS
ISW_PD
mV
mA
LINEAR GATE DRIVER (LNG)
VLNG_MAX
VLNG_MIN
ILNG_MAX
LNG Maximum output voltage
6.3
1.4
V
V
LNG Minimum output voltage
LNG Maximum output current
mA
ANALOG/PWM DIMMING (SADJ, LADJ)
fDIM
Internal PWM dimming frequency
500
2.5
0.1
2.5
0.1
10
Hz
V
High
Low
High
Low
SADJ triangle voltage for analog input
Vtri
LADJ triangle voltage for analog input
V
ms
V
SADJ Pulse detect timer
LADJ Pulse detect timer
SADJ PWM input threshold
LADJ PWM input threshold
SADJ PWM input hysteresis
LADJ PWM input hysteresis
SADJ Pull up current
tTIMER
10
2.7
2.7
500
500
5
VADJ
VADJ_HYS
IADJ_PU
tSADJ
mV
µA
µs
µs
LADJ Pull up current
5
Rising
Falling
Rising
Falling
1.2
1.2
1.2
1.2
SADJ to GATE delay
LADJ to LNG delay
tLADJ
REFERENCE VOLTAGE (REF)
VREF
IREF
Voltage reference
2.92
1.6
3
3.08
V
VREF maximum source current
mA
THERMAL SHUTDOWN
Thermal shutdown temperature
Thermal shutdown hysteresis
165
25
°C
°C
TSD
Copyright © 2013, Texas Instruments Incorporated
5
TPS92660
ZHCSB27 –APRIL 2013
www.ti.com.cn
DEVICE INFORMATION
TSSOP PACKAGE
20-PINS
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
SVDD
SCL
20
19
18
17
16
15
14
13
12
11
EN/UVLO
VIN
SDA
REF
SADJ
LADJ
RON
VO
VCC
BOOT
GATE
SW
Exposed
Thermal
Pad
LNG
LNCS
CS
COMP
NC
GND
NC – No internal connection
PIN FUNCTIONS(1)
NAME
SVDD
NO.
1
I/O
P
I
DESCRIPTION
I2C VDD input.
I2C clock input.
SCL
2
SDA
REF
3
I/O
O
I
I2C data input/output.
3.0V output reference.
Switching regulator dimming input.
Linear regulator dimming input.
4
SADJ
LADJ
RON
VO
5
6
I
7
I
Connect to resistor and capacitor which sets the switching frequency of the switching regulator.
Output voltage sense for control and protection.
8
I
COMP
NC
9
O
-
Switching regulator error amplifier (EA) compensation connection.
No internal connection.
10
11
12
13
14
15
16
17
18
19
20
-
GND
CS
G
I
System ground connection.
Switching regulator LED Current sense input.
LNCS
LNG
SW
I
Linear regulator current sense input.
O
I
Linear FET gate driver output.
Connect to the switch node of the switching regulator.
Switching controller high-side N-channel FET driver output.
MOSFET drive bootstrap pin.
GATE
BOOT
VCC
VIN
O
I
O
P
I
Output of internal regulator. Bypass it with 1µFminimum ceramic capacitor to GND.
Input voltage supply for device. Maximum of 80V operating voltage.
This pin is a multi function input. Enable of device, Under-voltage lock-out (UVLO).
Exposed thermal pad. Connected to the system ground. Place vias on DAP.
EN/UVLO
DAP
-
(1) I=Input, O=Output, P=Power, G=Ground
6
Copyright © 2013, Texas Instruments Incorporated
TPS92660
www.ti.com.cn
ZHCSB27 –APRIL 2013
FUNCTIONAL BLOCK DIAGRAM
Supply
VIN 19
18 VCC
Regulator
Voltage
Reference
VCC
UVLO
17 BOOT
Thermal
On-Timer
RON Complete
Shutdown
RON
VO
7
8
Start
16 GATE
15 SW
Level
Shift
Current Limit
10 mA
+
Logic
VIN - 275 mV
+
9
COMP
+
EN/UVLO 20
+
12 CS
REF
1.8 V
4
+
–
1.2 V
+
–
3.0 V
LNG
Control
SADJ
5
SW Dim Control
LDO Dim Control
13 LNCS
+
LADJ
6
1
VVCC
SVDD
SW VREF
14 LNG
11 GND
SCL
SDA
2
3
I2C
I/O
I2C
OTP ROM
LDO VREF
UDG-12211
Copyright © 2013, Texas Instruments Incorporated
7
TPS92660
ZHCSB27 –APRIL 2013
www.ti.com.cn
TYPICAL CHARACTERISTICS
Unless otherwise stated, –40°C ≤ TA = TJ ≤+125°C, VIN = 48 V, RT= 51.1 kΩ, CT = 1000 pF, CVCC = 1 μF, CCOMP = 1 μF
7.0
6.9
6.8
6.7
6.6
6.5
6.4
6.3
6.2
6.1
6.0
5.9
5.8
5.7
5.6
2.6
2.5
2.5
2.5
2.4
2.4
2.3
2.2
2.2
2.1
2.1
2.0
2.0
VIN = 80 V
VCC UVLO Rising
VCC UVLO Falling
−40 −25 −10
5
20 35 50 65 80 95 110 125
Temperature (°C)
−40 −25 −10
5
20 35 50 65 80 95 110 125
Temperature (°C)
G000
G000
G000
G000
Figure 1. Supply Voltage (VCC) UVLO Threshold
vs Junction Temperature
Figure 2. Quiescent Current
vs Junction Temperature
1.6
1.5
1.4
1.3
1.2
1.1
1.0
0.9
0.8
6.0
5.9
5.8
5.7
5.6
5.5
5.4
5.3
5.2
5.1
5.0
−40 −25 −10
5
20 35 50 65 80 95 110 125
−40 −25 −10
5
20 35 50 65 80 95 110 125
Temperature (°C)
Temperature (°C)
G000
Figure 3. Enable Threshold Voltage
vs Junction Temperature
Figure 4. Boot UVLO Threshold
vs Junction Temperature
9.0
8.8
8.6
8.4
8.2
8.0
7.8
7.6
7.4
7.2
7.0
3.25
3.20
3.15
3.10
3.05
3.00
2.95
2.90
2.85
2.80
2.75
−40 −25 −10
5
20 35 50 65 80 95 110 125
−40 −25 −10
5
20 35 50 65 80 95 110 125
Temperature (°C)
Temperature (°C)
G000
Figure 5. Supply Voltage (VCC)
vs Junction Temperature
Figure 6. Voltage Reference
vs Junction Temperature
8
Copyright © 2013, Texas Instruments Incorporated
TPS92660
www.ti.com.cn
ZHCSB27 –APRIL 2013
TYPICAL CHARACTERISTICS
Unless otherwise stated, –40°C ≤ TA = TJ ≤+125°C, VIN = 48 V, RT= 51.1 kΩ, CT = 1000 pF, CVCC = 1 μF, CCOMP = 1 μF
250
240
230
220
210
200
190
180
170
160
150
250
240
230
220
210
200
190
180
170
160
150
−40 −25 −10
5
20 35 50 65 80 95 110 125
Temperature (°C)
−40 −25 −10
5
20 35 50 65 80 95 110 125
Temperature (°C)
G000
G000
Figure 7. Linear Current Voltage Regulation
vs Junction Temperature
Figure 8. Switching Current Voltage Regulation
vs Junction Temperature
840
830
820
810
800
790
780
770
760
20.5
20.4
20.3
20.2
20.1
20.0
19.9
19.8
19.7
19.6
19.5
Load = 8 LEDs
Load = 4 LEDs
25 30 35 40 45 50 55 60 65 70 75 80
Input Voltage (V)
15
20
25
30
35
40
45
50
55
60
Input Voltage (V)
G000
G000
Figure 9. Switching Regulator LED Current
vs Input Voltage
Figure 10. Linear Regulator LED Current
vs Input Voltage
1000
920
840
760
680
600
80
75
70
65
60
55
50
45
40
RS = 0.25Ω
RS =3.32 Ω
0
8
16
24
32
40
48
56
64
0
3
6
9
12
15
Trim Step
Trim Step
G000
G000
Figure 11. Switching Regulator LED Current
vs I2C Trim Step
Figure 12. Linear Regulator LED Current
vs I2C Trim Step
Copyright © 2013, Texas Instruments Incorporated
9
TPS92660
ZHCSB27 –APRIL 2013
www.ti.com.cn
TYPICAL CHARACTERISTICS (continued)
Unless otherwise stated, –40°C ≤ TA = TJ ≤+125°C, VIN = 48 V, RT= 51.1 kΩ, CT = 1000 pF, CVCC = 1 μF, CCOMP = 1 μF
100
99
98
97
96
95
94
93
92
91
90
9.0
8.8
8.6
8.4
8.2
8.0
7.8
7.6
7.4
7.2
7.0
fSW = 200 kHz
ILED = 800 mA
Load = 12 LEDs
45
50
55
60
65
70
75
80
10
20
30
40
50
60
70
80
Input Voltage (V)
Input Voltage (V)
G000
G000
Figure 13. Switching Regulator Efficiency
vs Input Voltage
Figure 14. VCC vs Input Voltage
10
Copyright © 2013, Texas Instruments Incorporated
TPS92660
www.ti.com.cn
ZHCSB27 –APRIL 2013
APPLICATION INFORMATION
Theory of Operation
The TPS92660 is a dual-channel LED current controller. It has a high-voltage, non-synchronous buck controller
capable of driving an N-channel high-side MOSFET and a linear controller capable of driving an N-channel low-
side MOSFET. The buck controller uses a controlled on-time (COT) control scheme to regulate the LED current.
The controlled on-time varies with input and output voltage to produce pseudo-fixed frequency operation.
The TPS92660 buck controller also employs a transconductance error amplifier that regulates average the LED
current. When the buck converter operates in continuous conduction mode (CCM) the controlled on-time
maintains a relatively constant switching frequency over the change of input and output voltages. The linear
controller regulates the LED current by controlling the gate voltage of the N-channel low side MOSFET. This
MOSFET is connected in series with the LED string and operates in the linear region when LED current is in
regulation. The linear controller senses the LED current and compares it with the internal reference voltage
(default 200 mV without OTP trim) to generate the MOSFET gate-drive voltage.
Figure 15 shows a simplified version of the feedback system used to control the current through the LED string
connected to the buck converter. The LED current flows through the current sense resistor RSNS and generates
the current sense voltage. This voltage is fed to the CS pin. Inside the IC, the current sense voltage is internally
integrated and compared to a reference voltage. The error amplifier is a transconductance (gM) amplifier which
sorces/sinks current to/from the comp pin and effectively maintains the voltage at the CS pin to be equal to the
voltage VSW_REF ( default 202 mV without OTP trim). The comparator turns on the high-side MOSFET of the buck
converter when the CS voltage falls below the COMP pin voltage minus 1.8V level shift.
VOUT
Gate ON
1.8 V
+
CS
+
VSW_REF
RSNS
COMP
UDG-12206
Figure 15. Current Control Circuitry
Figure 16 shows how the MOSFET conducts for a controlled on-time (tON), set by the external resistor RT, the
external capacitor CT, the input voltage and the output voltage. At the conclusion of the controlled on-time period,
the MOSFET turns off and must remain off for a minimum of 255 ns. Once the minimum off-time period is
complete, the comparator compares the CS voltage with the COMP pin voltage again to start the next cycle.
A capacitor with a value of 0.1 µF or higher is recommended between the COMP pin and GND. This
compensation capacitor provides a dominant pole in the feedback loop and makes the control loop stable.
Copyright © 2013, Texas Instruments Incorporated
11
TPS92660
ZHCSB27 –APRIL 2013
www.ti.com.cn
VIN
VOUT
RT
RON
RVO1
Gate OFF
+
VO
CT
Reset
RVO2
UDG-12207
Figure 16. On-Time Circuitry
Switching Frequency
The TPS92660 does not contain a clock, however the on-time is modulated in proportion to both the input
voltage and the output voltage in order to maintain a relatively constant switching frequency.
The on-time circuitry is shown in Figure 16. Estimate the switching frequency based on timing resistor RT, timing
capacitor CT and the resistor divider of RVO1 and RVO2. Equation 1 and Equation 2 show how to derive the
switching frequency estimation.
D
f
=
SW
t
ON
(1)
V
OUT
D =
V
IN
(2)
The on-time period ends when the voltage at the capacitor CT is charged to the voltage on the VO pin. The
charging current ratio is shown in Equation 3.
V
IN
I
=
CHRG
R
T
where
•
VIN >> VVO
RT ´ CT
(3)
(4)
RVO2
tON
=
´
´ VOUT
V
R
(
VO1 + RVO2
)
IN
Use Equation 3 and Equation 4 to derive Equation 5.
R
+ R
VO2
(
R
)
VO1
f
=
SW
´R ´ C
T
VO2
T
(5)
LED Current Setting
The current sense resistor (RSNS), which is connected between the CS pin and GND, sets the LED current of the
switching regulator. The current sense resistor (RSNSLN), which is connected between the LNCS pin and GND,
sets the LED current of the linear regulator. The average LED current is calculated using Equation 6 and
Equation 7.
Equation 6 shows the calculation for the switching regulator current.
12
Copyright © 2013, Texas Instruments Incorporated
TPS92660
www.ti.com.cn
ZHCSB27 –APRIL 2013
V
=
SW _REF
I
LED _SW
R
SNS
where
•
VSW_REF is the switching regulator reference voltage which is default 202 mV without OTP trim
(6)
Equation 7 shows the linear regulator current calculation.
VLN_REF
=
ILED _LN
RSNS _LN
where
•
VLN_REF is the linear regulator reference voltage which is default 200mV without OTP trim
(7)
High Voltage Bias Regulator (VCC)
The TPS92660 contains an internal low dropout linear regulator (LDO), with an 8.2V output, connected between
the VIN and the VCC pins. Bypass the VCC pin to the GND pin with a 1µF ceramic capacitor connected close to
the pins of the device. VCC tracks VIN until VIN reaches 8.2 V and then regulates at 8.2V as VIN increases. The
TPS92660 comes out of UVLO and begins operating when VCC rises above 6.4V. The TPS92660 shuts down
when VCC falls below 6.1V. The VCC regulator current limit is 20mA.
Peak Switching Current Limit
The TPS92660 contains a current limit comparator to limit the peak current of the high-side switching MOSFET.
When the high-side switching MOSFET turns on, there is a 200ns leading edge blank time. After that if the
voltage difference between the VIN pin and the SW pin exceeds 275 mV, the switching MOSFET is turned off for
a cool down period of approximately 280µs. In the meanwhile, the COMP pin is pulled low. If the current limit
condition persists, this cycle of cool down period and restarting continues, creating a low-power hiccup mode,
and minimizes the thermal stress on the switching MOSFET. Equation 8 shows the peak current limit calculation.
275mV
IPEAK
=
RDS on
( )
where
•
RDS(on) is the on resistance of the switching MOSFET
(8)
Output Open Circuit Protection
The most common failure mode for power LEDs is a broken bond wire, and the result is an open circuit. When
this happens the feedback path is disconnected, and the output voltage of the switching regulator begins to rise.
The VO pin voltage (which senses the output voltage of the switching regulator through a resistor divider) rises
with it. When the VO pin voltage reaches 2.5 V, it triggers the output OV protection and the high-side gate driver
turns off. During this time, the COMP pin is also pulled low. There is 0.1 V hysteresis on the OVP. The converter
does not resume switching until the voltage on the OV pin falls below 2.4 V.
BOOT Under Voltage Lockout (UVLO)
The TPS92660 has a BOOT UVLO circuit. The switching regulator starts switching once the BOOT-SW voltage
rises to 5.6 V. There is 750 mV of hysteresis on the BOOT UVLO. It stops switching when the BOOT-SW voltage
falls to 4.85V. Once the BOOT UVLO is triggered, the SW pin is pulled down by an internal MOSFET, such that
the boot capacitor can be recharged. The maximum pull-down current is 60mA. When the BOOT-SW voltage is
charged above 5.6 V, the pull-down circuit is disabled.
Linear Regulator LED Current Control Overview
Figure 17 shows the TPS92660 linear regulator control circuit. The voltage drop across the current sense resistor
RSNSLN is applied on the LNCS pin. An internal operational amplifier compares this voltage with the linear
regulator reference voltage. The output of the operational amplifier drives the gate of an external N-channel
MOSFET. This MOSFET operates in the linear region when the LED current is in regulation.
Copyright © 2013, Texas Instruments Incorporated
13
TPS92660
ZHCSB27 –APRIL 2013
www.ti.com.cn
The gate-drive voltage controls the drain-to-source voltage of the MOSFET by changing the MOSFET on-
resistance. Applications must minimize the voltage difference between the linear regulator input voltage and the
LED string forward voltage in order to limit the power dissipation on the MOSFET.
VOUT
LNG
LNG
LNCS
Control
EA
+
VLN_REF
RSNSLN
UDG-12208
Figure 17. Linear Regulator Control
SADJ and LADJ Pins for Dimming
The SADJ pin controls the switching regulator dimming and the LADJ pin controls the linear regulator dimming.
There are two different types of dimming that can be performed on those two pins.
Analog to PWM Dimming
When a DC voltage is applied on the SADJ pin, the switching regulator LED current is PWM dimmed at a fixed
frequency of approximately 500 Hz. As shown in Figure 18, the PWM dimming duty cycle is linearly dependent
on the input voltage level, from 0% duty cycle at 0.1 V to 100% duty cycle at 2.5 V. Similarly when a DC voltage
is applied on the LADJ pin, the linear regulator LED current is PWM dimmed in the same way.
SADJ/LADJ
Input Voltage
2.5 V
500 Hz
Ramp
0.1 V
Ideal LED Current
UDG-12209
Figure 18. SADJ/LADJ Input to PWM Dimming
14
Copyright © 2013, Texas Instruments Incorporated
TPS92660
www.ti.com.cn
ZHCSB27 –APRIL 2013
PWM Dimming
During PWM dimming, the signal applied on the pin is a PWM signal instead of a DC voltage. The LED current is
PWM dimmed at the same frequency and duty cycle as the input PWM signal. To implement PWM dimming, the
rising edges of two consecutive pulses of the input PWM signal must be less than 10ms. Once the device
detects two consecutive rising edges, the regulator goes into PWM dimming mode. It turns on when the input
PWM signal rises above the 2.7-V threshold and turns off when the PWM signal falls below the 2.2V threshold.
For the switching regulator, when the input PWM signal is low, the regulator turns off the gate of the MOSFET
and the COMP pin capacitor is disconnected. When the input PWM signal is high, the regulator starts again and
the COMP pin capacitor is reconnected.
A low gate charge MOSFET is recommended for the linear regulator to prevent LED current overshoot during
PWM dimming.
Input Undervoltage Lockout (UVLO)
The TPS92660 enable pin (EN/UVLO) can also be used to implement input undervoltage lockout. The input
UVLO voltage is set by a resistor divider from VIN to ground and is compared against a 1.2 V threshold shown in
Figure 19. As soon as the input voltage is above the preset UVLO rising threshold, the internal circuitry becomes
active and a 1-µA current source at the UVLO pin is turned on. This extra current provides hysteresis to create a
lower input UVLO falling threshold.
VIN
10 mA
RUV1
EN/UVLO
ON/OFF
+
1.2 V
RUV2
UDG-12210
Figure 19. Input UVLO Circuit
The VIN turn-on threshold is defined by Equation 9.
1.2V ´ R
+ R
UV2
(
)
UV1
V
=
IN_ON
R
UV2
(9)
V
= R
´10mA
HYS
UV1
(10)
I2C OTP ROM LED Current Trim
I2C Compatible Interface
Interface Bus Overview
The I2C compatible synchronous serial interface provides access to the programmable functions and registers on
the device. This protocol uses a two-wire interface for bi-directional communications between the devices
connected to the bus. The two interface lines are the serial data line (SDA), and the serial clock line (SCL).
These lines should be connected to a positive supply, via a pull-up resistor, and remain HIGH even when the bus
is idle. Every device on the bus is assigned a unique address and acts as either a master or a slave depending
on whether it generates or receives the serial clock (SCL).
Copyright © 2013, Texas Instruments Incorporated
15
TPS92660
ZHCSB27 –APRIL 2013
www.ti.com.cn
Data Transactions
One data bit is transferred during each clock pulse. Data is sampled during the high state of the serial clock
(SCL). Consequently, throughout the high period, the data should remain stable. Any changes on the SDA line
during the high state of SCL and in the middle of a transaction aborts the current transaction. New data should
be sent during the low SCL state. This protocol permits a single data line to transfer both command/control
information and data using the synchronous serial clock.
I2C Data Validity
The data on SDA line must be stable during the HIGH period of the clock signal (SCL). In other words, the state
of the data line can only be changed when SCL is LOW.
SCL
SDA
Data
change
allowed
Data
change
allowed
Data
change
allowed
Data
valid
Data
valid
UDG-12224
Figure 20. I2C Signals: Data Validity
I2C Start and Stop Conditions
START and STOP bits classify the beginning and the end of the I2C session. START condition is defined as SDA
transitioning from HIGH to LOW while SCL is HIGH. STOP condition is defined as SDA transitioning from LOW
to HIGH while SCL is HIGH. The I2C master always generates START and STOP bits. Consider the I2C bus as
busy after a START condition and free after a STOP condition. During data transmission, the I2C master can
generate repeated START conditions. First START and repeated START conditions are functionally equivalent.
SDA
SCL
S
P
STOP condition
START condition
UDG-12222
Figure 21. I2C Start and Stop Conditions
16
Copyright © 2013, Texas Instruments Incorporated
TPS92660
www.ti.com.cn
ZHCSB27 –APRIL 2013
I2C Addresses and Transferring Data
Every data value put on the SDA line must be eight bits long with the most significant bit (MSB) being transferred
first. Each byte of data has to be followed by an acknowledge bit. The master generates the clock pulse for the
acknowledge bit. The transmitter releases the SDA line (HIGH) during the acknowledge clock pulse. The receiver
must pull down the SDA line during the 9th clock pulse, signifying an acknowledgement. A receiver which has
been addressed must generate an acknowledge bit after each byte has been received. After the START
condition, the I2C master sends a slave address. This address is seven bits long followed by an eighth bit which
is a data direction bit (R/W). The I2C slave address (7 bits) for TPS92660 is 28H. For the eighth bit, a “0”
indicates a WRITE and a “1” indicates a READ. The second byte selects the register to which the data is written.
The third byte contains data to write to the selected register.
MSB
LSB
ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 ADR0 R/W
bit2
bit7
bit6
bit5
bit4
bit3
bit1
bit0
I2C Slave Address (Chip Address)
UDG-12215
Figure 22. I2C Chip Address
Register changes take effect at the SCL rising edge during the last ACK from the slave as shown in Figure 23.
ack from slave
ack from slave
ack from slave
msb Chip Address lsb
w
ack
msb Register Add lsb
ack
msb
DATA
lsb
ack
stop
start
SCL
SDA
start
id = 28h
w
ack
addr = 02h
ack
address 02h data
ack
stop
UDG-12223
w = write (SDA = “0”)
r = read (SDA = “1”)
ack = acknowledge (SDA pulled down by either master or slave)
rs = repeated start
id = 7-bit chip address, 28H for TPS92660.
Figure 23. I2C Write Cycle
A WRITE function must precede the READ function, as shown in the read cycle waveform in Figure 24.
Copyright © 2013, Texas Instruments Incorporated
17
TPS92660
ZHCSB27 –APRIL 2013
www.ti.com.cn
ack from slave
repeated start
ack from slave
data from slave nack from master
ack from slave
start
msb Chip Address lsb
w
msb Register Add lsb
rs
msb Chip Address lsb
r
msb
DATA
lsb
stop
SCL
SDA
start
id = 28h
w
ack
addr = 00h
ack rs
id = 28h
r
ack
Address 00h data
nack stop
UDG-12214
Figure 24. I2C Read Cycle
I2C Timing Parameters (VSVDD = 5 V)
SDA
10
8
7
6
1
7
8
2
SCL
5
1
4
9
3
UDG-12221
Figure 25. I2C Timing Diagram
LIMIT
TIME
PERIOD
PARAMETER(1)
UNITS
MIN
0.6
MAX
1
2
Hold time (repeated) START condition
Clock low time
μs
µs
ns
ns
ns
ns
ns
ns
ns
ns
μs
pF
1.3
3
Clock high time
600
4
Setup time for a repeated START condition
Data hold time (output direction)
Data hold time (input direction)
Data setup time
600
5
300
5
0
6
100
7
Rise time of SDA and SCL
20+0.1Cb
15+0.1Cb
600
300
300
8
Fall time of SDA and SCL
9
Set-up time for STOP condition
Bus free time between a STOP and a START condition
Capacitive load for each bus line
10
Cb
1.3
10
200
(1) Data specified by design. Not production tested.
I2C Register Details
The I2C bus interacts with the TPS92660 to realize the features of LED current trim. The operation of these
functions requires the writing and reading of the internal registers of the TPS92660. Table 1 is the master
register map of the device.
18
Copyright © 2013, Texas Instruments Incorporated
TPS92660
www.ti.com.cn
ZHCSB27 –APRIL 2013
Table 1. Master Register Map
ADDR
01h
REGISTER
D7
D6
D5
D4
D3
STRIM[5:0]
D2
LTRIM[3:0]
D1
D0
DEFAULT
0001 1111
0000 0111
0000 1000
STRIM
LTRIM
RSV
RSV
RSV
RSV
RSV
RSV
02h
RSV
RSV
RSV
FFh
OTP ROM
BURNED
RSV
WRITE
RSV
READ
Register Definitions
STRIM Register Definition
ADDR
REG
D7
D6
D5
D4
D3
D2
D1
D0
DEFAULT
01h
STRIM
RSV
RSV
STRIM[5:0]
0001_1111
Bits
5:0
Description
The STRIM register is meant to be programmed with possible trim values. When the best values
have been found, the contents of this register may then be made permanent by burning them to OTP
ROM using the OTP ROM write cycle (described below).
Upon power-up, the values in OTP ROM are loaded into this register.
Switching Regulator LED Current Trim Table
CURRENT
CURRENT
CHANGE
CURRENT
CHANGE
CURRENT
CHANGE
STRIM[5:0]
STRIM[5:0]
STRIM[5:0]
STRIM[5:0]
CHANGE
–20.0%
–19.4%
–18.8%
–18.1%
–17.5%
–16.9%
–16.3%
–15.6%
–15.0%
–14.4%
–13.8%
–13.1%
–12.5%
–11.9%
–11.3%
–10.6%
XX11 1111
XX11 1110
XX11 1101
XX11 1100
XX11 1011
XX11 1010
XX11 1001
XX11 1000
XX11 0111
XX11 0110
XX11 0101
XX11 0100
XX11 0011
XX11 0010
XX11 0001
XX11 0000
XX10 1111
XX10 1110
XX10 1101
XX10 1100
XX10 1011
XX10 1010
XX10 1001
XX10 1000
XX10 0111
XX10 0110
XX10 0101
XX10 0100
XX10 0011
XX10 0010
XX10 0001
XX10 0000
–10.0%
–9.38%
–8.75%
–8.13%
–7.50%
–6.88%
–6.25%
–5.63%
–5.00%
–4.38%
–3.75%
–3.13%
–2.50%
–1.88%
–1.25%
–0.625%
XX01 1111
XX01 1110
XX01 1101
XX01 1100
XX01 1011
XX01 1010
XX01 1001
XX01 1000
XX01 0111
XX01 0110
XX01 0101
XX01 0100
XX01 0011
XX01 0010
XX01 0001
XX01 0000
0%
XX00 1111
XX00 1110
XX00 1101
XX00 1100
XX00 1011
XX00 1010
XX00 1001
XX00 1000
XX00 0111
XX00 0110
XX00 0101
XX00 0100
XX00 0011
XX00 0010
XX00 0001
XX00 0000
10.0%
10.6%
11.3%
11.9%
12.5%
13.1%
13.8%
14.4%
15.0%
15.6%
16.3%
16.9%
17.5%
18.1%
18.8%
19.4%
0.625%
1.25%
1.88%
2.50%
3.13%
3.75%
4.38%
5.00%
5.63%
6.25%
6.88%
7.50%
8.13%
8.75%
9.38%
LTRIM Register Definition
ADDR
REG
D7
D6
D5
D4
D3
D2
D1
D0
DEFAULT
02h
LTRIM
RSV
RSV
RSV
RSV
LTRIM[3:0]
0000_0111
Bits
3:0
Description
The LTRIM register is meant to be programmed with possible trim values. When the best values have
been found, the contents of this register may then be made permanent by burning them to OTP ROM
using the OTP ROM write cycle (described below).
Upon power-up, the values in OTP ROM are loaded into this register.
Copyright © 2013, Texas Instruments Incorporated
19
TPS92660
ZHCSB27 –APRIL 2013
www.ti.com.cn
Linear Regulator LED Current Trim Table
CURRENT
CURRENT
CHANGE
CURRENT
CHANGE
CURRENT
CHANGE
LTRIM[3:0]
LTRIM[3:0]
LTRIM[3:0]
LTRIM[3:0]
CHANGE
-25.0%
-21.9%
-18.8%
-15.6%
XXXX 1111
XXXX 1110
XXXX 1101
XXXX 1100
XXXX 1011
XXXX 1010
XXXX 1001
XXXX 1000
–12.5%
–9.38%
–6.25%
–3.13%
XXXX 0111
XXXX 0110
XXXX 0101
XXXX 0100
0%
XXXX 0011
XXXX 0010
XXXX 0001
XXXX 0000
12.5%
15.6%
18.8%
21.9%
3.13%
6.25%
9.38%
OTP ROM Register Definition
ADDR
REG
D7
D6
D5
D4
BURNED
D3
D2
D1
RSV
D0
DEFAULT
FFh
OTP ROM
RSV
RSV
RSV
RSV
WRITE
READ
0000_1000
Bits
Description
7:5
Reserved. These bits are reserved for future use. When writing to the OTP ROM register, always
write ‘0’s to these bits.
4
BURNED – This bit indicates that OTP ROM has been burned (when “BURNED” = 1). After burning
OTP ROM, an OTP ROM read cycle must take place in order for the BURNED bit to be updated.
This happens automatically upon power-up, or it can be accomplished manually by issuing an OTP
ROM read command (see bit 0).
3
2
RSV
WRITE – Burning the LTRIM and STRIM register values to OTP ROM is accomplished by writing this
bit to a ‘1’, waiting at least 25ms, and then writing this bit back to ‘0’.
1
0
RSV
READ – To reload the STRIM and LTRIM registers from OTP ROM, write this bit to a ‘1’. This bit
always reads back as a ‘0’. Writing this bit to a ‘1’ temporarily enables the 500 kHz oscillator to
perform the OTP ROM read. When the OTP ROM read is finished, the oscillator is disabled.
OTP ROM Programming
The programming of both the STRIM and the LTRIM registers to OTP ROM is performed in a single sequence as
follows
1. Write the STRIM and LTRIM registers with the desired values.
2. Write a ‘1’ to the WRITE bit of the OTP ROM register (this switches the internal EVDD from 5V to 8V).
3. Wait at least 25 ms.
4. Write a ‘0’ to the WRITE bit (this returns EVDD to 5 V).
20
Copyright © 2013, Texas Instruments Incorporated
TPS92660
www.ti.com.cn
ZHCSB27 –APRIL 2013
1
STRIM[5:0]
LTRIM[3:0]
must be valid
must be valid
8 V
5 V
EVDD
2
4
00h
04h
00h
OTP
ROM[7:0]
>25 ms
3
UDG-12213
Figure 26. OTP ROM Programming Sequence
OTP ROM Reading
The EPROM is read under either of the following conditions:
•
Power-on reset. Note that power-on reset starts when both EN pin and VCC voltages cross the UVLO
threshold. It takes apprimately 50µs to read the OTP ROM contents into the TRIM registers.
•
Writing a ‘1’ to the READ bit of the OTP ROM register. It is not necessary to clear the READ bit after writing it
to a ‘1’.
The device temporarily enables the 500-kHz oscillator during the OTP ROM read cycle. This operation is
necessary because the digital counters generate the timing for the OTP ROM read cycle. After the OTP ROM
read cycle is finished, the oscillator is disabled.
Figure 27 shows a power-on OTP ROM read cycle. The device reads all OTP ROM registers simultaneously. All
timing values are approximate and based on a 500-kHz internal oscillator.
POR
50 ms
STRIM [5:0]
LTRIM [3:0]
valid
valid
UDG-12212
Figure 27. Power-ON OTP ROM Read Timing
Reference Voltage
The TPS92660 provides a 3.0V reference voltage which can be used in the AC/DC main power supply
secondary-side control circuit.
Thermal Shutdown
Internal thermal shutdown circuitry protects the device in the event that the maximum junction temperature is
exceeded. The threshold for thermal shutdown is 165°C with a 25°C hysteresis. Thermal shutdown protection
disables the MOSFET drivers.
Copyright © 2013, Texas Instruments Incorporated
21
TPS92660
ZHCSB27 –APRIL 2013
DESIGN EXAMPLE
Specifications
www.ti.com.cn
Switching Regulator
•
•
•
•
•
Switching Regulator: (fSW): 200 kHz
Input voltage (VIN): 60 V
Output voltage (VOUT): 48 V
Charge current (ILED): 500 mA
Output overvoltage protection threshold (VOVP): 60 V
Linear Regulator
•
•
•
Input voltage (VIN): 30 V
Output voltage (VOUT): 24 V
Charge current (ILED): 20 mA
Design Procedure
Step 1: Select Overvoltage and Timing Components ROV1, ROV2, RT and CT
RVO2
VOVP
´
= 2.5V
R
(
VO1 + RVO2
)
(11)
(12)
•
•
•
VOVP = 60 V
Choose RVO2 = 1.00 kΩ
The calculated RVO1 = 23 kΩ, the standard resistor with the closest value (± 1%) is 23.2 kΩ
R
+ R
VO2
(
R
)
VO1
f
=
SW
´R ´ C
T
VO2
T
•
•
•
fSW = 200 KHz
RT × CT = 121 x 10-6, choose CT = 1000 pF
the calculated RT = 121 kΩ
Step 2: Select Current Sense Resistors RSNS and RSNS_LN
The current sense resistor of the switching regulator RSNS = 202 mV/500 mA = 0.404 Ω.
The current sense resistor of the linear regulator RSNS_LN = 200 mV/20 mA = 10 Ω.
Step 3: Select Inductor
Choose inductor current ripple ΔIL_PP = 0.15 A ( 30% of ILED
)
V
48 V
OUT
t
=
=
= 4ms
ON
V
´ f
60 V ´ 200kHz
IN
SW
(13)
(14)
60V - 48V ´ 4ms
)
(V - V
)´ t
ON
(
IN
OUT
L =
=
= 320mH
DI
0.15A
L P-P
(
)
The closest standard inductor value is 330 µH.
22
Copyright © 2013, Texas Instruments Incorporated
TPS92660
www.ti.com.cn
ZHCSB27 –APRIL 2013
Figure 28. Design Example Application Schematic
Copyright © 2013, Texas Instruments Incorporated
23
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS92660PWP/NOPB
TPS92660PWPR/NOPB
ACTIVE
HTSSOP
HTSSOP
PWP
20
20
73
RoHS & Green
SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
TP92660
PWP
ACTIVE
PWP
2500 RoHS & Green
SN
TP92660
PWP
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
MECHANICAL DATA
PWP0020A
MXA20A (Rev C)
www.ti.com
重要声明和免责声明
TI 均以“原样”提供技术性及可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资
源，不保证其中不含任何瑕疵，且不做任何明示或暗示的担保，包括但不限于对适销性、适合某特定用途或不侵犯任何第三方知识产权的暗示
担保。
所述资源可供专业开发人员应用TI 产品进行设计使用。您将对以下行为独自承担全部责任：(1) 针对您的应用选择合适的TI 产品；(2) 设计、
验证并测试您的应用；(3) 确保您的应用满足相应标准以及任何其他安全、安保或其他要求。所述资源如有变更，恕不另行通知。TI 对您使用
所述资源的授权仅限于开发资源所涉及TI 产品的相关应用。除此之外不得复制或展示所述资源，也不提供其它TI或任何第三方的知识产权授权
许可。如因使用所述资源而产生任何索赔、赔偿、成本、损失及债务等，TI对此概不负责，并且您须赔偿由此对TI 及其代表造成的损害。
TI 所提供产品均受TI 的销售条款 (http://www.ti.com.cn/zh-cn/legal/termsofsale.html) 以及ti.com.cn上或随附TI产品提供的其他可适用条款的约
束。TI提供所述资源并不扩展或以其他方式更改TI 针对TI 产品所发布的可适用的担保范围或担保免责声明。IMPORTANT NOTICE
邮寄地址：上海市浦东新区世纪大道 1568 号中建大厦 32 楼，邮政编码：200122
Copyright © 2020 德州仪器半导体技术（上海）有限公司
相关型号：
©2020 ICPDF网 联系我们和版权申明