UCC12040 [TI]
500mW、高效 3kVrms 隔离式直流/直流转换器;
| 型号： | UCC12040 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 500mW、高效 3kVrms 隔离式直流/直流转换器 转换器 |
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| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
UCC12040
SNVSBO5B – DECEMBER 2019 – REVISED MAY 2021
UCC12040 High-Density, Low-EMI, 3-kVRMS Basic Isolation DC/DC Module
1 Features
2 Applications
•
High-density DC/DC module with optimized
integrated transformer technology
Input voltage range: 4.5 V to 5.5 V
Output voltages (selectable): 5.4 V, 5.0 V, 3.7 V,
3.3 V
Output power: 500 mW
Peak efficiency: 60%
Line regulation (typical): 1%
Load regulation (typical): 1.5%
Meets CISPR32 Class B EMI limits without ferrite
beads on a 2-layer PCB
Spread spectrum modulation (SSM)
Robust isolation barrier:
•
•
•
•
•
•
PLC analog input & output modules
Grid protection relays & smart breakers
Medical patient monitors
Isolated bias for digital isolators
Isolated bias for RS-485/RS-422/CAN transceivers
Isolated bias for voltage and current sensors
•
•
•
•
•
•
•
3 Description
UCC12040 is a DC/DC power module with 3-kVRMS
basic isolation rating designed to provide efficient,
isolated power to isolated circuits that require a
bias supply with a well-regulated output voltage. The
device integrates a transformer and DC/DC controller
with a proprietary architecture to provide 500 mW
(typical) of isolated power with low EMI.
•
•
– Isolation rating: 3 kVRMS
– Surge capability: 6.5 kVPK
– Working voltage: 850 VRMS
– CMTI (typical): ±100 V/ns
Short circuit recovery
Thermal shutdown
16-pin wide-body SOIC package with > 8-mm
creepage and clearance
Extended temperature range: –40°C to 125°C
Safety-related certifications:
– 5657-VPK basic isolation per DIN V VDE V
0884-11:2017- 01
The UCC12040 integrates protection features for
increased system robustness. The device also has an
enable pin, synchronization capability, and regulated
5-V or 3.3-V output options with headroom. The
UCC12040 is a low-profile, miniaturized solution
offered in a wide-body SOIC package with 2.65-mm
height.
•
•
•
•
•
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
UCC12040
DVE SOIC (16)
10.30 mm × 7.50 mm
– 3000-VRMS isolation for 1 minute per UL 1577
– UL certification per IEC 60950-1, IEC 62368- 1
and IEC 60601-1 end equipment standards
– CQC approval per GB4943.1-2011
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
70
60
50
40
30
VINP
VISO
GNDS
SEL
ON
CIN
COUT
EN
OFF
GNDP
SYNC
SYNC_OK
20
VISO = 5.4 V
VISO = 5.0 V
VISO = 3.7 V
VISO = 3.3 V
Simplified Application
10
0
0
20
40
60 80
Load Current (mA)
100
120 140
D021
VINP = 5.0 V
TA = 25°C
Typical Efficiency vs. Load
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
UCC12040
SNVSBO5B – DECEMBER 2019 – REVISED MAY 2021
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Table of Contents
1 Features............................................................................1
2 Applications.....................................................................1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................4
6.4 Thermal Information....................................................4
6.5 Power Ratings.............................................................5
6.6 Insulation Specifications............................................. 5
6.7 Safety-Related Certifications...................................... 6
6.8 Safety Limiting Values.................................................6
6.9 Electrical Characteristics.............................................7
6.10 Switching Characteristics..........................................8
6.11 Insulation Characteristics Curves..............................9
6.12 Typical Characteristics............................................10
7 Detailed Description......................................................15
7.1 Overview...................................................................15
7.2 Functional Block Diagram.........................................15
7.3 Feature Description...................................................15
7.4 Device Functional Modes..........................................18
8 Application and Implementation..................................19
8.1 Application Information............................................. 19
8.2 Typical Application.................................................... 19
9 Power Supply Recommendations................................25
10 Layout...........................................................................25
10.1 Layout Guidelines................................................... 25
10.2 Layout Example...................................................... 26
11 Device and Documentation Support..........................27
11.1 Device Support........................................................27
11.2 Documentation Support.......................................... 27
11.3 Receiving Notification of Documentation Updates..27
11.4 Support Resources................................................. 27
11.5 Trademarks............................................................. 27
11.6 Electrostatic Discharge Caution..............................27
11.7 Glossary..................................................................27
12 Mechanical and Packaging Information....................27
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (April 2020) to Revision B (May 2021)
Page
•
•
•
•
Added Safety Certification Information. ............................................................................................................. 1
Updated ESD values. ........................................................................................................................................ 4
Updated voltage isolation specs per DIN V VDE V 0884-11:2017-01................................................................ 5
Updated Switching Characteristics (non-sync)...................................................................................................8
Changes from Revision * (December 2019) to Revision A (April 2020)
Page
•
Updated IVINO Typical Values in Electrical Characteristics Table .......................................................................7
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5 Pin Configuration and Functions
DVE Package 16-Pin SOIC Top View
1
16
15
14
13
12
11
10
9
GNDS
GNDS
VISO
SEL
EN
GNDP
VINP
2
3
4
5
6
7
8
SYNC
SYNC_OK
NC
NC
NC
NC
NC
NC
GNDS
Table 5-1. Pin Functions
PIN
TYPE (1)
DESCRIPTION
NAME
NO.
Enable pin. Forcing EN low disables the device. Pull high to enable normal device
functionality.
EN
1
I
GNDP
2
9
P
Power ground return connection for VINP.
Connect to GNDS plane on printed circuit board. Do not use as only ground connection for
VISO. Ensure pin 15 is connected to circuit ground.
GNDS
GNDS
P
P
16
Secondary side ground return connection for VISO. Connect bypass capacitor from VISO to
this pin.
15
6
7
Pins internally connected together. No other electrical connection. Pins belong to primary-
side voltage domain. Connect to GNDP on printed circuit board.
—
8
NC
10
11
12
No internal connection. Pin belongs to isolated voltage domain. Connect to GNDS on printed
circuit board.
—
I
Synchronous clock input pin. Provide a clock signal to synchronize multiple devices or
connect to GNDP for standalone operation using the internal oscillator. If the SYNC pin is left
open make sure to it separate it from any switching noise to avoid false clock coupling.
SYNC
4
5
Active-low, open-drain diagnostic output. Pin is asserted LOW if there is no external SYNC
clock or one that is outside of the operating range of the UCC12040 is detected. In this state,
the external clock is ignored and the DC-DC converter is clocked by the internal oscillator.
The pin is in high-impedance if a clock is applied on SYNC.
SYNC_OK
O
VISO selection pin. VISO setpoint is 5.0 V when SEL is shorted to VISO, 5.4 V when SEL is
connected to VISOthrough a 100-kΩ resistor, 3.3 V when SEL is shorted to GNDS, and 3.7
V when SEL is connected to GNDS through a 100-kΩ resistor. For more information see the
Section 7.4 section.
SEL
13
I
Primary side input supply voltage pin. A 10-μF ceramic capacitor to GNDP on pin 2, placed
close to the device pins, is required.
VINP
VISO
3
P
P
Isolated supply voltage pin. A 10-μF ceramic capacitor to GNDS on pin 15, placed close to
the device pins, is required. See Section 8.2.2.1 section.
14
(1) P = Power, G = Ground, I = Input, O = Output
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
UNIT
VINP to GNDP
–0.3
6.0
V
VINP + 0.3,
≤ 6.0
EN, SYNC, SYNC_OK, to GNDP
VISO to GNDS
–0.3
–0.3
–0.3
V
V
V
6.0
VISO + 0.3,
≤ 6.0
SEL to GNDS
(2)
VISO output power at Ta = 25°C, POUT_MAX
675
150
150
mW
°C
Operating junction temperature range, TJ
Storage temperature, Tstg
–40
–65
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) See the Section 7.3.3 section for maximum rated values across temperature and VINP conditions for each different VISO output mode.
6.2 ESD Ratings
VALUE
±3000
±1000
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
V(ESD)
Electrostatic discharge
V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
4.5
0
NOM
MAX
5.5
UNIT
V
VINP
Primary side supply voltage
EN pin input voltage
5.0
VEN
5.5
V
VSYNC
VSYNC-OK
VISO
VSEL
fSYNC
PVISO
Ta
SYNC pin input voltage
0
5.5
V
SYNC_OK pen drain pin voltage
Isolated power supply voltage
Input voltage
0
5.5
V
0
5.7
V
0
5.7
V
External DC/DC converter synchronization signal frequency
VISO output power at Ta = 25°C (1)
Ambient temperature
14.4
16.0
17.6
500
125
150
MHz
mW
°C
°C
–40
–40
TJ
Junction temperature
(1) See the Section 7.3.3 section for maximum rated values across temperature and VINP conditions for each different VISO output mode.
6.4 Thermal Information
DVE (SOIC)
THERMAL METRIC(1)
UNIT
16 PINS
RθJA
Junction-to-ambient thermal resistance
63.8
°C/W
RθJC(top)
RθJB
ψJT
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
21.4
38.5
10.2
37.2
°C/W
°C/W
°C/W
°C/W
Junction-to-top characterization parameter
Junction-to-board characterization parameter
ψJB
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DVE (SOIC)
UNIT
16 PINS
THERMAL METRIC(1)
Junction-to-case (bottom) thermal resistance
RθJC(bot)
—
°C/W
(1) The value of RθJA given in this table is only valid for comparison with other packages and can not be used for design purposes. This
value was calculated in accordance with JESD 51-7, and simulated on a 4-layer JEDEC board when PDP = 129 mW, PDC = 142 mW
and PDT = 129 mW. The board temperature is taken from Pin 12. For more information about traditional and new thermal metrics, see
the Semiconductor and IC Package Thermal Metrics application report.
6.5 Power Ratings
VINP = 5.0V, CINP = COUT = 10 uF, TJ = 150°C, Internal Clock mode
PARAMETER
TEST CONDITIONS
VALUE
460
UNIT
mW
mW
mW
mW
PD
Power dissipation
PDP
PDS
PDT
Power dissipation by driver side (primary)
Power dissipation by rectifier side (secondary)
Power dissipation by transformer
148
SEL connected to GNDS (3.3-V VISO output mode), IISO
135 mA
=
164
148
6.6 Insulation Specifications
PARAMETER
GENERAL
TEST CONDITIONS
VALUE
UNIT
CLR
CPG
External clearance(1)
Shortest terminal-to-terminal distance through air
> 8
> 8
mm
mm
Shortest terminal-to-terminal distance across the package
surface
External creepage(1)
DTI
CTI
Distance through the insulation
Comparative tracking index
Material group
Minimum internal gap (internal clearance)
DIN EN 60112 (VDE 0303-11); IEC 60112
According to IEC 60664-1
> 120
> 600
I
µm
V
Rated mains voltage ≤ 300 VRMS
Rated mains voltage ≤ 600 VRMS
Rated mains voltage ≤ 1000 VRMS
I-IV
I-IV
I-III
Overvoltage Category
DIN V VDE V 0884-11:2017-01(2)
VIORM Maximum repetitive peak isolation voltage
AC voltage (bipolar)
1202
850
VPK
VRMS
VDC
AC voltage (sine wave) Time dependent dielectric
breakdown (TDDB) test
VIOWM
Maximum working isolation voltage
DC voltage
1202
4243
VTEST = VIOTM, t = 60s (qualification);
VTEST = 1.2 × VIOTM, t = 1s (100% production)
VIOTM
VIOSM
Maximum transient isolation voltage
Maximum surge isolation voltage(3)
VPK
Test method per IEC 62368-1, 1.2/50 µs waveform,
VTEST = 1.3 × VIOSM = 6500 VPK (qualification)
5000
≤ 5
VPK
Method a: After I/O safety test subgroup 2/3,
Vini = VIOTM, tini = 60 s;
Vpd(m) = 1.2 × VIORM = 1442 VPK, tm = 10 s
Method a: After environmental tests subgroup 1,
Vini = VIOTM, tini = 60 s;
Vpd(m) = 1.2 × VIORM = 1442 VPK, tm = 10 s
≤ 5
≤ 5
qpd
Apparent charge(4)
pC
Method b1: At routine test (100% production) and
preconditioning (type test)
Vini = 1.2 × VIOTM, tini = 1 s;
Vpd(m) = 1.5 × VIORM = 1803 VPK, tm = 1 s
CIO
RIO
Barrier capacitance, input to output(5)
Isolation resistance, input to output(5)
VIO = 0.4 sin (2πft), f = 1 MHz
VIO = 500 V, TA = 25°C
~3.5
> 1012
> 1011
> 109
pF
Ω
VIO = 500 V, 100°C ≤ TA ≤ 125°C
VIO = 500 V at TS = 150°C
Pollution degree
Climatic category
2
40/125/21
UL 1577
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PARAMETER
TEST CONDITIONS
VALUE
UNIT
VTEST = VISO = 3000 VRMS, t = 60 s (qualification); VTEST
1.2 × VISO = 3600 VRMS, t = 1 s (100% production)
=
VISO
Withstand isolation voltage
3000
VRMS
(1) Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application.
Care should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of
the isolator on the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become
equal in certain cases. Techniques such as inserting grooves and/or ribs on a printed circuit board are used to help increase these
specifications.
(2) This coupler is suitable for safe electrical insulation only within the maximum operating ratings. Compliance with the safety ratings shall
be ensured by means of suitable protective circuits.
(3) Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.
(4) Apparent charge is electrical discharge caused by a partial discharge (pd).
(5) All pins on each side of the barrier tied together creating a two-terminal device
6.7 Safety-Related Certifications
VDE
UL
CQC
Recognized under UL 1577
Component Recognition
Program
Certified according to IEC
60601-1
Certified according to DIN V
VDE V 0884-11:2017- 01
Certified according to IEC
60950-1 and IEC 62368- 1
Certified according to
GB4943.1-2011
Basic insulation per UL
60601- 1:14 and IEC
60601-1 Ed.3+A1,AAMI ES
60601-1:2005/(R)2012 and
A1:2012, C1:2009/(R)2012
and A2:2010/(R)2012 CSA
C22.2 No. 60601-1:2014
IEC 60601-1:2012, 1
Basic insulation per UL
60950-1-07+A1+A2, IEC
60950-1 2nd Ed.+A1+A2,
UL 62368-1- 14 and IEC
62368-1 2nd Ed., 850
VRMS maximum working
voltage (pollution degree 1,
material group I)
Basic insulation Maximum
transient isolation voltage,
4243 VPK; Maximum
repetitive peak isolation
voltage, 1202 VPK;
Basic insulation, Altitude ≤ 5000
m, Tropical Climate, 800 VRMS
maximum working voltage
Single protection, 3000
VRMS
Maximum surge isolation
voltage, 5000 VPK
MOPP (Means of Patient
Protection), 250 VRMS
maximum working voltage
Certificate number:
US-36706-UL, US-36707-
UL
Certificate number:
US-36773-A1-UL
Certificate number:
40047657
Certificate number:
CQC20001268791
File number: E181974
6.8 Safety Limiting Values
Safety limiting intends to minimize potential damage to the isolation barrier upon failure of input or output circuitry.
PARAMETER
TEST CONDITIONS
RθJA = 63.8°C/W, VI = 5.5 V, TJ = 150°C, TA = 25°C
RθJA = 63.8°C/W, VI = 4.5 V, TJ = 150°C, TA = 25°C
RθJA = 63.8°C/W, TJ = 150°C, TA = 25°C
MAX
UNIT
356
IS
Safety input current (1)
mA
435
PS
TS
Safety input power
1960
150
mW
°C
Safety temperature (1)
(1) The maximum safety temperature, TS, has the same value as the maximum junction temperature, TJ, specified for the device. The
IS and PS parameters represent the safety current and safety power respectively. The maximum limits of IS and PS should not be
exceeded. These limits vary with the ambient temperature, TA. The junction-to-air thermal resistance, RθJA, in the Thermal Information
table is that of a device installed on a high-K test board for leaded surface-mount packages. Use these equations to calculate the value
for each parameter: TJ = TA + RθJA × P, where P is the power dissipated in the device. TJ(max) = TS = TA + RθJA × PS, where TJ(max) is
the maximum allowed junction temperature. PS = IS × VI, where VI is the maximum input voltage.
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6.9 Electrical Characteristics
Over operating temperature range (TJ = –40°C to 150°C), VINP = 4.5V to 5.5V, CINP = COUT = 10 µF, SEL connected to VISO
internal clock mode, unless otherwise noted. All typical values at TJ = 25°C and VINP = 5.0V.
,
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
INPUT SUPPLY
IVINQ
VINP quiescent current,disabled
EN=LOW
100
uA
EN=HI; SEL shorted to VISO (5.0V output)
EN=HI; SEL 100kΩ to VISO (5.4V output)
EN=HI; SEL shorted to GNDS (3.3V output)
EN=HI; SEL 100kΩ to GNDS (3.7V output)
50
45
90
80
IVINO
VINP operating current, no load
mA
DC current from VINP supplyunder
short circuit on VISO
IVIN_SC
VUVPR
VUVPF
VUVPH
VISO short to GNDS
245
4.2
3.7
0.5
mA
V
VINP under-voltage lockout rising
threshold
VINP under-voltage lockout falling
threshold
V
VINP under-voltage lockout
hysteresis
V
EN, SYNC INPUT PINS
VIR
Input voltage threshold, logic HIGH Rising edge
Input voltage threshold, logic LOW Falling edge
2.2
V
V
VIF
0.8
IEN
Enable Pin Input Current
SYNC Pin Input Current
VEN = 5.0 V
5
10
1
uA
uA
ISYNC
VSYNC = 5.0 V
0.02
SYNC_OK PIN
VOL
SYNC_OK output low voltage
SYNC_OK pin leakage current
ISYNC_OK = - 2 mA
VSYNC_OK = 5.0 V
0.15
V
ILKG_SYNC_OK
1
uA
DC/DC CONVERTER
SEL shorted to VISO (5.0V output); IISO = 55
mA (2)
4.7
5.1
3.1
3.5
5
5.4
3.3
3.7
5.3
5.7
3.5
3.9
V
V
V
V
SEL 100kΩ to VISO (5.4 V output); IISO = 45
mA (2)
VISO
Isolated supply output voltage
SEL shorted to GNDS (3.3V output); IISO
100 mA (2)
=
SEL 100kΩ to GNDS (3.7 V output); IISO = 90
mA (2)
20-MHz bandwidth, CLOAD = 10 uF || 0.1
uF, SEL shorted to VISO (5.0V output); IISO
100 mA
=
50
50
50
50
mV
mV
mV
mV
20-MHz bandwidth, CLOAD = 10 uF || 0.1 uF,
SEL 100kΩ to VISO (5.4V output); IISO = 90
mA
Voltage ripple on isolated supply
output (pk-pk)
VISO(RIP)
20-MHz bandwidth, CLOAD = 10 uF || 0.1 uF,
SEL shorted to GNDS (3.3V output); IISO
145 mA
=
20-MHz bandwidth, CLOAD = 10 uF || 0.1 uF,
SEL shorted to GNDS (3.7V output); IISO
130 mA
=
SEL shorted to VISO (5.0 V output); IISO = 50
mA, VINP = 4.5 V to 5.5 V
1%
1%
VISO(LINE)
VISO DC line regulation
SEL shorted to GNDS (3.3 V output); IISO
75 mA, VINP = 4.5 V to 5.5 V
=
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Over operating temperature range (TJ = –40°C to 150°C), VINP = 4.5V to 5.5V, CINP = COUT = 10 µF, SEL connected to VISO
internal clock mode, unless otherwise noted. All typical values at TJ = 25°C and VINP = 5.0V.
,
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
SEL shorted to VISO (5.0 V output); IISO = 0
to 100 mA
VISO DC load regulation
1.5%
VISO(LOAD)
SEL shorted to GNDS (3.3 V output); IISO = 0
to 145 mA
VISO DC load regulation
1.5%
60%
60%
50%
53%
750
SEL shorted to VISO (5.0 V output); IISO
100 mA
=
SEL 100kΩ to VISO (5.4V output); IISO = 90
mA
Efficiency at maximum
recommended load (1)
EFF
SEL shorted to GNDS (3.3V output); IISO
145 mA
=
SEL 100kΩ to GNDS (3.7V output); IISO
130 mA
=
EN = change from LO to HI, SEL shorted to
VISO (5.0V output); IISO = 1 mA
µs
µs
tRISE
VISO rise time, 10% - 90%
EN = change from LO to HI, SEL 100kΩ to
GNDS (3.3V output); IISO = 1 mA
300
THERMAL SHUTDOWN
TSDTHR
Thermal shutdown threshold
Thermal shutdown hysteresis
Junction Temperature, Rising
Junction Temperature, Falling
165
27
°C
°C
TSDHYST
(1) Efficiency calculation: EFF = (VISO x IISO) / (VINP x IINP
)
(2) See the Section 7.3.3 section for discussion of VISO regulation across load and temperature conditions for all output voltage settings.
6.10 Switching Characteristics
Over operating temperature range (TJ = –40°C to 150°C), VINP = 4.5V to 5.5V, CINP = COUT = 10 µF, SEL connected to VISO
internal clock mode, unless otherwise noted. All typical values at TJ = 25°C and VINP = 5.0V.
,
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
fSW_INT
CMTI
DC/DC Converter Clock
Internal clock mode
7.2
8
8.8 MHz
V/ns
Static common-mode transient
immunity
Slew Rate of GNDP versus GNDS, VCM
1000 V
=
100
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6.11 Insulation Characteristics Curves
>>100 Yrs
1.E+12
>>100
1.E+11
Yrs
87.5%
1.E+10
1.E+09
1.E+08
1.E+07
1.E+06
TDDB Line (< 1 ppm fail rate)
Operating Zone
VDE Safety Margin Zone
20 %
1.E+05
1.E+04
1.E+03
1.E+02
1.E+01
500 1000 1500 2000 2500 3000 3500 4000 4500 5000 5500 6000 6500
Applied Voltage (VRMS
)
Working isolation voltage = 850 VRMS
TA up to 150°C
Projected insulation lifetime = 11840 years
Applied voltage frequency = 60 Hz
Figure 6-1. Insulation Lifetime Projection Data
450
400
350
300
250
200
150
100
50
2000
1750
1500
1250
1000
750
VINP = 4.5 V
VINP = 5.5 V
500
250
0
0
0
20
40
60
80
100
Ambient Temperature (ºC)
120
140
160
0
20
40
60
80
100
Ambient Temperature (ºC)
120
140
160
D031
D029
Figure 6-3. Thermal Derating Curve for Safety
Limiting Power per VDE
Figure 6-2. Thermal Derating Curve for Safety
Limiting Current per VDE
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6.12 Typical Characteristics
700
650
600
550
500
450
400
350
300
250
200
700
650
600
550
500
450
400
350
300
250
200
150
100
50
150
VINP = 5.5 V
VINP = 5.0 V
VINP = 4.5 V
VINP = 5.5 V
VINP = 5.0 V
VINP = 4.5 V
100
50
0
0
-40 -20
0
20
Ambient Temperature (ºC)
40
60
80 100 120 140 160
-40 -20
0
20
Ambient Temperature (ºC)
40
60
80 100 120 140 160
D022
D023
VISO = 5.0 V
VISO = 5.4 V
Figure 6-4. Maximum VISO Output Power vs.
Temperature
Figure 6-5. Maximum VISO Output Power vs.
Temperature
600
550
500
450
400
350
300
250
200
150
650
600
550
500
450
400
350
300
250
200
150
VINP = 5.5 V
VINP = 5.0 V
VINP = 4.5 V
VINP = 5.5 V
VINP = 5.0 V
VINP = 4.5 V
100
50
0
100
50
0
-40 -20
0
20
Ambient Temperature (ºC)
40
60
80 100 120 140 160
-40 -20
0
20
Ambient Temperature (ºC)
40
60
80 100 120 140 160
D024
D025
VISO = 3.3 V
VISO = 3.7 V
Figure 6-6. Maximum VISO Output Power vs.
Temperature
Figure 6-7. Maximum VISO Output Power vs.
Temperature
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140
120
100
80
140
120
100
80
60
60
40
40
VINP = 5.5 V
VINP = 5.0 V
VINP = 4.5 V
VINP = 5.5 V
VINP = 5.0 V
VINP = 4.5 V
20
20
0
0
-40 -20
0
20
Ambient Temperature (ºC)
40
60
80 100 120 140 160
-40 -20
0
20
Ambient Temperature (ºC)
40
60
80 100 120 140 160
D026
D027
VISO = 5.0 V
VISO = 5.4 V
Figure 6-8. Maximum VISO Output Current vs.
Temperature
Figure 6-9. Maximum VISO Output Current vs.
Temperature
180
160
140
120
100
80
180
160
140
120
100
80
60
60
40
40
VINP = 5.5 V
VINP = 5.0 V
VINP = 4.5 V
VINP = 5.5 V
VINP = 5.0 V
VINP = 4.5 V
20
0
20
0
-40 -20
0
20
Ambient Temperature (ºC)
40
60
80 100 120 140 160
-40 -20
0
20
Ambient Temperature (ºC)
40
60
80 100 120 140 160
D028
D029
VISO = 3.3 V
VISO = 3.7 V
Figure 6-10. Maximum VISO Output Current vs.
Temperature
Figure 6-11. Maximum VISO Output Current vs.
Temperature
70
60
50
40
30
20
10
0
70
60
50
40
30
20
10
0
0
10
20
30
40
Load Current (mA)
50
60
70
80
90 100
0
10
20
30
40
Load Current (mA)
50
60
70
80
90 100
D006
D008
VINP = 5.0 V
VISO = 5.0 V
TA = 25°C
VINP = 5.0 V
VISO = 5.4 V
TA = 25°C
Figure 6-12. Power Supply Efficiency vs Load
Figure 6-13. Power Supply Efficiency vs Load
Current (IISO
Current (IISO
)
)
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60
50
40
30
20
10
0
60
50
40
30
20
10
0
0
20
40
60
Load Current (mA)
80
100
120
140
0
20
40
60
Load Current (mA)
80
100
120
140
D007
D009
VINP = 5.0 V
VISO = 3.3 V
TA = 25°C
VINP = 5.0 V
VISO = 3.7 V
TA = 25°C
Figure 6-14. Power Supply Efficiency vs Load
Current (IISO
Figure 6-15. Power Supply Efficiency vs Load
Current (IISO
)
)
5.1
5.05
5
5.5
5.45
5.4
VINP = 4.5 V
VINP = 5.0 V
VINP = 5.5 V
VINP = 4.5 V
VINP = 5.0 V
VINP = 5.5 V
4.95
4.9
5.35
5.3
0
10
20
30
40
Load Current (mA)
50
60
70
80
90 100
0
10
20
30
40
Load Current (mA)
50
60
70
80
90 100
D012
D013
VISO = 5.0 V
TA = 25°C
VISO = 5.4 V
TA = 25°C
Figure 6-16. Isolated Supply Voltage (VISO) vs Load Figure 6-17. Isolated Supply Voltage (VISO) vs Load
Current (IISO Current (IISO
)
)
3.4
3.35
3.3
3.8
3.75
3.7
VINP = 4.5 V
VINP = 5.0 V
VINP = 5.5 V
VINP = 4.5 V
VINP = 5.0 V
VINP = 5.5 V
3.65
3.6
3.25
3.2
0
20
40
60
80
Load Current (mA)
100
120
140
0
20
40
60
80
Load Current (mA)
100
120
140
D010
D011
VISO = 3.7 V
TA = 25°C
VISO = 3.3 V
TA = 25°C
Figure 6-19. Isolated Supply Voltage (VISO) vs Load
Figure 6-18. Isolated Supply Voltage (VISO) vs Load
Current (IISO
Current (IISO
)
)
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5.20
5.60
5.50
5.40
5.30
5.20
5.10
5.00
4.90
4.80
-40
-20
0
20
Free-Air Temperature (ºC)
40
60
80
100 120 140
-40
-20
0
20
Free-Air Temperature (ºC)
40
60
80
100 120 140
D014
D015
VINP = 5.0 V
VISO = 5.0 V
IISO = 50 mA
VINP = 5.0 V
VISO = 5.4 V
IISO = 50 mA
Figure 6-20. Isolated Supply Voltage (VISO) vs Free- Figure 6-21. Isolated Supply Voltage (VISO) vs Free-
Air Temperature Air Temperature
3.50
3.40
3.30
3.20
3.10
3.90
3.80
3.70
3.60
3.50
-40
-20
0
20
Free-Air Temperature (ºC)
40
60
80
100 120 140
-40
-20
0
20
Free-Air Temperature (ºC)
40
60
80
100 120 140
D016
D017
VINP = 5.0 V
VISO = 3.3 V
IISO = 75 mA
VINP = 5.0 V
VISO = 3.7 V
IISO = 75 mA
Figure 6-22. Isolated Supply Voltage (VISO) vs Free- Figure 6-23. Isolated Supply Voltage (VISO) vs Free-
Air Temperature Air Temperature
280
260
240
220
200
250
200
150
100
50
VISO = 3.3 V
VISO = 3.7 V
VISO = 5.0 V
VISO = 5.4 V
0
4.5 4.6 4.7 4.8 4.9
5
Input Suppy Voltage (V)
5.1 5.2 5.3 5.4 5.5
0
20
40
60
80
100
Load Current (mA)
120
140
160
D018
D019
TA = 25°C
VINP = 5.0 V
TA = 25°C
Figure 6-24. Short-Circuit Supply Current (IVIN_SC
)
Figure 6-25. Input Supply Current (IVINP) vs Load
Current (IISO
vs Supply Voltage (VINP
)
)
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4.5
4.4
4.3
4.2
4.1
4
3.9
3.8
3.7
3.6
3.5
3.4
3.3
3.2
3.1
3
Falling Threshold
RisingThreshold
-40
-20
0
20
40 60
Temperature (ºC)
80
100 120 140
Figure 6-26. Typical VINP UVLO Threshold vs Junction Temperature (TJ)
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7 Detailed Description
7.1 Overview
The UCC12040 device integrates a high-efficiency, low-emissions isolated DC/DC converter. This approach
provides typically 500 mW of clean, steady power across a 3000VRMS basic isolation barrier.
The integrated DC/DC converter uses switched mode operation and proprietary circuit techniques to reduce
power losses and boost efficiency. Specialized control mechanisms, clocking schemes, and the use of an
on-chip transformer provide high efficiency and low radiated emissions.
The VINP supply is provided to the primary power controller that switches the power stage connected to the
integrated transformer. Power is transferred to the secondary side, rectified, and regulated to a level set by the
SEL pin condition.
A fast feedback control loop monitors VISO and the output load, and ensures low overshoots and undershoots
during load transients. Undervoltage lockout (UVLO) with hysteresis is integrated on the VINP supply, which
ensures robust system performance under noisy conditions.
UCC12040 is suitable for applications that have limited board space and require more integration. These devices
are also suitable for very-high voltage applications, where power transformers meeting the required isolation
specifications are bulky and expensive.
7.2 Functional Block Diagram
VINP
Control
SEL
UVLO
EN
VISO
Transformer
Rectifier
OSC
÷ 2
Driver
GNDS
SYNC
SYNC_OK
GNDP
Ext CLK
Detect
7.3 Feature Description
7.3.1 Enable and Disable
Forcing EN low disables the device, which greatly reduces the VINP power consumption. Pull the EN pin high to
enable normal device functionality. The EN pin has a weak internal pull-down resistor, so the device floats to the
disable state if the pin is left open.
7.3.2 UVLO, Power-Up, and Power-Down Behavior
The UCC12040 has an undervoltage lockout (UVLO) on the VINP power supply. Upon power-up, while the VINP
voltage is below the threshold voltage VUVPR, the primary side transformer driver is disabled, and VISO output
is off. The output powers up once the threshold is met. Likewise, if VINP falls below VUVPF, the converter is
disabled and there is no output at VISO. Both UVLO threshold voltages have hysteresis to avoid chattering.
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7.3.3 VISO Load Recommended Operating Area
Figure 7-1 depicts the device VISO regulation behavior across the output load range, including when the output
is overloaded. For proper device operation, ensure that the device VISO output load does not exceed the
maximum output current (IOUT_MAX). The value for IOUT_MAX over different temperature and VINP conditions are
shown from Figure 6-8 to Figure 6-11. The following protection mechanisms will be engaged if the UCC12040 is
loaded beyond the recommended operating area:
1. The device limits the maximum output power. If a load exceeding IOUT_MAX is applied, VISO drops accordingly
to meet the maximum power limit.
2. If VISO drops below nominal 3.8 V while operating in the constant power limit region, the over-power
fold-back feature will switch the power converter from active rectification to passive rectification, and the
built-in recovery hysteresis will ensure the UCC12040 recovers at a lower output power. The device returns
to active rectification when load drops and VISO increases above nominal 4.3V.
3. The device triggers a soft-start reset if VISO drops below the nominal 1.8-V threshold. This reset is designed
to protect the device during VISO short-circuit conditions.
4. Thermal shutdown protection disables the converter if the device is operated in any of the above regions
long enough to raise the silicon junction temperature above the thermal shutdown threshold. See the Section
7.3.4 section for more details on this device feature.
VISO
1
Constant Power Limit
VISO_SET
Active Rectification
2
Passive Rectification
Recommended
Operating
Area
Reset Threshold
3
Overload
Protection
IOUT_MAX
IOUT
Figure 7-1. VISO Load Recommended Operating Area Description
7.3.4 Thermal Shutdown
Thermal protection is also integrated to help prevent the device from getting damaged during overload and short-
circuit conditions on the isolated output. Under these conditions, the device temperature starts to increase. When
the silicon junction temperature Tj sensed at the primary side die goes above the threshold TSDTHR(typical
165°C), thermal shutdown activates and the primary controller turns off which removes the energy supplied
to the VISO load, which causes the device to cool off. When the junction temperature drops approximately
27°C (TSDHYST) from the shutdown point, the device starts to function normally. If an overload or output short-
circuit condition prevails, this protection cycle is repeated. Make sure the design prevents the device junction
temperatures from reaching such high values.
7.3.5 External Clocking and Synchronization
The UCC12040 has an internal oscillator trimmed to drive the transformer at 8.0 MHz. An external clock may be
applied at the SYNC pin to override the internal oscillator. This external clock will be divided by 2, so the target
range for the external clock signal at SYNC is 16 MHz ±10%. When a valid external clock signal is detected,
the internal spread spectrum modulation (SSM) algorithm is disabled. This allows an external clock signal with a
unique SSM to be applied. The depth and frequency of SSM is a tradeoff verses low frequency modulated VISO
voltage ripple. The SYNC_OK pin is asserted LOW if there is no external SYNC clock or one that is outside of
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the operating range of the device is detected. In this state, the external clock is ignored and the DC/DC converter
is clocked by the internal oscillator. The pin is in high impedance if a valid clock is applied on SYNC.
7.3.6 VISO Output Voltage Selection
The SEL pin is monitored during power-up — within the first 1 ms after applying VINP above the UVLO rising
threshold or enabling via the EN pin — to detect the desired regulation voltage for the VISO output. Note that
after this initial monitoring, the SEL pin no longer affects the VISO output level. In order to change the output
mode selection, either the EN pin must be toggled or the VINP power supply must be cycled off and back on.
Section6.4 provides more details on the SEL pin functionality.
7.3.7 Electromagnetic Compatibility (EMC) Considerations
UCC12040 devices use spread spectrum modulation algorithm for the internal oscillator and advanced internal
layout scheme to minimize radiated emissions at the system level.
Many applications in harsh industrial environment are sensitive to disturbances such as electrostatic discharge
(ESD), electrical fast transient (EFT), surge and electromagnetic emissions. These electromagnetic disturbances
are regulated by international standards such as IEC 61000-4-x and CISPR 32. Although system-level
performance and reliability depends, to a large extent, on the application board design and layout, the device
incorporates many chip-level design improvements for overall system robustness.
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7.4 Device Functional Modes
Table 7-1 lists the supply functional modes for this device.
Table 7-1. Device Functional Modes
INPUTS
Isolated Supply Output Voltage (VISO) Setpoint
EN
SEL
HIGH
HIGH
HIGH
HIGH
HIGH
LOW
Shorted to VISO
100 kΩ to VISO
Shorted to GNDS
100 kΩ to GNDS
OPEN(1)
5.0 V
5.4 V
3.3 V
3.7 V
UNSUPPORTED
0 V
X
(1) The SEL pin has an internal weak pull-down resistance to ground, but leaving this pin open is not recommended.
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8 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
8.1 Application Information
The UCC12040 device is suitable for applications that have limited board space and desire more integration.
This device is also suitable for very high voltage applications, where power transformers meeting the required
isolation specifications are bulky and expensive.
8.2 Typical Application
Figure 8-1 shows the typical application schematic for the UCC12040 device supplying an isolated load.
5 V
10 ꢀF 0.1 ꢀF
0.1 ꢀF
10 ꢀF
Load
1
2
3
4
5
6
7
8
EN
GNDS 16
GNDS 15
VISO 14
SEL 13
NC 12
RPU
GNDP
VINP
SYNC
SYNC_OK
NC
RSEL
PWM
RSYNC
NC 11
NC
NC 10
NC
GNDS
9
Figure 8-1. Typical Application
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8.2.1 Design Requirements
To design using UCC12040, a few simple design considerations must be evaluated. Table 8-1 shows some
recommended values for a typical application. See Section 9 and Section 10 sections to review other key design
considerations for the UCC12040.
Table 8-1. Design Parameters
PARAMETER
RECOMMENDED VALUE
4.5 V to 5.5 V
Input supply voltage, VINP
Decoupling capacitance between VINP and GNDP
10 µF, 16 V, ± 10%, X7R
10 µF, 16 V, ± 10%, X7R
0.1 µF, 50 V,± 10%, X7R
100 kΩ
Decoupling capacitance between VISO and GNDS (1)
Optional additional capacitance on VISO or VINP to reduce high-frequency ripple
Pull-up resistor from SYNC_OK to VINP, RPU
Pull-up resistor from SEL to VISO for 5.0V output voltage mode, RSEL
Pull-up resistor from SEL to VISO for 5.4V output voltage mode, RSEL
0 Ω
100 kΩ
Match source — typical values are 50 Ω, 75 Ω,
100 Ω, or 1 kΩ
Optional SYNC signal impedance-matching resistor, RSYNC
External clock signal applied on SYNC
16 MHz
(1) See Section 8.2.2.1 section.
8.2.2 Detailed Design Procedure
Place ceramic decoupling capacitors as close as possible to the device pins. For the input supply, place the
capacitor(s) between pin 3 (VINP) and pin 2 (GNDP). For the isolated output supply, place the capacitor(s)
between pin 14 (VISO) and pin 15 (GNDS). This location is of particular importance to the input decoupling
capacitor, because this capacitor supplies the transient current associated with the fast switching waveforms of
the power drive circuits. The recommended capacitor value is 10 µF. Ensure the capacitor dielectric material is
compatible with the target application temperature.
8.2.2.1 VISO Output Capacitor Selection
The UCC12040 is optimized to run with an effective output capacitance of 5 µF to 20 µF. A ceramic capacitor is
recommended. Ceramic capacitors have DC-Bias and temperature derating effects, which both have influence
the final effective capacitance. Choose the right capacitor carefully in combination with considering its package
size, dielectric and voltage rating. It is good design practice to include one 0.1-µF capacitor close to the device
for high-frequency noise reduction.
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8.2.3 Application Curves
Time (2.0 ms/div)
Time (2.0 ms/div)
D033
D034
VINP = 5.0 V
VISO = 5.4 V
Bandwidth = 20 MHz
VINP = 5.0 V
VISO = 5.4 V
Bandwidth = 20 MHz
Figure 8-2. VISO Ripple, 5.4-V Output, 10% Load
Figure 8-3. VISO Ripple, 5.4-V Output, 90% Load
Time (2.0 ms/div)
Time (2.0 ms/div)
D035
D036
VINP = 5.0 V
VISO = 5.0 V
Bandwidth = 20 MHz
VINP = 5.0 V
VISO = 5.0 V
Bandwidth = 20 MHz
Figure 8-4. VISO Ripple, 5.0-V Output, 10% Load
Figure 8-5. VISO Ripple, 5.0-V Output, 90% Load
Time (2.0 ms/div)
Time (2.0 ms/div)
D037
D038
VINP = 5.0 V
VISO = 3.7 V
Bandwidth = 20 MHz
VINP = 5.0 V
VISO = 3.7 V
Bandwidth = 20 MHz
Figure 8-6. VISO Ripple, 3.7-V Output, 10% Load
Figure 8-7. VISO Ripple, 3.7-V Output, 90% Load
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Time (2.0 ms/div)
Time (2.0 ms/div)
D039
D040
VINP = 5.0 V
VISO = 3.3 V
Bandwidth = 20 MHz
VINP = 5.0 V
VISO = 3.3 V
Bandwidth = 20 MHz
Figure 8-8. VISO Ripple, 3.3-V Output, 10% Load
Figure 8-9. VISO Ripple, 3.3-V Output, 90% Load
VISO
IISO load
VISO
IISO load
Time (200 ms/div)
Time (200 ms/div)
D041
D042
Figure 8-10. VISO Load Transient Response, 10% to Figure 8-11. VISO Load Transient Response, 90% to
90% Load Step, 5.0-V Input, 5.4-V Output
10% Load Step, 5.0-V Input, 5.4-V Output
VISO
IISO load
VISO
IISO load
Time (200 ms/div)
Time (200 ms/div)
D043
D044
Figure 8-12. VISO Load Transient Response, 10% to Figure 8-13. VISO Load Transient Response, 90% to
90% Load Step, 5.0-V Input, 5.0-V Output
10% Load Step, 5.0-V Input, 5.0-V Output
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VISO
IISO load
VISO
IISO load
Time (200 ms/div)
Time (200 ms/div)
D045
D046
Figure 8-14. VISO Load Transient Response, 10% to Figure 8-15. VISO Load Transient Response, 90% to
90% Load Step, 5.0-V Input, 3.7-V Output
10% Load Step, 5.0-V Input, 3.7-V Output
VISO
IISO load
VISO
IISO load
Time (200 ms/div)
Time (200 ms/div)
D047
D047
Figure 8-16. VISO Load Transient Response, 10% to Figure 8-17. VISO Load Transient Response, 90% to
90% Load Step, 5.0-V Input, 3.3-V Output
10% Load Step, 5.0-V Input, 3.3-V Output
7
7
6
5
4
3
2
1
0
6
5
4
3
2
1
0
-1
-1
Time (400 ms/div)
Time (400 ms/div)
D049
D050
Figure 8-18. VISO Soft Start at 10% Rated Load,
5.0-V Input, 5.4-V Output
Figure 8-19. VISO Soft Start at 90% Rated Load,
5.0-V Input, 5.4-V Output
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7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
-1
-1
Time (400 ms/div)
Time (400 ms/div)
D051
D052
Figure 8-20. VISO Soft Start at 10% Rated Load,
5.0-V Input, 5.0-V Output
Figure 8-21. VISO Soft Start at 90% Rated Load,
5.0-V Input, 5.0-V Output
5
4
3
2
1
0
5
4
3
2
1
0
-1
-1
Time (400 ms/div)
Time (400 ms/div)
D053
Figure 8-22. VISO Soft Start at 10% Rated Load,
5.0-V Input, 3.7-V Output
D054
Figure 8-23. VISO Soft Start at 90% Rated Load,
5.0-V Input, 3.7-V Output
5
4
3
2
1
0
5
4
3
2
1
0
-1
-1
Time (400 ms/div)
Time (400 ms/div)
D055
Figure 8-24. VISO Soft Start at 10% Rated Load,
5.0-V Input, 3.3-V Output
D056
Figure 8-25. VISO Soft Start at 90% Rated Load,
5.0-V Input, 3.3-V Output
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9 Power Supply Recommendations
The recommended input supply voltage (VINP) for the UCC12040 is between 4.5 V and 5.5 V. To help ensure
reliable operation, adequate decoupling capacitors must be located as close to supply pins as possible. Place
local bypass capacitors between the VINP and GNDP pins at the input, and between VISO and GNDS at the
isolated output supply. Low ESR, ceramic surface mount capacitors are recommended. It is further suggested
that one place two such capacitors: one with a value of 10 µF for supply bypassing, and an additional 100-nF
capacitor in parallel for high frequency filtering. The input supply must have an appropriate current rating to
support output load required by the end application.
10 Layout
10.1 Layout Guidelines
The UCC12040 integrated isolated power solution simplifies system design and reduces board area usage.
Proper PCB layout is important in order to achieve optimum performance. Here is a list of recommendations:
1. Place decoupling capacitors as close as possible to the device pins. For the input supply, place the
capacitor(s) between pin 3 (VINP) and pin 2 (GNDP). For the isolated output supply, place the capacitor(s)
between pin 14 (VISO) and pin 15 (GNDS). This location is of particular importance to the input decoupling
capacitor, because this capacitor supplies the transient current associated with the fast switching waveforms
of the power drive circuits.
2. Because the device does not have a thermal pad for heat-sinking, the device dissipates heat through the
respective GND pins. Ensure that enough copper (preferably a connection to the ground plane) is present on
all GNDP and GNDS pins for best heat-sinking.
3. If space and layer count allow, it is also recommended to connect the VINP, GNDP, VISO and GNDS pins to
internal ground or power planes through multiple vias of adequate size. Alternatively, make traces for these
nets as wide as possible to minimize losses.
4. TI also recommends grounding the no-connect pins (NC) to their respective ground planes. For pins 6, 7,
and 8, connect to GNDP. For pins 10, 11, and 12, connect to GNDS. This will allow more continuous ground
planes and larger thermal mass for heat-sinking.
5. A minimum of four layers is recommended to accomplish a low-EMI PCB design. Inner layers can be spaced
closer than outer layers and used to create a high-frequency bypass capacitor between GNDP and GNDS
to reduce radiated emissions. Ensure proper spacing, both inter-layer and layer-to-layer, is implemented to
avoid reducing isolation capabilities. These spacings will vary based on the printed circuit board construction
parameters, such as dielectric material and thickness.
6. Pay close attention to the spacing between primary ground plane (GNDP) and secondary ground plane
(GNDS) on the PCB outer layers. The effective creepage and or clearance of the system will be reduced if
the two ground planes have a lower spacing than that of the device package.
7. To ensure isolation performance between the primary and secondary side, avoid placing any PCB traces or
copper below the UCC12040 device on the outer copper layers.
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10.2 Layout Example
Figure 10-1. Layout Example
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Development Support
For development support, refer to:
•
•
•
High-efficiency, low-emission, isolated DC/DC converter-based analog input module reference design
Isolated delta-sigma modulator based AC/DC voltage and current measurement module reference design
Isolated power architecture reference design for communication and analog input/output modules
11.2 Documentation Support
11.2.1 Related Documentation
For related documentation see the following:
•
•
•
UCC12050 Evaluation Module User Guide
Isolation Glossary
A Reinforced-isolated Analog Input Chain for Space-constrained Applications
11.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
11.4 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.5 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
11.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.7 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical and Packaging Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
14-Jan-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
UCC12040DVE
ACTIVE
ACTIVE
SO-MOD
SO-MOD
DVE
DVE
16
16
40
RoHS & Green
NIPDAU
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 125
-40 to 125
UCC12040
UCC12040
UCC12040DVER
2000 RoHS & Green
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
14-Jan-2021
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
4-Jan-2022
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
UCC12040DVER
SO-MOD
DVE
16
2000
330.0
16.4
10.75 10.7
2.7
12.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
4-Jan-2022
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SO-MOD DVE 16
SPQ
Length (mm) Width (mm) Height (mm)
350.0 350.0 43.0
UCC12040DVER
2000
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
4-Jan-2022
TUBE
*All dimensions are nominal
Device
Package Name Package Type
DVE SO-MOD
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
UCC12040DVE
16
40
506.98
12.7
4826
6.6
Pack Materials-Page 3
PACKAGE OUTLINE
DVE0016A
SO-MOD - 2.65 mm max height
S
C
A
L
E
1
.
5
0
0
SMALL OUTLINE INTEGRATED CIRCUIT
C
10.63
9.97
SEATING PLANE
TYP
PIN 1 ID
AREA
0.1 C
A
14X 1.27
16
1
2X
10.5
10.1
NOTE 3
8.89
8
9
0.51
0.31
16X
7.6
7.4
B
2.65 MAX
0.25
C A B
NOTE 4
0.33
0.10
TYP
SEE DETAIL A
0.25
GAGE PLANE
0.3
0.1
0 - 8
1.27
0.40
DETAIL A
TYPICAL
(1.4)
4224275/B 04/2023
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm, per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side.
5. Reference JEDEC registration MS-013.
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EXAMPLE BOARD LAYOUT
DVE0016A
SO-MOD - 2.65 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
SYMM
SYMM
16X (2)
1
16X (1.65)
SEE
DETAILS
SEE
DETAILS
1
16
16
16X (0.6)
16X (0.6)
(R0.05) TYP
(R0.05) TYP
SYMM
SYMM
14X (1.27)
8
14X (1.27)
9
9
8
(9.79)
(9.3)
HV / ISOLATION OPTION
8.14 mm CLEARANCE/CREEPAGE
IPC-7351 NOMINAL
7.3 mm CLEARANCE/CREEPAGE
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:4X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
METAL
EXPOSED
METAL
EXPOSED
METAL
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4224275/A 04/2023
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DVE0016A
SO-MOD - 2.65 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
SYMM
SYMM
16X (1.65)
16X (2)
1
1
16
16
16X (0.6)
16X (0.6)
SYMM
SYMM
(R0.05) TYP
(R0.05) TYP
14X (1.27)
8
14X (1.27)
8
9
9
(9.79)
(9.3)
HV / ISOLATION OPTION
8.14 mm CLEARANCE/CREEPAGE
IPC-7351 NOMINAL
7.3 mm CLEARANCE/CREEPAGE
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:4X
4224275/B 04/2023
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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