V62/08622-01XE [TI]
12-BIT 200-KSPS 11-CHANNEL LOW-POWER SERIAL ANALOG-TO-DIGITAL CONVERTER WITH INTERNAL REFERENCE; 12位200 KSPS 11通道低功耗串行模拟到数字，内置电压基准转换器
| 型号： | V62/08622-01XE |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 12-BIT 200-KSPS 11-CHANNEL LOW-POWER SERIAL ANALOG-TO-DIGITAL CONVERTER WITH INTERNAL REFERENCE |
| 文件： | 总37页 (文件大小：689K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TLV2556-EP
www.ti.com ................................................................................................................................................... SLAS598A–NOVEMBER 2008–REVISED JULY 2009
12-BIT 200-KSPS 11-CHANNEL LOW-POWER SERIAL ANALOG-TO-DIGITAL CONVERTER
WITH INTERNAL REFERENCE
1
FEATURES
PW AND DW PACKAGE
•
12-Bit-Resolution Analog-to-Digital Converter
(ADC)
(TOP VIEW)
•
Up to 200-KSPS (150-KSPS for 3 V)
Throughput Bit With 12-Output Mode Over
Operating Temperature Range
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
AIN8
GND
V
CC
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
INT/EOC
I/O CLOCK
DATA IN
DATA OUT
CS
•
•
•
11 Analog Input Channels
3 Built-In Self-Test Modes
Programmable Reference (2.048 V/4.096 V
Internal or External)
REF+
REF−
•
•
•
•
Inherent Sample and Hold Function
Linearity Error...±1 LSB Max
On-Chip Conversion Clock
AIN10
AIN9
Programmable Conversion Status Output: INT
or EOC
DESCRIPTION
The TLV2556 is
a
12-bit, switched-capacitor,
•
•
•
•
•
Unipolar or Bipolar Output Operation
Programmable MSB or LSB First
Programmable Power Down
successive-approximation, analog-to-digital converter
(ADC). The ADC has three control inputs [chip select
(CS), the input-output clock, and the address/control
input (DATAIN)], designed for communication with the
serial port of a host processor or peripheral through a
serial 3-state output.
Programmable Output Data Length
SPI Compatible Serial Interface With I/O Clock
Frequencies up to 15 MHz (CPOL = 0,
CPHA = 0)
In addition to the high-speed converter and versatile
control capability, the device has an on-chip
14-channel multiplexer that can select any one of 11
inputs or any one of three internal self-test voltages
using configuration register 1. The sample-and-hold
function is automatic. At the end of conversion, when
programmed as EOC, the pin 19 output goes high to
indicate that conversion is complete. If pin 19 is
programmed as INT, the signal goes low when the
conversion is complete. The converter incorporated in
the device features differential, high-impedance
reference inputs that facilitate ratiometric conversion,
scaling, and isolation of analog circuitry from logic
and supply noise. A switched-capacitor design allows
low-error conversion over the full operating
temperature range. An internal reference is available
and its voltage level is programmable via
configuration register 2 (CFGR2).
SUPPORTS DEFENSE, AEROSPACE,
AND MEDICAL APPLICATIONS
•
•
•
•
Controlled Baseline
One Assembly/Test Site
One Fabrication Site
Available in Military (–55°C/125°C)
Temperature Range(1)
Extended Product Life Cycle
Extended Product-Change Notification
Product Traceability
•
•
•
APPLICATIONS
•
•
•
•
Industrial Process Control
Portable Data Logging
Battery Powered Instruments
Automotive
(1) Additional temperature ranges are available - contact factory
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2008–2009, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
TLV2556-EP
SLAS598A–NOVEMBER 2008–REVISED JULY 2009 ................................................................................................................................................... www.ti.com
The TLV2556 is characterized for operation from TA = –55°C to 125°C.
ORDERING INFORMATION(1)
TA
PACKAGE(2)
ORDERABLE PART NUMBER
TOP-SIDE MARKING
–55°C to 125°C
TSSOP – PW
Reel of 2000
TLV2556MPWREP
TL2556EP
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
Functional Block Diagram
V
20
REF+
14
REF−
13
CC
3
Self Test
4.096/2.048 V
Internal Reference
Reference CTRL
1
2
3
4
5
6
7
8
9
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
AIN8
AIN9
AIN10
Low Power
12-Bit
SAR ADC
Sample
and Hold
19
INT/EOC
14-Channel
Analog
Multiplexer
12
4
Input Address
Register
12
Output Data
Register
11
12
12-to-1
Data
Selector
and Driver
16
DATA
OUT
17
15
18
4
DATA IN
CS
Control Logic
and I/O
Counters
Internal
OSC
I/O CLOCK
10
GND
2
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Product Folder Link(s): TLV2556-EP
TLV2556-EP
www.ti.com ................................................................................................................................................... SLAS598A–NOVEMBER 2008–REVISED JULY 2009
TERMINAL FUNCTIONS
TERMINAL
I/O
DESCRIPTION
NAME
NO.
1–9,
11, 12
AIN0–AIN10
I
Analog input. These 11 analog-signal inputs are internally multiplexed.
Chip select. A high-to-low transition on CS resets the internal counters and controls and enables
DATA OUT, DATA IN, and I/O CLOCK. A low-to-high transition disables DATA IN and I/O CLOCK
within a setup time.
CS
15
17
I
I
Serial data input. The 4-bit serial data can be used as address selects the desired analog input
channel or test voltage to be converted next, or a command to activate other features. The input
data is presented with the MSB (D7) first and is shifted in on the first four rising edges of the I/O
CLOCK. After the four address/command bits are read into the command register CMR, I/O
CLOCK clocks the remaining four bits of configuration in.
DATA IN
The 3-state serial output for the A/D conversion result. DATA OUT is in the high-impedance state
when CS is high and active when CS is low. With a valid CS, DATA OUT is removed from the
high-impedance state and is driven to the logic level corresponding to the MSB(most significant
bit)/LSB(least significant bit) value of the previous conversion result. The next falling edge of I/O
CLOCK drives DATA OUT to the logic level corresponding to the next MSB/LSB, and the remaining
bits are shifted out in order.
DATA OUT
16
O
O
Status output, used to indicate the end of conversion (EOC) or an interrupt (INT) to host processor.
Programmed as INT (interrupt): INT goes from a high to a low logic level after the conversion is
complete and the data is ready for transfer. INT is cleared by a rising I/O CLOCK transition.
INT/EOC
GND
19
10
Programmed as EOC: EOC goes from a high to a low logic level after the falling edge of the last I/O
CLOCK and remains low until the conversion is complete and the data is ready for transfer.
Ground. GND is the ground return terminal for the internal circuitry. Unless otherwise noted, all
voltage measurements are with respect to GND.
Input /output clock. I/O CLOCK receives the serial input and performs the following four functions:
1. It clocks the eight input data bits into the input data register on the first eight rising edges of
I/O CLOCK with the multiplexer address available after the fourth rising edge.
2. On the fourth falling edge of I/O CLOCK, the analog input voltage on the selected multiplexer
input begins charging the capacitor array and continues to do so until the last falling edge of
I/O CLOCK.
I/O CLOCK
18
I
3. The remaining 11 bits of the previous conversion data are shifted out on DATA OUT. Data
changes on the falling edge of I/O CLOCK.
4. Control of the conversion is transferred to the internal state controller on the falling edge of the
last I/O CLOCK.
Positive reference voltage The upper reference voltage value (nominally VCC) is applied to REF+.
The maximum analog input voltage range is determined by the difference between the voltage
applied to terminals REF+ and REF–.
REF+
14
I/O
I/O
When the internal reference is used it is capable of driving a 10-kΩ, 10-pF load.
Negative reference voltage. The lower reference voltage value (nominally ground) is applied to
REF–. This pin is connected to analog ground (GND of the ADC) when the internal reference is
used.
REF–
VCC
13
20
Positive supply voltage
Copyright © 2008–2009, Texas Instruments Incorporated
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SLAS598A–NOVEMBER 2008–REVISED JULY 2009 ................................................................................................................................................... www.ti.com
ABSOLUTE MAXIMUM RATINGS(1)(2)
over operating free-air temperature range (unless otherwise noted)
VCC
VI
Supply voltage range
–0.5 V to 6.5 V
–0.3 V to VCC + 0.3 V
–0.3 V to VCC + 0.3 V
–0.3 V to VCC + 0.3 V
–0.3 V to VCC + 0.3 V
±20 mA
Input voltage range (any input)
VO
Output voltage range
VREF+
VREF–
II
Positive reference voltage range
Negative reference voltage range
Peak input current (any input)
Peak total input current (all inputs)
Operating virtual-junction temperature range
Operating free-air temperature range
Storage temperature range
±30 mA
TJ
–55°C to 150°C
–55°C to 125°C
–65°C to 150°C
260°C
TA
Tstg
Lead temperature 1,6 mm (1/16 inch) from the case for 10 seconds
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to the GND terminal with REF– and GND wired together (unless otherwise noted).
RECOMMENDED OPERATING CONDITIONS
MIN NOM
2.7
MAX UNIT
VCC
Supply voltage
5.5
15
V
16-bit I/O
12-bit I/O
8-bit I/O
0.01
VCC = 4.5 V to 5.5 V
0.01
15
SCLK frequency
MHz
0.01
15
VCC = 2.7 V to 3.6 V
VCC = 4.5 V to 5.5 V
VCC = 4.5 V to 5.5 V
VCC = 4.5 V to 5.5 V
VCC = 3 V to 3.6 V
VCC = 2.7 V to 3 V
VCC = 4.5 V to 5.5 V
VCC = 2.7 V to 3.6 V
VCC = 4.5 V to 5.5 V
VCC = 2.7 V to 3.6 V
0.01
10
Tolerable clock jitter, I/O CLOCK
Aperture jitter
0.38
ns
ps
100
0
0
(REF+) – (REF–)
(REF+) – (REF–)
(REF+) – (REF–)
Analog input voltage(1)
V
V
0
2
VIH
High level control input voltage
2.1
0.8
0.6
VIL
TA
Low level control input voltage
Operating free-air temperature
V
–55
125
°C
(1) Analog input voltages greater than the voltage applied to REF+ convert as all ones (111111111111), while input voltages less than the
voltage applied to REF– convert as all zeros (000000000000).
4
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TLV2556-EP
www.ti.com ................................................................................................................................................... SLAS598A–NOVEMBER 2008–REVISED JULY 2009
ELECTRICAL CHARACTERISTICS
over recommended operating free-air temperature range, VREF+ = 5 V,
SCLK frequency = 15 MHz when VCC = 5 V, VREF+ = 2.5 V,
SCLK frequency = 10 MHz when VCC = 2.7 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC = 4.5 V, IOH = –1.6 mA
MIN TYP(1)
MAX UNIT
2.4
VCC = 2.7 V, IOH = –0.2 mA
VOH
High-level output voltage
30 pF
V
VCC = 4.5 V, IOH = –20 µA
VCC = 2.7 V, IOH = –20 µA
VCC – 0.1
VCC = 5.5 V, IOL = 1.6 mA
VCC = 3.6 V, IOL = 0.8 mA
0.4
V
VOH
Low-level output voltage
30 pF
VCC = 5.5 V, IOL = –20 µA
VCC = 3.6 V, IOL = –20 µA
0.1
VO = VCC, CS = VCC
VO = 0 V, CS = VCC
1
2.5
µA
IOZ
High impedance off state output current
–1
–2.5
VCC = 5 V
VCC = 2.7 V
VCC = 5 V
VCC = 2.7 V
1.2
CS at 0 V, External reference
CS at 0 V, Internal reference
0.9
mA
3
ICC
Operating supply current
2.4
External
reference
0.1
0.1
0.1
10
µA
10
For all digital inputs,
0 V ≤ VI ≤ 0.5 V or
VI ≥ VCC – 0.5 V, SCLK = 0 V
ICC(SP
D)
Software power down current
Auto power down current
Internal
reference
External
reference
10
µA
For all digital inputs,
0 V ≤ VI ≤ 0.5 V or
VI ≥ VCC – 0.5 V, SCLK = 0 V
ICC(AP
D)
Internal
reference
1800
IIH
IIL
High-level input current
Low-level input current
VI = VCC
VI = 0 V
0.005
2.5
µA
µA
–0.005
–2.5
Selected channel at VCC
Unselected channel at 0 V
,
1
Ilkg
Selected channel leakage current
µA
Selected channel at 0 V,
Unselected channel at VCC
–1
VCC = 4.5 V to 5.5 V
VCC = 2.7 V to 3.6 V
VCC = 4.5 V to 5.5 V
VCC = 2.7 V to 3.6 V
3.0
2.1
f(OSC) Internal oscillator frequency
MHz
4.53
6.46
tconv
Conversion time = 13.5 × f(OSC) + 25 ns
µs
V
Internal oscillator frequency
switch-over voltage
3.9
VCC = 4.5 V
VCC = 2.7 V
Analog inputs
Control inputs
600
500
45
Zi
Analog input MUX impedance(2)
Ω
Ci
Input capacitance
pF
5
(1) All typical values are at VCC = 5 V, TA = 25°C.
(2) The switch resistance is very nonlinear and varies with input voltage and supply voltage.
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SLAS598A–NOVEMBER 2008–REVISED JULY 2009 ................................................................................................................................................... www.ti.com
EXTERNAL REFERENCE SPECIFICATIONS(1)
PARAMETER
TEST CONDITIONS
MIN TYP(2)
MAX UNIT
VCC = 4.5 V to 5.5 V
VCC = 2.7 V to 3.6 V
VCC = 4.5 V to 5.5 V
VCC = 2.7 V to 3.6 V
VCC = 4.5 V to 5.5 V
VCC = 2.7 V to 3.6 V
–0.1
–0.1
2
0
0
0.1
V
Reference input voltage, REF–
0.1
VCC
Reference input voltage, REF+
V
2
VCC
1.9
1.9
VCC
External reference input voltage
difference, (REF+) – (REF–)
V
VCC
VCC = 4.5 V to 5.5 V
1
mA
0.7
External reference supply current
CS = 0 V
VCC = 2.7 V to 3.6 V
Static
1
9
1
9
MΩ
kΩ
VCC = 5 V
VCC = 2.7 V
During sampling/conversion
Static
Reference input impedance
MΩ
kΩ
During sampling/conversion
(1) Add a 0.1-µF capacitor between REF+ and REF– pins when external reference is used.
(2) All typical values are at VCC = 5 V, TA = 25°C.
INTERNAL REFERENCE SPECIFICATIONS(1)
PARAMETER
TEST CONDITIONS
MIN TYP(2)
MAX
UNIT
Reference input voltage, REF–
VCC = 2.7 V to 5.5 V, REF– = Analog GND
VCC = 5.5 V, Internal 4.096-V VREF selected
VCC = 5.5 V, Internal 2.048-V VREF selected
VCC = 2.7 V, Internal 2.048-V VREF selected
0
3.95 4.065
1.94 2.019
1.94 2.019
20
V
4.25
2.15
2.15
Internal reference voltage delta, (REF+) – (REF–)
V
VCC = 5 V
Internal reference start up time
With 10-µF load
VCC = 2.7 V
ms
20
Internal reference temperature coefficient
VCC = 2.7 V to 5.5 V
±50
ppm/°C
(1) When an internal reference is used, the following conditions are required:
a. Add 0.1-µF and 10-µF capacitors between REF+ and REF– pins.
b. REF– must be connected to analog GND (the ground pin of the ADC).
(2) All typical values are at VCC = 5 V, TA = 25°C.
6
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OPERATING CHARACTERISTICS
over recommended operating free-air temperature range, VREF+ = 5 V,
SCLK frequency = 15 MHz when VCC = 5 V, VREF+ = 2.5 V,
SCLK frequency = 10 MHz when VCC = 2.7 V (unless otherwise noted)
PARAMETER
Integral nonlinearity error(2)
TEST CONDITIONS
MIN TYP(1)
MAX UNIT
INL
DNL
EO
–1
1
1
2
3
LSB
LSB
mV
Differential nonlinearity error
Offset error(3)(4)
Gain error(3)(4)
–1
–2
EG
–3
mV
ET
Total unadjusted error(5)
±1.5
2048
0
LSB
Address data input = 1011
Address data input = 1100
Address data input = 1101
Self-test output code(6) (see Table 2)
4095
(1) All typical values are at VCC = 5 V, TA = 25°C.
(2) Linearity error is the maximum deviation from the best straight line through the A/D transfer characteristics.
(3) Analog input voltages greater than the voltage applied to REF+ convert as all ones (111111111111), while input voltages less than the
voltage applied to REF– convert as all zeros (000000000000).
(4) Gain error is the difference between the actual mid-step value and the nominal mid-step value in the transfer diagram at the specified
gain point after the offset error has been adjusted to zero. Offset error is the difference between the actual mid-step value and the
nominal mid-step value at the offset point.
(5) Total unadjusted error comprises linearity, zero-scale, and full-scale errors.
(6) Both the input address and the output codes are expressed in positive logic.
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TIMING CHARACTERISTICS(1)
operating characteristics, VREF+ = 5 V, SCLK frequency = 15 MHz, VCC = 5 V, load = 25 pF, TA= -40°C to 85°C (unless
otherwise noted)
PARAMETER
Pulse duration I/O CLOCK high or low
MIN
26.7
12
0
TYP
MAX UNIT
tw1
tsu1
th1
tsu2
th2
th3
th4
th5
th6
100000
ns
ns
ns
ns
ns
ns
ns
ns
ns
Setup time DATA IN valid before I/O CLOCK rising edge (see Figure 38)
Hold time DATA IN valid after I/O CLOCK rising edge (see Figure 38)
Setup time CS low before 1st rising I/O CLOCK edge(2) (see Figure 39)
Hold time CS pulse duration high time (see Figure 39)
25
100
0
Hold time CS low after last I/O CLOCK falling edge (see Figure 39)
Hold time DATA OUT valid after I/O CLOCK falling edge (see Figure 40)
Hold time CS high after EOC rising edge when CS is toggled (see Figure 43)
Hold time CS high after INT falling edge (see Figure 43)
2
0
0
Hold time I/O CLOCK low after EOC rising edge or INT falling edge when CS is held
low (see Figure 44)
th7
td1
10
ns
ns
Load = 25 pF
Load = 10 pF
28
20
10
20
55
1.5
Delay time CS falling edge to DATA OUT valid
(MSB or LSB) (see Figure 37)
td2
td3
td4
td5
td6
Delay time CS rising edge to DATA OUT high impedance (see Figure 37)
Delay time I/O CLOCK falling edge to next DATA OUT bit valid (see Figure 40)
Delay time last I/O CLOCK falling edge to EOC falling edge (see Figure 41)
Delay time last I/O CLOCK falling edge to CS falling edge to abort conversion
Delay time last I/O CLOCK falling edge to INT falling edge (see Figure 41)
ns
ns
ns
µs
ns
2
MAX(tconv
)
Delay time EOC rising edge or INT falling edge to DATA OUT valid: MSB or LSB first
(see Figure 42)
td7
4
ns
td9
tt1
tt2
tt3
tt4
Delay time I/O CLOCK high to INT rising edge when CS is held low (see Figure 44)
Transition time I/O CLOCK(2) (see Figure 40)
1
28
1
ns
µs
ns
ns
µs
Transition time DATA OUT (see Figure 40)
5
Transition time INT/EOC, CL = 7 pF (see Figure 41 and Figure 42)
Transition time DATA IN, CS
2.4
10
MAX(tconv) +
I/O period
tcyc
Total cycle time (sample, conversion and delays)(2)
µs
(8/12/16 CLKs)
Source impedance = 25 Ω
Source impedance = 100 Ω
600
650
tsample Channel acquisition time (sample), at 1 kΩ(2)
ns
Source impedance = 500 Ω
Source impedance = 1 kΩ
700
1000
(1) Timing parameters are not production tested.
(2) I/O CLOCK period = 8x [1/(I/O CLOCK frequency)] or 12x [1/(I/O CLOCK frequency)] or 16x [1/(I/O CLOCK frequency)] depends on I/O
format selected.
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www.ti.com ................................................................................................................................................... SLAS598A–NOVEMBER 2008–REVISED JULY 2009
TIMING CHARACTERISTICS(1)
operating characteristics, VREF+ = 2.5 V, SCLK frequency = 10 MHz, VCC = 2.7 V, load = 25 pF, TA= -40°C to 85°C (unless
otherwise noted)
PARAMETER
Pulse duration I/O CLOCK high or low
MIN
40
22
0
TYP
MAX UNIT
tw1
tsu1
th1
tsu2
th2
th3
th4
th5
th6
100000
ns
ns
ns
ns
ns
ns
ns
ns
ns
Setup time DATA IN valid before I/O CLOCK rising edge (see Figure 38)
Hold time DATA IN valid after I/O CLOCK rising edge (see Figure 38)
Setup time CS low before 1st rising I/O CLOCK edge(2) (see Figure 39)
Hold time CS pulse duration high time (see Figure 39)
33
100
0
Hold time CS low after last I/O CLOCK falling edge (see Figure 39)
Hold time DATA OUT valid after I/O CLOCK falling edge (see Figure 40)
Hold time CS high after EOC rising edge when CS is toggled (see Figure 43)
Hold time CS high after INT falling edge (see Figure 43)
2
0
0
Hold time I/O CLOCK low after EOC rising edge or INT falling edge when CS is held
low (see Figure 44)
th7
td1
10
ns
ns
Load = 25 pF
Load = 10 pF
30
22
10
33
75
1.5
Delay time CS falling edge to DATA OUT valid
(MSB or LSB) (see Figure 37)
td2
td3
td4
td5
td6
Delay time CS rising edge to DATA OUT high impedance (see Figure 37)
Delay time I/O CLOCK falling edge to next DATA OUT bit valid (see Figure 40)
Delay time last I/O CLOCK falling edge to EOC falling edge (see Figure 41)
Delay time last I/O CLOCK falling edge to CS falling edge to abort conversion
Delay time last I/O CLOCK falling edge to INT falling edge (see Figure 41)
ns
ns
ns
µs
ns
2
MAX(tconv
)
Delay time EOC rising edge or INT falling edge to DATA OUT valid: MSB or LSB first
(see Figure 42)
td7
20
ns
td9
tt1
tt2
tt3
tt4
Delay time I/O CLOCK high to INT rising edge when CS is held low (see Figure 44)
Transition time I/O CLOCK(2) (see Figure 40)
1
55
1
ns
µs
ns
ns
µs
Transition time DATA OUT (see Figure 40)
5
Transition time INT/EOC, CL = 7 pF (see Figure 41 and Figure 42)
Transition time DATA IN, CS
4
10
MAX(tconv) +
I/O period
tcyc
Total cycle time (sample, conversion and delays)(2)
µs
(8/12/16 CLKs)
Source impedance = 25 Ω
Source impedance = 100 Ω
800
850
tsample Channel acquisition time (sample), at 1 kΩ(2)
ns
Source impedance = 500 Ω
Source impedance = 1 kΩ
1000
1600
(1) Timing parameters are not production tested.
(2) I/O CLOCK period = 8x [1/(I/O CLOCK frequency)] or 12x [1/(I/O CLOCK frequency)] or 16x [1/(I/O CLOCK frequency)] depends on I/O
format selected.
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TYPICAL CHARACTERISTICS
All typical curves are with internal reference unless specified otherwise. See the TLV2553 data sheet (SLAS354) for typical
curves using an external reference.
SUPPLY CURRENT
vs
AUTO POWER DOWN
vs
FREE-AIR TEMPERATURE
FREE-AIR TEMPERATURE
1100
1050
1000
0.8
V
V
V
= 3.3 V
CC
= 2.048 V
REF+
= 0 V
REF−
I/O CLOCK = 10 MHz
150 KSPS,
0.78
T
A
= 25°C
0.76
0.74
V
V
V
= 3.3 V
CC
= 2.048 V
= 0 V
REF+
REF−
950
900
0.72
0.7
I/O CLOCK = 10 MHz
150 KSPS,
T
A
= 25°C
25
85
−40
−40
25
85
T
A
− Free-Air Temperature − °C
T
A
− Free-Air Temperature − °C
Figure 1.
Figure 2.
SOFTWARE POWER DOWN
vs
2-V INTERNAL REFERENCE CURRENT
vs
FREE-AIR TEMPERATURE
FREE-AIR TEMPERATURE
0.25
0.2
1.15
1.1
V
V
V
= 3.3 V
CC
= 2.048 V
= 0 V
REF+
REF−
I/O CLOCK = 10 MHz
150 KSPS,
T
A
= 25°C
0.15
1.05
1
0.1
V
V
V
= 3.3 V
CC
= 2.048 V
= 0 V
REF+
REF−
0.05
0
I/O CLOCK = 10 MHz
150 KSPS,
T
A
= 25°C
0.95
−40
25
85
25
85
−40
T
A
− Free-Air Temperature − °C
T
A
− Free-Air Temperature − °C
Figure 3.
Figure 4.
10
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TYPICAL CHARACTERISTICS (continued)
All typical curves are with internal reference unless specified otherwise. See the TLV2553 data sheet (SLAS354) for typical
curves using an external reference.
MINIMUM DIFFERENTIAL NONLINEARITY
MAXIMUM DIFFERENTIAL NONLINEARITY
vs
vs
FREE-AIR TEMPERATURE
FREE-AIR TEMPERATURE
1
0
V
V
V
= 2.7 V
V
V
V
= 2.7 V
CC
CC
= 2.048 V
= 0 V
= 2.048 V
= 0 V
REF+
REF−
REF+
REF−
−0.1
0.9
0.8
I/O CLOCK = 10 MHz
150 KSPS,
T = 25°C
A
I/O CLOCK = 10 MHz
150 KSPS,
−0.2
−0.3
−0.4
−0.5
−0.6
−0.7
T
A
= 25°C
0.7
0.6
0.5
0.4
0.3
0.2
−0.8
−0.9
−1
0.1
0
−40
25
85
−40
25
85
T
A
− Free-Air Temperature − °C
T
A
− Free-Air Temperature − °C
Figure 5.
Figure 6.
MAXIMUM INTEGRAL NONLINEARITY
MINIMUM INTEGRAL NONLINEARITY
vs
vs
FREE-AIR TEMPERATURE
FREE-AIR TEMPERATURE
0
1
V
CC
= 2.7 V
V
V
= 2.048 V
= 0 V
REF+
REF−
−0.1
0.9
I/O CLOCK = 10 MHz
150 KSPS,
0.8
0.7
0.6
−0.2
−0.3
−0.4
T
A
= 25°C
−0.5
−0.6
0.5
0.4
−0.7
V
CC
= 2.7 V
0.3
V
V
= 2.048 V
= 0 V
REF+
REF−
−0.8
−0.9
−1
0.2
0.1
0
I/O CLOCK = 10 MHz
150 KSPS,
T
A
= 25°C
−40
25
85
25
85
−40
T
A
− Free-Air Temperature − °C
Figure 7.
T
A
− Free-Air Temperature − °C
Figure 8.
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TYPICAL CHARACTERISTICS (continued)
All typical curves are with internal reference unless specified otherwise. See the TLV2553 data sheet (SLAS354) for typical
curves using an external reference.
DIFFERENTIAL NONLINEARITY ERROR
vs
CODES
1.5
V
CC
= 2.7 V, V = 2.048 V, V
REF+ REF−
= 0 V, I/O
CLOCK = 10 MHz, 150 KSPS, T = 25°C
1
0.5
0
A
−0.5
−1
−1.5
0
1024
2048
3072
4096
Codes
Figure 9.
INTEGRAL NONLINEARITY ERROR
vs
CODES
1.5
V
= 2.7 V, V
= 2.048 V, V
= 0 V, I/O
CC
REF+
REF−
A
1
0.5
0
CLOCK = 10 MHz, 150 KSPS, T = 25°C
−0.5
−1
−1.5
0
1024
2048
3072
4096
Codes
Figure 10.
12
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TYPICAL CHARACTERISTICS (continued)
All typical curves are with internal reference unless specified otherwise. See the TLV2553 data sheet (SLAS354) for typical
curves using an external reference.
GAIN ERROR
vs
OFFSET ERROR
vs
FREE-AIR TEMPERATURE
FREE-AIR-TEMPERATURE
0.05
0.04
0.03
0
V
V
V
= 3.3 V
CC
= 2.048 V
= 0 V
REF+
REF−
I/O CLOCK = 10 MHz
150 KSPS,
T
A
= 25°C
−0.05
−0.1
0.02
0.01
0
V
V
V
= 3.3 V
CC
= 2.048 V
= 0 V
REF+
REF−
I/O CLOCK = 10 MHz
150 KSPS,
T
A
= 25°C
−0.15
−40
T
25
85
−40
T
25
85
− Free-Air Temperature − °C
− Free-Air Temperature − °C
A
A
Figure 11.
Figure 12.
SUPPLY CURRENT
vs
AUTO POWER DOWN
vs
FREE-AIR TEMPERATURE
FREE-AIR TEMPERATURE
1120
0.99
0.98
V
= 5.5 V
= 4.096 V
= 0 V
CC
V
V
V
CC
V
V
REF+
REF−
I/O CLOCK = 15 MHz
200 KSPS,
I/O CLOCK = 15 MHz
200 KSPS,
1100
1080
T
A
= 25°C
T
A
= 25°C
0.97
0.96
0.95
1060
1040
0.94
0.93
1020
−40
25
85
25
85
−40
T
A
− Free-Air Temperature − °C
T
A
− Free-Air Temperature − °C
Figure 13.
Figure 14.
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TYPICAL CHARACTERISTICS (continued)
All typical curves are with internal reference unless specified otherwise. See the TLV2553 data sheet (SLAS354) for typical
curves using an external reference.
SOFTWARE POWER DOWN
vs
4-V INTERNAL REFERENCE CURRENT
vs
FREE-AIR TEMPERATURE
FREE-AIR TEMPERATURE
1.55
1.5
0.5
0.4
0.3
V
V
V
= 5.5 V
CC
= 4.096 V
= 0 V
REF+
REF−
I/O CLOCK = 15 MHz
200 KSPS,
1.45
1.4
T
A
= 25°C
1.35
1.3
0.2
0.1
0
V
V
V
= 5.5 V
CC
= 4.096 V
= 0 V
REF+
REF−
I/O CLOCK = 15 MHz
200 KSPS,
1.25
1.2
T
A
= 25°C
−40
25
85
−40
25
85
T
A
− Free-Air Temperature − °C
T
A
− Free-Air Temperature − °C
Figure 15.
Figure 16.
MAXIMUM DIFFERENTIAL NONLINEARITY
MINIMUM DIFFERENTIAL NONLINEARITY
vs
vs
FREE-AIR TEMPERATURE
FREE-AIR TEMPERATURE
0
1
0.9
0.8
V
V
V
= 5.5 V
CC
V
V
V
= 5.5 V
CC
= 4.096 V
= 0 V
REF+
REF−
= 4.096 V
= 0 V
−0.1
−0.2
REF+
REF−
I/O CLOCK = 15 MHz
200 KSPS,
I/O CLOCK = 15 MHz
200 KSPS,
T
A
= 25°C
T
A
= 25°C
−0.3
0.7
0.6
−0.4
−0.5
0.5
0.4
−0.6
−0.7
0.3
0.2
−0.8
−0.9
−1
0.1
0
−40
25
85
25
85
−40
T
A
− Free-Air Temperature − °C
T
A
− Free-Air Temperature − °C
Figure 17.
Figure 18.
14
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TYPICAL CHARACTERISTICS (continued)
All typical curves are with internal reference unless specified otherwise. See the TLV2553 data sheet (SLAS354) for typical
curves using an external reference.
MAXIMUM INTEGRAL NONLINEARITY
MINIMUM INTEGRAL NONLINEARITY
vs
vs
FREE-AIR TEMPERATURE
FREE-AIR TEMPERATURE
1
0.9
0.8
0
−0.1
−0.2
−0.3
−0.4
0.7
0.6
V
V
V
= 5.5 V
CC
= 4.096 V
= 0 V
REF+
REF−
I/O CLOCK = 15 MHz
200 KSPS,
−0.5
−0.6
0.5
0.4
T
A
= 25°C
V
V
V
= 5.5 V
CC
−0.7
0.3
= 4.096 V
= 0 V
REF+
REF−
−0.8
−0.9
−1
0.2
0.1
0
I/O CLOCK = 15 MHz
200 KSPS,
T
A
= 25°C
−40
25
85
−40
25
85
T
A
− Free-Air Temperature − °C
T
A
− Free-Air Temperature − °C
Figure 19.
Figure 20.
DIFFERENTIAL NONLINEARITY ERROR
vs
CODES
1.5
1
V
= 5.5 V, V
= 4.096 V, V
= 0 V, I/O
CC
REF+
REF−
A
CLOCK = 15 MHz, 200 KSPS, T = 25°C
0.5
0
−0.5
−1
−1.5
0
1024
2048
3072
4096
Codes
Figure 21.
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TYPICAL CHARACTERISTICS (continued)
All typical curves are with internal reference unless specified otherwise. See the TLV2553 data sheet (SLAS354) for typical
curves using an external reference.
INTEGRAL NONLINEARITY ERROR
vs
CODES
1.5
V
CC
= 5.5 V, V
= 4.096 V, V
= 0 V, I/O
REF+
REF−
CLOCK = 15 MHz, 200 KSPS, T = 25°C
A
1
0.5
0
−0.5
−1
−1.5
0
1024
2048
3072
4096
Codes
Figure 22.
OFFSET ERROR
vs
GAIN ERROR
vs
FREE-AIR-TEMPERATURE
FREE-AIR TEMPERATURE
0
0.2
0.15
0.1
V
V
V
= 5.5 V
V
V
V
= 5.5 V
CC
CC
= 4.096 V
= 0 V
= 4.096 V
= 0 V
REF+
REF−
REF+
REF−
I/O CLOCK = 15 MHz
200 KSPS,
I/O CLOCK = 15 MHz
200 KSPS,
−0.2
T
A
= 25°C
T
A
= 25°C
−0.4
−0.6
−0.8
0.05
0
−40
25
85
−40
25
85
T
A
− Free-Air Temperature − °C
T
A
− Free-Air Temperature − °C
Figure 24.
Figure 23.
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TYPICAL CHARACTERISTICS (continued)
All typical curves are with internal reference unless specified otherwise. See the TLV2553 data sheet (SLAS354) for typical
curves using an external reference.
SUPPLY CURRENT
vs
SOFTWARE POWER DOWN
vs
FREE-AIR TEMPERATURE
FREE-AIR TEMPERATURE
0.96
0.94
0.92
0.9
0.5
0.4
0.3
V
V
V
= 5.5 V
CC
V
V
V
= 5.5 V
CC
= 2.048 V
= 0 V
REF+
REF−
= 2.048 V
= 0 V
REF+
REF−
I/O CLOCK = 15 MHz
200 KSPS,
I/O CLOCK = 15 MHz
200 KSPS,
T
A
= 25°C
T
A
= 25°C
0.88
0.86
0.2
0.1
0
0.84
0.82
−40
T
25
85
−40
T
25
85
− Free-Air Temperature − °C
Figure 25.
− Free-Air Temperature − °C
A
A
Figure 26.
AUTO POWER DOWN
vs
2-V INTERNAL REFERENCE CURRENT
vs
FREE-AIR TEMPERATURE
FREE-AIR TEMPERATURE
1.25
1.2
1010
1005
V
V
V
= 5.5 V
CC
V
= 5.5 V
= 2.048 V
= 0 V
CC
= 2.048 V
= 0 V
REF+
REF−
V
V
REF+
REF−
I/O CLOCK = 15 MHz
200 KSPS,
I/O CLOCK = 15 MHz
200 KSPS,
T
A
= 25°C
T
A
= 25°C
1.15
1000
995
1.1
1.05
1
990
985
0.95
25
85
−40
T
−40
25
85
T
A
− Free-Air Temperature − °C
− Free-Air Temperature − °C
A
Figure 27.
Figure 28.
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TYPICAL CHARACTERISTICS (continued)
All typical curves are with internal reference unless specified otherwise. See the TLV2553 data sheet (SLAS354) for typical
curves using an external reference.
MAXIMUM DIFFERENTIAL NONLINEARITY
MINIMUM DIFFERENTIAL NONLINEARITY
vs
vs
FREE-AIR TEMPERATURE
FREE-AIR TEMPERATURE
1
0
V
V
V
= 5.5 V
CC
0.9
0.8
−0.1
−0.2
= 2.048 V
= 0 V
REF+
REF−
I/O CLOCK = 15 MHz
200 KSPS,
T
A
= 25°C
−0.3
0.7
0.6
−0.4
−0.5
0.5
0.4
−0.6
−0.7
V
V
V
= 5.5 V
0.3
0.2
CC
= 2.048 V
= 0 V
REF+
REF−
−0.8
−0.9
−1
I/O CLOCK = 15 MHz
200 KSPS,
0.1
0
T
A
= 25°C
−40
25
85
−40
25
85
T
A
− Free-Air Temperature − °C
T
A
− Free-Air Temperature − °C
Figure 29.
Figure 30.
MAXIMUM INTEGRAL NONLINEARITY
MINIMUM INTEGRAL NONLINEARITY
vs
vs
FREE-AIR TEMPERATURE
FREE-AIR TEMPERATURE
1
0
−0.1
−0.2
−0.3
−0.4
V
= 5.5 V
= 2.048 V
= 0 V
CC
V
V
REF+
REF−
0.9
0.8
I/O CLOCK = 15 MHz
200 KSPS,
T
A
= 25°C
0.7
0.6
0.5
0.4
−0.5
−0.6
V
V
V
= 5.5 V
0.3
CC
−0.7
−0.8
= 2.048 V
= 0 V
REF+
REF−
0.2
0.1
I/O CLOCK = 15 MHz
200 KSPS,
−0.9
−1
T
A
= 25°C
0
−40
25
85
−40
25
85
T
A
− Free-Air Temperature − °C
T
A
− Free-Air Temperature − °C
Figure 31.
Figure 32.
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TYPICAL CHARACTERISTICS (continued)
All typical curves are with internal reference unless specified otherwise. See the TLV2553 data sheet (SLAS354) for typical
curves using an external reference.
OFFSET ERROR
vs
GAIN ERROR
vs
FREE-AIR-TEMPERATURE
FREE-AIR TEMPERATURE
0.4
0.3
0.2
0.1
0
0
V
V
V
= 5.5 V
CC
= 2.048 V
= 0 V
REF+
REF−
I/O CLOCK = 15 MHz
200 KSPS,
−0.2
T
A
= 25°C
−0.4
−0.6
−0.8
V
V
V
= 5.5 V
CC
= 2.048 V
= 0 V
REF+
REF−
I/O CLOCK = 15 MHz
200 KSPS,
T
A
= 25°C
−40
25
85
−40
25
85
T
A
− Free-Air Temperature − °C
T
A
− Free-Air Temperature − °C
Figure 33.
Figure 34.
DIFFERENTIAL NONLINEARITY ERROR
vs
CODES
1.5
1
V
= 5.5 V, V
= 2.048 V, V
= 0 V, I/O
CC
REF+
REF−
A
CLOCK = 10 MHz, 200 KSPS, T = 25°C
0.5
0
−0.5
−1
−1.5
0
1024
2048
3072
4096
Codes
Figure 35.
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TYPICAL CHARACTERISTICS (continued)
All typical curves are with internal reference unless specified otherwise. See the TLV2553 data sheet (SLAS354) for typical
curves using an external reference.
INTEGRAL NONLINEARITY ERROR
vs
CODES
1.5
V
= 5.5 V, V
= 2.048 V, V
= 0 V, I/O
CC
REF+ REF−
1
0.5
0
CLOCK = 15 MHz, 200 KSPS, T = 25°C
A
−0.5
−1
−1.5
0
1024
2048
3072
4096
Codes
Figure 36.
20
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PARAMETER MEASUREMENT INFORMATION
V
IH
Data Valid
CS
V
IL
V
V
IH
DATA IN
V
IL
t
d1
t
d2
t
h1
V
V
OH
DATA
OUT
t
su1
OL
IH
IL
I/O CLOCK
V
Figure 37. DATA OUT to Hi-Z Voltage Waveforms
Figure 38. DATA IN and I/O CLOCK Voltage
t
t1
V
IH
t
t1
CS
V
IL
V
IH
I/O CLOCK
t
h2
V
IL
t
h3
t
su2
I/O CLOCK Period
V
V
IH
t
d3
I/O CLOCK
Last
Clock
IL
t
h4
V
V
OH
DATA
OUT
OL
t
t2
Figure 39. CS and I/O CLOCK Voltage Waveforms
Figure 40. I/O CLOCK and DATA OUT Voltage
Waveforms
V
IH
t
t3
t3
I/O CLOCK
V
V
OH
Last
V
IL
EOC
INT
Clock
OL
t
conv
t
d4
t
V
V
OH
V
V
OH
EOC
INT
OL
OL
t
t3
t
d7
t
t3
V
OH
V
V
OH
DATA
OUT
V
OL
OL
t
MSB
Valid
d6
Figure 41. I/O CLOCK and EOC Voltage Waveforms
Figure 42. EOC and DATA OUT Voltage Waveforms
V
I/O CLOCK
EOC
IL
CS
V
IL
t
h7
t
h5
V
OH
V
OH
EOC
t
d9
t
h6
V
OH
V
OL
INT
INT
V
OL
Figure 43. CS and EOC Voltage Waveforms
Figure 44. I/O CLOCK and EOC Voltage Waveforms
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PARAMETER MEASUREMENT INFORMATION (continued)
Timing Information
First Cycle After Power-Up: Configure CFGR2
Configure CFGR1
1st Conversion Cycle
CS
Access Cycle
Data Cycle
1
3
4
7
2
5
6
8
9
10
11
12
16
1
I/O CLOCK
DATA OUT
DATA IN
Invalid Conversion Data
Hi−Z State
Command 1111
CFGR2 Data
D2 D1
D3
D0
D7
Figure 45. Timing for CFGR2 Configuration
The host must configure CFGR2 before valid device conversions can begin. This can be accessed through
command 1111. This can be done using 8, 12, or 16 I/O CLOCK clocks. (A minimum of 8 is required to fully
program CFGR2.)
After CFGR2 is configured, the following cycle configures CFGR1 and a valid sample/conversion is performed.
CS can be held low for each remaining cycle. First valid conversion output data is available on the third cycle
after power up.
Timing Diagrams
Shift in New Multiplexer Address,
Simultaneously Shift Out Previous Conversion Result
CS
Access
Sample Cycle
Cycle
1
3
4
7
2
5
6
8
9
10
11
12
3
1
2
I/O
CLOCK
Previous Conversion Data
MSB MSB−1 MSB−2 MSB−3 MSB−4 MSB−5 MSB−6 MSB−7 MSB−8 MSB−9 LSB+1 LSB
Hi−Z State
DATA
OUT
MSB MSB−1 MSB−2
Channel
Address
Output Data
Format
DATA
IN
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
A/D Conversion Interval
t
conv
EOC
INT
Initialize
Initialize
A. To minimize errors caused by noise at CS, the internal circuitry waits for a setup time after the CS falling edge before
responding to control input signals. Therefore, no attempt should be made to clock in an address until the minimum
CS setup time has elapsed.
Figure 46. Timing for 12-Clock Transfer Using CS With DATA OUT Set for MSB First
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PARAMETER MEASUREMENT INFORMATION (continued)
Shift in New Multiplexer Address,
Simultaneously Shift Out Previous Conversion Result
CS
Access
Sample Cycle
Cycle
1
3
4
2
5
6
7
8
9
10
11
12
3
1
2
I/O
CLOCK
Previous Conversion Data
DATA
OUT
MSB MSB−1 MSB−2 MSB−3 MSB−4 MSB−5 MSB−6 MSB−7 MSB−8 MSB−9 LSB+1 LSB
MSB−1 MSB−2
MSB
Low Level
Channel
Address
Output Data
Format
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
DATA IN
A/D Conversion Interval
t
conv
EOC
INT
Initialize
Initialize
A. To minimize errors caused by noise at CS, the internal circuitry waits for a setup time after the CS falling edge before
responding to control input signals. Therefore, no attempt should be made to clock in an address until the minimum
CS setup time has elapsed.
Figure 47. Timing for 12-Clock Transfer Not Using CS With DATA OUT Set for MSB First
Shift in New Multiplexer Address,
Simultaneously Shift Out Previous Conversion Result
CS
Access
Cycle
Sample Cycle
1
3
4
7
2
5
6
8
4
7
1
3
5
6
2
I/O
CLOCK
Previous Conversion Data
Hi−Z State
DATA
OUT
MSB MSB−1 MSB−2 MSB−3 MSB−4 MSB−5 LSB+1
LSB
D0
MSB−5 MSB−6
MSB MSB−1 MSB−2 MSB−3 MSB−4
Channel
Address
Output Data
Format
D7
D6
D5
D4
D3
D2
D1
D7
D6
D5
D4
D3
D2
D1
DATA IN
A/D Conversion Interval
t
conv
EOC
INT
Initialize
Initialize
A. To minimize errors caused by noise at CS, the internal circuitry waits for a setup time after the CS falling edge before
responding to control input signals. Therefore, no attempt should be made to clock in an address until the minimum
CS setup time has elapsed.
Figure 48. Timing for 8-Clock Transfer Using CS With DATA OUT Set for MSB First
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PARAMETER MEASUREMENT INFORMATION (continued)
Shift in New Multiplexer Address,
Simultaneously Shift Out Previous Conversion Result
CS
Access
Sample Cycle
Cycle
1
3
4
7
2
5
6
8
1
2
3
4
5
7
6
I/O
CLOCK
Previous Conversion Data
DATA
OUT
MSB MSB−1 MSB−2 MSB−3 MSB−4 MSB−5 LSB+1
LSB
MSB−2 MSB−3 MSB−4 MSB−5
MSB−6
MSB
MSB−1
Low Level
Channel
Address
Output Data
Format
D7
D6
D5
D4
D3
D2
D1
D0
D7
D4
D3
D2
D1
D6
D5
DATA IN
A/D Conversion Interval
t
conv
EOC
INT
Initialize
Initialize
A. To minimize errors caused by noise at CS, the internal circuitry waits for a setup time after the CS falling edge before
responding to control input signals. Therefore, no attempt should be made to clock in an address until the minimum
CS setup time has elapsed.
Figure 49. Timing for 8-Clock Transfer Not Using CS With DATA OUT Set for MSB First
Shift in New Multiplexer Address,
Simultaneously Shift Out Previous Conversion Result
CS
Access Cycle
Sample Cycle
1
3
4
7
2
5
6
8
9
10
11
12
16
1
I/O
CLOCK
Pad
Zeros
Previous Conversion Data
Hi−Z State
DATA
OUT
MSB MSB−1 MSB−2 MSB−3 MSB−4 MSB−5 MSB−6 MSB−7 MSB−8 MSB−9 LSB+1
LSB
MSB
D7
Channel
Address
Output Data
Format
D7
D6
D5
D4
D3
D2
D1
D0
DATA IN
A/D Conversion Interval
t
conv
EOC
INT
Initialize
Initialize
A. To minimize errors caused by noise at CS, the internal circuitry waits for a setup time after the CS falling edge before
responding to control input signals. Therefore, no attempt should be made to clock in an address until the minimum
CS setup time has elapsed.
Figure 50. Timing for 16-Clock Transfer Using CS With DATA OUT Set for MSB First
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PARAMETER MEASUREMENT INFORMATION (continued)
Shift in New Multiplexer Address,
Simultaneously Shift Out Previous Conversion Result
CS
Access Cycle
Sample Cycle
1
3
4
7
2
5
6
8
9
10
11
12
16
1
I/O
CLOCK
Pad
Zeros
Previous Conversion Data
DATA
OUT
MSB MSB−1 MSB−2 MSB−3 MSB−4 MSB−5 MSB−6 MSB−7 MSB−8 MSB−9 LSB+1
LSB
MSB
Low Level
Channel
Address
Output Data
Format
D7
D6
D5
D4
D3
D2
D1
D0
D7
DATA IN
A/D Conversion Interval
t
conv
EOC
INT
Initialize
Initialize
A. To minimize errors caused by noise at CS, the internal circuitry waits for a setup time after the CS falling edge before
responding to control input signals. Therefore, no attempt should be made to clock in an address until the minimum
CS setup time has elapsed.
Figure 51. Timing for 16-Clock Transfer Not Using CS With DATA OUT Set for MSB First
Shift in New Multiplexer Address, Simultaneously
Shift Out Previous Conversion Result
CS
Access Cycle
Sample Cycle
10
1
3
4
7
2
5
6
8
9
11
12
16
1
I/O CLOCK
DATA OUT
Previous Conversion Data
Pad Zeros
Hi−Z State
MSB MSB−1 MSB−2 MSB−3 MSB−4 MSB−5 MSB−6 MSB−7 MSB−8 MSB−9 LSB+1
LSB
MSB
D7
Channel
Address
Output Data
Format
DATA IN
DATA IN Can be Tied or Held High
A/D Conversion Interval
t
conv
EOC Initialize
Initialize
A. To minimize errors caused by noise at CS, the internal circuitry waits for a setup time after the CS falling edge before
responding to control input signals. Therefore, no attempt should be made to clock in an address until the minimum
CS setup time has elapsed.
Figure 52. Timing for Default Mode Using CS: (16-Clock Transfer, MSB First, External Reference, Pin 19 =
EOC, Input = AIN0)
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PARAMETER MEASUREMENT INFORMATION (continued)
Shift in New Multiplexer Address, Simultaneously
Shift Out Previous Conversion Result
CS
Access Cycle
Sample Cycle
10
1
3
4
7
2
5
6
8
9
11
12
16
1
I/O CLOCK
DATA OUT
DATA IN
Previous Conversion Data
Pad Zeros
MSB MSB−1 MSB−2 MSB−3 MSB−4 MSB−5 MSB−6 MSB−7 MSB−8 MSB−9 LSB+1
LSB
Low Level
MSB
Channel
Address
Output Data
Format
D7
DATA IN Can be Tied or Held High
A/D Conversion Interval
t
conv
EOC
Initialize
Initialize
A. To minimize errors caused by noise at CS, the internal circuitry waits for a setup time after the CS falling edge before
responding to control input signals. Therefore, no attempt should be made to clock in an address until the minimum
CS setup time has elapsed.
Figure 53. Timing for Default Mode Not Using CS: (16-Clock Transfer, MSB First, External Reference, Pin
19 = EOC, Input = AIN0)
To remove the device from default mode, CFGR2–D0 must be reset to 0. Valid sample/convert cycles can
resume on the cycle following the CFGR2 configuration.
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PRINCIPLES OF OPERATION
Initially, with chip select (CS) high, I/O CLOCK and DATA IN are disabled and DATA OUT is in the
high-impedance state. CS going low begins the conversion sequence by enabling I/O CLOCK and DATA IN and
removes DATA OUT from the high-impedance state. The input data is an 8-bit data stream consisting of a 4-bit
address or command (D7–D4) and a 4-bit configuration data (D3–D0). There are two sets of configuration
registers, configuration register 1 – CFGR1 and configuration register 2 – CFGR2. CFGR1, which controls output
data format configuration, consists of a 2-bit data length select (D3–D2), an output MSB or LSB first bit (D1), and
a unipolar or bipolar output select bit (D0) that are applied to any command (from DATA IN) except for command
1111b. CFGR2, which provides configuration information other than data format, consists of a 2-bit reference
select (D3–D2), an EOC/INT program bit (D1), and a default mode select bit (D0) that are applied to command
1111b. The I/O CLOCK sequence applied to the I/O CLOCK terminal transfers this data to the input data
register. During this transfer, the I/O CLOCK sequence also shifts the previous conversion result from the output
data register to DATA OUT. I/O CLOCK receives the input sequence of 8, 12, or 16 clock cycles long depending
on the data-length selection in the input data register. Sampling of the analog input begins on the fourth falling
edge of the input I/O CLOCK sequence and is held after the last falling edge of the I/O CLOCK sequence. The
last falling edge of the I/O CLOCK sequence also takes EOC low (if pin 19 = EOC) and begins the conversion.
Converter Operation
The operation of the converter is organized as a succession of three distinct cycles: 1) the data I/O cycle, 2) the
sampling cycle, and 3) the conversion cycle. The first two are partially overlapped.
Data I/O Cycle
The data I/O cycle is defined by the externally provided I/O CLOCK and lasts 8, 12, or 16 clock periods,
depending on the selected output data length. During the I/O cycle, the following two operations take place
simultaneously. An 8-bit data stream consisting of address/command and configuration information is provided to
DATA IN. This data is shifted into the device on the rising edge of the first eight I/O CLOCK clocks. Data input is
ignored after the first eight clocks during 12- or 16-clock I/O transfers. The data output, with a length of 8, 12, or
16 bits, is provided serially on DATA OUT. When CS is held low, the first output data bit occurs on the rising
edge of EOC. When CS is toggled between conversions, the first output data bit occurs on the falling edge of
CS. This data is the result of the previous conversion period, and after the first output data bit, each succeeding
bit is clocked out on the falling edge of each succeeding I/O CLOCK.
Sampling Period
During the sampling period, one of the analog inputs is internally connected to the capacitor array of the
converter to store the analog input signal. The converter starts sampling the selected input immediately after the
four address/command bits have been clocked into the input data register. Sampling starts on the fourth falling
edge of I/O CLOCK. The converter remains in the sampling mode until the eighth, twelfth, or sixteenth falling
edge of I/O CLOCK depending on the data-length selection.
After the 8-bit data stream has been clocked in, DATA IN should be held at a fixed digital level until EOC goes
high or INT goes low (indicating that the conversion is complete) to maximize the sampling accuracy and
minimize the influence of external digital noise.
Conversion Cycle
A conversion cycle is started only after the I/O cycle is completed, which minimizes the influence of external
digital noise on the accuracy of the conversion. This cycle is transparent to the user because it is controlled by
an internal clock (oscillator). The total conversion time is equal to 13.5 OSC clocks plus a small delay (~25 ns) to
start the OSC. During the conversion period, the device performs a successive-approximation conversion on the
analog input voltage.
When programmed as EOC, pin 19 goes low at the start of the conversion cycle and goes high when the
conversion is complete and the output data register is latched. After EOC goes low, the analog input can be
changed without affecting the conversion result. Since the delay from the falling edge of the last I/O CLOCK to
the falling edge of EOC is fixed, any time-varying analog input signals can be digitized at a fixed rate without
introducing systematic harmonic distortion or noise due to timing uncertainty.
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When programmed as INT, pin 19 goes low when the conversion is complete and the output data register is
latched. The next I/O CLOCK rising edge clears the INT output. The time from the last I/O CLOCK falling edge to
the falling INT edge is equivalent to the EOC delay mentioned above plus the maximum conversion time. INT is
cancelled by (or brought to high) by either the next CS falling edge or the next SCLK rising edge (when CS is
held low all of the time for multiple cycles). When CS is held low continuously (for multiple cycles) MSB output
occurs after the first rising edge of I/O CLOCK after EOC is inactive or the falling edge of INT.
Power Up and Initialization
After power up, CS must be taken from high to low to begin an I/O cycle. INT/EOC pin is initially high, and both
configuration registers are set to all zeroes. The contents of the output data register are random, and the first
conversion result should be ignored. To initialize during operation, CS is taken high and is then returned low to
begin the next I/O cycle. The first conversion after the device has returned from the power-down state may not
read accurately due to internal device settling.
Table 1. Operational Terminology
The entire I/O CLOCK sequence that transfers address and control data into the data register and
Current (N) I/O cycle
clocks the digital result from the previous conversion from DATA OUT.
The conversion cycle starts immediately after the current I/O cycle. The end of the current I/O cycle is
Current (N) conversion cycle
the last clock falling edge in the I/O CLOCK sequence. The current conversion result is loaded into
the output register when conversion is complete.
Current (N) conversion result
Previous (N–1) conversion cycle
Next (N+1) I/O cycle
The current conversion result is serially shifted out on the next I/O cycle.
The conversion cycle just prior to the current I/O cycle
The I/O period that follows the current conversion cycle
Example
In 12-bit mode, the result of the current conversion cycle is a 12-bit serial-data stream clocked out during the
next I/O cycle. The current I/O cycle must be exactly 12 bits long to maintain synchronization, even when this
corrupts the output data from the previous conversion. The current conversion is begun immediately after the
twelfth falling edge of the current I/O cycle.
Default Mode
When the DATA IN pin is held high, the ADC goes into hardware default mode because the CFGR2 bits are all
programmed to the default values after eight I/O CLOCK cycles. This means the ADC is programmed for an
external reference and pin 19 as EOC. In addition, channel AIN0 is selected. The first conversion is invalid
therefore the conversion result should be ignored. On the next cycle, AIN0 is sampled and converted. This mode
of operation is valid when CS is toggled or held low after the first cycle.
To remove the device from hardware default mode, CFGR2 bit D0 must be reset to 0. Once this is done, the host
must program CFGR1 on the next cycle and disregard the result from the current cycle’s conversion.
Data Input
The data input is internally connected to an 8-bit serial-input address and control register. The register defines
the operation of the converter and the output data length. The host provides the input data byte with the MSB
first. Each data bit is clocked in on the rising edge of the I/O CLOCK sequence (see Table 2 for the data
input-register format).
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Table 2. Command Set (CMR) and Configuration
SDI D[7:4]
COMMAND
Binary,
0000b
0001b
0010b
0011b
0100b
0101b
0110b
0111b
1000b
1001b
1010b
1011b
HEX
0h
1h
2h
3h
4h
5h
6h
7h
8h
9h
Ah
Bh
SELECT analog input channel 0
SELECT analog input channel 1
SELECT analog input channel 2
SELECT analog input channel 3
SELECT analog input channel 4
SELECT analog input channel 5
SELECT analog input channel 6
SELECT analog input channel 7
SELECT analog input channel 8
SELECT analog input channel 9
SELECT analog input channel 10
SELECT TEST,
CFGR1
SDI
D[3:0]
CONFIGURATION
01: 8-bit output length
X0: 12-bit output length
11: 16-bit output length (default)
0: MSB out first (default)
1: LSB out first
0: Unipolar binary (default)
1: Bipolar 2s complement
D[3:2]
D1
D0
Voltage = (VREF+ + VREF−)/2
SELECT TEST, Voltage = REFM
SELECT TEST, Voltage = REFP
SW POWERDOWN (analog + reference)
ACCESS CFGR2
1100b
1101b
1110b
1111b
Ch
Dh
Eh
Fh
CFGR2
SDI
D[3:0]
CONFIGURATION
D[3:2]
00: Internal 4.096 reference
01: Internal 2.048 reference
11: External reference (default)
0: Pin 19 output EOC (default)
1: Pin 19 output Int
D1
D0
0: Normal mode
(CFGR1 needs to be programmed)
1: Default mode enabled
(D[3:0] of CFGR1 and D[3:1] of
CFGR2 set to default)
Data Input – Address/Command Bits
The four MSBs (D7–D4) of the input data register are the address or command. These bits can be used to
address one of the 11 input channels, select one of three reference-test voltages, activate the software
power-down mode, or access the second configuration register, CFGR2. All address/command bits affect the
current conversion, which is the conversion that immediately follows the current I/O cycle. They also allow
access to CFGR1 except for command 1111b, which allows access to CFGR2.
Data Output Length
CFGR1 bits (D3 and D2) of the data register select the output data length. The data-length selection is valid for
the current I/O cycle (the cycle in which the data is read). The data-length selection, being valid for the current
I/O cycle, allows device start-up without losing I/O synchronization. A data length of 8, 12, or 16 bits can be
selected. Since the converter has 12-bit resolution, a data length of 12 bits is suggested.
With D3 and D2 set to 00 or 10, the device is in the 12-bit data-length mode and the result of the current
conversion is output as a 12-bit serial data stream during the next I/O cycle. The current I/O cycle must be
exactly 12 bits long for proper synchronization, even when this means corrupting the output data from a previous
conversion. The current conversion is started immediately after the twelfth falling edge of the current I/O cycle.
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With bits D3 and D2 set to 11, the 16-bit data-length mode is selected, which allows convenient communication
with 16-bit serial interfaces. In the 16-bit mode, the result of the current conversion is output as a 16-bit serial
data stream during the next I/O cycle with the four LSBs always reset to 0 (pad bits). The current I/O cycle must
be exactly 16 bits long to maintain synchronization even when this means corrupting the output data from the
previous conversion. The current conversion is started immediately after the sixteenth falling edge of the current
I/O cycle.
With bits D3 and D2 set to 01, the 8-bit data-length mode is selected, which allows fast communication with 8-bit
serial interfaces. In the 8-bit mode, the result of the current conversion is output as an 8-bit serial data stream
during the next I/O cycle. The current I/O cycle must be exactly eight bits long to maintain synchronization, even
when this means corrupting the output data from the previous conversion. The four LSBs of the conversion result
are truncated and discarded. The current conversion is started immediately after the eighth falling edge of the
current I/O cycle.
Because the D3 and D2 register settings take effect on the I/O cycle when the data length is programmed, there
can be a conflict with the previous cycle if the data-word length was changed. This may occur when the data
format is selected to be least significant bit first, since at the time the data length change becomes effective (six
rising edges of I/O CLOCK), the previous conversion result has already started shifting out. In actual operation,
when different data lengths are required within an application and the data length is changed between two
conversions, no more than one conversion result can be corrupted and only when it is shifted out in LSB-first
format.
LSB Out First
D1 in the CFGR1 controls the direction of the output (binary) data transfer. When D1 is reset to 0, the conversion
result is shifted out MSB first. When set to 1, the data is shifted out LSB first. Selection of MSB first or LSB first
always affects the next I/O cycle and not the current I/O cycle. When changing from one data direction to
another, the current I/O cycle is never disrupted.
Bipolar Output Format
D0 in the CFGR1 controls the binary data format used to represent the conversion result. When D0 is cleared to
0, the conversion result is represented as unipolar (unsigned binary) data. Nominally, the conversion result of an
input voltage equal to or less than VREF– is a code with all zeros (000...0) and the conversion result of an input
voltage equal to or greater than VREF+ is a code of all ones (111...1). The conversion result of (VREF+ + VREF–)/2 is
a code of a one followed by zeros (100 ...0).
When D0 is set to 1, the conversion result is represented as bipolar (signed binary) data. Nominally, conversion
of an input voltage equal to or less than VREF– is a code of a one followed by zeros (100...0), and the conversion
of an input voltage equal to or greater than VREF+ is a code of a zero followed by all ones (011...1). The
conversion result of (VREF+ + VREF–)/2 is a code of all zeros (000...0). The MSB is interpreted as the sign bit. The
bipolar data format is related to the unipolar format in that the MSBs are always each other’s complement.
Selection of the unipolar or bipolar format always affects the current conversion cycle, and the result is output
during the next I/O cycle. When changing between unipolar and bipolar formats, the data output during the
current I/O cycle is not affected.
Reference
The device has a built-in reference with a programmable level of 2.048 V or 4.096 V. If the internal reference is
used, REF+ is set to 2.048 V or 4.096 V and REF– is set to analog GND. An external reference can also be used
through two reference input pins, REF+ and REF–, if the reference source is programmed as external. The
voltage levels applied to these pins establish the upper and lower limits of the analog inputs to produce a
full-scale and zero-scale reading respectively. The values of REF+, REF–, and the analog input should not
exceed the positive supply or be lower than GND consistent with the specified absolute maximum ratings. The
digital output is at full scale when the input signal is equal to or higher than REF+ and at zero when the input
signal is equal to or lower than REF–.
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V
CC
Analog
Supply
Internal
Reference
S1, S2:
Closed = Internal Reference Used
Opened = External Reference Used
S1
S2
REF+
Sample
Convert
50 pF
CDAC
C2
10 µF
Int Reference
Compensation Cap
C1
0.1 µF
Decoupling Cap
REF−
C2 and Grounding REF− Are Required
When Either 4.096 V or 2.048 Internal
Reference Is Used
GND
Figure 54. Reference Block
INT/EOC Output
Pin 19 outputs the status of the ADC conversion. When programmed as EOC, the output indicates the beginning
and the end of conversion. In the reset state, EOC is always high. During the sampling period (beginning after
the fourth falling edge of the I/O CLOCK sequence), EOC remains high until the internal sampling switch of the
converter is safely opened. The opening of the sampling switch occurs after the eighth, twelfth, or sixteenth I/O
CLOCK falling edge, depending on the data-length selection in the input data register. After the EOC signal goes
low, the analog input signal can be changed without affecting the conversion result.
The EOC signal goes high again after the conversion is completed and the conversion result is latched into the
output data register. The rising edge of EOC returns the converter to a reset state and a new I/O cycle begins.
On the rising edge of EOC, the first bit of the current conversion result is on DATA OUT when CS is low. When
CS is toggled between conversions, the first bit of the current conversion result occurs on DATA OUT at the
falling edge of CS.
When programmed as INT, the output indicates that the conversion is completed and the output data is ready to
be read. In the reset state, INT is always high. INT is high during the sampling period and until the conversion is
complete. After the conversion is finished and the output data is latched, INT goes low and remains low until it is
cleared by the host. When CS is held low, the MSB (or LSB) of the conversion result is presented on DATA OUT
on the falling edge of INT. A rising I/O CLOCK edge clears the interrupt.
Chip-Select Input (CS)
CS enables and disables the device. During normal operation, CS should be low. Although the use of CS is not
necessary to synchronize a data transfer, it can be brought high between conversions to coordinate the data
transfer of several devices sharing the same bus.
When CS is brought high, the serial-data output is immediately brought to the high-impedance state, releasing its
output data line to other devices that may share it. After an internally generated debounce time, I/O CLOCK is
inhibited, thus preventing any further change in the internal state.
When CS is subsequently brought low again, the device is reset. CS must be held low for an internal debounce
time before the reset operation takes effect. After CS is debounced low, I/O CLOCK must remain inactive (low)
for a minimum time before a new I/O cycle can start.
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TLV2556-EP
SLAS598A–NOVEMBER 2008–REVISED JULY 2009 ................................................................................................................................................... www.ti.com
CS can interrupt any ongoing data transfer or any ongoing conversion. When CS is debounced low long enough
before the end of the current conversion cycle, the previous conversion result is saved in the internal output
buffer and shifted out during the next I/O cycle.
When CS is held low continuously for multiple cycles, the first data bit of the newly completed conversion occurs
on DATA OUT on the rising edge of EOC or falling edge of INT. Note that the first cycle in the series still requires
a transition of CS from high to low. When a new conversion is started after the last falling edge of I/O CLOCK,
EOC goes low and the serial output is forced low until EOC goes high again.
When CS is toggled between conversions, the first data bit occurs on DATA OUT on the falling edge of CS. On
each subsequent falling edge of I/O CLOCK after the first data bit appears, the data is changed to the next bit in
the serial conversion result until the required number of bits has been output.
Power-Down Features
When command (D7–D4) 1110b is clocked into the input data register during the first four I/O CLOCK cycles, the
software power-down mode is selected. Software power down is activated on the falling edge of the fourth I/O
CLOCK pulse.
During software power down, all internal circuitry is put in a low-current standby mode. The internal reference (if
being used) is powered down. No conversion is performed. The internal output buffer keeps the previous
conversion cycle data results provided that all digital inputs are held above VCC – 0.5 V or below 0.5 V. The I/O
logic remains active so the current I/O cycle must be completed even when the power-down mode is selected.
Upon power-on reset and before the first I/O cycle, the converter normally begins in the power-down mode. The
device remains in the software power-down mode until a valid input address (other than command 1110b) is
clocked in. Upon completion of that I/O cycle, a normal conversion is performed with the results being shifted out
during the next I/O cycle. If using the internal reference, care must be taken to allow the reference to power on
completely before a valid conversion can be performed. It requires 1 ms to resume from a software power down.
The ADC also has an auto power-down mode. This is transparent to users. The ADC goes into auto power down
within one I/O CLOCK cycle after the conversion is complete and resumes, with a small delay after an active CS
is sent to the ADC. This mode keeps built-in reference so resumption is fast enough to be used between cycles.
Analog Multiplexer
The 11 analog inputs, three internal voltages, and power-down mode are selected by the input multiplexer
according to the input addresses shown in Table 2. The input multiplexer is a break-before-make type to reduce
input-to-input noise rejection resulting from channel switching. Sampling of the analog inputs starts on the falling
edge of the fourth I/O CLOCK and continues for the remaining I/O CLOCK pulses. The sample is held on the
falling edge of the last I/O CLOCK pulse. The three internal test inputs are applied to the multiplexer, then
sampled and converted in the same manner as the external analog inputs. The first conversion after the device
has returned from the power-down state may not read accurately due to internal device settling.
32
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Copyright © 2008–2009, Texas Instruments Incorporated
Product Folder Link(s): TLV2556-EP
PACKAGE OPTION ADDENDUM
www.ti.com
16-Oct-2009
PACKAGING INFORMATION
Orderable Device
TLV2556MPWREP
TLV2556MPWREPG4
V62/08622-01XE
Status (1)
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
TSSOP
PW
20
20
20
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TSSOP
TSSOP
PW
PW
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TLV2556-EP :
Catalog: TLV2556
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Jul-2009
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0 (mm)
B0 (mm)
K0 (mm)
P1
W
Pin1
Diameter Width
(mm) W1 (mm)
(mm) (mm) Quadrant
TLV2556MPWREP
TSSOP
PW
20
2000
330.0
16.4
6.95
7.1
1.6
8.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Jul-2009
*All dimensions are nominal
Device
Package Type Package Drawing Pins
TSSOP PW 20
SPQ
Length (mm) Width (mm) Height (mm)
346.0 346.0 33.0
TLV2556MPWREP
2000
Pack Materials-Page 2
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
M
0,10
0,65
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
9,80
9,60
A MAX
A MIN
7,70
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
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