V62/10603-01XE_技术文档

TLV2548-EP

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3.0-V TO 5.5-V, 12-BIT, 200-KSPS, 4-/8-CHANNEL, LOW-POWER SERIAL

ANALOG-TO-DIGITAL CONVERTER WITH AUTOPOWER-DOWN

Check for Samples: TLV2548-EP

1

FEATURES

SUPPORTS DEFENSE, AEROSPACE,

AND MEDICAL APPLICATIONS

•

Maximum Throughput 200-KSPS

•

Controlled Baseline

One Assembly/Test Site

One Fabrication Site

Available in Military (–55°C/125°C)

Temperature Range⁽¹⁾

Extended Product Life Cycle

Extended Product-Change Notification

Product Traceability

•

Built-In Reference, Conversion Clock and

8x FIFO

•

Differential/Integral Nonlinearity Error: ±1.2

LSB

Signal-to-Noise and Distortion Ratio: 70 dB,

f_i= 12 kHz

•

Spurious Free Dynamic Range: 75 dB,

f_i= 12 kHz

SPI (CPOL = 0, CPHA = 0)/DSP-Compatible

Serial Interfaces With SCLK up to 20 MHz

PW PACKAGE

(TOP VIEW)

•

Single Wide Range Supply 3.0 Vdc to 5.5 Vdc

SDO

SDI

1

20 CS

Analog Input Range 0 V to Supply Voltage

With 500-kHz BW

2

19

18

17

16

15

14

13

12

11

REFP

REFM

FS

3

SCLK

4

EOC/(INT)

•

Hardware Controlled and Programmable

Sampling Period

5

V

PWDN

GND

CSTART

A7

CC

6

A0

A1

A2

A3

A4

Low Operating Current (1.0 mA at 3.3 V,

2.0 mA at 5.5 V With External Ref, 1.7-mA at

3.3V, 2.4-mA at 5.5-V With Internal Ref)

7

8

9

A6

•

Power Down: Software/Hardware

Power-Down Mode (1 μA Max, Ext Ref),

Autopower-Down Mode (1 μA, Ext Ref)

10

A5

•

Programmable Auto-Channel Sweep

(1) Custom temperature ranges available

DESCRIPTION

The TLV2548 is a high performance, 12-bit low-power, 3.86-μs, CMOS analog-to-digital converter (ADC) which

operates from a single 3.0-V to 5.5-V power supply. This device has three digital inputs and a 3-state output [chip

select (CS), serial input-output clock (SCLK), serial data input (SDI), and serial data output (SDO)] that provide a

direct 4-wire interface to the serial port of most popular host microprocessors (SPI interface). When interfaced

with a TI DSP, a frame sync (FS) signal is used to indicate the start of a serial data frame.

In addition to a high-speed A/D converter and versatile control capability, this device has an on-chip analog

multiplexer that can select any analog inputs or one of three internal self-test voltages. The sample-and-hold

function is automatically started after the fourth SCLK edge (normal sampling) or can be controlled by a special

pin, CSTART, to extend the sampling period (extended sampling). The normal sampling period can also be

programmed as short (12 SCLKs) or as long (24 SCLKs) to accommodate faster SCLK operation popular among

high-performance signal processors. The TLV2548 is designed to operate with very low power consumption. The

power-saving feature is further enhanced with software/hardware/autopower-down modes and programmable

conversion speeds. The conversion clock (OSC) and reference are built-in. The converter can use the external

SCLK as the source of the conversion clock to achieve higher (up to 2.8 μs when a 20-MHz SCLK is used)

conversion speed. Two different internal reference voltages are available. An optional external reference can also

be used to achieve maximum flexibility.

The TLV2548 is characterized for operation from –55°C to 125°C.

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

TLV2548-EP

SLAS668 –OCTOBER 2009

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FUNCTIONAL BLOCK DIAGRAM

V

CC

4/2 V

Reference

REFP

REFM

FIFO

12 Bit × 8

A0

A1

A2

A3

A4

A5

A6

A7

Low Power

12-BIT

SAR ADC

S/H

OSC

INT

Command

Decode

Conversion

Clock

M

U

X

EXT

SDO

CFR

SDI

CMR (4 MSBs)

DIV

SCLK

CS

FS

Control Logic

EOC/(INT)

CSTART

PWDN

GND

Table 1. ORDERING INFORMATION⁽¹⁾

ORDERABLE PART

NUMBER

TOP-SIDE MARKING

(2)

T_A

PACKAGE

–55°C to 125°C

TSSOP-PW

Tape and Reel of 2000

TLV2548MPWREP

TV2548EP

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

Web site at www.ti.com.

(2) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at

www.ti.com/sc/package.

Table 2. TERMINAL FUNCTIONS

TERMINAL

I/O

DESCRIPTION

NAME

NO.

A0

A1

A2

A3

A4

A5

A6

A7

6

7

8

Analog signal inputs. The analog inputs are applied to these terminals and are internally

multiplexed. The driving source impedance should be less than or equal to 1 kΩ.

xxx

For a source impedance greater than 1 kΩ, use the asynchronous conversion start signal

CSTART (CSTART low time controls the sampling period) or program long sampling period

to increase the sampling time.

9

I

10

11

12

13

Chip select. A high-to-low transition on the CS input resets the internal 4-bit counter,

enables SDI, and removes SDO from 3-state within a maximum setup time. SDI is disabled

within a setup time after the 4-bit counter counts to 16 (clock edges) or a low-to-high

transition of CS whichever happens first.

CS

20

I

NOTE: CS falling and rising edges need to happen when SCLK is low for a microprocessor

interface such as SPI.

2

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Table 2. TERMINAL FUNCTIONS (continued)

TERMINAL

I/O

DESCRIPTION

NAME

NO.

This terminal controls the start of sampling of the analog input from a selected multiplex

channel. Sampling time starts with the falling edge of CSTART and ends with the rising edge

of CSTART as long as CS is held high. In mode 01, select cycle, CSTART can be issued as

soon as CHANNEL is selected which means the fifth SCLK during the select cycle, but the

effective sampling time is not started until CS goes to high. The rising edge of CSTART

(when CS = 1) also starts the conversion. Tie this terminal to V_CCif not used.

CSTART

14

I

End of conversion or interrupt to host processor. [PROGRAMMED AS EOC]: This output

goes from a high-to-low logic level at the end of the sampling period and remains low until

the conversion is complete and data are ready for transfer. EOC is used in conversion mode

00 only.

EOC/(INT)

4

O

xxx

[PROGRAMMED AS INT]: This pin can also be programmed as an interrupt output signal to

the host processor. The falling edge of INT indicates data are ready for output. The following

CS↓ or FS clears INT.

DSP frame sync input. Indication of the start of a serial data frame in or out of the device. If

FS remains low after the falling edge of CS, SDI is not enabled until an active FS is

presented. A high-to-low transition on the FS input resets the internal 4-bit counter and

enables SDI within a maximum setup time. SDI is disabled within a setup time after the 4-bit

counter counts to 16 (clock edges) or a low-to-high transition of CS whichever happens first.

xxx

FS

17

I

Tie this terminal to V_CCif not used. See the Data Code Information section, item 1.

Ground return for the internal circuitry. Unless otherwise noted, all voltage measurements

are with respect to GND.

GND

15

16

I

Both analog and reference circuits are powered down when this pin is at logic zero. The

device can be restarted by active CS, FS or CSTART after this pin is pulled back to logic

one.

PWDN

Input serial clock. This terminal receives the serial SCLK from the host processor. SCLK is

used to clock the input SDI to the input register. When programmed, it may also be used as

the source of the conversion clock.

SCLK

3

I

NOTE: This device supports CPOL (clock polarity) = 0, which is SCLK returns to zero when

idling for SPI compatible interface.

Serial data input. The input data is presented with the MSB (D15) first. The first 4-bit MSBs,

D(15−12) are decoded as one of the 16 commands. The configure write commands require

an additional 12 bits of data.

xxx

When FS is not used (FS =1), the first MSB (D15) is expected after the falling edge of CS

and is latched in on the rising edges of SCLK (after CS↓).

xxx

SDI

2

I

When FS is used (typical with an active FS from a DSP) the first MSB (D15) is expected

after the falling edge of FS and is latched in on the falling edges of SCLK.

xxx

SDI is disabled within a setup time after the 4-bit counter counts to 16 (clock edges) or a

low-to-high transition of CS whichever happens first.

The 3-state serial output for the A/D conversion result. SDO is kept in the high-impedance

state when CS is high and after the CS falling edge and until the MSB is presented. The

output format is MSB first.

xxx

When FS is not used (FS = 1 at the falling edge of CS), the MSB is presented to the SDO

pin after the CS falling edge, and successive data are available at the rising edge of SCLK

and changed on the falling edge.

xxx

SDO

1

O

When FS is used (FS = 0 at the falling edge of CS), the MSB is presented to SDO after the

falling edge of CS and FS = 0 is detected. Successive data are available at the falling edge

of SCLK and changed on the rising edge. (This is typically used with an active FS from a

DSP.)

xxx

For conversion and FIFO read cycles, the first 12 bits are result from previous conversion

(data) followed by 4 don’t care bits. The first four bits from SDO for CFR read cycles should

be ignored. The register content is in the last 12 bits. SDO is 3-state (float) after the 16th bit.

See the Data Code Information section, item 2.

External reference input or internal reference decoupling. Tie this pin to analog ground if

internal reference is used.

REFM

18

I

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Table 2. TERMINAL FUNCTIONS (continued)

TERMINAL

NAME

I/O

DESCRIPTION

NO.

19

5

External reference input or internal reference decoupling (shunt capacitors of 10 μF and

0.1 μF between REFP and REFM). The maximum input voltage range is determined by the

difference between the voltage applied to this terminal and the REFM terminal when an

external reference is used.

REFP

VCC

I

Positive supply voltage

Detailed Description

Analog Inputs and Internal Test Voltages

The 4/8 analog inputs and three internal test inputs are selected by the analog multiplexer depending on the

command entered. The input multiplexer is a break-before-make type to reduce input-to-input noise injection

resulting from channel switching.

Converter

The TLV2548 uses a 12-bit successive approximation ADC utilizing a charge redistribution DAC. Figure 1 shows

a simplified version of the ADC.

The sampling capacitor acquires the signal on Ain during the sampling period. When the conversion process

starts, the SAR control logic and charge redistribution DAC are used to add and subtract fixed amounts of charge

from the sampling capacitor to bring the comparator into a balanced condition. When the comparator is balanced,

the conversion is complete and the ADC output code is generated.

Charge

Redistribution

DAC

_

Ain

Control

Logic

+

ADC Code

REFM

Figure 1. Simplified Model of the Successive-Approximation System

Serial Interface

INPUT DATA FORMAT

MSB

LSB

D15−D12

Command ID[15:12]

D11−D0

Configuration data field ID[11:0]

Input data is binary. All trailing blanks can be filled with zeros.

OUTPUT DATA FORMAT READ CFR/FIFO READ

MSB

LSB

D15−D12

D11−D0

Register content or FIFO content OD[11:0]

Don’t care

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OUTPUT DATA FORMAT CONVERSION

MSB

LSB

D15−D4

D3−D0

Conversion result

OD[11:0]

Don’t care

The output data format is binary (unipolar straight binary).

Binary

Zero scale code = 000h, Vcode = VREFM.

Full scale code = FFFh, Vcode = VREFP − 1 LSB

Control and Timing

Power Up and Initialization Requirements

•

Determine processor type by writing A000h to the TLV2548 (CS must be toggled).

Configure the device (CS must make a high-to-low transition, then can be held low if in DSP mode;

i.e., active FS).

The first conversion after power up or resuming from power down is not valid.

Start of the Cycle

•

When FS is not used (FS = 1 at the falling edge of CS), the falling edge of CS is the start of the cycle.

When FS is used (FS is an active signal from a DSP), the falling edge of FS is the start of the cycle.

First 4-MSBs: The Command Register (CMR)

The TLV2548 has a 4-bit command set (see Table 3) plus a 12-bit configuration data field. Most of the

commands require only the first 4 MSBs, i.e., without the 12-bit data field.

The valid commands are listed in Table 3.

Table 3. TLV2548 Command Set⁽¹⁾

SDI D(15−12) BINARY

COMMAND

0000b

0001b

0010b

0011b

0100b

0101b

0110b

0111b

1000b

1001b

0h

1h

2h

3h

4h

5h

6h

7h

8h

9h

Select analog input channel 0

Select analog input channel 1

Select analog input channel 2

Select analog input channel 3

Select analog input channel 4

Select analog input channel 5

Select analog input channel 6

Select analog input channel 7

SW power down (analog + reference)

Read CFR register data shown as SDO D(11-0)

Write CFR followed by 12–bit data, e.g., 0A100h means external reference,

short sampling, SCLK/4, single shot, INT

1010b

Ah plus data

1011b

1100b

1101b

1110b

1111b

Bh

Select test, voltage = (REFP+REFM)/2

Select test, voltage = REFM

Ch

Dh

Select test, voltage = REFP

Eh

FIFO read, FIFO contents shown as SDO D(15-4), D(3-0) = 0000

Reserved

Fh plus data

(1) The status of the CFR can be read with a read CFR command when the device is programmed for one–shot conversion mode

(CFR D[6,5] = 00).

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Configuration

Configuration data is stored in one 12–bit configuration register (CFR) (see Table 4 for CFR bit definitions). Once

configured after first power up, the information is retained in the H/W or S/W power down state. When the device

is being configured, a write CFR cycle is issued by the host processor. This is a 16–bit write. If the SCLK stops

after the first eight bits are entered, then the next eight bits can be taken after the SCLK is resumed.

Table 4. TLV2548 Configuration Register (CFR) Bit Definitions

BIT

DEFINITION

Reference select

0: External

D11

1: Internal (Tie REFM to analog ground if the internal reference is selected.)

Internal reference voltage select

0: Internal ref = 4 V

1: internal ref = 2 V

D10

D9

Sample period select

0: Short sampling 12 SCLKs (1x sampling time)

1: Long sampling 24 SCLKs (2x sampling time)

Conversion clock source select

00: Conversion clock = internal OSC

01: Conversion clock = SCLK

10: Conversion clock = SCLK/4

11: Conversion clock = SCLK/2

D(8,7)

D(6,5)

Conversion mode select

00: Single shot mode [FIFO not used, D(1,0) has no effect.]

01: Repeat mode

10: Sweep mode

11: Repeat sweep mode

Sweep auto sequence select

00: 0-1-2-3-4-5-6-7

01: 0-2-4-6-0-2-4-6

D(4,3)⁽¹⁾

10: 0-0-2-2-4-4-6-6

11: 0-2-0-2-0-2-0-2

EOC/INT - pin function select

0: Pin used as INT

D2

1: Pin used as EOC

FIFO trigger level (sweep sequence length)

00: Full (INT generated after FIFO level 7 filled)

01: 3/4 (INT generated after FIFO level 5 filled)

10: 1/2 (INT generated after FIFO level 3 filled)

11: 1/4 (INT generated after FIFO level 1 filled)

D(1,0)

(1) These bits only take effect in conversion modes 10 and 11.

Sampling

The sampling period starts after the first four input data are shifted in if they are decoded as one of the

conversion commands. These are select analog input (channels 0 through 7) and select test (channels 1 through

3).

Normal Sampling

When the converter is using normal sampling, the sampling period is programmable. It can be 12 SCLKs (short

sampling) or 24 SCLKs (long sampling). Long sampling helps when SCLK is faster than 10 MHz or when input

source resistance is high.

Extended Sampling

CSTART - An asynchronous (to the SCLK) signal, via dedicated hardware pin, CSTART, can be used in order to

have total control of the sampling period and the start of a conversion. This extended sampling is user defined

and is totally independent of SCLK. While CS is high, the falling edge of CSTART is the start of the sampling

period and is controlled by the low time of CSTART. The minimum low time for CSTART should be at least equal

to the minimum t_(SAMPLE). In a select cycle used in mode 01 (REPEAT MODE), CSTART can be started as soon

6

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as the channel is selected (after the fifth SCLK). In this case the sampling period is not started until CS has

become inactive. Therefore the non-overlapped CSTART low time must meet the minimum sampling time

requirement. The low–to–high transition of CSTART terminates the sampling period and starts the conversion

period. The conversion clock can also be configured to use either internal OSC or external SCLK. This function is

useful for an application that requires:

•

The use of an extended sampling period to accommodate different input source impedance.

The use of a faster I/O clock on the serial port but not enough sampling time is available due to the fixed

number of SCLKs. This could be due to a high input source impedance or due to higher MUX ON resistance

at lower supply voltage.

Once the conversion is complete, the processor can initiate a read cycle by using either the read FIFO command

to read the conversion result or by simply selecting the next channel number for conversion. Since the device

has a valid conversion result in the output buffer, the conversion result is simply presented at the serial data

output. To completely get out of the extended sampling mode, CS must be toggled twice from a high-to-low

transition while CSTART is high. The read cycle mentioned above followed by another configuration cycle of the

ADC qualifies this condition and successfully puts the ADC back to its normal sampling mode. This can be

viewed in Figure 9.

Table 5. Sample and Convert Conditions

CONDITIONS

SAMPLE

CONVERT

No sampling clock (SCLK) required.

Sampling period is totally controlled by the low

time of CSTART. The high–to–low transition

of CSTART (when CS = 1) starts the sampling

of the analog input signal. The low time of

CSTART dictates the sampling period. The

low–to–high transition of CSTART ends

sampling period and begins the conversion

cycle. (Note: this trigger only works when

internal reference is selected for conversion

modes 01, 10, and 11.)

CS = 1

(see Figure 11 and

Figure 19)

CSTART

1) If the internal clock OSC is selected, a

maximum conversion time of 3.86 μs can be

achieved.

2) If external SCLK is selected, conversion

time is t_conv= 14 x DIV/f_(SCLK), where DIV can

be 1, 2, or 4.

CSTART = 1

FS = 1

SCLK is required. Sampling period is

CS

programmable under normal sampling. When

programmed to sample under short sampling,

12 SCLKs are generated to complete

sampling period. 24 SCLKs are generated

when programmed for long sampling. A

command set to configure the device requires

4 SCLKs thereby extending to 16 or 28

SCLKs respectively before conversion takes

place. (Note: Because the ADC only bypasses

a valid channel select command, the user can

use select channel 0, 0000b, as the SDI input

when either CS or FS is used as trigger for

conversion. The ADC responds to commands

such as SW powerdown, 1000b.)

CSTART = 1

CS = 0

FS

TLV2548 Conversion Modes

The TLV2548 has four different conversion modes (mode 00, 01, 10, 11). The operation of each mode is slightly

different, depending on how the converter performs the sampling and which host interface is used. The trigger for

a conversion can be an active CSTART (extended sampling), CS (normal sampling, SPI interface), or FS (normal

sampling, TMS320 DSP interface). When FS is used as the trigger, CS can be held active, i.e. CS does not need

to be toggled through the trigger sequence. SDI can be one of the channel select commands, such as SELECT

CHANNEL 0. Different types of triggers should not be mixed throughout the repeat and sweep operations. When

CSTART is used as the trigger, the conversion starts on the rising edge of CSTART. The minimum low time for

CSTART is equal to t_(SAMPLE). If an active CS or FS is used as the trigger, the conversion is started after the 16th

or 28th SCLK edge. Enough time (for conversion) should be allowed between consecutive triggers so that no

conversion is terminated prematurely.

One Shot Mode (Mode 00)

One shot mode (mode 00) does not use the FIFO, and the EOC is generated as the conversion is in progress (or

INT is generated after the conversion is done).

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Repeat Mode (Mode 01)

Repeat mode (mode 01) uses the FIFO. This mode setup requires configuration cycle and channel select cycle.

Once the programmed FIFO threshold is reached, the FIFO must be read, or the data is lost when the sequence

starts over again with the SELECT cycle and series of triggers. No configuration is required except for

re-selecting the channel unless the operation mode is changed. This allows the host to set up the converter and

continue monitoring a fixed input and come back to get a set of samples when preferred.

Triggered by CSTART: The first conversion can be started with a select cycle or CSTART. To do so, the user

can issue CSTART during the select cycle, immediately after the 4-bit channel select command. The first sample

started as soon as the select cycle is finished (i.e., CS returns to 1). If there is enough time (2 μs) left between

the SELECT cycle and the following CSTART, a conversion is carried out. In this case, you need one less trigger

to fill the FIFO. Succeeding samples are triggered by CSTART.

Sweep Mode (Mode 10)

Sweep mode (mode 10) also uses the FIFO. Once it is programmed in this mode, all of the channels listed in the

selected sweep sequence are visited in sequence. The results are converted and stored in the FIFO. This sweep

sequence may not be completed if the FIFO threshold is reached before the list is completed. This allows the

system designer to change the sweep sequence length. Once the FIFO has reached its programmed threshold,

an interrupt (INT) is generated. The host must issue a read FIFO command to read and clear the FIFO before

the next sweep can start.

Repeat Sweep Mode (Mode 11)

Repeat sweep mode (mode 11) works the same way as mode 10 except the operation has an option to continue

even if the FIFO threshold is reached. Once the FIFO has reached its programmed threshold, an interrupt (INT)

is generated. Then two things may happen:

1. The host may choose to act on it (read the FIFO) or ignore it. If the next cycle is a read FIFO cycle, all of the

data stored in the FIFO is retained until it has been read in order.

2. If the next cycle is not a read FIFO cycle, or another CSTART is generated, all of the content stored in the

FIFO is cleared before the next conversion result is stored in the FIFO, and the sweep is continued.

Table 6. TLV2548 Conversion Mode^{(1) (2) (3)}

CONVERSION

MODE

CFR

D(6,5)

SAMPLING

TYPE

OPERATION

•

Single conversion from a selected channel

CS or FS to start select/sampling/conversion/read

One INT or EOC generated after each conversion

Normal

Host must serve INT by selecting channel, and converting and reading the

previous output.

One shot

00

•

Single conversion from a selected channel

CS to select/read

CSTART to start sampling and conversion

One INT or EOC generated after each conversion

Extended

Host must serve INT by selecting next channel and reading the previous

output.

(1) Programming the EOC/INT pin as the EOC signal works for mode 00 only. The other three modes automatically generate an INT signal

irrespective of how EOC/INT is programmed.

(2) Extended sampling mode using CSTART as the trigger only works when internal reference is selected for conversion modes 01, 10, and

11.

(3) When using CSTART to sample in extended mode, the falling edge of the next CSTART trigger should occur no more than 2.5 μs after

the falling CS edge (or falling FS edge if FS is active) of the channel select cycle. This is to prevent an ongoing conversion from being

canceled.

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(1) (2) (3)

Table 6. TLV2548 Conversion Mode

(continued)

CONVERSION

CFR

D(6,5)

SAMPLING

TYPE

OPERATION

MODE

•

Repeated conversions from a selected channel

CS or FS to start sampling/conversion

One INT generated after FIFO is filled up to the threshold

Normal

Host must serve INT by either 1) (FIFO read) reading out all of the FIFO

contents up to the threshold, then repeat conversions from the same selected

channel or 2) writing another command(s) to change the conversion mode. If

the FIFO is not read when INT is served, it is cleared.

Repeat

01

10

11

•

Same as normal sampling except CSTART starts each sampling and

conversion when CS is high.

Extended

Normal

•

One conversion per channel from a sequence of channels

CS or FS to start sampling/conversion

One INT generated after FIFO is filled up to the threshold

Sweep

Host must serve INT by (FIFO read) reading out all of the FIFO contents up to

the threshold, then write another command(s) to change the conversion mode.

•

Same as normal sampling except CSTART starts each sampling and

conversion when CS is high.

Extended

•

Repeated conversions from a sequence of channels

CS or FS to start sampling/conversion

One INT generated after FIFO is filled up to the threshold

Normal

Host must serve INT by either 1) (FIFO read) reading out all of the FIFO

contents up to the threshold, then repeat conversions from the same selected

channel or 2) writing another command(s) to change the conversion mode. If

the FIFO is not read when INT is served it is cleared.

Repeat sweep

•

Same as normal sampling except CSTART starts each sampling and

conversion when CS is high.

Extended

Timing Diagrams

The timing diagrams can be categorized into two major groups: non-conversion and conversion. The

non-conversion cycles are read and write (configuration). None of these cycles carry a conversion. Conversion

cycles are those four modes of conversion.

Read Cycle (Read FIFO or Read CFR)

Read CFR Cycle

The read command is decoded in the first four clocks. SDO outputs the contents of the CFR after the fourth

SCLK. This command works only when the device is programmed in the single shot mode (mode 00).

14

1

15

1

2

3

4

7

12 13

16

6

5

SCLK

CS

FS

ID15 ID14 ID13 ID12

ID15

SDI

INT

EOC

SDO

OD11 OD10 OD9

OD4 OD3 OD2

OD1 OD0

Figure 2. TLV2548 Read CFR Cycle (FS active)

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1

2

3

4

5

6

7

12 13

14

1

15

16

SCLK

CS

FS

ID15 ID14 ID13 ID12

ID15 ID14

SDI

INT

EOC

SDO

OD11 OD10 OD9

OD0

OD4

OD2

OD3

OD1

Figure 3. TLV2548 Read CFR Cycle (FS = 1)

FIFO Read Cycle

The first command in the active cycle after INT is generated, if the FIFO is used, is assumed as the FIFO read

command. The first FIFO content is output immediately before the command is decoded. If this command is not

a FIFO read, then the output is terminated but the first data in the FIFO is retained until a valid FIFO read

command is decoded. Use of more layers of the FIFO reduces the time taken to read multiple data. This is

because the read cycle does not generate EOC or INT, nor does it carry out any conversion.

14

1

2

3

4

12

15

1

2

5

6

7

13

16

SCLK

CS

FS

ID15 ID14 ID13 ID12

ID15 ID14

SDI

INT

EOC

SDO

OD0

OD11 OD10 OD9 OD8 OD7 OD6 OD5

OD11 OD10

These devices can perform continuous FIFO read cycles (FS = 1) controlled by SCLK; SCLK can stop between each 16 SCLKs.

Figure 4. TLV2548 FIFO Read Cycle (FS = 1)

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Write Cycle (Write CFR)

The write cycle is used to write to the configuration register CFR (with 12-bit register content). The write cycle

does not generate an EOC or INT, nor does it carry out any conversion (see power up and initialization

requirements).

4

12

14

6

7

13

15

1

2

3

5

16

1

SCLK

CS

FS

ID11 ID10

ID4

ID2

ID1

ID15 ID14 ID13 ID12

ID3

ID0

ID15

ID9

SDI

INT

EOC

SDO

Figure 5. TLV2548 Write Cycle (FS Active)

1

2

3

4

12 13 14 15 16

1

6

5

7

SCLK

CS

FS

ID11 ID10

ID2

ID1

ID15 ID14 ID13 ID12

ID3

ID0

ID15 ID14

ID9

ID4

SDI

INT

EOC

SDO

Figure 6. TLV2548 Write Cycle (FS = 1)

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Conversion Cycles

DSP/Normal Sampling

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16 Short Sampling

28 Long Sampling

30 Short Sampling

42 Long Sampling

(If CONV

CLK = SCLK0

1

2

3

4

5

6

7

12

SCLK

t

c

(30 or 42 SCLKs)

CS

FS

ID15 ID14I ID13 ID12

ID15

SDI

INT

t

(12 or 24 SCLKs)

(sample)

EOC

SDO

(SDOZ on SCLK16L Regardless

of Sampling Time)

t

(conv)

MSB-1 MSB-2 MSB-3 MSB-4

MSB-5 MSB-6

LSB

MSB

Figure 7. Mode 00 Single Shot/Normal Sampling (FS Signal Used)

16 Short Sampling

28 Long Sampling

30 Short Sampling

42 Long Sampling

(If CONV

CLK = SCLK0

1

2

3

4

5

6

7

12

13

SCLK

CS

t

c

(30 or 42 SCLKs)

FS

ID15 ID14 ID13 ID12

ID15

SDI

INT

t

(12 or 24 SCLKs)

(sample)

EOC

SDO

(SDOZ on SCLK16L Regardless

of Sampling Time)

t

(conv)

MSB-1 MSB-2 MSB-3 MSB-4 MSB-5 MSB-6

LSB

MSB

Figure 8. Mode 00 Single Shot/Normal Sampling (FS = 1, FS Signal Not Used)

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Device Get Out

Extended Sampling

Mode

Device Going Into

Extended Sampling Mode

Select/Read

Cycle

Select/Read

Cycle

Read

Cycle

CS

t

(sample )

Normal

Cycle

CSTART

FS

t

(conv)

†

SDI

INT

EOC

Previous Conversion

Result

Previous Conversion

Result

Hi-Z

SDO

†

This is one of the single shot commands. Conversion starts on next rising edge of CSTART.

Figure 9. Mode 00 Single Shot/Extended Sampling (FS Signal Used, FS Pin Connected to TMS320 DSP)

Modes Using the FIFO: Modes 01, 10, 11 Timing

Conversion #1

Configure Select From Channel 2

Conversion #4

From Channel 2

Select

CS

FS

CSTART

§

¶

†

‡

§

SDI

INT

Hi-Z

SDO

Read FIFO

#1

#2

#3

#4

Top of FIFO

†

Command = Configure write for mode 01, FIFO threshold = 1/2

Command = Read FIFO, first FIFO read

‡

§

¶

Command = Select ch2.

Use any channel select command to trigger SDI input.

Figure 10. TLV2548 Mode 01 DSP Serial Interface (Conversions Triggered by FS)

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Conversion #1 From Channel 2

¶

Conversion #4 From Channel 2

Select

Configure Select

CS

FS

(DSP)

t

(sample)

t

(sample)

t

(sample)

CSTART

§

‡

§

†

SDI

INT

Hi-Z

SDO

Read FIFO

#1

#2

#3

#4

Sample Times ≥ MIN t

(sample)

(See Operating Characteristics)

First FIFO Read

†

Command = Configure write for mode 01, FIFO threshold = 1/2

Command = Read FIFO, first FIFO read

Command = Select ch2.

‡

§

¶

Minimum CS low time for select cycle is 6 SCLKs. The same amount of time is required between FS low to CSTART for proper channel decoding.

The low time of CSTART, not overlapped with CS low time, is the valid sampling time for the select cycle (see Figure 19).

Figure 11. TLV2548 Mode 01 μp/DSP Serial Interface (Conversions Triggered by CSTART)

Conversion

From Channel 3

From Channel 0

From Channel 3

Configure

From Channel 0

CS

FS

(DSP)

CSTART

SDI

‡

†

§

‡

INT

SDO

Read FIFO #1

#2

#3

#4

Read FIFO #1

Repeat

Top of FIFO

First FIFO Read

Second FIFO Read

†

Command = Configure write for mode 10 or 11, FIFO threshold = 1/2, sweep seq = 0-1-2-3.

Command = Read FIFO

‡

§

Use any channel select command to trigger SDI input.

Figure 12. TLV2548 Mode 10/11 DSP Serial Interface (Conversions Triggered by FS)

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Conversion

From Channel 0

From Channel 3

From Channel 0

Configure

CS

FS

(DSP)

CSTART

t

(sample)

t

(sample)

t

(sample)

t

(sample)

‡

†

‡

SDI

INT

SDO

Read FIFO #1

#2

#3

#4

Read FIFO

#1

Repeat

Top of FIFO

Second FIFO Read

First FIFO Read

†

‡

Command = Configure write for mode 10 or 11, FIFO threshold = 1/2, sweep seq = 0-1-2-3.

Command = Read FIFO

Figure 13. TLV2548 Mode 10/11 DSP Serial Interface (Conversions Triggered by CSTART)

Conversion

From Channel 0

From Channel 3

Configure

CS

CSTART

SDI

‡

§

†

‡

INT

SDO

Read FIFO #1

#2

#3

#4

Read FIFO

#1

Repeat

Top of FIFO

First FIFO Read

Second FIFO Read

†

‡

§

Command = Configure write for mode 10 or 11, FIFO threshold = 1/2, sweep seq = 0-1-2-3.

Command = Read FIFO

Use any channel select command to trigger SDI input.

Figure 14. TLV2548 Mode 10/11 μp Serial Interface (Conversions Triggered by CS)

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FIFO Operation

Serial

SDO

12-BITx8

FIFO

ADC

7

6

5

4

3

2

1

0

FIFO Full

FIFO 1/2 Full

FIFO 3/4 Full

FIFO 1/4 Full

FIFO Threshold Pointer

Figure 15. TLV2548 FIFO

The device has an eight-layer FIFO that can be programmed for different thresholds. An interrupt is sent to the

host after the pre-programmed threshold is reached. The FIFO can be used to store data from either a fixed

channel or a series of channels based on a pre-programmed sweep sequence. For example, an application may

require eight measurements from channel 3. In this case, the FIFO is filled with eight data sequentially taken

from channel 3. Another application may require data from channel 0, channel 2, channel 4, and channel 6 in an

orderly manner. Therefore, the threshold is set for 1/2 and the sweep sequence 0−2−4−6−0−2−4−6 is chosen.

An interrupt is sent to the host as soon as all four data are in the FIFO.

In single shot mode, the FIFO automatically uses a 1/8 FIFO depth. Therefore the CFR bits (D1,0) controlling

FIFO depth are don’t care.

SCLK and Conversion Speed

There are two ways to adjust the conversion speed.

•

The SCLK can be used as the source of the conversion clock to get the highest throughput of the device.

The minimum onboard OSC is 3.6 MHz and 14 conversion clocks are required to complete a conversion

(corresponding 3.86-μs conversion time). The devices can operate with an SCLK up to 20 MHz for the supply

voltage range specified. When a more accurate conversion time is desired, the SCLK can be used as the

source of the conversion clock. The clock divider provides speed options appropriate for an application where

a high speed SCLK is used for faster I/O. The total conversion time is 14 x (DIV/f_SCLK) where DIV is 1, 2, or 4.

For example a 20-MHz SCLK with the divide by 4 option produces a 14 x (4/20 M) = 2.8-μs conversion time.

When an external serial clock (SCLK) is used as the source of the conversion clock, the maximum equivalent

conversion clock (f_SCLK/DIV) should not exceed 6 MHz.

•

Autopower down can be used to slow down the device at a reduced power consumption level. This mode is

always used by the converter. If the device is not accessed (by CS or CSTART), the converter is powered

down to save power. The built-in reference is left on in order to quickly resume operation within one half

SCLK period. This provides unlimited choices to trade speed with power savings.

Reference Voltage

The device has a built-in reference with a programmable level of 2 V or 4 V. If the internal reference is used,

REFP is set to 2 V or 4 V and REFM should be connected to the analog ground of the converter. An external

reference can also be used through two reference input pins, REFP and REFM, if the reference source is

programmed as external. The voltage levels applied to these pins establish the upper and lower limits of the

analog inputs to produce a full-scale and zero-scale reading respectively. The values of REFP, REFM, and the

analog input should not exceed the positive supply or be lower than GND consistent with the specified absolute

maximum ratings. The digital output is at full scale when the input signal is equal to or higher than REFP and at

zero when the input signal is equal to or lower than REFM.

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Reference Block Equivalent Circuit

INTERNAL

REF

Close = Int Ref Used

Open = Ext Ref Used

REFP

Sample

Convert

10-mF

Internal

0.1-

mF

Decoupling

Cap

~50 pF

CDAC

Reference

Compensation

Cap

REFM (See Note 1)

External to the Device

A. If internal reference is used, tie REFM to analog ground and install a 10-μF (or 4.7-μF) internal reference

compensation capacitor between REFP and REFM to store the charge as shown in the figure above.

B. If external reference is used, the 10-μF (internal reference compensation) capacitor is optional. REFM can be

connected to external REFM or AGND.

C. Internal reference voltage drift, due to temperature variations, is approximately ±10 mV about the nominal 2 V

(typically) from –10°C to 100°C. The nominal value also varies approximately ±50 mV across devices.

D. Internal reference leakage during low ON time: Leakage resistance is on the order of 100 MΩ or more. This means

the time constant is about 1000 s with 10-μF compensation capacitance. Since the REF voltage does not vary much,

the reference comes up quickly after resuming from auto power down. At power up and power down the internal

reference sees a glitch of about 500 μV when 2-V internal reference is used (1 mV when 4-V internal reference is

used). This glitch settles out after about 50 μs.

Figure 16. Reference Block Equivalent Circuit

Power Down

The device has three power-down modes.

Autopower-Down Mode

The device enters the autopower-down state at the end of a conversion.

In autopower-down, the power consumption reduces to about 1 mA when an internal reference is selected. The

built-in reference is still on to allow the device to resume quickly. The resumption is fast enough (within

0.5 SCLK) for use between cycles. An active CS, FS, or CSTART resumes the device from power-down state.

The power current is 1 μA when an external reference is programmed and SCLK stops.

Hardware/Software Power-Down Mode

Writing 8000h to the device puts the device into a software power-down state, and the entire chip (including the

built-in reference) is powered down. For a hardware power down, the dedicated PWDN pin provides another way

to power down the device asynchronously. These two power-down modes power down the entire device

including the built-in reference to save power. The power-down current is reduced to about 1 μA as the SCLK is

stopped.

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An active CS, FS, or CSTART restores the device. There is no time delay when an external reference is

selected. However, if an internal reference is used, it takes about 20 ms to warm up. Deselect PWDN pin to

remove the device from the hardware power-down state. This requires about 20 ms to warm up if an internal

reference is also selected.

The configuration register is not affected by any of the power-down modes but the sweep operation sequence

has to be started over again. All FIFO contents are cleared by the power-down modes.

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range (unless otherwise noted)

(1)

VALUE

–0.3 to 6.5

–0.3 to V_CC+ 0.3

V_CC+ 0.3

UNIT

V

Supply voltage range, GND to V_CC

Analog input voltage range

V

Reference input voltage

V

Digital input voltage range

–0.3 to V_CC+ 0.3

–55 to 150

–55 to 125

–65 to 150

260

V

T_J

Operating virtual junction temperature range

Operating free-air temperature range

Storage temperature range

°C

T_A

T_stg

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds

(1) Stresses beyond those listed under the absolute maximum ratings may cause permanent damage to the device. These are stress

ratings only, and functional operation of the device at these or any other conditions beyond those indicated under the recommended

operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

DISSIPATION RATINGS

T_A< 25°C

POWER RATING

DERATING FACTOR

ABOVE T_A= 25°C

T_A= 125°C

POWER RATING

PACKAGE

(1)

20 PW

977 mW

7.8 mW/°C

195 mW

(1) This is the inverse of the traditional junction-to-ambient thermal resistance (R_θJA). Thermal resistance is not production tested and the

values given are for informational purposes only.

RECOMMENDED OPERATING CONDITIONS

over operating free-air temperature range (unless otherwise noted)

MIN

3

NOM

MAX

5.5

UNIT

V_CC

Supply voltage

3.3

V

Analog input voltage⁽¹⁾

High level control input voltage

Low–level control input voltage

0

V_CC

V_IH

V_IL

2.1

0.6

Delay time, delay from CS falling edge to FS rising edge

(see Figure 17).

t_d(CSL–FSH)

0.5

SCLKs

Delay time, delay from 16th SCLK falling edge to CS

rising edge (FS = 1), or 17th rising edge (FS is active)

(see Figure 17 and Figure 20).

t_{d(SCLK–CSH)}

SCLKs

Setup time, FS rising edge before SCLK falling edge

(see Figure 17).

t_{su(FSH–SCLKL}

t_{h(FSH–SCLKL)}

20

30

ns

Hold time, FS hold high after SCLK falling edge

(see Figure 17).

t_wH(CS)

t_wH(FS)

Pulse width, CS high time (see Figure 17 and Figure 20).

Pulse width, FS high time (see Figure 17).

100

0.75

67

ns

1

SCLKs

SCLK cycle time

(see Figure 17 and

Figure 20).

V_CC= 3.0 V to 3.6 V

V_CC= 4.5 V to 5.5V

10000

t_c(SCLK)

ns

50

10000

(1) When binary output format is used, analog input voltages greater than that applied to REFP convert as all ones (111111111111), while

input voltages less than that applied to REFM convert as all zeros (000000000000). The device is functional with reference down to 1 V.

(VREFP − VREFM − 1); however, the electrical specifications are no longer applicable.

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RECOMMENDED OPERATING CONDITIONS (continued)

over operating free-air temperature range (unless otherwise noted)

MIN

NOM

MAX

UNIT

Pulse width, SCLK low

time (see Figure 17 and

Figure 20)

V_CC= 4.5 V

V_CC= 3.0 V

V_CC= 4.5 V

V_CC= 3.0 V

22

t_wL(SCLK)

ns

27

22

27

Pulse width, SCLK high

time (see Figure 17 and

Figure 20)

t_wH(SCLK)

t_su(DI–SCLK

t_h(DI–SCLK)

ns

Setup time, SDI valid before falling edge of SCLK (FS is

active) or the rising edge of SCLK (FS=1)

(see and Figure 20).

25

5

Hold time, SDI hold valid after falling edge of SCLK (FS

is active) or the rising edge of SCLK (FS=1)

(see Figure 17).

Delay time, delay from CS falling edge to SDO valid

(see Figure 17 and Figure 20).

t_d(CSL–DOV)

t_d(FSL–DOV)

25

ns

Delay time, delay from FS falling edge to SDO valid

(see Figure 17).

Delay time, delay from

SCLK falling edge (FS is

active) or SCLK rising

edge (FS=1) to SDO valid

(see Figure 17 and

Figure 20).

For a date code later than

xxx, see the Data Code

Information section, item

3.

SDO = 0 pF

SDO = 60 pF

SDO = 5 pF

0.5 SCLK + 5

0.5 SCLK + 12

V_CC= 5.5 V

0.5 SCLK + 24

0.5 SCLK + 33

t_{d(SCLK–DOV)}

ns

V_CC= 3.0 V

SDO = 25 pF

Delay time, delay from 17th SCLK rising edge (FS is

active) or the 16th falling edge (FS=1) to EOC falling

edge

t_{d(SCLK–EOCL)}

45

ns

(see Figure 17 and Figure 20).

Delay time, delay from 16th SCLK falling edge to INT

falling edge (FS =1) or from the 17th rising edge SCLK

to INT falling edge (when FS active) (see Figure 20).

t_{d(SCLK–INTL)}

Min t_(conv)

µs

ns

t_{d(CSL–INTH)}

or

t_{d(FSH–INTH)}

Delay time, delay from CS falling edge or FS rising edge

to INT rising edge (see Figure 17, Figure 18, Figure 19

and Figure 20).

50

Delay time, delay from CS rising edge to CSTART falling

edge (see Figure 18 and Figure 19).

t_{d(CSH–CSTARTL)}

t_{d(CSTARTH–EOCL)}

t_wL(CSTART)

100

ns

μs

Delay time, delay from CSTART rising edge to EOC

falling edge (see Figure 18 and Figure 19).

Pulse width, CSTART low time (see Figure 18 and

Figure 19).

Min t_(sample)

Max t_(conv)

Delay time, delay from CSTART rising edge to CSTART

falling edge (see Figure 19).

t_{d(CSTARTH–CSTARTL)}

Delay time, delay from CSTART rising edge to INT

falling edge (see Figure 18 and Figure 19).

t_{d(CSTARTH–INTL)}

T_A

Max t_(conv)

μs

Operating free–air temperature

–55

125

°C

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ELECTRICAL CHARACTERISTICS

over operating free-air temperature range, V_CC= V_REFP= 3 V to 5.5 V, V_REFM= 0 V, SCLK frequency = 20 MHz at 5 V,

15 MHz at 3 V (unless otherwise noted)

(1)

PARAMETER

TEST CONDITIONS

MIN

2.4

TYP

MAX

UNIT

V_CC= 5.5 V, I_OH= -0.2 mA at 30 pF load

V_CC= 3.0 V, I_OH= –20 μA at 30 pF load

V_CC= 5.5 V, I_OL= 0.8 mA at 30 pF load

V_CC= 3.0 V, I_OL= 20 μA at 30 pF load

V_OH

V_OL

I_OZ

High–level output voltage

V

V_CC-0.2

0.4

0.1

2.5

Low–level output voltage

V

V_O= V_CC

V_O= 0

CS = V_CC

Off–state output current

(high–impedance–state)

μA

–2.5

I_IH

I_IL

High–level input current

Low–level input current

V_I= V_CC

V_I= 0 V

0.005

2.5

2

μA

–0.005

V_CC= 4.5 V to 5.5 V

V_CC= 3.0 V to 3.3 V

V_CC= 4.5 V to 5.5 V

V_CC= 3.0 V to 3.3 V

V_CC= 4.5 V to 5.5 V

V_CC= 3.0 V to 3.3 V

V_CC= 4.5 V to 5.5 V

V_CC= 3.0 V to 3.3 V

CS at 0 V, Ext ref

CS at 0 V, Int ref

CS at 0 V, Ext ref

CS at 0 V, Int ref

1

Operating supply current,

normal short sampling

2.4

1.7

I_CC

mA

1.1

1

Operating supply current,

extended sampling

2.1

1.6

1

Power down supply current

for all digital inputs,

0 ≤ V_I≤ 0.3 V or

V_CC= 4.5 V to 5.5 V, Ext clock

I_CC(PD)

μA

V_CC= 2.7 V to 3.3 V, Ext clock

1

1.0⁽²⁾

1.0⁽³⁾

V_I≥ VCC - 0.3 V, SCLK = 0

Auto power–down current

for all digital inputs,

0 ≤ V_I≤ 0.3 V or

V_CC= 4.5 V to 5.5 V, Ext clock, Ext ref

V_CC= 2.7 V to 3.3 V, Ext ref, Ext clock

I_CC(AUTOPWDN)

μA

V_I≥ V_CC- 0.3 V, SCLK = 0

Selected channel at V_CC

Selected channel at 0 V

2.5

Selected channel leakage

current

Maximum static analog

reference current into

REFP (use external

reference)

VREFP = V_CC= 5.5 V, VREFM = GND

1

Analog inputs

Control Inputs

V_CC= 4.5 V

V_CC= 2.7 V

45

5

50

25

C_i

Z_i

Input capacitance

pF

500

600

Input MUX ON resistance

Ω

AC SPECIFICATIONS

Signal-to-noise ratio +

distortion

SINAD

f_I= 12 kHz at 200 KSPS

65

71

–82

dB

T_A= –55°C

–73

–75

THD

Total harmonic distortion

Effective number of bits

f_I= 12 kHz at 200 KSPS

All other

temperatures

ENOB

11.6

–84

Bits

dB

SFDR

Spurious free dynamic range f_I= 12 kHz at 200 KSPS

–75

Analog Input

Full-power bandwidth, –3 dB

Full-power bandwidth, –1 dB

1

MHz

kHz

500

(1) All typical values are at V_CC= 5 V, T_A= 25°C.

(2) 1.2 mA if internal reference is used, 165 μA if internal clock is used.

(3) 0.8 mA if internal reference is used, 116 μA if internal clock is used.

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ELECTRICAL CHARACTERISTICS (continued)

over operating free-air temperature range, V_CC= V_REFP= 3 V to 5.5 V, V_REFM= 0 V, SCLK frequency = 20 MHz at 5 V,

15 MHz at 3 V (unless otherwise noted)

(1)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

REFERENCE SPECIFICATIONS⁽⁴⁾

(0.1 μF and 10 μF between REFP and

REFM pins)

Positive reference input

voltage

REFP

V_CC= 2.7 V to 5.5 V

2

V_CC

2

V

Negative reference input

voltage

REFM

V_CC= 2.7 V to 5.5 V

V_CC= 5.5 V

0

100

20

V

CS = 1, SCLK = 0, (off)

MΩ

kΩ

MΩ

kΩ

SCLK = 20 MHz

CS = 0,

(on)

25

Reference Input impedance

CS = 1, SCLK = 0 (off)

100

20

V_CC= 2.7 V

SCLK = 15 MHz

CS = 0,

(on)

Reference Input voltage

REFP-REFM

difference

V_CC= 2.7 V to 5.5 V

2

V_CC

V

V_CC= 5.5 V

V_CC= 2.7 V

VREF SELECT = 4 V

VREF SELECT = 2 V

3.85

1.925

4

2

4.15

2.075

REFP-REFM

Internal reference voltage

Internal reference start–up

time

V_CC= 5.5 V, 2.7 V with 10 μF compensation cap

20

16

ms

Internal reference

temperature coefficient

V_CC= 2.7 V to 5.5 V

40⁽⁵⁾PPM/°C

(4) Specified by design.

(5) Specified by design.

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OPERATING CHARACTERISTICS

over operating free-air temperature range, V_CC= V_REFP= 3 V to 5.5 V, V_REFM= 0 V, SCLK frequency = 20 MHz at 5 V,

15 MHz at 3 V (unless otherwise noted)

(1)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

±1.2 LSB

EL

Integral linearity error (INL)⁽²⁾

(3)

ED

Differential linearity error (DNL)

See

T_A= 25°C and

125°C

–4

6

(4)

EO

Offset error

LSB

T_A= –55°C

6.2

T_A= 25°C and

125°C

6

(4)

(3)

EFS

Full scale error

See

LSB

T_A= –55°C

7.6

800h

(2048D)

SDI = B000h

SDI = C000h

SDI = D000h

(5)

Self–test output code

000h (0D)

FFFh

(4095D)

Internal OSC

External SCLK

3.2

4.5

t_(conv)

Conversion time

μs

(14 x DIV) /

f_SCLK

With a maximum of 1-kW input source

impedance

t_(sample)Sampling time

600

ns

(1) All typical values are at T_A= 25°C.

(2) Linear error is the maximum deviation from the best straight line through the A/D transfer characteristics.

(3) Analog input voltages greater than that applied to REFP convert as all ones (111111111111), while input voltages less than that applied

to REFM convert as all zeros (000000000000).

(4) Zero error is the difference between 000000000000 and the converted output for zero input voltage: full-scale error is the difference

between 111111111111 and the converted output for full-scale input voltage.

(5) Both the input data and the output codes are expressed in positive logic.

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PARAMETER MEASUREMENT INFORMATION

V

IH

CS

t

V

IL

t

wH(CS)

t

WH(FS)

d(CSL-FSH)

V

IH

FS

V

IL

t

h(FSH-SCLKL)

t

d(CSL-INTH)

t

wH(SCLK)

d(SCLK-CSH)

16

t

c(SCLK)

su(FSH-SCLKL)

t

d(FSH-INTH)

1

2

15

SCLK

t

wL(SCLK)

t

su(DI-SCLK)

t

d(CSL-DOV)

h(DI-SCLK)

V

IH

SDI

ID15

ID14

ID1

ID0

V

IL

t

d(FSL-DOV)

V

OH

Hi-Z

SDO

OD11

OD10

don’t care

t

don’t care

OD15

V

OL

t

d(SCLK-EOCL)

d(SCLK-DOV)

t

V

OH

(conv)

EOC

INT

V

OL

t

d(SCLK-INTL)

V

OH

V

OL

Figure 17. Critical Timing, DSP Mode (Normal Sampling, FS is Active)

SELECT CYCLE

V

IH

CS

IL

t

d(CSH-CSTARTL)

t

wL(CSTART)

V

IH

CSTART

IL

†

t

d(CSTARTH-INTL)

t

(CONV)

V

OH

EOC

INT

V

OL

t

d(CSTARTH-EOCL)

t

d(CSL-INTH)

V

OH

V

OL

†

CSTART falling edge may come before the rising edge of CS but no sooner than the fifth SCLK of the SELECT CYCLE.

Figure 18. Critical Timing (Extended Sampling, Single Shot)

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PARAMETER MEASUREMENT INFORMATION (continued)

SELECT CYCLE

V

IH

CS

t

wL(CSTART)

IL

t

d(CSTARTHCSTARTL)

d(CSH-CSTARTL)

V

IH

CSTART

IL

†

V

OH

EOC

t

V

OL

d(CSL-INTH)

t

d(CSTARTH-EOCL)

t

d(CSTARTH-INTL)

V

OH

INT

V

OL

†

CSTART falling edge may come before the rising edge of CSbut no sooner than the fifth SCLK of the SELECT CYCLE. In this case, the actual

sampling time is measured from the rising edge CS to the rising edge of CSTART.

Figure 19. Critical Timing (Extended Sampling, Repeat/Sweep/Repeat Sweep)

V

IH

CS

V

IL

t

wH(CS)

t

wH(SCLK)

d(SCLK-CSH)

15 16

t

c(SCLK)

1

2

V

IH

SCLK

IL

t

wL(SCLK)

t

su(DI-SCLK)

t

h(DI-SCLK)

V

IH

SDI

ID15

ID14

ID1

ID0

IL

t

d(CSL-DOV)

V

OH

Hi-Z

SDO

OD11

OD10

don’t care

t

don’t care

V

OL

t

d(SCLK-EOCL)

d(SCLK-DOV)

t

V

OH

(conv)

EOC

INT

V

OL

t

d(SCLK-INTL)

d(CSL-INTH)

V

OH

V

OL

Figure 20. Critical Timing, Microprocessor Mode (Normal Sampling, FS = 1)

24

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TYPICAL CHARACTERISTICS

INTEGRAL NONLINEARITY

vs

TEMPERATURE

0.6

0.595

0.59

0.53

0.52

0.51

0.585

0.5

0.58

0.575

0.49

V

= 2.7 V, Internal Reference = 2 V,

Internal Oscillator, Single Shot,

CC

0.57

0.565

0.56

Short Sample, Mode 00 mP Mode

V

= 5.5 V, Internal Reference = 2 V,

Internal Oscillator, Single Shot,

CC

0.48

0.47

Short Sample, Mode 00 mP Mode

41.25 57.5 73.75

-23.75

25

90

-23.75

25 41.25 57.5

90

8.75

-40

-7.5

-40

-7.5 8.75

73.75

T

A

- Temperature - °C

T

A

- Temperature - °C

Figure 21.

Figure 22.

DIFFERENTIAL NONLINEARITY

vs

TEMPERATURE

0.496

0.494

0.492

0.49

0.48

0.47

0.46

0.45

0.44

0.43

0.42

0.488

0.486

0.484

0.482

V

= 5.5 V, Internal Reference = 2 V,

Internal Oscillator, Single Shot,

CC

V

= 2.7 V, Internal Reference = 2 V,

Internal Oscillator, Single Shot,

CC

Short Sample, Mode 00 mP Mode

0.48

0.478

-23.75

25

90

-23.75

25

- Temperature - °C

90

-40

-7.5 8.75

41.25 57.5 73.75

-40

-7.5 8.75

41.25

57.5 73.75

T

A

- Temperature - °C

A

T

Figure 23.

Figure 24.

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TYPICAL CHARACTERISTICS (continued)

OFFSET ERROR

GAIN ERROR

vs

TEMPERATURE

1.2

1

0.5

0

-0.5

0.8

-1

0.6

0.4

-1.5

V

CC

= 5 V, Internal Reference = 4 V,

V

CC

= 5 V, Internal Reference = 4 V,

External Oscillator = SCLK/4,

Single Shot, Long Sample,

Mode 00 mP Mode

External Oscillator = SCLK/4,

Single Shot, Long Sample,

Mode 00 mP Mode

-2

0.2

0

-2.5

-23.75

25 41.25 57.5 73.75 90

- Temperature - °C

-40

-7.5 8.75

T

41.25 57.5

73.75 90

-23.75

25

-40

-7.5 8.75

T

A

- Temperature - °C

A

Figure 25.

Figure 26.

SUPPLY CURRENT

vs

POWER DOWN CURRENT

vs

TEMPERATURE

0.4

0.2

0

1.4

1.2

1

External Reference = 4 V, Internal Oscillator,

Single Shot, Short Sample, Mode 00 mP Mode

Long Sample

V

CC

= 5 V

0.2

Short Sample

0.4

0.6

V

CC

= 2.7 V

0.8

0.6

V

CC

= 5.5 V

V

= 5 V, External Reference = 4 V,

Internal Oscillator, Single Shot,

CC

0.8

1

Short Sample, Mode 00 mP Mode

-23.75

25

90

-23.75

25 41.25 57.5

73.75

- Temperature -

°C

90

-40

-7.5 8.75

41.25 57.5 73.75

-40

-7.5 8.75

T

A

- Temperature - °C

A

Figure 27.

Figure 28.

26

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TYPICAL CHARACTERISTICS (continued)

INTEGRAL NONLINEARITY

vs

SAMPLES

1.0

0.5

V

= 2.7 V, Internal Reference = 2 V, Internal Oscillator,

CC

Single Shot, Short Sample, Mode 00 mP Mode

0.0

-0.5

-1.0

0

4097

Samples

Figure 29.

DIFFERENTIAL NONLINEARITY

vs

SAMPLES

1.0

0.5

V

= 2.7 V, Internal Reference = 2 V, Internal Oscillator,

CC

Single Shot, Short Sample, Mode 00 mP Mode

0.0

-0.5

-1.0

0

4097

Samples

Figure 30.

INTEGRAL NONLINEARITY

vs

SAMPLES

1.0

0.5

0.0

V

= 5 V, Internal Reference = 2 V, Internal Oscillator,

CC

Single Shot, Short Sample, Mode 00 mP Mode

-0.5

-1.0

0

4097

Samples

Figure 31.

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TYPICAL CHARACTERISTICS (continued)

DIFFERENTIAL NONLINEARITY

vs

SAMPLES

1.0

V

= 5 V, Internal Reference = 2 V, Internal Oscillator,

CC

Single Shot, Short Sample, Mode 00 mP Mode

0.5

0.0

-0.5

-1.0

0

4097

Samples

Figure 32.

MAGNITUDE

vs

FREQUENCY

100%

160

150

140

130

120

110

100

90

V

= 5 V, External Reference = 4 V,

Internal Oscillator , Single Shot, Long Sample, Mode 00 mP

CC

Mode @ 200 KSPS

80

70

60

50

40

30

20

10

0

5

10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100

f - Frequency - kHz

Figure 33.

28

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TYPICAL CHARACTERISTICS (continued)

SIGNAL-TO-NOISE + DISTORTION

EFFECTIVE NUMBER OF BITS

vs

INPUT FREQUENCY

-67

-67.50

-68

11.50

11.40

11.30

11.20

-68.50

-69

11.10

11

-69.50

-70

V

= 5 V,

External Reference = 4 V,

CC

V

= 5 V,

External Reference = 4 V,

CC

Internal Oscillator,

Single Shot, Long Sample,

Mode 00 mP Mode

Internal Oscillator,

Single Shot, Long Sample,

Mode 00 mP Mode

10.90

10.80

-70.50

-71

0

50

100

150

0

50

100

150

f - Frequency - kHz

Figure 35.

Figure 34.

TOTAL HARMONIC DISTORTION

SPURIOUS FREE DYNAMIC RANGE

vs

INPUT FREQUENCY

-69

-70

-71

-72

-73

-74

-75

-76

-77

-73

-74

-75

-76

-77

-78

-79

-80

V

= 5 V,

External Reference = 4 V,

CC

V

= 5 V,

External Reference = 4 V,

CC

Internal Oscillator,

Single Shot, Long Sample,

Mode 00 mP Mode

Internal Oscillator,

Single Shot, Long Sample,

Mode 00 mP Mode

-81

-82

-78

-79

0

50

100

150

0

50

100

150

f - Frequency - kHz

Figure 36.

Figure 37.

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TYPICAL CHARACTERISTICS (continued)

SIGNAL-TO-NOISE RATIO

vs

INPUT FREQUENCY

-70.2

V

= 5 V,

External Reference = 4 V,

CC

Internal Oscillator,

Single Shot, Long Sample,

Mode 00 mP Mode

-70.4

-70.6

-70.8

-71

-71.2

-71.4

0

50

100

150

f - Frequency - kHz

Figure 38.

PRINCIPLES OF OPERATION

v

cc

10 kΩ

V

DD

XF

CS

TXD

RXD

SDI

SDO

A

IN

CLKR

CLKX

SCLK

TMS320 DSP

BIO

INT

TLV2548

FSR

FSX

FS

GND

Figure 39. Typical Interface to a TMS320 DSP

DATA CODE INFORMATION

Parts with a date code earlier than 31xxxxx have the following discrepancies:

1. Earlier devices react to FS input irrespective of the state of the CS signal.

2. The earlier silicon was designed with SDO prereleased half clock ahead. This means in the microcontroller

mode (FS=1) the SDO is changed on the rising edge of SCLK with a delay; and for DSP serial port (when FS

is active) the SDO is changed on the falling edge of SCLK with a delay. This helps the setup time for

processor input data, but may reduce the hold time for processor input data. It is recommended that a

100-pF capacitance be added to the SDO line of the ADC when interfacing with a slower processor that

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requires longer input data hold time.

3. For earlier silicon, the delay time is specified as:

MIN NOM

MAX UNIT

SDO = 0 pF

SDO = 100 pF

SDO = 0 pF

16

20

24

30

V_CC= 4.5 V

Delay time, delay from SCLK falling edge (FS is

active) or SDO = 100 pF 20 ns SCLK rising edge

ns

(FS = 1) to next SDO valid, t_d(SCLK-DOV)

.

V_CC= 2.7 V

SDO = 100 pF

This is because the SDO is changed at the rising edge in the up mode with a delay. This is the hold time

required by the external digital host processor, therefore, a minimum value is specified. The newer silicon

has been revised with SDO changed at the falling edge in the up mode with a delay. Since at least 0.5 SCLK

exists as the hold time for the external host processor, the specified maximum value helps with the

calculation of the setup time requirement of the external digital host processor.

For an explanation of the DSP mode, reverse the rising/falling edges in item 2. above.

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PACKAGE MATERIALS INFORMATION

www.ti.com

14-Jul-2012

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0

B0

K0

P1

W

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

TLV2548MPWREP

TSSOP

PW

20

2000

330.0

16.4

6.95

7.1

1.6

8.0

16.0

Q1

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

14-Jul-2012

*All dimensions are nominal

Device

Package Type Package Drawing Pins

TSSOP PW 20

SPQ

Length (mm) Width (mm) Height (mm)

367.0 367.0 38.0

TLV2548MPWREP

2000

Pack Materials-Page 2

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型号：	V62/10603-01XE
厂家：	TEXAS INSTRUMENTS
描述：	3.0-V TO 5.5-V, 12-BIT, 200-KSPS, 4-/8-CHANNEL, LOW-POWER SERIAL ANALOG-TO-DIGITAL CONVERTER WITH AUTOPOWER-DOWN 3.0 V至5.5 V ，12位， 200 KSPS ，4 / 8通道，低功耗串行ANALOG -TO -DIGITAL与自功率降压转换器转换器
文件：	总38页 (文件大小：1117K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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