T6L76E [TOSHIBA]
IC LIQUID CRYSTAL DISPLAY DRIVER, UUC461, TCP-461, Display Driver;
| 型号： | T6L76E |
| 厂家： | 
TOSHIBA |
| 描述： | IC LIQUID CRYSTAL DISPLAY DRIVER, UUC461, TCP-461, Display Driver 驱动 接口集成电路 |
| 文件： | 总20页 (文件大小：384K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
T6L76E
TOSHIBA CMOS Digital Integrated Circuits Silicon Monolithic
T6L76E
Source Driver for TFT LCD Panels
The T6L76E is a 256-gray-level and 384-channel-output source
driver for TFT LCD panels. The device accepts 8 bit × 6 dot
digital data inputs, for which the direction of data transfer can be
selected by the U/D pin. The 12 (6 × 2) external power supply and
the internal DA converter realize display 16,700,000 colors, on
which reference analog voltage inputs is made.
Unit: mm
User Pitch Area
IN OUT
T6L76E
Since the T6L76E supports a dot line inversion system, it
eliminates the need for inversion of the LCD panel’ s counter
electrode, allowing for high picture quality.
Please contact Toshiba or an authorized
Toshiba dealer TCP specification and
product lineup.
Moreover, its output dynamic range is a large 12.8 Vp-p (max).
Based on high-speed CMOS, the T6L76E offers both low power
consumption and high-speed operation. To configure an SXGA or
XGA-compatible TFT-LCD module, it allows a maximum
operating frequency of 37.5 MHz.
TCP (tape carrier package)
Features
•
Grayscale data
Panel drive outputs
Fast operation
Power supply voltage : Digital power supply voltage…3.0 to 3.6 V
Analog power supply voltage…7.5 to 13.0 V
: Digital CMOS-level 48-bit (8 bits × 6 outputs) parallel transfer method, selectable
transfer direction
•
: 384 outputs, 256 gray levels, R-DAC system, reference analog voltage, 12 (6 × 2)
external reference analog voltage inputs, dot/line inversion drive
•
•
: max 37.5 MHz
•
•
•
Operating temperature : −20 to 75°C
Package
: Tape carrier package (TCP)
Cascading of multiple devices
1
2002-04-03
T6L76E
Block Diagram
DI/O
CPH
U/D
DO/I
Data control unit
D00 to D07
D10 to D17
D20 to D27
D30 to D37
D40 to D47
D50 to D57
Sampling register (REG1)
DINV1
DINV2
LOAD
POL
Load register (REG2)
DA converter
V0 to V11
Output circuit
AV
DV
DD
DD
AV
DV
SS
SS
OUT1
OUT3
OUT382
OUT384
OUT2
OUT383
2
2002-04-03
T6L76E
Pin Assignment
OUT1 78
OUT2 79
OUT3 80
OUT4 81
OUT5 82
OUT6 83
OUT7 84
OUT8 85
OUT9 86
OUT10 87
77 AV
76 AV
SS
DD
75 D07
68 D00
67 D47
60 D40
59 D27
52 D20
51 DI/O
50 DINV1
49 DV
48 DV
SS
DD
47 CPH
46 TEST
45 V0
44 V1
43 V2
42 V3
41 V4
T6L76E
(chip top view)
40 V5
39 V6
38 V7
37 V8
36 V9
35 V10
34 V11
33 DO/I
32 LOAD
31 POL
30 D37
23 D30
22 D17
15 D10
14 D57
7
6
5
4
3
2
1
D50
DINV2
OUT375 452
OUT376 453
OUT377 454
OUT378 455
OUT379 456
OUT380 457
OUT381 458
OUT382 459
OUT383 460
OUT384 461
DV
SS
U/D
DV
AV
AV
DD
DD
SS
The above diagram shows the device’ pin configuration only and does not necessarily correspond to the pad layout
on the chip.
Please contact Toshiba or our distributors for the latest TCP specification.
3
2002-04-03
T6L76E
Pin Function
Pin Name
I/O
I/O
Function
Data transfer enable pins
These pins are used to input/output grayscale data.
Input and output are switched as shown below according to the setting of the U/D pin.
U/D
DI/O
DO/I
H
L
Input
Output
Output
Input
DI/O
DO/I
When set for input
A high on DI/O or DO/I is latched into the internal logic synchronously with the rising edge of
CPH. When the internal circuit is in standby state, the device is ready to transfer data. The
grayscale data are latched in sequentially, starting at the next rise of CPH.
When set for output
The pin is used to transfer the enable signal to the T6L76E at the next stage of the LCD driver.
The pin enters standby state after outputting a high.
Transfer direction select pin
This pin controls the direction in which the data are transferred into the sampling register. Data
are transferred synchronously with each rising edge of CPH in one of the following sequences:
When U/D is high, data is transferred in the order OUT1 to OUT6, OUT7 to OUT12, and so
on.
U/D
I
When U/D is low, the direction is reversed to the order OUT379 to OUT384, OUT373 to
OUT378, and so on.
The voltage applied to this pin must be a DC-level voltage that is either high or low.
Data transfer clock input
This clock input is used to transfer the grayscale data.
The result of logical operation between grayscale data and polarity inverting pin is latched into
the REG1 sequentially at each rising edge of CPH.
CPH
I
I
Always make sure that a constant-period clock is input to this pin.
Grayscale data bus
D00 to D07
D10 to D17
D20 to D27
D30 to D37
D40 to D47
D50 to D57
The data inputs consist of 8-bit words for each of the six channels, that are transferred in
parallel at the rising edge of CPH. The relationship between the grayscale data and the the
output pins is as follows:
Grayscale data = 128 × Dn7 + 64 × Dn6 + 32 × Dn5 + 16 × Dn4 + 8 × Dn3 + 4 × Dn2 +
2 × Dn1 + Dn0
(*) where n = 0, 1, 2, 3, 4, 5
Data polarity inverting pin
These pins select whether or not the polarity of input data be inverted.
Logic operation: Data bus (Dxx) XOR DINV1, 2
when DINV1, 2 = high: data is inverted.
DINV1
DINV2
I
when DINV1, 2 = low: data is not inverted.
DINV1 chooses whether or not to invert grayscale data
(D00 to D07, D10 to D17, D20 to D27).
DINV2 chooses whether or not to invert grayscale data
(D30 to D37, D40 to D47, D50 to D57).
Data load input pin
When a high voltage is supplied to the load input, the data are transferred from the sampling
register to the load register synchronously at the rising edge of CPH. The selected analog
voltage corresponding to the data is sent the LCD.
LOAD
POL
I
I
Polarity inverting pin
The signal of this pin is latched into the internal logic when a high voltage is supplied to the load
input.
When POL = high, the reference voltages for odd number outputs are V6 to V11 and
those for even-number outputs are V0 to V5.
When POL = low, the reference voltages for odd-number outputs are V0 to V5 and
those for even-number outputs are V6 to V11.
Reference analog input pins
These pins are used to input the voltages used for the DAC.
V0 to V11
I
>
>
>
>
>
>
>
>
>
>
>
Conditions: AV
AV
> V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 >
=
=
=
=
=
=
=
=
=
=
=
DD
SS
OUT1 to OUT384
O
LCD panel drive pins
AV
AV
DV
DV
Analog power supply pin
Analog GND pin
DD
SS
DD
SS
This pin must be at the same potential level as the digital GND pin.
Digital power supply pin.
Digital GND pin
This pin must be at the same potential level as the analog GND pin.
Test pin
TEST
I
Leave this pin open.
4
2002-04-03
T6L76E
Device Operation
(1) Starting data transfer
A high input to the data transfer enable pin (DI/O or DO/I) is latched into the internal logic synchronously
with the rising edge of CPH, setting the device ready to transfer data.
Data transfer starts at the next rise of CPH.
This enable pin must not be held high for more than one CPH period.
(2) Data transfer method
The data in the grayscale data bus is latched to the sampling register (REG1) synchronously with each rising
edge of CPH.
Grayscale data for six outputs are latched into the device simultaneously in one transfer. Therefore, 64
transfers are performed to latch the data. When the data loading is completed, the device enters a standby state.
The data written into REG1 is the result of logical operation between the grayscale data bus and DINV.
Note 1: Make sure that a clock of the same period as applied during data transfer is input even while in standby
state. The LOAD input must not be driven high during data transfer.
(3) Terminating data transfer
The data transfer enable pin (DO/I or DI/O) output goes high synchronously with the rising edge of CPH, one
clock period before the last data item is latched in. It is held high until the next rise of CPH.
(4) Panel drive output
After the data transfer enable pin (DO/I, DI/O) = H outputs, when a high voltage is supplied to the load input,
the data in the sampling register (REG1) are transferred to the load register (REG2), and the device starts
updating output to the LCD panel drive pins.
Note 2: Make sure the LOAD input is held high for more than 2 clock periods.
(5) Output offset correction function
The T6L76E incorporates a function which corrects offset to reduce output offset (see page 19).
Number of output offset crrection timing pulses can be selected (126, 196, 208, 224, 280, 288, 378 or 490).
Note 3: When t
> t
depending on the frequency of the CPH used, consult Toshiba.
pdDX2
pdDX1
5
2002-04-03
T6L76E
(6) Reference power supply circuit
The DA converter is comprised of ladder resistors and switches.
Unit: (Ω)
V0
V1
V00H
V01H
V02H
V1FH
V20H
V21H
V7FH
V80H
V81H
VDFH
VE0H
VE1H
VFEH
VFFH
VFFH’
VFEH’
VE1H’
VE0H’
VDFH’
V81H’
V80H’
V7FH’
V21H’
V20H’
V1FH’
Resistor Resistance Resistor Resistance Resistor Resistance Resistor Resistance
Name
Value
200
Name
Value
100
Name
Value
50
Name
Value
25
R
0
R
1
R
2
R
3
R
4
R
5
R
6
R
7
R
8
R
9
R
32
R
33
R
34
R
35
R
36
R
37
R
38
R
39
R
40
R
41
R
42
R
43
R
44
R
45
R
46
R
47
R
48
R
49
R
50
R
51
R
52
R
53
R
54
R
55
R
56
R
57
R
58
R
59
R
60
R
61
R
62
R
63
R
64
R
65
R
66
R
67
R
68
R
69
R
70
R
71
R
72
R
73
R
74
R
75
R
76
R
77
R
78
R
79
R
80
R
81
R
82
R
83
R
84
R
85
R
86
R
87
R
88
R
89
R
90
R
91
R
92
R
93
R
94
R
95
R
R
R
R
96
97
98
99
200
200
200
200
200
200
200
200
200
200
200
175
175
175
175
175
175
175
175
150
150
150
150
150
150
150
150
100
100
100
100
100
100
100
75
75
75
75
75
75
75
75
75
75
75
75
75
75
75
75
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
R
100
R
101
R
102
R
103
R
104
R
105
R
106
R
107
R
108
R
109
R
110
R
111
R
112
R
113
R
114
R
115
R
116
R
117
R
118
R
119
R
120
R
121
R
122
R
123
R
124
R
125
R
126
R
127
V2
V3
V4
R
10
R
11
R
12
R
13
R
14
R
15
R
16
R
17
R
18
R
19
R
20
R
21
R
22
R
23
R
24
R
25
R
26
R
27
R
28
R
29
R
30
R
31
V5
V6
V7
V8
V9
V02H’
V01H’
V10
V11
V00H’
6
2002-04-03
T6L76E
Unit: (Ω)
Resistor Resistance Resistor Resistance Resistor Resistance Resistor Resistance
Name
Value
25
Name
Value
25
Name
Value
25
Name
Value
50
R
128
R
129
R
130
R
131
R
132
R
133
R
134
R
135
R
136
R
137
R
138
R
139
R
140
R
141
R
142
R
143
R
144
R
145
R
146
R
147
R
148
R
149
R
150
R
151
R
152
R
153
R
154
R
155
R
156
R
157
R
158
R
159
R
160
R
161
R
162
R
163
R
164
R
165
R
166
R
167
R
168
R
169
R
170
R
171
R
172
R
173
R
174
R
175
R
176
R
177
R
178
R
179
R
180
R
181
R
182
R
183
R
184
R
185
R
186
R
187
R
188
R
189
R
190
R
191
R
192
R
193
R
194
R
195
R
196
R
197
R
198
R
199
R
200
R
201
R
202
R
203
R
204
R
205
R
206
R
207
R
208
R
209
R
210
R
211
R
212
R
213
R
214
R
215
R
216
R
217
R
218
R
219
R
220
R
221
R
222
R
223
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
75
75
75
75
75
75
75
75
75
75
75
75
100
100
100
100
100
100
100
100
200
200
200
ΣR
= 0.2 kΩ
= 5.2 kΩ
= 4.0 kΩ
= 2.7 kΩ
= 2.7 kΩ
= 14.8 kΩ
0
ΣR to R
31
1
ΣR to R
32 127
ΣR
to R
128
224
223
254
ΣR
to R
Total
7
2002-04-03
T6L76E
(7) Grayscale data and output voltages
The device’ s LCD drive output voltages are determined by the grayscale data values and the 12 (6 × 2)
reference analog inputs corresponding to the the range of possible line voltages (V0 to V11). Note that since the
T6L76E is corresponding to the dot inversion drive system, it can generate different grayscale voltages for
even-numbered and odd-numbered outputs.
● Schematic representation of reference analog voltage inputs
AVDD
Number of
divisions
V0
1
V1
31
V2
96
V3
V4
96
31
V5
V6
31
V7
96
V8
96
V9
31
V10
1
V11
Number of
divisions
AVSS
“00”
“20”
“40”
“60”
“80”
“A0”
“C0”
“E0”
“FF”
Grayscale data input (HEX)
8
2002-04-03
T6L76E
Grayscale Data and Output Voltages
(positive polarity output: V0 > V1 > V2 > V3 > V4 > V5)
●
Note 4: The output voltage (anticipated value) below is calculated using the voltage input to V0 to V11 and
reference analog voltage.
Grayscale
Output Voltage (anticipated value)
Dn7 Dn6 Dn5 Dn4 Dn3 Dn2 Dn1 Dn0
Data
00H
01H
02H
↓
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
V00H V0
V01H V1
V02H V1 + (V2 − V1) × (200 × 1)/5200
↓
↓
↓
↓
↓
↓
0CH
0DH
↓
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
1
V0CH V1 + (V2 − V1) × (200 × 11)/5200
V0DH V1 + (V2 − V1) × (2200 + 175 × 1)/5200
↓
↓
14H
15H
↓
0
0
0
0
0
0
1
1
0
0
1
1
0
0
0
1
V14H V1 + (V2 − V1) × (2200 + 175 × 8)/5200
V15H V1 + (V2 − V1) × (3600 + 150 × 1)/5200
↓
↓
18H
19H
↓
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
1
V18H V1 + (V2 − V1) × (3600 + 150 × 4)/5200
V19H V1 + (V2 − V1) × (4200 + 150 × 1)/5200
↓
↓
1CH
1DH
1EH
1FH
20H
21H
↓
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
1
1
1
1
0
0
1
1
1
1
0
0
0
0
1
1
0
0
0
1
0
1
0
1
V1CH V1 + (V2 − V1) × (4200 + 150 × 4)/5200
V1DH V1 + (V2 − V1) × (4800 + 100 × 1)/5200
V1EH V1 + (V2 − V1) × (4800 + 100 × 2)/5200
V1FH V1 + (V2 − V1) × (4800 + 100 × 3)/5200
V20H V2
V21H V2 + (V3 − V2) × (100 × 1)/4000
↓
↓
↓
↓
↓
↓
↓
↓
24H
25H
↓
0
0
0
0
1
1
0
0
0
0
1
1
0
0
0
1
V24H V2 + (V3 − V2) × (100 × 4)/4000
V25H V2 + (V3 − V2) × (400 + 75 × 1)/4000
↓
↓
34H
35H
↓
0
0
0
0
1
1
1
1
0
0
1
1
0
0
0
1
V34H V2 + (V3 − V2) × (400 + 75 × 16)/4000
V35H V2 + (V3 − V2) × (1600 + 50 × 1)/4000
↓
↓
3FH
40H
↓
0
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
V3FH V2 + (V3 − V2) × (1600 + 50 × 11)/4000
V40H V2 + (V3 − V2) × (1600 + 50 × 12)/4000
↓
↓
48H
49H
↓
0
0
1
1
0
0
0
0
1
1
0
0
0
0
0
1
V48H V2 + (V3 − V2) × (1600 + 50 × 20)/4000
V49H V2 + (V3 − V2) × (2600 + 25 × 1)/4000
↓
↓
5FH
60H
↓
0
0
1
1
0
1
1
0
1
0
1
0
1
0
1
0
V5FH V2 + (V3 − V2) × (2600 + 25 × 23)/4000
V60H V2 + (V3 − V2) × (2600 + 25 × 24)/4000
↓
↓
7FH
0
1
1
1
1
1
1
1
V7FH V2 + (V3 − V2) × (2600 + 25 × 55)/4000
9
2002-04-03
T6L76E
Grayscale
Data
Output Voltage (anticipated value)
Dn7 Dn6 Dn5 Dn4 Dn3 Dn2 Dn1 Dn0
80H
81H
↓
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
V80H V3
V81H V3 + (V4 − V3) × (25 × 1)/2700
↓
↓
↓
↓
↓
↓
9FH
A0H
↓
1
1
0
0
0
1
1
0
1
0
1
0
1
0
1
0
V9FH V3 + (V4 − V3) × (25 × 31)/2700
VA0H V3 + (V4 − V3) × (25 × 32)/2700
↓
↓
BFH
C0H
↓
1
1
0
1
1
0
1
0
1
0
1
0
1
0
1
0
VBFH V3 + (V4 − V3) × (25 × 63)/2700
VC0H V3 + (V4 − V3) × (25 × 64)/2700
↓
↓
D4H
D5H
↓
1
1
1
1
0
0
1
1
0
0
1
1
0
0
0
1
VD4H V3 + (V4 − V3) × (25 × 84)/2700
VD5H V3 + (V4 − V3) × (2100 + 50 × 1)/2700
↓
↓
DFH
E0H
E1H
↓
1
1
1
1
1
1
0
1
1
1
0
0
1
0
0
1
0
0
1
0
0
1
0
1
VDFH V3 + (V4 − V3) × (2100 + 50 × 11)/2700
VE0H V4
VE1H V4 + (V5 − V4) × (50 × 1)/2700
↓
↓
↓
↓
↓
E8H
E9H
↓
1
1
1
1
1
1
0
0
1
1
0
0
0
0
0
1
VE8H V4 + (V5 − V4) × (50 × 8)/2700
VE9H V4 + (V5 − V4) × (400 + 75 × 1)/2700
↓
↓
F4H
F5H
↓
1
1
1
1
1
1
1
1
0
0
1
1
0
0
0
1
VF4H V4 + (V5 − V4) × (400 + 75 × 12)/2700
VF5H V4 + (V5 − V4) × (1300 + 100 × 1)/2700
↓
↓
FCH
FDH
FEH
FFH
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
VFCH V4 + (V5 − V4) × (1300 + 100 × 8)/2700
VFDH V4 + (V5 − V4) × (2100 + 200 × 1)/2700
VFEH V4 + (V5 − V4) × (2100 + 200 × 2)/2700
VFFH V5
10
2002-04-03
T6L76E
● Grayscale Data and Output Voltages
(negative polarity output: V11 < V10 < V9 < V8 < V7 < V6)
Grayscale
Output Voltage (anticipated value)
Dn7 Dn6 Dn5 Dn4 Dn3 Dn2 Dn1 Dn0
Data
00H
01H
02H
↓
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
V00H’ V11
V01H’ V10
V02H’ V10 + (V9 − V10) × (200 × 1)/5200
↓
↓
↓
↓
↓
↓
0CH
0DH
↓
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
1
V0CH’ V10 + (V9 − V10) × (200 × 11)/5200
V0DH’ V10 + (V9 − V10) × (2200 + 175 × 1)/5200
↓
↓
14H
15H
↓
0
0
0
0
0
0
1
1
0
0
1
1
0
0
0
1
V14H’ V10 + (V9 − V10) × (2200 + 175 × 8)/5200
V15H’ V10 + (V9 − V10) × (3600 + 150 × 1)/5200
↓
↓
18H
19H
↓
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
1
V18H’ V10 + (V9 − V10) × (3600 + 150 × 4)/5200
V19H’ V10 + (V9 − V10) × (4200 + 150 × 1)/5200
↓
↓
1CH
1DH
1EH
1FH
20H
21H
↓
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
1
1
1
1
0
0
1
1
1
1
0
0
0
0
1
1
0
0
0
1
0
1
0
1
V1CH’ V10 + (V9 − V10) × (4200 + 150 × 4)/5200
V1DH’ V10 + (V9 − V10) × (4800 + 100 × 1)/5200
V1EH’ V10 + (V9 − V10) × (4800 + 100 × 2)/5200
V1FH’ V10 + (V9 − V10) × (4800 + 100 × 3)/5200
V20H’ V9
V21H’ V9 + (V8 − V9) × (100 × 1)/4000
↓
↓
↓
↓
↓
↓
↓
↓
24H
25H
↓
0
0
0
0
1
1
0
0
0
0
1
1
0
0
0
1
V24H’ V9 + (V8 − V9) × (100 × 4)/4000
V25H’ V9 + (V8 − V9) × (400 + 75 × 1)/4000
↓
↓
34H
35H
↓
0
0
0
0
1
1
1
1
0
0
1
1
0
0
0
1
V34H’ V9 + (V8 − V9) × (400 + 75 × 16)/4000
V35H’ V9 + (V8 − V9) × (1600 + 50 × 1)/4000
↓
↓
3FH
40H
↓
0
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
V3FH’ V9 + (V8 − V9) × (1600 + 50 × 11)/4000
V40H’ V9 + (V8 − V9) × (1600 + 50 × 12)/4000
↓
↓
48H
49H
↓
0
0
1
1
0
0
0
0
1
1
0
0
0
0
0
1
V48H’ V9 + (V8 − V9) × (1600 + 50 × 20)/4000
V49H’ V9 + (V8 − V9) × (2600 + 25 × 1)/4000
↓
↓
5FH
60H
↓
0
0
1
1
0
1
1
0
1
0
1
0
1
0
1
0
V5FH’ V9 + (V8 − V9) × (2600 + 25 × 23)/4000
V60H’ V9 + (V8 − V9) × (2600 + 25 × 24)/4000
↓
↓
7FH
0
1
1
1
1
1
1
1
V7FH’ V9 + (V8 − V9) × (2600 + 25 × 55)/4000
11
2002-04-03
T6L76E
Grayscale
Data
Output Voltage (anticipated value)
Dn7 Dn6 Dn5 Dn4 Dn3 Dn2 Dn1 Dn0
80H
81H
↓
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
V80H’ V8
V81H’ V8 + (V7 − V8) × (25 × 1)/2700
↓
↓
↓
↓
↓
↓
9FH
A0H
↓
1
1
0
0
0
1
1
0
1
0
1
0
1
0
1
0
V9FH’ V8 + (V7 − V8) × (25 × 31)/2700
VA0H’ V8 + (V7 − V8) × (25 × 32)/2700
↓
↓
BFH
C0H
↓
1
1
0
1
1
0
1
0
1
0
1
0
1
0
1
0
VBFH’ V8 + (V7 − V8) × (25 × 63)/2700
VC0H’ V8 + (V7 − V8) × (25 × 64)/2700
↓
↓
D4H
D5H
↓
1
1
1
1
0
0
1
1
0
0
1
1
0
0
0
1
VD4H’ V8 + (V7 − V8) × (25 × 84)/2700
VD5H’ V8 + (V7 − V8) × (2100 + 50 × 1)/2700
↓
↓
DFH
E0H
E1H
↓
1
1
1
1
1
1
0
1
1
1
0
0
1
0
0
1
0
0
1
0
0
1
0
1
VDFH’ V8 + (V7 − V8) × (2100 + 50 × 11)/2700
VE0H’ V7
VE1H’ V7 + (V6 − V7) × (50 × 1)/2700
↓
↓
↓
↓
↓
E8H
E9H
↓
1
1
1
1
1
1
0
0
1
1
0
0
0
0
0
1
VE8H’ V7 + (V6 − V7) × (50 × 8)/2700
VE9H’ V7 + (V6 − V7) × (400 + 75 × 1)/2700
↓
↓
F4H
F5H
↓
1
1
1
1
1
1
1
1
0
0
1
1
0
0
0
1
VF4H’ V7 + (V6 − V7) × (400 + 75 × 12)/2700
VF5H’ V7 + (V6 − V7) × (1300 + 100 × 1)/2700
↓
↓
FCH
FDH
FEH
FFH
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
VFCH’ V7 + (V6 − V7) × (1300 + 100 × 8)/2700
VFDH’ V7 + (V6 − V7) × (2100 + 200 × 1)/2700
VFEH’ V7 + (V6 − V7) × (2100 + 200 × 2)/2700
VFFH’ V6
12
2002-04-03
T6L76E
● LOAD, POL, and output waveforms
CPH
LOAD
POL
OUT
2N-1
OUT
2N
POL
OUT
OUT
2N
2N-1
L
V0 to V5
V6 to V11
V0 to V5
H
V6 to V11
(*) OUT
2N-1
(odd-numbered outputs); OUT (even-numbered outputs)
2N
13
2002-04-03
T6L76E
Timing Diagrams 1
● Start pulse and data sequence
DI/O, DO/I
(input)
0
1
2
3
62
63
64
CPH
(*)
D00 to D07
XOR DINV1
OUT1/
OUT7/
OUT13/
OUT367
OUT373/
OUT7
OUT379/
OUT1
OUT379
OUT373
D10 to D17
XOR DINV1
OUT2/
OUT8/
OUT14/
OUT368
OUT374/
OUT8
OUT380/
OUT2
OUT380
OUT374
D20 to D27
XOR DINV1
OUT3/
OUT9/
OUT15/
OUT369
OUT375/
OUT9
OUT381/
OUT3
OUT381
OUT375
D30 to D37
XOR DINV2
OUT4/
OUT10/
OUT376
OUT16/
OUT370
OUT376/
OUT10
OUT382/
OUT4
OUT382
D40 to D47
XOR DINV2
OUT5/
OUT11/
OUT377
OUT17/
OUT371
OUT377/
OUT11
OUT383/
OUT5
OUT383
D50 to D57
XOR DINV2
OUT6/
OUT12/
OUT378
OUT18/
OUT372
OUT378/
OUT12
OUT384/
OUT6
OUT384
DO/I, DI/O
(output)
(*) Upper stage: OUT1 → U/D = high
Lower stage: OUT379 → U/D = low
14
2002-04-03
T6L76E
Timing Diagrams 2
● Load and cascaded operations
0
1
2
3
4
63
64
0
1
CPH
DI/O
DO/I
Grayscale
data bus
First DATA
Last DATA
First data at
next stage
LOAD
POL
OUT1 to
OUT384
15
2002-04-03
T6L76E
Absolute Maximum Ratings (AV = DV = 0 V)
SS
SS
Characteristics
Analog supply voltage
Symbol
Rating
Unit
AV
DV
−0.3 to 15.0
−0.5 to 6.0
V
V
DD
Digital supply voltage
Reference analog voltage
Digital input voltage
DD
V0 to V11
−0.3 to AV
+ 0.3
V
DD
DD
V
−0.3 to DV
+ 0.3
V
IN
Storage temperature
T
−55 to 125
°C
stg
Recommended Operating Conditions (AV = DV = 0 V)
SS
SS
Characteristics
Analog supply voltage
Symbol
Rating
Unit
Remarks
AV
DV
7.5 to 13.0
3.0 to 3.6
V
V
DD
Digital supply voltage
DD
V0 to V5
0.5 × AV
to AV
− 0.1
DD
DD
Reference analog voltage
V
V6 to V11
0.1 to 0.5 × AV
−20 to 75
DD
Operating temperature
T
°C
OP
Maximum operating frequency
f
37.5 (max)
MHz
CPH
CPH
OUT1 to
OUT384
Output load capacitance
C
L
200
pF/PIN
16
2002-04-03
T6L76E
Electrical Characteristics
DC Characteristics
(AV = 7.5 to 13.0 V, DV = 3.0 to 3.6 V, AV = DV = 0 V, Ta = −20 to 75°C)
DD
DD
SS
SS
Test
Relevant
Pin
Characteristics
Symbol
Test Condition
= 3.3 ± 0.3 V
= 3.3 ± 0.3 V
Min
Typ.
Max
Unit
V
Circuit
0.3 ×
Low level
V
DV
DV
0
IL
DD
DD
DV
DD
Logic
input
Input voltage
0.7 ×
High level
Low level
High level
V
DV
IH
OL
OH
DD
DV
DD
V
I
I
=1 mA
0
0.5
OL
Logic
Output voltage
V
V
DV
output
DD
V
= −1 mA
DV
AV
OH
DD
− 0.5
OUT1 to
OUT384
DD
Output voltage range
VDO
0.2
− 0.2
±20
±15
±10
±15
0 G/S
1 to 31 G/S
32 to 224 G/S
225 to 255 G/S
OUT1 to
OUT384
Output voltage deviation
∆V
(Note 5)
mV
O
Logic
input
Input leakage current
Standby current
I
1
µA
µA
IN
ID
STB
1
20
5
DV
AV
DV
DD
DD
DD
AI
DD
DD
Current consumption
(Note 6)
mA
DI
Note 5: Output voltage after offset correction (Typ. 208 CPH)
Please refer to Page 19 output offset timing chart.
>
AV
DD
− V0 1.0 V
Note 6: CPH = 33 MHz, 1H = 20 µs, no load
17
2002-04-03
T6L76E
AC Characteristics
(AV = 7.5 to 13.0 V, DV = 3.0 to 3.6 V, AV = DV = 0 V, Ta = −20 to 75°C)
DD
DD
SS
SS
Test
Characteristics
Symbol
Test Condition
Min
Typ.
Max
Unit
Circuit
CPH pulse width H
CPH pulse width L
Enable setup time
Enable hold time
Data setup time
Data hold time
t
4
4
4
0
4
0
4
ns
ns
ns
ns
ns
ns
ns
CWH
t
CWL
t
t
sDI
hDI
t
sDD
hDD
t
LOAD setup time
t
sDL
CPH
LOAD high duration
t
2
2
1
wDL
period
CPH
LOAD to enable input duration
LOAD to enable output duration
t
t
sLD1
sLD2
period
CPH
period
t
4
0
ns
ns
ns
POL setup time
sDP
t
POL hold time
hDP
t
C
L
= 25 pF
10.0
Enable output delay time
pdDO
Target output voltage × 0.9
(Note 7)
Target output voltage ± ∆V
t
3.0
µs
µs
Output delay time 1
pdDE
O
t
7.0
Output delay time 2
pdDX1
pdDX2
(Note 7)
CPH
t
208
Output offset correction time
period
Note 7: Output load condition
R = 1 kΩ
C = 40 pF
LCD drive output pin
R
R
R
R
R
C
C
C
C
C
Measured here
•
Output Offset Correction Timing Chart
LOAD
t
pdDX2
5
CPH
0
1
2
3
4
206
207
208
209
210
OUTPUT
t
pdDX1
(*) t
: Output voltage before offset correction (max 7 µs)
pdDX1
pdDX2
t
: Output voltage after offset correction (typ. 208 CPH)
18
2002-04-03
T6L76E
t
t
CWL
CWH
0.7 × DV
DD
CPH
0.3 × DV
DD
DI/O
(input)
0.7 × DV
DD
t
t
hDI
sDI
t
sLD1
0.7 × DV
DD
LOAD
CPH
0.7 × DV
DD
t
t
hDD
sDD
D00 to D57
XOR DINV
0.7 × DV /0.3 × DV
DD
DD
0.7 × DV
0.7 × DV
DD
DD
0.7 × DV
DD
CPH
t
pdDO
t
pdDO
0.7 × DV
0.7 × DV
DD
DD
DO/I
(output)
t
t
sDL
sLD2
0.7 × DV
DD
LOAD
CPH
0.7 × DV
DD
t
wDL
0.7 × DV
0.7 × DV
DD
DD
LOAD
POL
t
t
hDP
sDP
0.7 × DV /0.3 × DV
t
pdDE
DD
DD
OUT1 to
OUT384
t
pdDX1
t
pdDX2
19
2002-04-03
T6L76E
RESTRICTIONS ON PRODUCT USE
000707EBE
• TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor
devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical
stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of
safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of
such TOSHIBA products could cause loss of human life, bodily injury or damage to property.
In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as
set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and
conditions set forth in the “Handling Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability
Handbook” etc..
• The TOSHIBA products listed in this document are intended for usage in general electronics applications
(computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances,
etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires
extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or
bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control instruments, airplane or
spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments,
medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this
document shall be made at the customer’s own risk.
• Polyimide base film is hard and thin. Be careful not to injure yourself on the film or to scratch any other parts with
the film. Try to design and manufacture products so that there is no chance of users touching the film after
assembly, or if they do , that there is no chance of them injuring themselves. When cutting out the film, try to
ensure that the film shavings do not cause accidents. After use, treat the leftover film and reel spacers as
industrial waste.
• Light striking a semiconductor device generates electromotive force due to photoelectric effects. In some cases
this can cause the device to malfunction.
This is especially true for devices in which the surface (back), or side of the chip is exposed. When designing
circuits, make sure that devices are protected against incident light from external sources. Exposure to light both
during regular operation and during inspection must be taken into account.
• The products described in this document are subject to the foreign exchange and foreign trade laws.
• The information contained herein is presented only as a guide for the applications of our products. No
responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other
rights of the third parties which may result from its use. No license is granted by implication or otherwise under
any intellectual property or other rights of TOSHIBA CORPORATION or others.
• The information contained herein is subject to change without notice.
20
2002-04-03
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