XA95144XL-15CSG144I [XILINX]
Flash PLD, 15.5ns, CMOS, PBGA144, CSP-144;
| 型号： | XA95144XL-15CSG144I |
| 厂家： | 
XILINX, INC |
| 描述： | Flash PLD, 15.5ns, CMOS, PBGA144, CSP-144 输入元件 可编程逻辑 |
| 文件： | 总11页 (文件大小：234K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
0
R
XA95144XL Automotive CPLD
0
0
DS600 (v1.1) April 3, 2007
Product Specification
gates with propagation delays of 15.5 ns. See Figure 2 for
overview.
Features
•
AEC-Q100 device qualification and full PPAP support
available in I-grade.
Power Estimation
Power dissipation in CPLDs can vary substantially depend-
ing on the system frequency, design application and output
loading. Each macrocell in an XA9500XL automotive device
must be configured for low-power mode (default mode for
XA9500XL devices). In addition, unused product-terms and
macrocells are automatically deactivated by the software to
further conserve power.
•
Guaranteed to meet full electrical specifications over
TA = -40° C to +85° C (I-grade)
15.5 ns pin-to-pin logic delays
System frequency up to 64.5 MHz
144 macrocells with 3,200 usable gates
Available in the following package
•
•
•
•
-
144-CSP (117 user I/O pins)
For a general estimate of ICC, the following equation may be
used:
-
Pb-free package only
•
Optimized for high-performance 3.3V systems
-
-
Low power operation
5V tolerant I/O pins accept 5V, 3.3V, and 2.5V
signals
3.3V or 2.5V output capability
Advanced 0.35 micron feature size CMOS
Fast FLASH™ technology
I
CC(mA) = MC(0.052*PT + 0.272) + 0.04 * MCTOG * MC * f
where:
MC = # macrocells
-
-
PT = average number product terms per macrocell
f = maximum clock frequency
•
Advanced system features
-
-
In-system programmable
MCTOG = average % of flip-flops toggling per clock
(~12%)
Superior pin-locking and routability with
Fast CONNECT™ II switch matrix
Extra wide 54-input Function Blocks
Up to 90 product-terms per macrocell with
individual product-term allocation
Local clock inversion with three global and one
product-term clocks
Individual output enable per output pin with local
inversion
Input hysteresis on all user and boundary-scan pin
inputs
This calculation was derived from laboratory measurements
of an XA9500XL part filled with 16-bit counters and allowing
a single output (the LSB) to be enabled. The actual ICC
value varies with the design application and should be veri-
fied during normal system operation. Figure 1 shows the
above estimation in a graphical form. For a more detailed
discussion of power consumption in this device, see Xilinx
application note XAPP114, “Understanding XC9500XL
CPLD Power.”
-
-
-
-
-
-
-
Bus-hold circuitry on all user pin inputs
Full IEEE Standard 1149.1 boundary-scan (JTAG)
150
•
•
•
•
Fast concurrent programming
Slew rate control on individual outputs
Enhanced data security features
Excellent quality and reliability
100
64.4 MHz
50
0
-
Endurance exceeding 10,000 program/erase
cycles
-
-
20 year data retention
ESD protection exceeding 2,000V
100
DS600_01_121106
50
Clock Frequency (MHz)
Figure 1: Typical ICC vs. Frequency for XA95144XL
WARNING: Programming temperature range of
TA = 0° C to +70° C
Description
The XA95144XL is a 3.3V CPLD targeted for high-perfor-
mance, low-voltage automotive applications. It is comprised
of eight 54V18 Function Blocks, providing 3,200 usable
© 2007 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS600 (v1.1) April 3, 2007
www.xilinx.com
1
Product Specification
R
XA95144XL Automotive CPLD
3
JTAG
In-System Programming Controller
1
JTAG Port
Controller
54
Function
18
18
18
18
Block 1
I/O
Macrocells
1 to 18
I/O
I/O
I/O
54
54
54
Function
Block 2
Macrocells
1 to 18
I/O
Blocks
I/O
I/O
Function
Block 3
Macrocells
1 to 18
I/O
I/O
3
I/O/GCK
I/O/GSR
I/O/GTS
Function
Block 4
1
4
Macrocells
1 to 18
54
Function
Block 8
18
Macrocells
1 to 18
DS056_02_101300
Figure 2: XA95144XL Architecture
Function Block outputs (indicated by the bold line) drive the I/O Blocks directly.
2
www.xilinx.com
DS600 (v1.1) April 3, 2007
Product Specification
R
XA95144XL Automotive CPLD
(1,3)
Absolute Maximum Ratings
Symbol
Description
Value
–0.5 to 4.0
–0.5 to 5.5
–0.5 to 5.5
–65 to +150
+125
Units
V
VCC
VIN
Supply voltage relative to GND
Input voltage relative to GND(2)
Voltage applied to 3-state output(2)
Storage temperature (ambient)(4)
Junction temperature
V
VTS
TSTG
TJ
V
oC
oC
Notes:
1. All automotive customers are required to set the Macrocell Power Setting to low, and set Logic Optimization to density.
2. Maximum DC undershoot below GND must be limited to either 0.5V or 10 mA, whichever is easier to achieve. During transitions, the
device pins may undershoot to –2.0 V or overshoot to +7.0V, provided this over- or undershoot lasts less than 10 ns and with the
forcing current being limited to 200 mA. External I/O voltage may not exceed VCCINT by 4.0V.
3. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions
is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability.
4. For soldering guidelines and thermal considerations, see the Device Packaging information on the Xilinx website. For Pb-free
packages, see XAPP427.
Recommended Operation Conditions
Symbol
TA
Parameter
Min
–40
3.0
3.0
2.3
0
Max
+85
3.6
Units
oC
V
Ambient temperature
VCCINT
Supply voltage for internal logic and input buffers
Supply voltage for output drivers for 3.3V operation
Supply voltage for output drivers for 2.5V operation
Low-level input voltage
3.6
V
VCCIO
2.7
V
VIL
VIH
VO
0.80
5.5
V
High-level input voltage
2.0
0
V
Output voltage
VCCIO
V
Quality and Reliability Characteristics
Symbol
Parameter
Min
20
Max
Units
TDR
Data Retention
-
-
-
Years
Cycles
Volts
NPE
Program/Erase Cycles (Endurance) @ TA = 70°
Electrostatic Discharge (ESD)
10,000
2,000
VESD
DC Characteristic Over Recommended Operating Conditions
Symbol
Parameter
Test Conditions
IOH = –4.0 mA
OH = –500 μA
IOL = 8.0 mA
OL = 500 μA
Min
Max
Units
V
Output high voltage for 3.3V outputs
Output high voltage for 2.5V outputs
Output low voltage for 3.3V outputs
Output low voltage for 2.5V outputs
Input leakage current
2.4
-
VOH
I
90% VCCIO
-
V
-
-
-
-
0.4
0.4
±10
±10
V
VOL
I
V
IIL
VCC = Max; VIN = GND or VCC
VCC = Max; VIN = GND or VCC
μA
μA
IIH
I/O high-Z leakage current
DS600 (v1.1) April 3, 2007
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3
Product Specification
R
XA95144XL Automotive CPLD
Symbol
Parameter
Test Conditions
Min
Max
Units
I/O high-Z leakage current
VCC = Max; VCCIO = Max;
-
±10
μA
VIN = GND or 3.6V
IIH
V
CC Min < VIN < 5.5V
-
-
±50
10
μA
pF
CIN
ICC
I/O capacitance
VIN = GND; f = 1.0 MHz
Operating supply current
(low power mode, active)
VIN = GND, No load; f = 1.0 MHz
45 (Typical)
mA
AC Characteristics
XA95144XL-15
Symbol
Parameter
Min
Max
Units
TPD
TSU
I/O to output valid
I/O setup time before GCK
-
15.5
ns
ns
ns
ns
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
12.0
-
TH
I/O hold time after GCK
GCK to output valid
0
-
-
5.8
64.5
-
TCO
fSYSTEM
TPSU
TPH
Multiple FB internal operating frequency
I/O setup time before p-term clock input
I/O hold time after p-term clock input
P-term clock output valid
-
7.6
0.0
-
-
TPCO
TOE
10.2
7.0
7.0
11.0
11.0
14.5
15.3
-
GTS to output valid
-
TOD
GTS to output disable
-
TPOE
TPOD
TAO
Product term OE to output enabled
Product term OE to output disabled
GSR to output valid
-
-
-
TPAO
TWLH
TAPRPW
TPLH
TSUEC
THEC
P-term S/R to output valid
-
GCK pulse width (High or Low)
Asynchronous preset/reset pulse width (High or Low)
P-term clock pulse width (High or Low)
Clock enable setup
4.5
7.0
7.0
6.5
0
-
-
-
Clock enable hold
-
V
TEST
R
1
2
Output Type
V
V
R
R
C
L
CCIO
TEST
1
2
Device Output
3.3V
2.5V
3.3V
2.5V
320 Ω
250 Ω
360 Ω
660 Ω
35 pF
35 pF
C
L
R
DS058_03_081500
Figure 3: AC Load Circuit
4
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DS600 (v1.1) April 3, 2007
Product Specification
R
XA95144XL Automotive CPLD
Internal Timing Parameters
XA95144XL-15
Symbol
Parameter
Min
Max
Units
Buffer Delays
TIN
Input buffer delay
GCK buffer delay
GSR buffer delay
GTS buffer delay
Output buffer delay
-
-
-
-
-
-
3.5
1.8
4.5
7.0
3.0
0
ns
ns
ns
ns
ns
ns
TGCK
TGSR
TGTS
TOUT
TEN
Output buffer enable/disable delay
Product Term Control Delays
TPTCK
TPTSR
TPTTS
Product term clock delay
-
-
-
2.7
1.8
7.5
ns
ns
ns
Product term set/reset delay
Product term 3-state delay
Internal Register and Combinatorial Delays
TPDI
TSUI
Combinatorial logic propagation delay
Register setup time
-
3.0
3.5
3.0
3.5
-
1.7
ns
ns
ns
ns
ns
ns
ns
ns
ns
-
-
THI
Register hold time
TECSU
TECHO
TCOI
TAOI
Register clock enable setup time
Register clock enable hold time
Register clock to output valid time
Register async. S/R to output delay
Register async. S/R recover before clock
Internal logic delay
-
-
1.0
7.0
-
-
TRAI
10.0
-
TLOGI
7.3
Feedback Delays
TF
Time Adders
TPTA
Fast CONNECT II feedback delay
-
4.2
ns
Incremental product term allocator delay
Slew-rate limited delay
-
-
1.0
4.5
ns
ns
TSLEW
DS600 (v1.1) April 3, 2007
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5
Product Specification
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XA95144XL Automotive CPLD
XA95144XL I/O Pins
Function
Block
BScan
Order
Function
Block
BScan
Order
Macrocell
1
CSG144
H3
F1
Macrocell
CSG144
M3
L1(1)
K4
N4
L2
L3
L5
N2(1)
N3
N5
M4
K5
-
1
429
426
423
420
417
414
411
408
405
402
399
396
393
390
387
384
381
378
375
372
369
366
363
360
357
354
351
348
345
342
339
336
333
330
327
324
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
1
2(1)
3
321
318
315
312
309
306
303
300
297
294
291
288
285
282
279
276
273
270
267
264
261
258
255
252
249
246
243
240
237
234
231
228
225
222
219
216
1
2
1
3
G2
J1
1
4
4
1
5
G3
G4
-
5
1
6
6
1
7
7
8(1)
1
8
H1
H2
K3
H4
J2
1
9
9
1
10
11
12
13
14
15
16
17(1)
18
1
10
11
12
13
14
15
16
17
18
1
1
1
1
-
1
J3
K6
L6
-
1
J4
1
M1
K2(1)
-
1
M6
-
1
2
C3
A2(1)
-
C9
A7
A5
-
2
2(1)
2
2
3
3
2
4
C1
B1(1)
C2(1)
-
D4(1)
D3(1)
D2
E4
E3
E1
E2
F4
4
2
5(1)
6(1)
7
5
D7
A6
-
2
6
2
7
2
8(1)
9(1)
10
11
12
13
14
15
16
17
18
8
B6
C6
C5
D6
B5
A4
D5
B4
C4
A3
-
2
9
2
10
11
12
13
14
15
16
17
18
2
2
2
2
2
2
F3
2
F2
2
-
Notes:
1. Global control pin.
6
www.xilinx.com
DS600 (v1.1) April 3, 2007
Product Specification
R
XA95144XL Automotive CPLD
XA95144XL (Continued)
Function
Block
BScan
Order
Function
Block
BScan
Macrocell
CS144
-
Macrocell
CS144
-
Order
105
102
99
96
93
90
87
84
81
78
75
72
69
66
63
60
57
54
51
48
45
42
39
36
33
30
27
24
21
18
15
12
9
5
1
2
213
210
207
204
201
198
195
192
189
186
183
180
177
174
171
168
165
162
159
156
153
150
147
144
141
138
135
132
129
126
123
120
117
114
111
108
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
1
2
5
N6
L8
N12
L12
-
5
3
3
5
4
-
4
5
5
M7
N7
M10
K7
N8
N11
M8
K8
L11
N9
K9
-
5
M13
L13
K10
K11
K13
K12
J11
H10
J10
H11
H12
J12
H13
-
5
6
6
5
7
7
5
8
8
5
9
9
5
10
11
12
13
14
15
16
17
18
1
10
11
12
13
14
15
16
17
18
1
5
5
5
5
5
5
5
M11
-
5
6
-
-
6
2
C11
-
2
G11
F11
E13
G10
F13
-
6
3
3
6
4
B11
A12
A11
-
4
6
5
5
6
6
6
6
7
7
6
8
D10
A10
B10
B9
A9
-
8
F12
F10
D13
E12
E10
D11
D12
C13
B13
C12
-
6
9
9
6
10
11
12
13
14
15
16
17
18
10
11
12
13
14
15
16
17
18
6
6
6
6
D8
A8
D9
B7
-
6
6
6
6
3
6
0
DS600 (v1.1) April 3, 2007
www.xilinx.com
7
Product Specification
R
XA95144XL Automotive CPLD
XA95144XL Global, JTAG and Power Pins
Pin Type
I/O/GCK1
I/O/GCK2
I/O/GCK3
I/O/GTS1
I/O/GTS2
I/O/GTS3
I/O/GTS4
I/O/GSR
TCK
CSG144
K2
L1
N2
D4
D3
B1
C2
A2
L10
TDI
L9
TDO
C8
TMS
N10
V
CCINT 3.3V
B3, D1, J13, L4
V
CCIO 2.5V/3.3V
GND
A1, A13, C7, L7, N1, N13
B2, B8, B12, C10, E11, G1, G12, G13, K1, M2, M5, M9, M12
–
No Connects
8
www.xilinx.com
DS600 (v1.1) April 3, 2007
Product Specification
R
XA95144XL Automotive CPLD
Device Part Marking and Ordering Combination Information.
R
Device Type
Package
XA95144XL
CSG144
This line not
related to device
part number
15I
Speed
Operating Range
1
Sample package with part marking.
Speed
Device Ordering and
(pin-to-pin
delay)
Pkg.
Symbol
No. of
Pins
Operating
Range(1)
Part Marking Number
XA95144XL-15CSG144I
Notes:
Package Type
Chip Scale Package (CSP); Pb-free
15.5 ns
CSG144 144-ball
I
1. I-Grade: TA = –40° to +85°C
-15 CS
G
144
I
XA95144XL
Example:
Device
Speed Grade
Package Type
-Free
Pb
Number of Pins
Temperature Range
XA9500XL Automotive Requirements and Recommendations
I/O pins should be appropriately terminated with
keeper/bus-hold. Unused I/Os can also be configured
as CGND (programmable GND).
Requirements
The following requirements are for all automotive applica-
tions:
4. Do not drive I/O pins without VCC/VCCIO powered.
1. All automotive customers are required to keep the
Macrocell Power selection set to low, and the Logic
Optimization set to density when designing with ISE
software. These are the default settings when
XA9500XL devices are selected for design. These
settings are found on the Process Properties page for
Implement Design. See the ISE Online Help for details
on these properties.
5. Sink current when driving LEDs. Because all Xilinx
CPLDs have N-channel pull-down transistors on
outputs, it is required that an LED anode is sourced
through a resistor externally to VCC. Consequently, this
will give the brightest solution.
6. Avoid external pull-down resistors. Always use external
pull-up resistors if external termination is required. This
is because the XA9500XL Automotive CPLD, which
includes some I/O driving circuits beyond the input and
output buffers, may have contention with external
pull-down resistors, and, consequently, the I/O will not
switch as expected.
2. Use a monotonic, fast ramp power supply to power up
XA9500XL . A VCC ramp time of less than 1 ms is
required.
3. Do not float I/O pins during device operation. Floating
I/O pins can increase ICC as input buffers will draw
1-2 mA per floating input. In addition, when I/O pins are
floated, noise can propagate to the center of the CPLD.
7. Do not drive I/Os pins above the VCCIO assigned to its
I/O bank.
DS600 (v1.1) April 3, 2007
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9
Product Specification
R
XA95144XL Automotive CPLD
a. The current flow can go into VCCIO and affect a user
voltage regulator.
internals with INTEST, identifying stuck pins, and
inspecting programming patterns (if not secured).
b. It can also increase undesired leakage current
associated with the device.
3. XA9500XL Automotive CPLDs work with any power
sequence, but it is preferable to power the VCCI
(internal VCC) before the VCCIO for the applications in
which any glitches from device I/Os are unwanted.
c. If done for too long, it can reduce the life of the
device.
4. Do not disregard report file warnings. Software
identifies potential problems when compiling, so the
report file is worth inspecting to see exactly how your
design is mapped onto the logic.
8. Do not rely on the I/O states before the CPLD
configures.
9. Use a voltage regulator which can provide sufficient
current during device power up. As a rule of thumb, the
regulator needs to provide at least three times the peak
current while powering up a CPLD in order to guarantee
the CPLD can configure successfully.
5. Understand the Timing Report. This report file provides
a speed summary along with warnings. Read the timing
file (*.tim) carefully. Analyze key signal chains to
determine limits to given clock(s) based on logic
analysis.
10. Ensure external JTAG terminations for TMS, TCK, TDI,
TDO comply with IEEE 1149.1. All Xilinx CPLDs have
internal weak pull-ups of ~50 kΩ on TDI, TMS, and
TCK.
6. Review Fitter Report equations. Equations can be
shown in ABEL-like format, or can also be displayed in
Verilog or VHDL formats. The Fitter Report also
includes switch settings that are very informative of
other device behaviors.
11. Attach all CPLD VCC and GND pins in order to have
necessary power and ground supplies around the
CPLD.
7. Let design software define pinouts if possible. Xilinx
CPLD software works best when it selects the I/O pins
and manages resources for users. It can spread signals
around and improve pin-locking. If users must define
pins, plan resources in advance.
12. Decouple all VCC and VCCIO pins with capacitors of
0.01 μF and 0.1 μF closest to the pins for each
VCC/VCCIO-GND pair.
Recommendations
8. Perform a post-fit simulation for all speeds to identify
any possible problems (such as race conditions) that
might occur when fast-speed silicon is used instead of
slow-speed silicon.
The following recommendations are for all automotive appli-
cations.
1. Use strict synchronous design (only one clocking event)
if possible. A synchronous system is more robust than
an asynchronous one.
9. Distribute SSOs (Simultaneously Switching Outputs)
evenly around the CPLD to reduce switching noise.
2. Include JTAG stakes on the PCB. JTAG stakes can be
used to test the part on the PCB. They add benefit in
reprogramming part on the PCB, inspecting chip
10. Terminate high speed outputs to eliminate noise caused
by very fast rising/falling edges.
10
www.xilinx.com
DS600 (v1.1) April 3, 2007
Product Specification
R
XA95144XL Automotive CPLD
Warranty Disclaimer
THIS WARRANTY DOES NOT EXTEND TO ANY IMPLEMENTATION IN AN APPLICATION OR ENVIRONMENT THAT IS
NOT CONTAINED WITHIN XILINX SPECIFICATIONS. PRODUCTS ARE NOT DESIGNED TO BE FAIL-SAFE AND ARE
NOT WARRANTED FOR USE IN THE DEPLOYMENT OF AIRBAGS. FURTHER, PRODUCTS ARE NOT WARRANTED
FOR USE IN APPLICATIONS THAT AFFECT CONTROL OF THE VEHICLE UNLESS THERE IS A FAIL-SAFE OR
REDUNDANCY FEATURE AND ALSO A WARNING SIGNAL TO THE OPERATOR OF THE VEHICLE UPON FAILURE.
USE OF PRODUCTS IN SUCH APPLICATIONS IS FULLY AT THE RISK OF CUSTOMER SUBJECT TO APPLICABLE
LAWS AND REGULATIONS GOVERNING LIMITATIONS ON PRODUCT LIABILITY.
Further Reading
The following Xilinx links go to relevant XC9500XL CPLD documentation, including XAPP111, Using the XC9500XL Timing
Model, and XAPP784, Bulletproof CPLD Design Practices. Simply click on the link and scroll down.
Data Sheets, Application Notes, and White Papers.
Packaging
Revision History
The following table shows the revision history for this document.
Date
Version
1.0
Revision
01/12/07
04/03/07
Initial Release.
1.1
Add programming temperature range warning on page 1.
DS600 (v1.1) April 3, 2007
www.xilinx.com
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Product Specification
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