E-L6258E中文资料_数据手册_规格书

L6258E

PWM CONTROLLED - HIGH CURRENT

DMOS UNIVERSAL MOTOR DRIVER

NOT FOR NEW DESIGN

Figure 1. Package

1 FEATURES

■ ABLE TO DRIVE BOTH WINDINGS OF A

BIPOLAR STEPPER MOTOR OR TWO DC

MOTORS

■ OUTPUT CURRENT UP TO 1.2A EACH

WINDING

PowerSO36

■ WIDE VOLTAGE RANGE: 12V TO 40V

■ FOUR QUADRANT CURRENT CONTROL,

IDEAL FOR MICROSTEPPING AND DC

MOTOR CONTROL

■ PRECISION PWM CONTROL

■ NO NEED FOR RECIRCULATION DIODES

■ TTL/CMOS COMPATIBLE INPUTS

■ CROSS CONDUCTION PROTECTION

■ THERMAL SHUTDOW

Table 1. Order Codes

Part Number

Package

L6258E

(Replaced by L6258EX)

PowerSO36

plete control and drive circuit. It has high efficiency

phase shift chopping that allows a very low current

ripple at the lowest current control levels, and makes

this device ideal for steppers as well as for DC mo-

tors.The power stage is a dual DMOS full bridge ca-

pable of sustaining up to 40V, and includes the

diodes for current recirculation.The output current ca-

pability is 1.2A per winding in continuous mode, with

peak start-up current up to 1.5A. A thermal protection

circuitry disables the outputs if the chip temperature

exceeds the safe limits.

2 DESCRIPTION

L6258E is a dual full bridge for motor control applica-

tions realized in BCD technology, with the capability

of driving both windings of a bipolar stepper motor or

bidirectionally control two DC motors.

L6258E and a few external components form a com-

Figure 2. Block Diagram

R₁1M

R_C1

C_C1

C_BOOT

VS

C_P

VCP2

EA_IN1

EA_OUT1

VBOOT

TRI_0

+

VCP1

OUT1A

CHARGE

PUMP

C

ERROR

AMP

-

POWER

BRIDGE

1

V_R

+

-

VREF1

I3_1

+

-

OUT1B

INPUT

&

TRI_180

C

SENSE1B

SENSE

AMP

I2_1

DAC

VR GEN

DAC

R_s

I1_1

I0_1

PH_1

SENSE1A

DISABLE

THERMAL

PROT.

V_DD(5V)

V_R(V_DD/2)

VS

VREF1

I3_2

ERROR

AMP

TRI_0

V_R

+

-

OUT2A

INPUT

&

SENSE

AMP

+

-

C

I2_2

POWER

BRIDGE

2

I1_2

+

-

OUT2B

I0_2

SENSE2B

PH_2

TRI_180

R_s

TRI_CAP

C_FREF

TRI_0

TRIANGLE

GENERATOR

TRI_180

SENSE2A

GND

EA_IN2

EA_OUT2

D96IN430D

R_C2

C_C2

R₂1M

Rev. 7

1/24

September 2004

L6258E

Table 2. Absolute Maximum Ratings

Symbol

Parameter

Value

45

Unit

V

s

Supply Voltage

V

Logic Supply Voltage

Reference Voltage

7

V

DD

V

/V

2.5

V

ref1 ref2

I

Output Current (peak)

Output Current (continuous)

Logic Input Voltage Range

Bootstrap Supply

1.5

A

O

1.2

A

V

-0.3 to 7

60

V

in

V

boot

V

- V

Maximum Vgate applicable

Junction Temperature

Storage Temperature Range

15

V

boot

s

T

150

°C

j

T

-55 to 150

stg

Figure 3. Pin Connection (Top view)

PWR_GND

PH_1

1

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

20

19

PWR_GND

2

SENSE1

OUT1B

I3_1

3

I1_1

4

I0_1

5

I2_1

OUT1A

DISABLE

TRI_CAP

V_DD

6

VS

7

EA_OUT1

EA_IN1

VREF1

SIG_GND

VREF2

EA_IN2

EA_OUT2

I2_2

8

9

GND

10

11

12

13

14

15

16

17

18

VCP1

VCP2

VBOOT

VS

OUT2A

I0_2

I3_2

OUT2B

SENSE2

PWR_GND

I1_2

PH_2

PWR_GND

D96IN432E

2/24

L6258E

Table 3. Pins Function

Pin #

1, 36

2, 17

Name

Description

PWR_GND

PH_1, PH_2

Ground connection (1). They also conduct heat from die to printed circuit copper.

These TTL compatible logic inputs set the direction of current flow through the load. A

high level causes current to flow from OUTPUT A to OUTPUT B.

3

I

Logic input of the internal DAC (1). The output voltage of the DAC is a percentage of the

Vref voltage applied according to the thruth table of page 7

1_1

4

5

6

I

See pin 3

0_1

OUT1A

Bridge output connection (1)

DISABLE

Disables the bridges for additional safety during switching. When not connected the

bridges are enabled

7

TRI_cap

Triangular wave generation circuit capacitor. The value of this capacitor defines the output

switching frequency

8

9

V_DD(5V)

GND

Supply Voltage Input for logic circuitry

Power Ground connection of the internal charge pump circuit

Charge pump oscillator output

10

V

CP1

CP2

11

Input for external charge pump capacitor

Overvoltage input for driving of the upper DMOS

Supply voltage input for output stage. They are shorted internally

Bridge output connection (2)

12

V

BOOT

13, 31

14

V

S

OUT2A

15

I

Logic input of the internal DAC (2). The output voltage of the DAC is a percentage of the

VRef voltage applied according to the truth table of page 7

0_2

16

I

See pin 15

1_2

18, 19

20, 35

PWR_GND

Ground connection. They also conduct heat from die to printed circuit copper

Negative input of the transconductance input amplifier (2, 1)

SENSE2,

SENSE1

21

22

OUT2B

Bridge output connection and positive input of the tranconductance (2)

I

See pin 15

3_2

23

See pin 15

2_2

24

EA_OUT_2

EA_IN_2

Error amplifier output (2)

Negative input of error amplifier (2)

25

26, 28

V

, V

Reference voltages for the internal DACs, determining the output current value. Output

current also depends on the logic inputs of the DAC and on the sensing resistor value

REF2

REF1

27

29

30

32

33

34

SIG_GND

EA_IN_1

Signal ground connection

Negative input of error amplifier (1)

EA_OUT_1

Error amplifier output (1)

I

See pin 3

2_1

See pin 3

3_1

OUT1B

Bridge output connection and positive input of the tranconductance (1)

Note: The number in parenthesis shows the relevant Power Bridge of the circuit. Pins 18, 19, 1 and 36 are connected together.

3/24

L6258E

Figure 4. Thermal Characteristics

Power Dissipated T Ambient Thermal J-A resistance

Conditions

(W)

(˚C)

(˚C/W)

5.3

70

15

pad layout + ground layers + 16 via hol

PCB ref.: 4 LAYER cm 12 x 12

4.0

2.3

70

20

35

pad layout + ground layers

PCB ref.: 4 LAYER cm 12 x 12

pad layout + 6cm2 on board heat sink

PCB ref.: 2 LAYER cm 12 x 12

D02IN1370

12

10

8

15˚C/W

20˚C/W

6

4

2

0

35˚C/W

0

20

40

60

80

100

120

140

160

D02IN1371

Ambient Temperature (˚C)

4/24

L6258E

Table 4. Electrical Characteristics (V_S= 40V; V_DD= 5V; T_j= 25°; unless otherwise specified.)

Symbol

Parameter

Supply Voltage

Test Condition

Min.

12

Typ.

Max.

40

Unit

V

S

V

Logic Supply Voltage

Storage Voltage

4.75

5.25

V

DD

V

V = 12 to 40V

V +6

S

V +12

S

V

BOOT

Sense

S

V

Max Drop Across Sense Resistor

Power off Reset

1.25

7.2

4.1

15

V

Off Threshold

6

V

S(off)

V

Power off Reset

Off Threshold

3.3

V

DD(off)

I

VS Quiescent Current

VDD Operative Current

Shut Down Hysteresis

Thermal shutdown

Both bridges ON, No Load

Both bridges OFF

mA

°C

KHz

S(on)

S(off)

I

7

I

15

DD

∆T

25

150

15

SD-H

T

SD

f

Triangular Oscillator Frequency

C = 1nF

FREF

12.5

18.5

osc

(*)

TRANSISTORS

I

Leakage Current

On Resistance

OFF State

ON State

If =1.0A

500

0.75

1.4

µA

Ω

DSS

R

0.6

1

ds(on)

V

Flywheel diode Voltage

V

f

CONTROL LOGIC

V

lnput Voltage

All Inputs

2

0

V

in(H)

DD

V

Input Voltage

0.8

+10

+150

2.5

in(L)

I

in

Input Current (Note 1)

Disable Pin Input Current

Reference Voltage

0 < V < 5V

-150

-10

0

µA

V

in

I

dis

V

/

operating

ref1 ref2

I

ref

V

Terminal Input Current

V

= 1.25

-2

5

µA

ref

FI =

PWM Loop Transfer Ratio

2

V_ref/V_sense

V

DAC Full Scale Precision

Current Loop Offset

DAC Factor Ratio

V

= 2.5V I /I /I /I = L

1.23

-30

-2

1.34

+30

+2

V

mV

%

FS

ref

0 1 2 3

V

offset

= 2.5V I /I /I /I = H

0 1 2 3

Normalized @ Full scale Value

SENSE AMPLIFIER

V

cm

lnput Common Mode Voltage

Range

-0.7

V +0.7

S

V

I

Input Bias

sense1/sense2

Open Loop

-200

0

µA

inp

ERROR AMPLIFIER

G

Open Loop Voltage Gain

Output Slew Rate

70

0.2

400

dB

V/µs

kHz

V

SR

GBW

Gain Bandwidth Product

Note 1: This is true for all the logic inputs except the disable input.

(*) Chopping frequency is twice fosc value.

5/24

L6258E

3 FUNCTIONAL DESCRIPTION

The circuit is intended to drive both windings of a bipolar stepper motor or two DC motors.

The current control is generated through a switch mode regulation.

With this system the direction and the amplitude of the load current are depending on the relation of phase and

duty cycle between the two outputs of the current control loop.

The L6258E power stage is composed by power DMOS in bridge configuration as it is shown in figure 5, where

the bridge outputs OUT_A and OUT_B are driven to V with an high level at the inputs IN_A and IN_B while are

s

driven to ground with a low level at the same inputs .

The zero current condition is obtained by driving the two half bridge using signals IN_A and IN_B with the same

phase and 50% of duty cycle.

In this case the outputs of the two half bridges are continuously switched between power supply (V ) and

s

ground, but keeping the differential voltage across the load equal to zero.

In figure 5A is shown the timing diagram of the two outputs and the load current for this working condition.

Following we consider positive the current flowing into the load with a direction from OUT_A to OUT_B, while

we consider negative the current flowing into load with a direction from OUT_B to OUT_A.

Now just increasing the duty cycle of the IN_A signal and decreasing the duty cycle of IN_B signal we drive pos-

itive current into the load.

In this way the two outputs are not in phase, and the current can flow into the load trough the diagonal bridge

formed by T1 and T4 when the output OUT_A is driven to V and the output OUT_B is driven to ground, while

s

there will be a current recirculation into the higher side of the bridge, through T1 and T2, when both the outputs

are at Vs and a current recirculation into the lower side of the bridge, through T3 and T4, when both the outputs

are connected to ground.

Since the voltage applied to the load for recirculation is low, the resulting current discharge time constant is high-

er than the current charging time constant during the period in which the current flows into the load through the

diagonal bridge formed by T1 and T4. In this way the load current will be positive with an average amplitude

depending on the difference in duty cycle of the two driving signals.

In figure 5B is shown the timing diagram in the case of positive load current

On the contrary, if we want to drive negative current into the load is necessary to decrease the duty cycle of the

IN_A signal and increase the duty cycle of the IN_B signal. In this way we obtain a phase shift between the two

outputs such to have current flowing into the diagonal bridge formed by T2 and T3 when the output OUT_A is

driven to ground and output OUT_B is driven to Vs, while we will have the same current recirculation conditions

of the previous case when both the outputs are driven to Vs or to ground.

So, in this case the load current will be negative with an average amplitude always depending by the difference

in duty cycle of the two driving signals.

In figure 5C is shown the timing diagram in the case of negative load current .

Figure 6 shows the device block diagram of the complete current control loop.

3.1 Reference Voltage

The voltage applied to VREF pin is the reference for the internal DAC and, together with the sense resistor val-

ue, defines the maximum current into the motor winding according to the following relation:

V

0.5 V

1

FI

REF

----- --------------

I

= -------------------------- =

MAX

R

S

R

S

where R = sense resistor value

s

6/24

L6258E

Figure 5. Power Bridge Configuration

V_S

IN_A

IN_B

T1

OUT_A

T2

LOAD

OUT_B

T3

T4

OUTA

OUTB

Iload

Fig. 1A

Fig. 1B

Fig. 1C

0

OUTA

OUTB

Iload

0

OUTA

OUTB

0

Iload

D97IN624

7/24

L6258E

Figure 6. Current Control Loop Block Diagram

POWER AMPL.

VS

OUTA

LOAD

R_L

-

Tri_0

INPUT TRANSCONDUCTANCE

+

ERROR AMPL.

AMPL.

L_L

V_R

VS

+

-

ia

VREF

R_S

-

I0

I1

ic

+

-

Tri_180

DAC

VDAC

I2

OUTB

Rc

Cc

I3

PH

ib

Gin=1/Ra

-

VSENSE

+

D97IN625

Gs=1/Rb

SENSE TRANSCONDUCTANCE

AMPL.

3.2 Input Logic (I₀- I₁- I₂- I₃)

The current level in the motor winding is selected according to this table:

Table 5.

Current level

% of IMAX

I3

I2

I1

I0

H

L

H

L

H

L

H

L

No Current

9.5

H

L

19.1

28.6

38.1

47.6

55.6

63.5

71.4

77.8

82.5

88.9

92.1

95.2

98.4

100

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

8/24

L6258E

3.3 Phase Input ( PH )

The logic level applied to this input determines the direction of the current flowing in the winding of the motor.

High level on the phase input causes the motor current flowing from OUT_A to OUT_B through the load.

3.4 Triangular Generator

This circuit generates the two triangular waves TRI_0 and TRI_180 internally used to generate the duty cycle

variation of the signals driving the output stage in bridge configuration.

The frequency of the triangular wave defines the switching frequency of the output, and can be adjusted by changing

the capacitor connected at TR1_CAP pin :

K

C

F

= ---

ref

-5

where : K = 1.5 x 10

3.5 Charge Pump Circuit

To ensure the correct driving of the high side drivers a voltage higher than Vs is supplied on the Vboot pin. This

boostrap voltage is not needed for the low side power DMOS transistors because their sources terminals are

grounded. To produce this voltage a charge pump method is used. It is made by using two external capacitors;

one connected to the internal oscillator (CP) and the other (Cboot) to storage the overvoltage needed for the

driving the gates of the high side DMOS. The value suggested for the capacitors are:

Table 6.

C

Storage Capacitor

PumpCapacitor

100

10

nF

boot

C

P

3.6 Current Control LOOP

The current control loop is a transconductance amplifier working in PWM mode.

The motor current is a function of the programmed DAC voltage.

To keep under control the output current, the current control modulates the duty cycle of the two outputs OUT_A

and OUT_B, and a sensing resistor Rs is connected in series with the motor winding in order to produce a volt-

age feedback compared with the programmed voltage of the DAC .

The duty cycle modulation of the two outputs is generated comparing the voltage at the outputs of the error am-

plifier, with the two triangular wave references .

In order to drive the output bridge with the duty cycle modulation explained before, the signals driving each out-

put ( OUTA & OUTB ) are generated by the use of the two comparators having as reference two triangular wave

signals Tri_0 and Tri_180 of the same amplitude, the same average value (in our case Vr), but with a 180° of

phase shift each other.

The two triangular wave references are respectively applied to the inverting input of the first comparator and to

the non inverting input of the second comparator .

The other two inputs of the comparators are connected together to the error amplifier output voltage resulting

by the difference between the programmed DAC. The reset of the comparison between the mentioned signals

is shown in fig. 7.

9/24

L6258E

Figure 7. Output comparator waveforms

Tri_0

Error Ampl.

Output

Tri_180

First Comp.

Output

Second Comp.

Output

In the case of V

equal to zero, the transconductance loop is balanced at the value of Vr, so the outputs of

DAC

the two comparators are signals having the same phase and 50% of duty cycle .

As we have already mentioned, in this situation, the two outputs OUT_A and OUT_B are simultaneously driven

from V to ground ; and the differential voltage across the load in this case is zero and no current flows in the

s

motor winding.

With a positive differential voltage on V

respected Vr.

(see Fig 6, the transconductance loop will be positively unbalanced

DAC

In this case being the error amplifier output voltage greater than Vr, the output of the first comparator is a square

wave with a duty cycle higher than 50%, while the output of the second comparator is a square wave with a duty

cycle lower than 50%.

The variation in duty cycle obtained at the outputs of the two comparators is the same, but one is positive and

the other is negative with respect to the 50% level.

The two driving signals, generated in this case, drive the two outputs in such a way to have switched current

flowing from OUT_A through the motor winding to OUT_B.

With a negative differential voltage V_DAC, the transconductance loop will be negatively unbalanced respected Vr.

In this case the output of the first comparator is a square wave with a duty cycle lower than 50%, while the output

of the second comparator is a square wave with a duty cycle higher than 50%.

The variation in the duty cycle obtained at the outputs of the two comparators is always of the same.

The two driving signals, generated in this case, drive the the two outputs in order to have the switched current

flowing from OUT_B through the motor winding to OUT_A.

3.7 Current Control Loop Compensation

In order to have a flexible system able to drive motors with different electrical characteristics, the non inverting

input and the output of the error amplifier ( EA_OUT ) are available.

Connecting at these pins an external RC compensation network it is possible to adjust the gain and the band-

width of the current control loop.

10/24

L6258E

4 PWM CURRENT CONTROL LOOP

4.1 Open Loop Transfer Function Analysis

Block diagram : refer to Fig. 6.

Table 7. Application data:

V = 24V

S

Gs transconductance gain = 1/Rb

L = 12mH

L

Gin transconductance gain = 1/Ra

R = 12Ω

L

Ampl. of the Tria_0_180 ref. = 1.6V (peak to peak)

R = 0.33Ω

S

R = 40KΩ

a

R

C

= to be calculated

R = 20KΩ

b

C

V = Internal reference equal to V /2 (Typ. 2.5V)

r

DD

these data refer to a typical application, and will be used as an example during the analysis of the stability of the

current control loop.

The block diagram shows the schematics of the L6258E internal current control loop working in PWM mode; the

current into the load is a function of the input control voltage V

is given by the following formula:

, and the relation between the two variables

DAC

I

· R · G = V

· G

DAC in

load

S

1

------

I

R

= V

LOAD

S

DAC

R

b

a

R

V

b

DAC

------------------

--------------

I

= V

= 0.5

(A)

LOAD

DAC

R

a

s

S

where:

V

DAC

is the control voltage defining the load current value

G

is the gain of the input transconductance amplifier ( 1/Ra )

is the gain of the sense transconductance amplifier ( 1/Rb )

in

s

R

is the resistor connected in series to the output to sense the load current

s

In this configuration the input voltage is compared with the feedback voltage coming from the sense resistor,

then the difference between this two signals is amplified by the error amplifier in order to have an error signal

controlling the duty cycle of the output stage keeping the load current under control.

It is clear that to have a good performance of the current control loop, the error amplifier must have an high DC

gain and a large bandwidth .

Gain and bandwidth must be chosen depending on many parameters of the application, like the characteristics

of the load, power supply etc..., and most important is the stability of the system that must always be guaran-

teed.

To have a very flexible system and to have the possibility to adapt the system to any application, the error am-

plifier must be compensated using an RC network connected between the output and the negative input of the

same.

For the evaluation of the stability of the system, we have to consider the open loop gain of the current control

loop:

11/24

L6258E

Aloop = ACerr · ACpw · ACload · ACsense

where AC... is the gain of the blocks that refers to the error, power and sense amplifier plus the attenuation of

the load block.

The same formula in dB can be written in this way:

Aloop = ACerr + ACpw + ACload + ACsense

dB

So now we can start to analyse the dynamic characteristics of each single block, with particular attention to the

error amplifier.

4.2 Power Amplifier

The power amplifier is not a linear amplifier, but is a circuit driving in PWM mode the output stage in full bridge

configuration.

The output duty cycle variation is given by the comparison between the voltage of the error amplifier and two

triangular wave references Tri_0 and Tri_180. Because all the current control loop is referred to the Vr refer-

ence, the result is that when the output voltage of the error amplifier is equal to the Vr voltage the two output

Out_A and Out_B have the same phase and duty cycle at 50%; increasing the output voltage of the error am-

plifier above the Vr voltage, the duty cycle of the Out_A increases and the duty cycle of the Out_B decreases

of the same percentage; on the contrary decreasing the voltage of the error amplifier below the Vr voltage, the

duty cycle of the Out_A decreases and the duty cycle of the Out_B increases of the same percentage.

The gain of this block is defined by the amplitude of the two triangular wave references; more precisely the gain

of the power amplifier block is a reversed proportion of the amplitude of the two references.

In fact a variation of the error amplifier output voltage produces a larger variation in duty cycle of the two outputs

Out_A and Out_B in case of low amplitude of the two triangular wave references.

The duty cycle has the max value of 100% when the input voltage is equal to the amplitude of the two triangular

references.

The transfer function of this block consist in the relation between the output duty cycle and the amplitude of the

triangular references.

Vout = 2 · V · (0.5 - DutyCycle)

S

∆V

2 V

out

S

--------------

ACpw

= 20 log

= ------------------------------------------------------

dB

∆V

Triangular Amplitude

in

2 24

1.6

-------------

= 29.5dB

ACpw

= 10 log

dB

Moreover, having the two references Tri_0 and Tri_180 a triangular shape it is clear that the transfer function of

this block is a linear constant gain without poles and zeros.

4.3 Load Attenuation

The load block is composed by the equivalent circuit of the motor winding (resistance and inductance) plus the

sense resistor.

We will considered the effect of the Bemf voltage of the motor in the next chapter.

The input of this block is the PWM voltage of the power amplifier and as output we have the voltage across the

sense resistor produced by the current flowing into the motor winding. The relation between the two variable is :

V

out

--------------------

V

=

R

sense

S

R + R

L

S

12/24

L6258E

so the gain of this block is:

V

R

S

sense

ACload = ------------------ = --------------------

v

R + R

out

L

S

R

S

--------------------

ACload

= 20 log

dB

R + R

L

S

0.33

12 + 0.33

------------------------

Aload

= 20 log

= –31.4dB

dB

where:

R = equivalent resistance of the motor winding

L

R = sense resistor

S

Because of the inductance of the motor L , the load has a pole at the frequency :

L

1

Fpole = --------------------------------

L

--------------------

2π

R + R

L

S

1

Fpole = ---------------------------------------- = 163Hz

–3

12 10

------------------------

6.28

12 + 0.33

Before analysing the error amplifier block and the sense transconductance block, we have to do this consider-

ation :

Aloop = Ax + Bx

dB

Ax| = ACpw| + ACload|

dB

and

Bx| = ACerr| + ACsense|

dB

this means that Ax|dB is the sum of the power amplifier and load blocks;

Ax| = (29,5) + (-31.4) = -1.9dB

dB

The BODE analysis of the transfer function of Ax is:

Figure 8.

The Bode plot of the Ax|dB function shows a DC gain of -1.9dB and a pole at 163Hz.

It is clear now that (because of the negative gain of the Ax function), Bx function must have an high DC gain in

13/24

L6258E

order to increment the total open loop gain increasing the bandwidth too.

4.4 Error Amplifier and Sense Amplifier

As explained before the gain of these two blocks is :

Bx = ACerr + ACsense

dB

Being the voltage across the sense resistor the input of the Bx block and the error amplifier voltage the output

of the same, the voltage gain is given by :

1

Rb

-------

ib = Vsense Gs = Vsense

1

Zc

------

Verr_out = -(ic · Zc) so ic = -(Verr_out ·

)

because ib = icwe have:

1

Rb

1

Zc

-------

------

Vsense ·

= -(Verr_out ·

)

Verr_out

Vsense Rb

Zc

Bx = –------------------------ = –-------

In the case of no external RC network is used to compensate the error amplifier, the typical open loop transfer

function of the error plus the sense amplifier is something with a gain around 80dB and a unity gain bandwidth

at 400kHz. In this case the situation of the total transfer function Aloop, given by the sum of the Ax and Bx

dB

is :

Figure 9.

The BODE diagram shows together the error amplifier open loop transfer function, the Ax function and the re-

sultant total Aloop given by the following equation :

Aloop = AxdB + Bx

dB

The total Aloop has an high DC gain of 78.1dB with a bandwidth of 15KHz, but the problem in this case is the

stability of the system; in fact the total Aloop cross the zero dB axis with a slope of -40dB/decade.

Now it is necessary to compensate the error amplifier in order to obtain a total Aloop with an high DC gain and

a large bandwidth. Aloop must have enough phase margin to guarantee the stability of the system.

A method to reach the stability of the system, using the RC network showed in the block diagram, is to cancel

the load pole with the zero given by the compensation of the error amplifier.

14/24

L6258E

The transfer function of the Bx block with the compensation on the error amplifier is :

1

------------------------

Rc – j

Zc

2π f Cc

Bx = –------- = –----------------------------------------

Rb Rb

In this case the Bx block has a DC gain equal to the open loop and equal to zero at a frequency given by the

following formula:

1

Fzero = -------------------------------

2π Rc Cc

In order to cancel the pole of the load, the zero of the Bx block must be located at the same frequency of 163Hz;

so now we have to find a compromise between the resistor and the capacitor of the compensation network.

Considering that the resistor value defines the gain of the Bx block at the zero frequency, it is clear that this

parameter will influence the total bandwidth of the system because, annulling the load pole with the error am-

plifier zero, the slope of the total transfer function is -20dB/decade.

So the resistor value must be chosen in order to have an error amplifier gain enough to guarantee a desired

total bandwidth .

In our example we fix at 35dB the gain of the Bx block at zero frequency, so from the formula:

Rc

-------

= 20 log

Bx_gain

@ zero freq.

Rb

where: Rb = 20k

Ω

we have: Rc = 1.1M

Ω

Therefore we have the zero with a 163Hz the capacitor value :

1

Cc = ---------------------------------------- = ------------------------------------------------------- = 880pF

–6

2π Fzero Rc

6.28 163 1.1 10

Now we have to analyse how the new Aloop transfer function with a compensation network on the error amplifier

is.

The following bode diagram shows :

– the Ax function showing the position of the load pole

– the open loop transfer function of the Bx block

– the transfer function of the Bx with the RC compensation network on the error amplifier

– the total Aloop transfer function that is the sum of the Ax function plus the transfer function of the com-

pensated Bx block.

15/24

L6258E

Figure 10.

We can see that the effect of the load pole is cancelled by the zero of the Bx block ; the total Aloop cross a the

0dB axis with a slope of -20dB/decade, having in this way a stable system with an high gain at low frequency

and a bandwidth of around 8KHz.

To increase the bandwidth of the system, we should increase the gain of the Bx block, keeping the zero in the

same position. In this way the result is a shift of the total Aloop transfer function up to a greater value.

4.5 Effect of the Bemf of the stepper motor on the current control loop stability

In order to evaluate what is the effect of the Bemf voltage of the stepper motor we have to look at the load block :

Figure 11.

OUT+

Bemf

R

L

to Sense

R

S

Amplifier

OUT-

The schematic now shows the equivalent circuit of the stepper motor including a sine wave voltage generator

of the Bemf. The Bemf voltage of the motor is not constant, its value changes depending on the speed of the

motor.

Increasing the motor speed the Bemf voltage increases :

Bemf = Kt ·

where:

ω

Kt is the motor constant

is the motor speed in radiant per second

ω

16/24

L6258E

The formula defining the gain of the load considering the Bemf of the stepper motor becomes:

R

S

--------------------

(V – Bemf)

S

R + R

Vsense

Vout

L

S

ACload = --------------------- = -----------------------------------------------------------

V

S

V – Bemf

R

S

---------------------------- --------------------

Acload =

V

R + R

L S

S

V – Bemf

R

S













S

---------------------------- --------------------

ACload

= 20 log

dB

V

R + R

L S

S

we can see that the Bemf influences only the gain of the load block and does not introduce any other additional

pole or zero, so from the stability point of view the effect of the Bemf of the motor is not critical because the

phase margin remains the same.

Practically the only effect of the Bemf is to limit the gain of the total Aloop with a consequent variation of the

bandwidth of the system.

5 APPLICATION INFORMATION

A typical application circuit is shown in Fig.12.

Note: For avoid current spikes on falling edge of DISABLE a "DC feedback" would be added to the ERROR

Amplifier. (R1-R2 on Fig. 12).

5.1 Interference

Due to the fact that the circuit operates with switch mode current regulation, to reduce the effect of the wiring

inductance a good capacitor (100nF) can be placed on the board near the package, between the power supply

line (pin 13,31) and the power ground (pin 1,36,18,19) to absorb the small amount of inductive energy.

It should be noted that this capacitor is usually required in addition to an electrolytic capacitor, that has poor

performance at the high frequencies, always located near the package, between power supply voltage (pin

13,31) and power ground (pin 1,36,18,19), just to have a current recirculation path during the fast current decay

or during the phase change.

The range value of this capacitor is between few µF and 100µF, and it must be chosen depending on application

parameters like the motor inductance and load current amplitude.

A decoupling capacitor of 100nF is suggested also between the logic supply and ground.

The EA_IN1 and EA_IN2 pins carry out high impedance lines and care must be taken to avoid coupled noise

on this signals. The suggestion is to put the components connected to this pins close to the L6258E, to surround

them with ground tracks and to keep as far as possible fast switching outputs of the device. Remember also an

1 Mohm resistor between EA_INx and EA_OUTx to avoid output current spike during supply startup/shutdown.

A non inductive resistor is the best way to implement the sensing. Whether this is not possible, some metal film

resistor of the same value can be paralleled.

The two inputs for the sensing of the winding motor current (SENSE_A & SENSE_B) should be connected di-

rectly on the sensing resistor Rs terminals, and the path lead between the Rs and the two sensing inputs should

be as short as possible.

17/24

L6258E

Figure 12. Typical Application Circuit.

0.33

VCP1

10

21

20

OUT2B

10nF

VCP2

11

SENSE2

STEPPER

MOTOR

VBOOT

12

M

OUT2A

100nF

VS

14

35

34

5

12mH 10Ω

VS

13,31

7

SENSE1

TRI_CAP

0.33

1nF

OUT1B

OUT1A

GND

E

L6258

PH1

I0_1

2

9

SOP36

4

I1_1

PACKAGE

3

I2_1

PWR_GND

1,36

32

33

17

15

16

23

22

18,19

I3_1

PH2

V_DD

8

V_DD(5V)

VREF

I0_2

SIG_GND

I1_2

27

I2_2

I3_2

28

26

24

VREF1

VREF2

DISABLE

6

29

30

25

EA_IN1

EA_OUT1

1M

EA_IN2

EA_OUT2

1M

820pF

D97IN626E

R1 1M

R2 1M

5.2 Motor Selection

Some stepper motor have such high core losses that they are not suitable for switch mode current regulation. Fur-

thermore, some stepper motors are not designed for continuous operating at maximum current. Since the circuit

can drive a constant current through the motor, its temperature might exceed, both at low and high speed operation.

5.3 Unused Inputs

Unused inputs should be connected to the proper voltage levels in order to get the highest noise immunity.

5.4 Notes on PCB Design

We recommend to observe the following layout rules to avoid application problems with ground and anomalous

recirculation current.

The by-pass capacitors for the power and logic supply must be kept as near as possible to the IC.

It's important to separate on the PCB board the logic and power grounds and the internal charge pump circuit

ground avoiding that ground traces of the logic signals cross the ground traces of the power signals.

Because the IC uses the board as a heat sink, the dissipating copper area must be sized in accordance with the

required value of R

.

thj-amb

18/24

L6258E

6 OPERATION MODE TIME DIAGRAMS

Figure 13. Full step operation mode timing diagram (Phase - DAC input and Motor Current)

Position

0

1

2

3

0

1

2

3

0

FULL Step Vector

5V

Phase

1

Ph1

0

5V

1

0

Phase

2

0

5V

I0_1

Ph2

0

5V

I1_1

I2_1

I3_1

I0_2

I1_2

I2_2

I3_2

0

DAC 1

Inputs

2

3

5V

0

Ph1

5V

0

Current level

I3

I2

I1

I0

% of I

5V

MAX

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

100

98.4

0

DAC 2

Inputs

5V

95.2

0

92.1

5V

88.9

0

82.5

77.8

71.4

95.2%

63.5

19.1%

Motor drive

Current 1

55.6

47.6

38.1

95.2%

19.1%

Motor drive

Current 2

28.6

0

19.1

D97IN629A

9.5

No Current

19/24

L6258E

Figure 14. Half step operation mode timing diagram (Phase - DAC input and Motor Current)

0

1

2

3

4

5

6

7

5V

0

Phase 1

Phase 2

5V

0

Half Step Vector

Ph1

2

5V

0

I0_1

5V

0

3

1

DAC 1

Inputs

I1_1

I2_1

I3_1

5V

0

5V

0

Ph2 4

0 Ph2

5V

0

I0_2

I1_2

I2_2

I3_2

5V

0

DAC 2

Inputs

5

7

5V

0

6

5V

0

Ph1

100%

Current level%

of I

71.4%

I3

I2

I1

I0

MAX

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

100

98.4

95.2

0

92.1

Motor drive

Current 1

88.9

82.5

-71.4%

-100%

100%

77.8

71.4

63.5

55.6

71.4%

47.6

38.1

Motor drive

Current 2

28.6

0

19.1

9.5

No Current

-71.4%

-100%

D97IN627C

20/24

L6258E

Figure 15. 4 bit microstep operation mode timing diagram (Phase - DAC input and Motor Current)

Position

0

4

8 12 16 20 24 28 32 36 40 44 48 52 56 60 64

Micro Step Vector

5V

Ph1

16

0

Phase

1

5V

24

8

0

Phase

5V

2

I0_1

I1_1

I2_1

I3_1

I0_2

I1_2

I2_2

I3_2

Ph2 32

0 Ph2

0

5V

0

DAC 1

Inputs

40

56

5V

48

0

Ph1

5V

0

5V

0

DAC 2

Inputs

5V

Current level%

of I

I3

I2

I1

I0

MAX

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

100

5V

98.4

95.2

0

92.1

88.9

0

82.5

100%

95.2%

82.5%

63.5%

47.6%

38.1%

77.8

71.4

Motor drive

Current 1

19.1%

0

0%

63.5

55.6

47.6

38.1

28.6

19.1

9.5

Motor drive

Current 2

0

No Current

D97IN628A

21/24

L6258E

Figure 16. PowerSO36 Mechanical Data & Package Dimensions

mm

inch

DIM.

MIN. TYP. MAX. MIN.

TYP. MAX.

0.138

0.13

OUTLINE AND

MECHANICAL DATA

A

A2

A4

A5

a1

b

3.25

3.5

3.3

1

0.128

0.031

0

0.8

0.039

0.008

0.003

0.015

0.012

0.630

0.38

0.2

0

0.075

0.22

0.23

15.8

9.4

0.38 0.008

0.32 0.009

c

D

16

0.622

0.37

D1

D2

E

9.8

1

0.039

0.57

13.9

10.9

14.5 0.547

11.1 0.429

2.9

E1

E2

E3

E4

e

0.437

0.114

0.244

1.259

0.026

0.435

0.003

0.625

0.043

5.8

2.9

6.2

3.2

0.228

0.114

0.65

e3

G

11.05

0

0.075

15.9

1.1

0

H

15.5

0.61

h

L

0.8

1.1

0.031

N

10˚ (max)

8˚ (max)

s

PowerSO36

Note: “D and E1” do not include mold flash or protusions.

- Mold flash or protusions shall not exceed 0.15mm (0.006”)

- Critical dimensions are "a3", "E" and "G".

N

a2

A

c

a1

e

A

DETAIL B

lead

E

DETAIL A

e3

H

DETAIL A

D

slug

a3

BOTTOM VIEW

36

19

E3

B

E1

E2

D1

DETAIL B

0.35

Gage Plane

- C -

SEATING PLANE

1

8

S

L

G

C

M

b

0.12

A B

PSO36MEC

h x 45

(COPLANARITY)

0096119 B

22/24

L6258E

Table 8. Revision History

Date

Revision

Description of Changes

First Issue in EDOCS DMS

Restyling of the graphic form, changed all V_CCwith V_DD

January 2004

May 2004

5

6

;

delete TSD parameter in the Electrical characteristic on the page 5/24.

NOT FOR NEW DESIGN, it has been replaced by equivalent L6258EX.

September 2004

7

Changed on the page 5 the f_oscparameter max. value from 17.5 to

18.5kHz

23/24

L6258E

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences

of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted

by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject

to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not

authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.

The ST logo is a registered trademark of STMicroelectronics.

All other names are the property of their respective owners

STMicroelectronics group of companies

Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan -

Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America

www.st.com

24/24

生命周期：	Active	Reach Compliance Code：	not_compliant
ECCN代码：	EAR99	风险等级：	1.45
JESD-30 代码：	R-PDSO-G36	JESD-609代码：	e3
湿度敏感等级：	3	端子数量：	36
封装主体材料：	PLASTIC/EPOXY	封装代码：	SSOP
封装等效代码：	SSOP36,.56	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE, SHRINK PITCH	电源：	5,40 V
认证状态：	Not Qualified	子类别：	Motion Control Electronics
表面贴装：	YES	技术：	BCDMOS
端子面层：	Matte Tin (Sn) - annealed	端子形式：	GULL WING
端子节距：	0.635 mm	端子位置：	DUAL
Base Number Matches：	1

型号	制造商	描述	价格	文档
E-L6258EA	STMICROELECTRONICS	PWM controlled high current DMOS universal motor driver	获取价格
E-L6258EP	STMICROELECTRONICS	PWM CONTROLLED - HIGH CURRENT DMOS UNIVERSAL MOTOR DRIVER	获取价格
E-L6258EX	STMICROELECTRONICS	PWM controlled high current DMOS universal motor driver	获取价格
E-L6258EXTR	STMICROELECTRONICS	PWM controlled high current DMOS universal motor driver	获取价格
E-L6385D	STMICROELECTRONICS	0.65A HALF BRDG BASED MOSFET DRIVER, PDSO8, SO-8	获取价格
E-L6385D013TR	STMICROELECTRONICS	0.65A HALF BRDG BASED MOSFET DRIVER, PDSO8, SOP-8	获取价格
E-L6386D	STMICROELECTRONICS	0.65A HALF BRDG BASED MOSFET DRIVER, PDSO14, SOP-14	获取价格
E-L6386D013TR	STMICROELECTRONICS	0.65A HALF BRDG BASED MOSFET DRIVER, PDSO14, SOP-14	获取价格
E-L6452	STMICROELECTRONICS	Dual 13x16 Matrix Head Ink Jet Driver	获取价格
E-L6506D	STMICROELECTRONICS	STEPPER MOTOR CONTROLLER, PDSO20, SOP-20	获取价格

E-L6258E

E-L6258E 概述

E-L6258E 规格参数

E-L6258E 数据手册

E-L6258E CAD模型

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