UCD7201RSAT
更新时间：2024-12-03 13:11:20
品牌：TI
描述：4A 2 CHANNEL, BUF OR INV BASED MOSFET DRIVER, PQCC16, PLASTIC, QFN-16
概述
规格参数
数据手册UCD7201RSAT 概述
4A 2 CHANNEL, BUF OR INV BASED MOSFET DRIVER, PQCC16, PLASTIC, QFN-16 MOSFET 驱动器
UCD7201RSAT 规格参数
| 生命周期： | Obsolete | 零件包装代码： | QFN |
| 包装说明： | VQCCN, LCC16,.16SQ,25 | 针数： | 16 |
| Reach Compliance Code： | unknown | ECCN代码： | EAR99 |
| HTS代码： | 8542.39.00.01 | 风险等级： | 5.73 |
| 高边驱动器： | NO | 接口集成电路类型： | BUFFER OR INVERTER BASED MOSFET DRIVER |
| JESD-30 代码： | S-PQCC-N16 | 长度： | 4 mm |
| 功能数量： | 2 | 端子数量： | 16 |
| 最高工作温度： | 105 °C | 最低工作温度： | -40 °C |
| 标称输出峰值电流： | 4 A | 封装主体材料： | PLASTIC/EPOXY |
| 封装代码： | VQCCN | 封装等效代码： | LCC16,.16SQ,25 |
| 封装形状： | SQUARE | 封装形式： | CHIP CARRIER, VERY THIN PROFILE |
| 电源： | 12 V | 认证状态： | Not Qualified |
| 座面最大高度： | 1 mm | 子类别： | MOSFET Drivers |
| 最大供电电压： | 15 V | 最小供电电压： | 4.5 V |
| 标称供电电压： | 12 V | 表面贴装： | YES |
| 温度等级： | INDUSTRIAL | 端子形式： | NO LEAD |
| 端子节距： | 0.65 mm | 端子位置： | QUAD |
| 断开时间： | 0.035 µs | 接通时间： | 0.035 µs |
| 宽度： | 4 mm | Base Number Matches： | 1 |
UCD7201RSAT 数据手册
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PDF下载UCD7201
www.ti.com
SLUS645B–FEBRUARY 2005–REVISED JULY 2005
Digital Control Compatible Dual Low-Side ±4 Amp MOSFET Drivers with Programmable
Common Current Sense
FEATURES
DESCRIPTION
•
•
•
•
•
Adjustable Current Limit Protection
The UCD7201 is a member of the UCD7K family of
digital control compatible drivers for applications
utilizing digital control techniques or applications re-
quiring fast local peak current limit protection.
3.3-V, 10-mA Internal Regulator
DSP/µC Compatible Inputs
Dual ±4-A TrueDrive™ High Current Drivers
The UCD7201 includes dual low-side ±4-A
high-current MOSFET gate drivers. It allows the
digital power controllers such as UCD9110 or
UCD9501 to interface to the power stage in double
ended topologies. It provides a cycle-by-cycle current
10-ns Typical Rise and Fall Times with 2.2-nF
Loads
•
•
20-ns Input-to-Output Propagation Delay
25-ns Current Sense-to-Output Propagation
Delay
limit function for both driver channels,
a
programmable threshold and a digital output current
limit flag which can be monitored by the host control-
ler. With a fast cycle-by-cycle current limit protection,
the driver can turn off the power stage in the event of
an overcurrent condition.
•
•
•
•
•
Programmable Current Limit Threshold
Digital Output Current Limit Flag
4.5-V to 15-V Supply Voltage Range
Rated from -40°C to 105°C
For fast switching speeds, the UCD7201 output
stages use the TrueDrive™ output architecture, which
delivers rated current of ±4 A into the gate of a
MOSFET during the Miller plateau region of the
switching transition. It also includes a 3.3-V, 10-mA
linear regulator to provide power to the digital control-
ler.
Lead(Pb)-Free Packaging
APPLICATIONS
•
•
•
•
Digitally Controlled Power Supplies
DC/DC Converters
Motor Controllers
Line Drivers
TYPICAL APPLICATION DIAGRAM (Push-Pull Converter)
VIN
Bias Winding
Bias Supply
VOUT
UCD7201PWP
DIGITAL
1
2
NC
NC 14
CONTROLLER
VDD
ADC1
VCC
3V3
13
PVDD 12
GND
PWMA
PWMB
4
3
5
6
7
AGND
IN1
OUT1 11
OUT2 10
ADC2
IN2
INTERRUPT or CCR
PWM or GPIO
ADC3
CLF
ILIM
PGND
CS
9
8
ADC4
Isolation
Amplifier
COMMUNICATION
(Programming & Status Reporting)
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
TrueDrive, PowerPAD are trademarks of Texas Instruments.
is a registered trademark of ~ Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2005, Texas Instruments Incorporated
UCD7201
www.ti.com
SLUS645B–FEBRUARY 2005–REVISED JULY 2005
DESCRIPTION (CONT.)
For similar applications requiring direct start-up capability from higher voltages such as the 48-V telecom input
line, the UCD7601 includes a 110-V high-voltage startup circuit.
The UCD7K driver family is compatible with standard 3.3-V I/O ports of DSPs, Microcontrollers, or ASICs.
UCD7201 is offered in PowerPAD™ HTSSOP-14 or space-saving QFN-16 packages.
CONNECTION DIAGRAMS
PWP−14 PACKAGE
(TOP VIEW)
RSA−16 PACKAGE
(BOTTOM VIEW)
1
2
3
4
5
6
7
14
13
12
11
10
9
NC
3V3
IN1
AGND
IN2
CLF
ILIM
NC
VDD
PVDD
OUT1
OUT2
PGND
CS
1
2
3
4
9
16
5
6
7
8
3V3
IN1
PVDD
OUT1
OUT2
PGND
15
14
13
8
AGND
IN2
NC − No internal connection
12 11 10
ORDERING INFORMATION
(1)(2)
PACKAGED DEVICES
110-V HV
CURRENT SENSE LIMIT
TEMPERATURE RANGE
STARTUP CIR-
CUIT
PowerPAD™ HTSSOP-14
QFN-16 (RSA)(3)
PER CHANNEL
(PWP)
-40°C to 105°C
Common
No
UCD7201PWP
UCD7201RSA
(1) These products are packaged in Pb-Free and Green lead finish of Pd-Ni-Au which is compatible with MSL level 1 at 255°C to 260°C
peak reflow temperature to be compatible with either lead free or Sn/Pb soldering operations.
(2) HTSSOP-14 (PWP) and QFN-16 (RSA), packages are available taped and reeled. Add R suffix to device type (e.g. UCD7201PWPR) to
order quantities of 2,000 devices per reel for the PWP package and 1,000 devices per reel for the RSA packages.
(3) Contact factory for availability of QFN packaging.
PACKAGING INFORMATION
θJC
θJA
POWER RATING
TA = 70°C,
DERATING FACTOR,
ABOVE 70°C (mW/°C)
PACKAGE
SUFFIX
(°C/W)
(°C/W)
TJ = 125°C (mW)
PowerPAD™
HTSSOP- 14
PWP
RSA
2.07
-
37.47(1)
-
1470
-
27
-
QFN-16
(1) PowerPAD® soldered to the PWB (TI recommended PWB as defind in TI's application report SLMA002 pg.33) with OLFM.
2
UCD7201
www.ti.com
SLUS645B–FEBRUARY 2005–REVISED JULY 2005
ABSOLUTE MAXIMUM RATINGS(1)(2)
SYMBOL
PARAMETER
UCD7201
UNIT
VDD
Supply Voltage
Supply Current
16
20
V
Quiescent
IDD
mA
V
Switching, TA = 25°C, , TJ = 125°C, VDD = 12 V
200
Output Gate Drive Volt-
age
VOUT
OUT
OUT
-1 to PVDD
IOUT(sink)
4.0
-4.0
Output Gate Drive Cur-
rent
A
IOUT(source)
ISET, CS
-0.3 to 3.6
-0.3 to 3.6
-0.3 to 3.6
2.67
Analog Input
ILIM
V
Digital I/O’s
IN, CLF
TA = 25°C (PWP-14 package), TJ = 125°C
TA = 25°C (QFN-16 package), TJ = 125°C
Power Dissipation
W
-
Junction Operating
Temperature
TJ
UCD7201
-55 to 150
°C
Tstr
Storage Temperature
-65 to 150
2000
HBM
CDM
TSOL
Human body model
ESD Rating
V
Change device model
500
Lead Temperature (Soldering, 10 sec)
+300
°C
(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating
conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are with respect to GND. Currents are positive into, negative out of the specified terminal.
ELECTRICAL CHARACTERISTICS
VDD = 12 V, 4.7-µF capacitor from VDD to GND, 0.22µF from 3V3 to AGND, TA = TJ = -40°C to 105°C, (unless otherwise
noted).
PARAMETER
SUPPLY SECTION
TEST CONDITIONS
MIN
TYP
MAX UNIT
Supply current, OFF
Supply current
VDD = 4.2 V
Outputs not switching IN = LOW
-
-
200
1.5
400
2.5
µA
mA
LOW VOLTAGE UNDER-VOLTAGE LOCKOUT
VDD UVLO ON
4.25
4.05
150
4.5
4.25
250
4.75
4.45
350
V
VDD UVLO OFF
VDD UVLO hysteresis
mV
REFERENCE / EXTERNAL BIAS SUPPLY
3V3 initial set point
TA = 25°C, ILOAD = 0
3.267
3.234
-
3.3
3.3
1
3.333
3.366
6.6
V
3V3 set point over temperature
3V3 load regulation
3V3 line regulation
ILOAD = 1 mA to 10 mA, VDD = 5 V
VDD = 4.75 V to 12 V, ILOAD = 10 mA
VDD = 4.75 to 12 V
mV
mA
V
-
1
6.6
Short circuit current
3V3 OK threshold, ON
3V3 OK threshold, OFF
INPUT SIGNAL
11
20
3.0
2.8
35
3.3 V rising
2.9
2.7
3.1
3.3 V falling
2.9
HIGH, positive-going input threshold
voltage (VIT+)
1.65
1.16
0.6
-
-
-
2.08
1.5
LOW negative-going input threshold
voltage (VIT-)
V
Input voltage hysteresis, (VIT+ -
VIT-)
0.8
3
UCD7201
www.ti.com
SLUS645B–FEBRUARY 2005–REVISED JULY 2005
ELECTRICAL CHARACTERISTICS (continued)
VDD = 12 V, 4.7-µF capacitor from VDD to GND, 0.22µF from 3V3 to AGND, TA = TJ = -40°C to 105°C, (unless otherwise
noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
Frequency
-
-
2
MHz
CURRENT LIMIT (ILIM)
ILIM internal current limit threshold
ILIM = OPEN
0.51
1.05
0.700
0.21
2.64
-
0.55
1.10
0.725
0.23
-
0.58
1.15
0.750
0.25
-
ILIM maximum current limit threshold ILIM = 3.3 V
ILIM current limit threshold ILIM = 0.75 V
ILIM minimum current limit threshold ILIM = 0.25 V
V
CLF output high level
CS > ILIM , ILOAD = -7 mA
CS ≤ ILIM, ILOAD = 7 mA
CLF output low level
-
0.66
20
Propagation delay from IN to CLF
CURRENT SENSE COMPARATOR
Bias voltage
IN rising to CLF falling after a current limit event
-
10
ns
Includes CS comp offset
5
-
25
–1
50
-
mV
uA
Input bias current
Propagation delay from CS to OUTx
ILIM = 0.5 V, measured on OUTx, CS = threshold + 60 mV
-
-
25
25
40
50
(1)
ns
Propagation delay from CS to CLF(1) ILIM = 0.5 V, measured on CLF, CS = threshold + 60 mV
CURRENT SENSE DISCHARGE TRANSISTOR
Discharge resistance
IN = low, resistance from CS to AGND
10
35
75
Ω
OUTPUT DRIVERS
(1)
Source current
VDD = 12 V, IN = high, OUTx = 5 V
VDD = 12 V, IN = low, OUTx = 5 V
VDD = 4.75 V, IN = high, OUTx = 0
VDD = 4.75 V, IN = low, OUTx = 4.75 V
CLOAD= 2.2 nF, VDD = 12 V
4
4
(1)
Sink current
A
Source current(1)
2
(1)
Sink current
3
Rise time, tR
10
10
0.8
20
15
ns
V
Fall time, tF
CLOAD = 2.2 nF, VDD = 12 V
Output with VDD < UVLO
VDD =1.0 V, ISINK = 10 mA
1.2
Propagation delay from IN to OUT1,
tD1
CLOAD = 2.2 nF, VDD = 12 V, CLK rising
CLOAD = 2.2 nF, VDD = 12 V, CLK falling
20
20
35
35
ns
Propagation delay from IN to OUT2,
tD2
(1) Ensured by design. Not 100% tested in production.
4
UCD7201
www.ti.com
SLUS645B–FEBRUARY 2005–REVISED JULY 2005
FUNCTIONAL BLOCK DIAGRAM
14
NC
1
2
3
13 VDD
NC
3V3
IN1
3V3 Regulator
and Reference
12 PVDD
UVLO
11
OUT1
4
5
6
AGND
IN2
10 OUT2
+
9
8
PGND
CS
Q
Q
S
25 mV
CLF
D
R
R
7
ILIM
Figure 1. UCD7201
Timing Diagram
VIT+
INPUT
VIT−
t
F
t
F
90%
t
D1
t
D2
OUTPUT
10%
5
UCD7201
www.ti.com
SLUS645B–FEBRUARY 2005–REVISED JULY 2005
TERMINAL FUNCTIONS
UCD7201
PIN
I/O
FUNCTION
HTSSOP QFN-16
NAME
-14 PIN #
PIN #
1
-
NC
-
No Connection
Regulated 3.3-V rail. The onboard linear voltage regulator is capable of sourcing up to 10 mA
of current. Place 0.22 µF of ceramic capacitance from this pin to ground.
2
1
3V3
O
The IN pin is a high impedance digital input capable of accepting 3.3-V logic level signals up
to 2 MHz. There is an internal Schmitt trigger comparator which isolates the internal circuitry
from any external noise.
3
4
5
2
3
4
IN1
AGND
IN2
I
-
I
Analog ground return.
The IN pin is a high impedance digital input capable of accepting 3.3-V logic level signals up
to 2 MHz. There is an internal Schmitt trigger comparator which isolates the internal circuitry
from any external noise.
Current limit flag. When the CS level is greater than the ILIM voltage minus 25 mV, the output
of the driver is forced low and the current limit flag (CLF) is set high. The CLF signal is
latched high until the device receives the next rising edge on the IN pin.
6
5
CLF
O
Current limit threshold set pin. The current limit threshold can be set to any value between
0.25 V and 1.0 V. The default value while open is 0.5 V.
7
8
9
6
7
ILIM
CS
I
I
-
Current sense pin. Fast current limit comparator connected to the CS pin is used to protect
the power stage by implementing cycle-by-cycle current limiting.
Power ground return. The pin should be connected very closely to the source of the power
MOSFET.
8, 9
PGND
10
11
10
11
OUT2
OUT1
O
O
The high-current TrueDrive™ driver output.
The high-current TrueDrive™ driver output.
Supply pin provides power for the output drivers. It is not connected internally to the VDD
supply rail. The bypass capacitor for this pin should be returned to PGND.
12
13
14
12
13
PVDD
VDD
NC
I
I
-
Supply input pin to power the driver. The UCD7K devices accept an input range of 4.5 V to 15
V. Bypass the pin with at least 4.7 µF of capacitance, returned to AGND.
14, 15,
16
No Connection.
6
UCD7201
www.ti.com
SLUS645B–FEBRUARY 2005–REVISED JULY 2005
APPLICATION INFORMATION
The UCD7201 is member of the UCD7K family of
digital compatible drivers targeting applications
utilizing digital control techniques or applications that
require local fast peak current limit protection.
If limiting the rise or fall times to the power device is
desired then an external resistance may be added
between the output of the driver and the load device,
which is generally the gate of a power MOSFET.
Supply
Current Sensing and Protection
The UCD7K devices accept a supply range of 4.5 V
to 15 V. The device has an internal precision linear
regulator that produces the 3V3 output from this VDD
input. A separate pin, PVDD, not connected internally
to the VDD supply rail provides power for the output
drivers. In all applications the same bus voltage
supplies the two pins. It is recommended that a low
value of resistance be placed between the two pins
so that the local capacitance on each pin forms low
pass filters to attenuate any switching noise that may
be on the bus.
A very fast current limit comparator connected to the
CS pin is used to protect the power stage by
implementing cycle-by-cycle current limiting.
The current limit threshold may be set to any value
between 0.25 V and 1.0 V by applying the desired
threshold voltage to the current limit (ILIM) pin. If the
ILIM pin is left floating, the internal current limit
threshold will be 0.5 volts. When the CS level is
greater than the ILIM voltage minus 25 mV, the output
of the driver is forced low and the current limit flag
(CLF) is set high. The CLF signal is latched high until
the device receives the next rising edge on either of
the IN pins.
Although quiescent VDD current is low, total supply
current depends on the gate drive output current
required for capacitive load and switching frequency.
Total VDD current is the sum of quiescent VDD
current and the average OUT current. Knowing the
operating frequency and the MOSFET gate charge
(QG), average OUT current can be calculated from:
When the CS voltage is below ILIM, the driver output
follows the PWM input. The CLF digital output flag
can be monitored by the host controller to determine
when a current limit event occurs and to then apply
the appropriate algorithm to obtain the desired current
limit profile (i.e. straight time, fold back, hickup or
latch-off).
IOUT = QG x f, where f is frequency.
For the best high-speed circuit performance, VDD
bypass capacitors are recommended to prevent noise
problems. A 4.7-µF ceramic capacitor should be
located closest to the VDD and the AGND connec-
tion. In addition, a larger capacitor with relatively low
ESR should be connected to the PVDD and PGND
pin, to help deliver the high current peaks to the load.
The capacitors should present a low impedance
characteristic for the expected current levels in the
driver application. The use of surface mount
components for all bypass capacitors is highly rec-
ommended.
A benefit of this local protection feature is that the
UCD7K devices can protect the power stage if the
software code in the digital controller becomes cor-
rupted. If the controller’s PWM output stays high, the
local current sense circuit turns off the driver output
when an over-current event occurs. The system
would then likely go into retry mode because most
DSP and microcontrollers have on-board watchdog,
brown-out, and other supervisory peripherals to
restart the device in the event that it is not operating
properly. But these peripherals typically do not react
fast enough to save the power stage. The UCD7K’s
local current limit comparator provides the required
fast protection for the power stage.
Reference / External Bias Supply
All devices in the UCD7K family are capable of
supplying a regulated 3.3-V rail to power various
types of external loads such as a microcontroller or
an ASIC. The onboard linear voltage regulator is
capable of sourcing up to 10 mA of current. For
normal operation, place 0.22-µF of ceramic capaci-
tance between the 3V3 pin to the AGND pin.
The CS threshold is 25 mV below the ILIM voltage. If
the user attempts to command zero current while the
CS pin is at ground the CLF flag will latch high until
the IN pin receives a pulse. At start-up it is necessary
to ensure that the ILIM pin will always be greater than
the CS pin for the handshaking to work as described
below. If for any reason the CS pin comes to within
25 mV of the ILIM pin during start-up, then the CLF
flag will be latched high and the digital controller must
poll the UCD7K device, by sending it a narrow IN
pulse. If a fault condition is not present the IN pulse
will reset the CLF signal to low indicating that the
UCD7K device is ready to process power pulses.
Input Pin
The input pins are high impedance digital inputs
capable of accepting 3.3-V logic level signals up to 2
MHz. There is an internal Schmitt Trigger comparator
which isolates the internal circuitry from any external
noise.
7
UCD7201
www.ti.com
SLUS645B–FEBRUARY 2005–REVISED JULY 2005
Handshaking
Drive Current and Power Requirements
The UCD7K family of devices have a built-in hand-
shaking feature to facilitate efficient start-up of the
digitally controlled power supply. At start-up the CLF
flag is held high until all the internal and external
supply voltages of the UCD7K device are within their
operating range. Once the supply voltages are within
acceptable limits, the CLF goes low and the device
will process input drive signals. The micro-controller
should monitor the CFL flag at start-up and wait for
the CLF flag to go LOW before sending power pulses
to the UCD7K device.
The UCD7K family of drivers can deliver high current
into a MOSFET gate for a period of several hundred
nanoseconds. High peak current is required to turn
the device ON quickly. Then, to turn the device OFF,
the driver is required to sink a similar amount of
current to ground. This repeats at the operating
frequency of the power device.
Reference [1] discusses the current required to drive
a
power MOSFET and other capacitive-input
switching devices.
When a driver device is tested with a discrete,
capacitive load it is a fairly simple matter to calculate
the power that is required from the bias supply. The
energy that must be transferred from the bias supply
to charge the capacitor is given by:
Driver Output
The high-current output stage of the UCD7K device
family is capable of supplying ±4-A peak current
pulses and swings to both PVDD and PGND. The
driver outputs follow the state of the IN pin provided
that the VDD and 3V3 voltages are above their
respective under-voltage lockout threshold.
1
2
2
E + CV
where C is the load capacitor and V is the bias
voltage feeding the driver.
The drive output utilizes Texas Instruments'
TrueDrive™ architecture, which delivers rated current
into the gate of a MOSFET when it is most needed,
during the Miller plateau region of the switching
transition providing efficiency gains.
There is an equal amount of energy transferred to
ground when the capacitor is discharged. This leads
to a power loss given by the following:
2
TrueDrive™ consists of pullup pulldown circuits with
bipolar and MOSFET transistors in parallel. The peak
output current rating is the combined current from the
bipolar and MOSFET transistors. This hybrid output
stage also allows efficient current sourcing at low
supply voltages.
P + CV f
where f is the switching frequency.
This power is dissipated in the resistive elements of
the circuit. Thus, with no external resistor between
the driver and gate, this power is dissipated inside the
driver. Half of the total power is dissipated when the
capacitor is charged, and the other half is dissipated
when the capacitor is discharged.
Each output stage also provides a very low im-
pedance to overshoot and undershoot due to the
body diode of the external MOSFET. This means that
in many cases, external-schottky-clamp diodes are
not required.
With VDD = 12 V, CLOAD = 2.2 nF, and f = 300 kHz,
the power loss can be calculated as:
Source/Sink Capabilities During Miller Plateau
2
P + 2.2 nF 12 300 kHz + 0.095 W
Large power MOSFETs present a large load to the
control circuitry. Proper drive is required for efficient,
reliable operation. The UCD7K drivers have been
optimized to provide maximum drive to a power
MOSFET during the Miller plateau region of the
switching transition. This interval occurs while the
drain voltage is swinging between the voltage levels
dictated by the power topology, requiring the charg-
ing/discharging of the drain-gate capacitance with
current supplied or removed by the driver device. See
Reference [1]
With a 12-V supply, this would equate to a current of:
0.095 W
12 V
P
V
I +
+
+ 7.9 mA
Operational Waveforms
Figure 24 shows the circuit performance achievable
with the output driving a 10-nF load at 12-V VDD. The
input pulsewidth (not shown) is set to 200 ns to show
both transitions in the output waveform. Note the
linear rising and falling edges of the switching
waveforms. This is due to the constant output current
characteristic of TrueDrive™ stage as opposed to the
resistive
output
impedance
of
traditional
MOSFET-based gate drivers.
8
UCD7201
www.ti.com
SLUS645B–FEBRUARY 2005–REVISED JULY 2005
Thermal Information
Note that the PowerPAD™ is not directly connected
to any leads of the package. However, it is electrically
and thermally connected to the substrate which is the
ground of the device. The PowerPad™ should be
connected to the quiet ground of the circuit.
The useful range of a driver is greatly affected by the
drive power requirements of the load and the thermal
characteristics of the device package. In order for a
power driver to be useful over a particular tempera-
ture range the package must allow for the efficient
removal of the heat produced while keeping the
junction temperature within rated limits. The UCD7K
family of drivers is available in PowerPAD™ TSSOP
and QFN/DFN packages to cover a range of appli-
cation requirements. Both have an exposed pad to
enhance thermal conductivity from the semiconductor
junction.
Circuit Layout Recommendations
In a power driver operating at high frequency, it is
critical to minimize stray inductance to minimize
overshoot/undershoots and ringing. The low output
impedance of these drivers produces waveforms with
high di/dt. This tends to induce ringing in the parasitic
inductances. It is advantageous to connect the driver
device close to the MOSFETs. It is recommended
that the PGND and the AGND pins be connected to
the PowerPad™ of the package with a thin trace. It is
critical to ensure that the voltage potential between
these two pins does not exceed 0.3 V. The use of
schottky diodes on the outputs to PGND and PVDD is
recommended when driving gate transformers.
As illustrated in Reference [2], the PowerPAD™
packages offer a leadframe die pad that is exposed at
the base of the package. This pad is soldered to the
copper on the PC board (PCB) directly underneath
the device package, reducing the TJC down to
2.07°C/W. The PC board must be designed with
thermal lands and thermal vias to complete the heat
removal subsystem, as summarized in Reference [3].
9
UCD7201
www.ti.com
SLUS645B–FEBRUARY 2005–REVISED JULY 2005
Additional Application Circuits
Figure 2 shows the UCD7201 in a half-bridge converter design. The digital controller is performing the output
voltage compensation and all supervisory functions. The isolation amplifier is made up of a linear opto-coupler
configured for a gain of 1/10, so the output voltage is transformed to a level comparable with the ADC of the
digital controller.
VOUT
VIN
Bias Winding
CS
XFMR
Bias Supply
UCD7201PWP
DIGITAL
1
NC
NC 14
CONTROLLER
PVDD
ADC1
VCC
2
3V3
12
VDD 13
GND
PWMA
PWMB
4
3
5
6
7
AGND
IN1
OUT1 11
OUT2 10
Gate Drive
Transformer
(3 winding)
ADC2
IN2
INTERRUPT or CCR
PWM or GPIO
ADC3
CLF
ILIM
PGND
CS
9
8
ADC4
Isolation
Amplifier
COMMUNICATION
(Programming & Status Reporting)
Figure 2. Half-Bridge Converter
Figure 3 shows the UCD7201 in an analog only implementation of an intermediate bus converter. The ILIM pin of
the UCD7201 is exponentially increased at start-up, which minimizes overshoot on the output voltage. The
UCC28089 is a push-pull controller with fixed dead-time. The UCC28089 operates at a fixed duty cycle close to
100% so the circuit acts like a DC transformer linearly transforming the input voltage via the turns ratio of the
transformer.
VIN
Bias Supply
Bias Winding
VOUT
UCC28089
UCD7201
NC 14
1
2
NC
VDD 16
PVDD
1
2
SYNC
12
3V3
DIS
CT
CS
VDD 13
GND 13
OUTA 15
OUTB 14
4
3
5
6
7
AGND
IN1
3
4
OUT1 11
OUT2 10
PGND 9
IN2
CLF
ILIM
CS
8
Figure 3. Intermediate Bus Converter
10
UCD7201
www.ti.com
SLUS645B–FEBRUARY 2005–REVISED JULY 2005
Typical Characteristics
UVLO THRESHOLDS
vs
TEMPERATURE
3V3 REFERENCE VOLTAGE
vs
TEMPERATURE
5.0
4.5
3.36
3.34
3.32
3.30
UVLO on
4.0
3.5
UVLO off
3.0
2.5
2.0
3.28
3.26
3.24
1.5
1.0
UVLO hysteresis
0.5
0.0
125
−50
−25
0
25
50
75
100
−50
−25
0
25
50
75
100
125
t − Temperature − °C
t − Temperature − °C
Figure 4.
Figure 5.
3V3 SHORT CIRCUIT CURRENT
SUPPLY CURRENT
vs
FREQUENCY (VDD = 5 V)
vs
TEMPERATURE
23.0
22.5
160
140
C
LOAD
= 10 nF
120
100
22.0
21.5
21.0
20.5
VDD = 4.75 V
80
60
VDD = 12 V
C
= 4.7 nF
LOAD
40
20
0
C
C
= 2.2 nF
= 1 nF
LOAD
LOAD
20.0
−50
−25
0
25
50
75
100
125
0
500
1000
1500
t − Temperature − °C
f − Frequency − kHz
Figure 6.
Figure 7.
11
UCD7201
www.ti.com
SLUS645B–FEBRUARY 2005–REVISED JULY 2005
SUPPLY CURRENT
vs
FREQUENCY (VDD = 8 V)
SUPPLY CURRENT
vs
FREQUENCY (VDD = 10 V)
280
240
320
280
240
200
C
LOAD
= 10 nF
C
LOAD
= 10 nF
200
160
120
C
LOAD
= 4.7 nF
= 2.2 nF
160
C
LOAD
= 4.7 nF
120
80
80
40
0
C
LOAD
C
C
= 2.2 nF
= 1 nF
LOAD
40
0
C
LOAD
= 1 nF
LOAD
1500
0
500
1000
0
500
1500
1000
f − Frequency − kHz
f − Frequency − kHz
Figure 8.
Figure 9.
SUPPLY CURRENT
vs
FREQUENCY (VDD = 12 V)
SUPPLY CURRENT
vs
FREQUENCY (VDD = 15 V)
400
500
450
350
300
400
350
C
LOAD
= 10 nF
C
LOAD
= 10 nF
250
300
250
C
LOAD
= 4.7 nF
200
150
100
C
= 4.7 nF
LOAD
200
150
100
50
C
LOAD
= 2.2 nF
C
C
= 2.2 nF
= 1 nF
LOAD
50
0
C
LOAD
= 1 nF
LOAD
0
1500
0
0
1000
500
500
1500
1000
f − Frequency − kHz
f − Frequency − kHz
Figure 10.
Figure 11.
12
UCD7201
www.ti.com
SLUS645B–FEBRUARY 2005–REVISED JULY 2005
INPUT THRESHOLDS
vs
OUTPUT RISE TIME AND FALL TIME
vs
TEMPERATURE
TEMPERATURE (VDD = 12 V)
2.5
2.0
18.0
16.0
C
LOAD
= 2.2 nF
t
R
= Rise Time
Input Rising
14.0
12.0
10.0
1.5
t
F
= Fall Time
Input Falling
8.0
6.0
4.0
2.0
0.0
1.0
0.5
0.0
−50
−25
0
25
50
75
100
125
−50
−25
0
25
50
75
100
125
T − Temperature − °C
J
T − Temperature − °C
J
Figure 12.
Figure 13.
RISE TIME
vs
SUPPLY VOLTAGE
FALL TIME
vs
SUPPLY VOLTAGE
65
45
40
55
45
35
C
LOAD
= 10 nF
35
30
C
= 10 nF
LOAD
C
LOAD
= 4.7 nF
25
C
= 4.7 nF
C
LOAD
20
15
25
15
= 2.2 nF
LOAD
C
C
= 2.2 nF
LOAD
C
= 1 nF
LOAD
10
5
= 1 nF
12.5
LOAD
5
5
7.5
10
15
5
7.5
10
12.5
15
V
DD
− Supply Voltage − V
V
DD
− Supply Voltage − V
Figure 14.
Figure 15.
13
UCD7201
www.ti.com
SLUS645B–FEBRUARY 2005–REVISED JULY 2005
IN to OUTx PROPAGATION DELAY RISING
IN to OUTx PROPAGATION DELAY FALLING
vs
vs
SUPPLY VOLTAGE
SUPPLY VOLTAGE
25
20
20
C
= 10 nF
C
= 10 nF
LOAD
15
10
LOAD
15
10
C
= 4.7 nF
LOAD
C
LOAD
= 4.7 nF
5
0
C
LOAD
= 2.2 nF
C
= 2.2 nF
LOAD
C
= 1 nF
LOAD
C
LOAD
= 1 nF
5
5
7.5
V
10
12.5
15
5
7.5
V
10
12.5
15
− Supply Voltage − V
− Supply Voltage − V
DD
DD
Figure 16.
Figure 17.
DEFAULT CURRENT LIMIT THRESHOLD
CS TO OUTx PROPAGATION DELAY
vs
vs
TEMPERATURE
TEMPERATURE
0.59
0.58
0.57
0.56
0.55
0.54
0.53
0.52
0.51
40
35
30
25
20
15
10
5
0
−50
−25
0
25
50
75
100
125
−50
−25
0
25
50
75
100
125
T − Temperature − °C
J
T − Temperature − °C
J
Figure 18.
Figure 19.
14
UCD7201
www.ti.com
SLUS645B–FEBRUARY 2005–REVISED JULY 2005
CS TO CLF PROPAGATION DELAY
IN TO OUT PROPAGATION DELAY
vs
vs
TEMPERATURE
TEMPERATURE
35
30
25
20
15
50
45
40
35
30
25
20
15
10
10
5
5
0
0
−50
−25
0
25
50
75
100
125
125
−50
−25
0
25
50
75
100
T − Temperature − °C
J
T − Temperature − °C
J
Figure 20.
Figure 21.
START-UP BEHAVIOR AT VDD = 12 V (INPUT TIED TO 3V3)
SHUT DOWN BEHAVIOR AT VDD = 12 V (INPUT TIED TO
3V3)
VDD (2 V/div)
VDD (2 V/div)
3V3 (2 V/div)
3V3 (2 V/div)
OUTx (2 V/div)
OUTx (2 V/div)
t − Time − 40 µs/div
t − Time − 40 µs/div
Figure 22.
Figure 23.
15
UCD7201
www.ti.com
SLUS645B–FEBRUARY 2005–REVISED JULY 2005
START-UP BEHAVIOR AT VDD = 12 V (INPUT SHORTED
TO GND)
SHUT DOWN BEHAVIOR AT VDD = 12 V (INPUT SHORTED
TO GND)
VDD (2 V/div)
VDD (2 V/div)
3V3 (2 V/div)
3V3 (2 V/div)
OUTx (2 V/div)
OUTx (2 V/div)
t − Time − 40 µs/div
t − Time − 40 µs/div
Figure 24.
Figure 25.
OUTPUT RISE AND FALL TIME (VDD = 12 V, CLOAD = 10 nF)
t − Time − 40 ns/div
Figure 26.
16
UCD7201
www.ti.com
SLUS645B–FEBRUARY 2005–REVISED JULY 2005
REFERENCES
1. Power Supply Seminar SEM-1400 Topic 2: Design And Application Guide For High Speed MOSFET Gate
Drive Circuits, by Laszlo Balogh, Texas Instruments Literature No. SLUP133.
2. Technical Brief, PowerPad Thermally Enhanced Package, Texas Instruments Literature No. SLMA002
3. Application Brief, PowerPAD Made Easy, Texas Instruments Literature No. SLMA004
RELATED PRODUCTS
TEMPERATURE RANGE
UCD7100
CURRENT SENSE LIMIT PER CHANNEL
Single Low Side ±4-A Driver with Independent CS
FEATURES
3V3, CS(1)(2)
3V3, CS(1)(2)
3V3, CS(1)(2)
UCD7200
Dual Low Side ±4-A Drivers with Independent CS
UCD7230
±4-A Synchronous Buck Driver with CS
(1)(2)(3)
UCD7500
Single Low Side ±4-A Driver with CS and 110-V High Voltage Startup
Dual Low Side ±4-A Drivers with Independent CS and 110-V High Voltage Startup
Dual Low Side ±4-A Drivers with Common CS and 110-V High Voltage Startup
3v3, CS, HVS110
3V3, CS, HVS110
(1)(2)(3)
UCD7600
3V3, CCS, HVS110
UCD7601
(1)(4)(3)
UCD9110
UCD9501
Digital Power Controller for High Performance Single-loop Applications
Digital Power Controller for High Performance Multi-Loop Applications
(1) 3V3 = 3.3-V linear regulator.
(2) CS = current sense and current limit function.
(3) HVS110 = 110-V high voltage startup circuit.
(4) CCS = Common current sense and current limit function.
REVISION HISTORY
DATE
3/4/05
4/1/05
7/14/05
REVISION
SLUS645
CHANGE DESCRIPTION
Initial release of preliminary datasheet.
Updated packaging information.
SLUS645A
SLUS645B
Initial release of production datasheet. Updated specification and application information.
17
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Copyright 2005, Texas Instruments Incorporated
UCD7201RSAT 相关器件
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