UCD7230A
更新时间：2025-01-13 12:50:26
品牌：TI
描述：Digital Control Compatible Synchronous Buck Gate Driver with Current Sense Conditioning Amplifier
概述
数据手册
替代型号UCD7230A 概述
Digital Control Compatible Synchronous Buck Gate Driver with Current Sense Conditioning Amplifier 数字控制兼容同步降压闸极驱动器具有电流感应调放大器
UCD7230A 数据手册
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SLUS995 –NOVEMBER 2009
Digital Control Compatible Synchronous Buck Gate Driver
with Current Sense Conditioning Amplifier
Check for Samples: UCD7230A
1
FEATURES
APPLICATIONS
•
Digitally-Controlled Synchronous-Buck Power
Stages for Single and Multi-Phase
Applications
Especially Suited for Use with UCD91xx or
UCD92xx Contollers
High-Current Multi-Phase VRM/EVRD
Regulators for Desktop, Server, Telecom and
Notebook Processors
2
•
Input from Digital Controller Sets Operating
Frequency and Duty Cycle
•
•
Up to 2-MHz Switching Frequency
•
•
Dual Current Limit Protection with
Independently Adjustable Thresholds
•
Fast Current Sense Circuit with Adjustable
Blanking Interval Prevents Catastrophic
Current Levels
•
Digitally-Controlled Synchronous-Buck Power
Supplies Using μCs or the TMS320™ DSP
Family
•
•
Digital Output Current Limit Flag
Low Offset, Gain of 48, Differential Current
Sense Amplifier
DESCRIPTION
•
•
•
3.3-V, 10-mA Internal Regulator
The UCD7230A is one in the UCD7k family of digital
control compatible drivers for applications utilizing
digital control techniques or applications requiring fast
local peak current limit protection.
Dual TrueDrive™ High-Current Drivers
10-ns Typical Rise/Fall Times with 2.2-nF
Loads
•
4.5-V to 15.5-V Supply Voltage Range
The UCD7230A is a MOSFET gate driver specifically
designed for synchronous buck applications. It is
ideally suited to provide the bridge between digital
controllers such as the UCD91xx or the UCD92xx
and the power stage. With cycle-by-cycle current limit
protection, the UCD7230A device protects the power
stage from faulty input signals or excessive load
currents.
V
V
IN
OUT
18
VDD CSBIAS CS+
3V3
16
17
13
14
15
12
11
10
BST OUT1 SW PVDD OUT2 PGND
POS
8
9
7
1
2
BIAS
NEG
AO
I
LOAD
AGND
UCD7230A
IN 20
PWM
SRE
SRE 19
4
5
ILIM
CLF
I
MAX
IO
6
3
I
DLY
CLF
DLY
UDG-09162
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
TMS320, TrueDrive are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2009, Texas Instruments Incorporated
UCD7230A
SLUS995 –NOVEMBER 2009
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
DESCRIPTION (CONTINUED)
The UCD7230A includes high-side and low-side gate drivers which utilize Texas Instrument’s TrueDrive™ output
architecture. This architecture delivers rated current into the gate capacitance of a MOSFET during the Miller
plateau region of the switching. Furthermore, the UCD7230A offers a low offset differential amplifier with a fixed
gain of 48. This amplifier greatly simplifies the task of conditioning small current sense signals inherent in high
efficiency buck converters.
The UCD7230A includes a 3.3-V, 10-mA linear regulator to provide power to digital controllers such as the
UCD91xx. The UCD7230A is compatible with standard 3.3-V I/O ports of the UCD91xx, the TMS320™ family
DSPs, microprocessors, or ASICs.
The UCD7230A is offered in the space-saving QFN package. Package pin out has been carefully designed for
optimal board layout
ORDERING INFORMATION(1) (2)
TEMPERATURE RANGE
PACKAGED DEVICES
PACKAGE QUANTITY
DELIVERY MEDIA
Small tape and reel
Large tape and reel
DEVICE NUMBER
UCD7230ARGWT
UCD7230ARGWR
250
-40°C to + 125°C
QFN-20 (RGW)
3000
(1) These products are packaged in Pb-Free and green lead finish of Pd-Ni-Au which is compatible with MSL level 1 between 255°C and
260°C peak reflow temperature to be compatible with either lead free or Sn/Pb soldering operations.
(2) QFN-20 (RGW) package is available taped and reeled only.
2
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ABSOLUTE MAXIMUM RATINGS(1)
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
VDD
16
VSW+16 V
20
Input voltage
BST
V
VDD
Supply current
OUT1
mA
V
200
36
OUT1, BST
Output gate drive voltage
OUT2
-1
-1
VVDD+0.3
4.0
OUT1 (sink)
OUT1 (source)
Output gate drive current
-2.0
4.0
A
V
OUT2 (sink)
OUT2 (source)
-4.0
20
SW
-1
CS+
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
20
Analog input voltage
CSBIAS
16
POS, NEG
ILIM, DLY, I0
A0
5.6
3.6
Analog output
Digital I/O’s
3.6
V
V
IN, SRE, CLF
3.6
Electrostatic discharge, human body model(HBM)
Electrostatic discharge, charged device model (CDM)
Operating junction temperature, TJ
2
kV
V
500
150
150
300
-55
-65
°C
°C
Storage temperature, Tstg
Lead temperature (soldering, 10 sec)
(1) Stresses beyond those listed in this table may cause permanent damage to the device. These are stress ratings only and functional
operation of the device at these or any other condition beyond those indicated is not implied. Exposure to absolute maximum rated
conditions for extended periods may affect device reliability. All voltages are with respect to GND. Currents are positive into, negative
out of the specified terminal. Consult company packaging information for thermal limitations and considerations of packages.
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
MIN
4.75
200
-40
TYP
12
MAX
15
UNIT
V
Input voltage
VDD
Switching Frequency
Operating ambient temperature
500
2000
85
kHz
°C
TA
DISSIPATION RATINGS TABLE (2 OZ. TRACE AND COPPER PAD WITH SOLDER)(1)
TA < 25°C
POWER RATING (W)
DERATING FACTOR
ABOVE TA = 25°C (mW/°C)
θJA
(°C/W)
PACKAGE
20-pin RGW
2.4
24.0
41.7
(1) For more information on the RGW package and the test method, refer to TI technical brief, literature number SZZA017.
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ELECTRICAL CHARACTERISTICS
VDD = PVDD = 12 V, 4.7 μF from VDD to AGND, 1 μF from PVDD to PGND, 0.1 μF from CSBIAS to AGND, 0.22 μF from BST to
SW, TA = TJ = -40°C to +125°C, RCS+ = 5 kΩ, RDLY = 50 kΩ over operating free-air temperature range (unless otherwise
noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY
IVDD
Supply current, off
Supply current
VDD = 4.2 V
Outputs not switching IN = LOW
4
5
5.2
8
mA
mA
IVDD
LOW-VOLTAGE UNDER-VOLTAGE LOCKOUT
VDD UVLO ON
VDD UVLO OFF
VDD rising
4.25
4.00
100
4.50
4.25
250
4.75
4.50
400
V
VDD falling
TA = 25°C
VDD UVLO hysteresis
REFERENCE / EXTERNAL BIAS SUPPLY
3V3 initial set point
mV
3.267
3.234
3.3
3.3
1
3.333
3.366
7
V
3V3 over temperature
3V3 load regulation
ILOAD = 1 mA to 10 mA, VDD = 5V
VDD = 4.75 V to 12 V, ILOAD = 10 mA
VDD = 4.75 V to 12 V
3.3 V rising
mV
mA
V
3V3 line regulation
3
10
Short circuit current
11
2.8
2.6
20
3
3V3 OK threshold, ON
3V3 OK threshold, OFF
INPUT SIGNAL (IN)
3.2
3.0
3.3 V falling
2.8
Positive-going input threshold
INHigh
voltage
1.6
1.0
0.4
1.9
1.3
2.2
1.6
Negative-going input threshold
voltage
INLow
V
INHigh –
Input voltage hysteresis
INLow
0.6
0.8
Input resistance to AGND
Frequency ceiling
50
2
100
150
kΩ
MHz
PWM minimum pulse width to
force OUT1 gate pulse
tMIN
CLOAD = 2.2 nF, VDD = 12 V
VILIM= OPEN
120
ns
CURRENT LIMIT (ILIM)
ILIM internal voltage setpoint
ILIM input impedance
CLF output high level
CLF output low level
0.47
20
0.50
42
0.53
65
V
kΩ
ILOAD = 4 mA
ILOAD = 4 mA
2.7
V
0.6
35
Propagation delay from IN to
reset CLF
2nd IN rising to CLF falling after a current limit
event
15
ns
CURRENT SENSE COMPARATOR (OUTPUT SENSE)
VILIM = open
40
80
60
15
50
100
75
60
120
90
VILIM = 3.3 V
VILIM = 0.75 V
VILIM = 0.25 V
VCS
CS threshold (POS - NEG)
mV
ns
25
35
Propagation delay from POS to
OUT1 falling(1)
VILIM = open, VCS = threshold + 60 mV
VILIM = open, VCS = threshold + 60 mV
90
Propagation delay from POS to
CLF(1)
100
(1) As designed and characterized. Not 100% tested in production.
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ELECTRICAL CHARACTERISTICS (continued)
VDD = PVDD = 12 V, 4.7 μF from VDD to AGND, 1 μF from PVDD to PGND, 0.1 μF from CSBIAS to AGND, 0.22 μF from BST to
SW, TA = TJ = -40°C to +125°C, RCS+ = 5 kΩ, RDLY = 50 kΩ over operating free-air temperature range (unless otherwise
noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
CURRENT SENSE COMPARATOR (INPUT SENSE)
RDLY = 24.3 kΩ (CSBIAS-CS+)
RDLY = 49.9 kΩ (CSBIAS-CS+)
170
90
235
114
300
140
CS threshold
mV
RDLY = 24.3 kΩ , IN rising to OUT1, IN falling to
OUT2, VDD = 6 V
120
CS blanking time(2)
RDELAY range(2)
ns
kΩ
ns
RDLY = 49.9 kΩ , IN rising to OUT1, IN falling to
OUT2, VDD = 6 V
230
50.0
80
24.3
100.0
Propagation delay from CS+ to
OUT1(2)
VCS = threshold + 60 mV
Propagation delay from CS+ to
CLF(2)
70
CURRENT SENSE AMPLIFIER
I0 = OPEN; (VPOS = VNEG)= 1.25 V; measure
AO - IO
VOO
Output offset voltage
Closed loop dc gain
Input impedance
-100
46
0
48
100
50
mV
V/V
kΩ
V
I0 = FLOAT; VPOS = 1.26 V; VNEG = 1.25 V,
RPOS = RNEG = 0 C
VPOS = 1.25 V, VNEG = 1.29 V,
5.5
0.3
8.3
12
R = (VPOS - VNEG) / (IPOS - INEG
)
Input Common Mode Voltage
Range
VCM
VCM(max) is limited to (VDD-1.2V), RPOS = 0
5.6
0.3
3.5
A0_Vol
Minimum Output Voltage
VPOS = 1.2 V; VNEG = 1.3 V; A0_ISINK = 250 μA
0.15
3.1
V
VPOS =1.3 V; VNEG = 1.2 V;
A0_ ISOURCE = 500 μA
A0_Voh Maximum Output Voltage
Input Bias Current, POS or NEG
3
I0 = FLOAT; VPOS = VNEG = 0.8 V to 5.0 V,
RPOS = RNEG = 0 V
-2
30
μA
ZERO CURRENT REFERENCE (IO)
Reference voltage
Measured at I0
0.54
10
0.6
60
15
0.66
120
21
V
Input transition voltage
With respect to IO reference
IZERO = 0.6 V
mV
kΩ
IO
Output impedance
10
(2) As designed and characterized. Not 100% tested in production.
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ELECTRICAL CHARACTERISTICS (continued)
VDD = PVDD = 12 V, 4.7 μF from VDD to AGND, 1 μF from PVDD to PGND, 0.1 μF from CSBIAS to AGND, 0.22 μF from BST to
SW, TA = TJ = -40°C to +125°C, RCS+ = 5 kΩ, RDLY = 50 kΩ over operating free-air temperature range (unless otherwise
noted).
PARAMETER
LOW-SIDE OUTPUT DRIVER (OUT2)
Source current(3)
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VDD = 12 V, IN = high, VOUT2 = 5 V
VDD = 12 V, IN = low, VOUT2 = 5 V
VDD = 4.75 V, IN = high, VOUT2 = 0
VDD = 4.75 V, IN = low, VOUT2 = 4.75 V
CLOAD = 2.2 nF, VDD = 12 V
2.2
3.5
1.6
2
(3)
Sink current
A
Source current(3)
(3)
Sink current
Rise time(3)
Fall time(3)
15
15
0.8
ns
CLOAD = 2.2 nF, VDD = 12 V
Output with VDD <UVLO
VDD = 1.0 V, Isink = 10 mA
1.2
V
Propagation delay from IN to
OUT2(3)
CLOAD = 2.2 nF, IN rising, SW = 2.5 V, BST =
PVDD = VDD = 12 V
30
ns
HIGH-SIDE OUTPUT DRIVER (OUT1)
Source current(3)
VDD = 12 V, BST = 12 V IN = High, VOUT1 = 5 V
VDD = 12 V, BST = 12 V IN = Low, VOUT1 = 5 V
1.7
3.5
(3)
Sink current
VDD = 4.75 V = BST = 4.75 V, IN = High, VOUT1
= 0
(3)
A
Source current
1
VDD = 4.75 V, BST = 4.75 V, IN = Low, VOUT1
4.75 V
=
(3)
Sink current
2.4
Rise time(3)
CLOAD = 2.2 nF OUT1 to SW, VDD = 12 V
CLOAD = 2.2 nF OUT1 to SW, VDD = 12 V
20
15
(3)
Fall time
ns
Propagation delay from IN to
OUT1(3)
CLOAD = 2.2 nF, IN falling, SW = 2.5 V, BST =
PVDD = VDD = 12 V
30
(3) As designed and characterized. Not 100% tested in production.
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DEVICE INFORMATION
RGW Package
(Top View)
20 19 18 17 16
1
2
3
4
5
15
14
13
12
11
3V3
AGND
DLY
SW
OUT1
BST
ILIM
PVDD
OUT2
CLF
6
7
8
9
10
TERMINAL FUNCTIONS
NAME
No.
I/O
DESCRIPTION
Regulated 3.3-V rail. The onboard linear voltage regulator is capable of sourcing up to 10 mA of current.
Bypass with 0.22-μF ceramic capacitance from this pin to analog ground, AGND.
3V3
1
O
Current sense linear amplifier output. The output voltage level on this pin represents the average output
current. Any value below the level on the I0 pin represents negative output current.
AO
7
2
O
-
AGND
BST
Analog ground return.
Floating OUT1 driver supply powered by an external Schottky diode from the PVDD pin during the
synchronous MOSFET on time.
13
I
Current Limit Flag. The CLF signal is a 3.3-V digital output which is latched high after an over current
event, triggered by either of the two current sense comparators and reset after two rising edges received on
the IN pin. CLF is also asserted on power-up while VDD is below the UVLO threshold. CLF goes low when
VDD crosses the UVLO threshold.
CLF
5
O
CSBIAS
CS+
16
17
I
I
Supply pin for the high-side current sense comparator.
Non-inverting Input for the high side current sense comparator. A resistor connected between this pin and
the high side MOSFET drain, in conjunction with the DLY resistor sets the high-side current limit threshold.
Requires a resistor to AGND for setting the current sense blanking time for both the high-side and low-side
current sense comparators. The value of this resistor in conjunction with the resistor in series with the CS+
pin sets the high side current sense threshold.
Output current limit threshold set pin. The output current threshold is 1/10th of the value set on this pin. If
left floating the voltage on this pin is 0.55 V. The voltage on the ILIM pin can range from 0.25 V to 1V to set
the threshold from 25 mV to 100 mV.
DLY
ILIM
3
4
I
I
The IN pin is a high impedance digital input capable of accepting 3.3-V logic level signals up to 2 MHz. A
Schmitt trigger input comparator desensitizes this pin from external noise.
IN
20
6
I
I
I
Sets the current sense linear amplifier “Zero” output level. The default value is 0.6 V which allows negative
current measurement.
IO
The high-side high-current TrueDrive™ driver output. Drives the gate of the high-side buck MOSFET
between SW and BST.
OUT1
14
The low-side high-current TrueDrive™ driver output. Drives the gate of the low-side synchronous MOSFET
between PVDD and PGND.
OUT2
NEG
11
9
I
I
-
Inverting input of the output current sense amplifier and current limit comparator.
Power ground return. This pin should be connected close to the source of the low-side synchronous
rectifier MOSFET.
PGND
10
POS
8
I
Non-inverting input of the output current sense amplifier and current limit comparator.
Thermal pad. Connect directly to AGND for thermal performance and EMI reduction.
PPAD
PAD
–
Supply pin provides power for the output drivers. It is not connected internally to the VDD supply rail. The
bypass capacitor for this pin should be returned to PGND.
PVDD
12
-
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TERMINAL FUNCTIONS (continued)
NAME
No.
I/O
DESCRIPTION
Synchronous Rectifier Enable. The SRE pin is a high impedance digital input capable of accepting 3.3-V
logic level signals, used to disable the synchronous rectifier switch. The synchronous rectifier is disabled
when this signal is low. A Schmitt trigger input comparator desensitizes this pin from external noise.
SRE
19
I
SW
15
18
I/O
-
OUT1 gate drive return and square wave input to output inductor.
Supply input pin to power the internal circuitry except the driver outputs. The UCD7230A accepts an input
range of 4.5 V to 15.5 V.
VDD
FUNCTIONAL BLOCK DIAGRAM
VDD
18
CSBIAS
16
CS+ BST OUT1 SW PVDD OUT2 PGND
17 13 14 15 12 11 10
6
IO
+
UVLO
I
DLY
0.6 V
+
Enable
Drive and Deadtime Control Logic
(D, 1-D)
3V3
Reg
3V3
1
Blanking
8
9
POS
NEG
48 x
Overcurrent
ILIM
CLF
4
5
Current Limit
Logic
7
AO
ILIM/10
20 IN
AGND
2
+
3
DLY
19 SRE
UCD7230A
UDG-09163
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APPLICATION INFORMATION
Introduction
The UCD7230A is a synchronous buck driver with peak-current limiting. It is a member of the UCD7K family of
digital compatible drivers suitable either for applications utilizing digital control techniques or analog applications
that require local fast peak current limit protection.
In systems using the UCD7230A, the feedback loop is closed externally and the IN signal represents the PWM
information required to regulate the output voltage. The PWM signal may be implemented by either a digital or
analog controller.
The UCD7230A has two over-current protection features, one that limits the peak current in the high-side switch
and one that limits the output current. Both limits are individually programmable. The internal current sense
blanking enables ease of design with real-world signals. In addition to over current limit protection, current sense
signals can be conditioned by the on board amplifier for use by the system controller.
V
IN
UCD7230A
18 VDD
CS+ 17
UCD9112
19 SRE CSBIAS 16
ADC3
RB0
20 IN
SW 15
DPWMA0
AD33
VD25
V
OUT
R
POS
1
2
3V3
OUT1 14
BST 13
AVSS
V
EAP
OUT
AGND
DLY
GSENSE
3
PVDD 12
OUT2 11
GSENSE
EAM
RST
DPWMB0
4
5
ILIM
CLF
RB1/TMRI1
10
PGND
R
NEG
6
7
IO
NEG
POS
9
8
COMMUNICATION
(Programming and
Status Reporting)
ADC2
AO
UDG-09164
Figure 1. Single-Phase Synchronous Buck Converter using UCD9112 and one UCD7230A
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V
IN
RB0
UCD7230A
18 VDD CS+ 17
UCD9112
19 SRE CSBIAS 16
ADC3
RB0
20 IN
SW 15
DPWMA0
AD33
VD25
V
OUT
R
POS1
1
2
3V3
OUT1 14
BST 13
AVSS
V
EAP
OUT
AGND
DLY
GSENSE
3
PVDD 12
OUT2 11
GSENSE
EAM
RST
DPWMB0
4
5
ILIM
CLF
RB1/TMRI1
10
PGND
R
NEG1
6
7
IO
NEG
POS
9
8
COMMUNICATION
(Programming and
Status Reporting)
ADC2
AO
UCD7230A
18 VDD CS+ 17
19 SRE CSBIAS 16
RB0
20 IN
SW 15
DPWMA1
R
POS2
1
2
3V3
OUT1 14
BST 13
AGND
DLY
3
PVDD 12
OUT2 11
DPWMB1
4
5
ILIM
CLF
10
RB3/TMRI0
PGND
R
NEG2
6
7
IO
NEG
POS
9
8
ADC5
AO
UDG-09165
Figure 2. Multi-Phase Synchronous Buck Converter using UCD9112 and two UCD7230A
Supply Requirements
The UCD7230A operates on a supply range of 4.5 V to 15.5 V. The supply voltage should be applied to three
pins, PVDD, VDD, and CSBIAS. PVDD is the supply pin for the lower driver, and has the greatest current
demands. The supply connection to PVDD is also the point where an external Schottky diode provides current to
the high side flying driver. PVDD should be bypassed to PGND with a low ESR ceramic capacitor. In the same
fashion, the flying driver should be bypassed between BST and SW.
VDD and CSBIAS are less demanding supply pins, and should be resistively coupled to the supply voltage for
isolation from noise generated by high current switching and parasitic board inductance. Use a value of 10 Ω for
CSBIAS and 1 Ω for VDD. VDD should be bypassed to AGND with a 4.7-μF ceramic capacitor while CSBIAS
should be bypassed to AGND with 0.1 μF. Although the three supply pins are not internally connected, they must
be biased to the same voltage. It is important that all bypassing be done with low parasitic inductance techniques
to good ground planes.
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PGND and AGND are the ground return connections to the chip. Ground plane construction should be used for
both pins. For a MOSFET driver operating at high frequency, it is critical to minimize the stray inductance to
minimize overshoot, undershoot, and ringing. The low output impedance of the drivers produces waveforms with
high di/dt. This induces ringing in the parasitic inductances. It is highly desirable that the UCD7230A and the
MOSFETs be collocated. PGND and the AGND pins should be connected to the PowerPAD™ of the package
with two thin traces. It is critical to ensure that the voltage potential between these two pins does not exceed
0.3 V.
Although quiescent VDD current is low, total supply current depends on the gate drive output current required for
the capacitive load and the switching frequency. Total supply current is the sum of quiescent VDD current and
the average OUT current. Knowing the operating frequency and the MOSFET gate charge (Qg), average OUT
current can be calculated from (IOUT = Qg x f), where f is the operating frequency.
Reference / External Bias Supply
The UCD7230A includes a series pass regulator to provide a regulated 3.3 V at the 3V3 pin that can be used to
power other circuits such as the UCD91xx, a microcontroller or an ASIC. 3V3 can source 10 mA of current. For
normal operation, place a 0.22-μF ceramic capacitor between 3V3 and AGND.
Control Inputs
The IN and SRE pins are high impedance digital inputs designed for 3.3-V logic-level signals. They both have
100-kΩ pull-down resistors. Schmitt Trigger input stage design immunizes the internal circuitry from external
noise. IN is the command input for the upper driver, OUT1, and can function up to 2 MHz. SRE controls the
function of the lower driver, OUT2. When SRE is false (low), OUT2 is held low. When SRE is true, OUT2 is
inverted from OUT1 with appropriate delays that preclude cross conduction in the Buck MOSFETs.
Driver Stages
The driver outputs utilize Texas Instruments’ TrueDrive™ architecture, which delivers rated current into the gate
of a MOSFET when it is most needed, during the Miller plateau region of the switching transition. This provides
best switching speeds and reduces switching losses. TrueDrive™ consists of pull-up/ pull-down circuits using
bipolar and MOSFET transistors in parallel. This hybrid output stage also allows relatively constant current
sourcing even at reduced supply voltages.
The low-side high-current output stage of the UCD7230A device is capable of sourcing 1.7-A and sinking 3.5-A
current pulses and swings from PVDD to PGND. The high-side floating output driver is capable of sourcing 2.2-A
and sinking 3.5-A peak-current pulses. This ratio of gate currents, common to synchronous buck applications,
minimizes the possibility of parasitic turn on of the low-side power MOSFET due to dv/dt currents during the
rising edge switching transition. See the typical curves of sink and source current in Figure 3 and Figure 4 .
If further limiting of the rise or fall times to the power device is desired, an external resistance can be added
between the output of the driver and the power MOSFET gate. The external resistor also helps remove power
dissipation from the driver.
Driver outputs follow IN and SRE as previously described provided that VDD and 3V3 are above their respective
under-voltage lockout thresholds. When the supplies are insufficient, the chip holds both OUT1 and OUT2 low.
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It is worth reiterating the need mentioned in the supply section for sound high frequency design techniques in the
circuit board layout and bypass capacitor selection and placement. Some applications may generate excessive
ringing at the switch-inductor node. This ringing can drag SW to negative voltages that might cause functional
irregularities. To prevent this, carefull board layout and appropriate snubbing are essential. In addition, it may be
appropriate to couple SW to the inductor with a 1-Ω resistor, and then bypass SW to PGND with a low
impedance Schottky diode.
SINK/SOURCE CURRENT
SINK/SOURCE CURRENT
vs
vs
HIGH-SIDE DRIVER OUTPUT VOLTAGE
LOW-SIDE DRIVER OUTPUT VOLTAGE
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
I
SINK
I
V
= 12 V
SOURCE
VDD
V
= 12 V
VDD
I
SINK
I
SOURCE
I
I
SINK
SINK
V
= 5 V
VDD
I
V
I
= 5 V
SOURCE
VDD
SOURCE
5
0
1
2
3
4
6
0
1
2
3
4
5
6
OUT1 – High-Side Driver Output Voltage – V
OUT2 – Low-Side Driver Output Voltage – V
Figure 3.
Figure 4.
Current Sensing and Overload Protection
Since the UCD7230A is physically collocated with the high-current elements of the power converter, it is logical
that current be monitored by the chip. An internal instrumentation amplifier conditions current sense signals so
that they can be used by the control chip generating the PWM signal.
POS and NEG are inputs to an instrumentation amplifier circuit. This amplifier has a nominal gain of 48 and
presents its output at AO. This can be used to monitor either an external current sense shunt or a parallel RC
around the buck inductor shown in Figure 5. The shunt yields the highest accuracy and is insensitive to inductor
core saturation effects. It comes with the price of added power dissipation. Using the shunt, AO is calculated in
Equation 1.
AO = 48´I
(
´R
+ IO
SHUNT
)
OUT
(1)
The internal configuration of the instrumentation amplifier is such that AO is 0.6 V when POS – NEG = 0.
Because of this output offset, the amplifier can accurately pass information for both positive and negative load
current. The offset is controlled by IO. If IO is left to float, the offset is 0.6 V. 0.6 V is present at IO through an
internal 10-kΩ resistor and should be bypassed to AGND. If a higher value of offset is desired, a voltage in
excess of 0.66 V can be externally applied to IO. Once IO is forced above 0.66 V, the internal 10 kΩ is
disconnected, and the AO output offset is now equal to the voltage applied to IO.
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SW
IO
+
6
I/O Buffer
Amplifier
POS
8.33 kΩ
400 kΩ
8
9
Current Sense
Amplifier
R
C
+
SHUNT
AO
NEG
8.33 kΩ
400 kΩ
V
OUT
7
OUT
UDG-09171
Figure 5. Current Sense Using External Shunt
SW
IO
+
6
I/O Buffer
Amplifier
POS
NEG
R
POS
8.33 kΩ
400 kΩ
8
9
Current Sense
Amplifier
L
+
+
C
R
AO
8.33 kΩ
400 kΩ
V
OUT
7
R
NEG
C
OUT
UDG-09172
Figure 6. Lossless Average Output Current Sensing Using DC Resistance of the Output Inductor
Figure 6 also shows lossless current sensing utilizing an RC across the buck inductor to generate an analog of
the IR drop in the copper of the inductor. As long as the RPOS x C time constant is the same as the L/R of the
inductor and its parasitic equivalent series resistance, then the voltage on C is the same as the IR drop on the
parasitic inductor resistance. A resistor, RNEG = RPOS is used for amplifier bias current cancellation. The transfer
function of the amplifier is calculated in Equation 2.
AO = A ´I
(
´R
+ IO
COPPER
)
OUT
(2)
With the addition of RPOS and RNEG, the natural gain, A, of the current sense is predictably decreased as shown
in Equation 3.
48
A =
æ R
ö
÷
ø
POS
1+
ç
8.33kW
è
(3)
13
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For RPOS << 8.33 kΩ, the gain is 48. While the 400 kΩ and 8.33 kΩ are well matched, it is important to keep
RPOS as small as possible since they have absolute variation from chip-to-chip and over temperature. The graph
in Figure 7 shows the band of expected gain for A as a function of RPOS. The gain variation at RPOS = 1 kΩ
results in around ±4% error. However, the tolerance of the value of R in the inductor has a more significant effect
on measurement accuracy as does the temperature coefficient of R. Copper has a temperature coefficient of
approximately 3800 ppm/°C. For a 100°C rise in winding temperature, the dc resistance of the inductor increases
by 38%. The worst case scenario would be a cracked core or under-designed inductor in which cases the core
could tend towards saturation. In that scenario, inductor current could change slope drastically and is not
correctly modeled by the capacitor voltage.
.
CURRENT SENSE AMPIFIER GAIN
vs
POS INPUT RESISTANCE
49
Maximum Gain
Tolerance
47
Nominal
45
43
41
39
37
Minimum Gain
Tolerance
35
0
500
1000
1500
2000
R
– POS Input Resistance – W
POS
Figure 7. Current Sense Amplifier Gain as a Function of RPOS
The RC time constant is . The LR time constant is shown in Equation 5.
t
=
R
´ C
RC
POS
(4)
(5)
L
t
=
LR
R
When Equation 4 equals Equation 5, the voltage across the capacitor is the same as the voltage drop across the
equivalent resistance of the inductor. If the time constraints don’t match, (Equation 4 does not equal Equation 5)
the calculation of the ripple current amplitude can be incorrect. Load transients result in overshoot when tRC is
much shorter than tLR. Load transients result in undershoot when tRC is much longer than tLR
.
While the amplifier faithfully passes the sensed dc current signal, it should be noted that the amplifier is
bandwidth limited for normal switching frequencies. Therefore, AO represents a moving average of the sensed
current.
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The amplifier output can go up to 3.3 V, so reasonable designs limit full scale to 3.0 V. Should attenuation be
necessary, use a resistive divider between AO and the control chip A/D input as shown in Figure 8.
To
A0
7
A/D
UDG-09166
Figure 8. Attenuating and Filtering the Voltage Representation of the Average Output Current
While the current sense amplifier is useful for accurate current monitoring or controlling overload conditions,
extreme overload conditions must be handled in timeframes that are generally much shorter than the A/D of a
control chip can achieve. Therefore, there are two comparators on the UCD7230A to sense extreme overload
and protect the driven power MOSFETs.
Extreme current overload is handled in two ways by the UCD7230A. One is a comparator that monitors the
voltage between POS and NEG, or effectively the output current of the converter.. The other is a comparator that
monitors the voltage drop across the high-side MOSFET, or effectively the input current. Should either condition
exceed a preset value, OUT1 is immediately turned off for the remainder of the cycle.
To program the high-side MOSFET current limit threshold, a value of resistance from DLY to AGND must first be
chosen to establish a blanking time during which the comparator outputs are ignored or blanked. Blanking is
required because the high amplitude ringing that occurs on the rising edge of SW would otherwise cause false
triggering of the fault comparators. The required amount of blanking time is a function of the switching speed of
the high-side FET, the PCB layout, and whether or not a snubber network is being used. A value of 100ns after
the rising edge of SW is a typical starting point. In the UCD7230A, the blanking interval timing begins at the
rising edge of IN. Due to propagation delays and anti-cross-conduction intervals, there is approximately 45ns
delay from the rising edge of IN to the rising edge of SW. This propagation delay must be added to the required
amount of blanking time after the rising edge of SW when calculating the overall blanking time.
The overall blanking time is calculated in Equation 6.
t
ns » 5´R
kW
DLY ( )
BLANK ( )
(6)
where
•
RDLY is the resistor from DLY to AGND
RDLY should be limited to a range between 25 kΩ and 100 kΩ. The blanking interval should be kept as short as
possible, consistent with reliable fault detection. The blanking interval (minus the 45-ns propagation delay) sets
the minimum duty cycle pulse width where high-side fault detection is possible. When the on-time of the IN
pulses are narrower than the blanking time, the high-side fault detection comparator is held off for the entire
on-time and is, therefore, blind to any high-side faults.
Once RDLY has been chosen, the value of RCS+ can be calculated. RCS+ is the resistor from the CS+ pin to the
drain of the high-side FET which sets the high-side fault detection threshold. When the high-side FET is on, the
current flow in the FET produces a voltage drop across the device. The magnitude of this voltage is equal to the
RDS(on) times the current through the FET. An absolute maximum current level can be set during the design stage
and the resultant voltage drop across the FET can be calculated. This maximum voltage drop, ΔVMAX, sets the
high-side fault threshold.
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Internally, a high-speed comparator monitors the voltage between the SW pin and the CS+ pin when the
high-side FET is on. Whenever the voltage on the SW pin is lower than the voltage on the CS+ pin, a fault is
flagged. To prevent false tripping during the ringing that accompanies the rising edge of SW, the output of the
comparator is held off (blanked) for a time interval set by the DLY pin. The voltage on the CS+ pin is set by a
resistor connected from the pin to the high-side FET drain. The RCS+ resistor value is calculated from Equation 7.
DV
´R
DLY
MAX
R
=
CS+
1200
(7)
where
•
•
ΔVMAX is in mV
RCS+ and RDLY are in kΩ
For example, if ΔVMAX is 100 mV and RDLY is 50 kΩ, then RCS+ is 4.2 kΩ.
Equation 7 can be restated as Equation 8.
R
´I
´R
(
MAX DLY
)
DS on HOT
( )
R
=
CS+
1200
(8)
where
•
•
•
•
IMAX is the peak current flowing through the high-side FET when it is on
RCS+ and RDLY in kΩ
RDS(on) in mΩ
IMAX is in amperes
IMAX is the sum of the load current and one half of the inductor ripple current. As a general rule, the value of IMAX
should be set to about 150% of the expected maximum steady-state load current. This allows some headroom to
avoid nuisance fault events due to transient load currents and the inductor ripple current. With low inductor
values and lower switching frequencies, the magnitude of the inductor ripple current can be quite high. Be certain
to account for it in the IMAX calculation. Also, keep in mind that the RDS(on) of a FET has a large positive
temperature coefficient of approximately 4000 ppm/°C. The junction temperature of the FET is elevated when
operating at currents near the IMAX threshold. In Equation 9, use a value of RDS(on)HOT that is approximately 140%
of its typical room temperature value. Note that the FET, when turned on, is driven to a VGS enhancement
voltage of approximately the value of VDD. Most FET data sheets provide RDS(on) values for VGS values of 4.5 V
and 10 V. Most manufacturers provide a graph of RDS(on)) vs VGS. If provided, use the graph with the value of
VGS = VDD to determine the room temperature RDS(on) value.
A current sink proportional to RDLY pulls current through RCS+. This sets up a reference voltage drop equal to
ΔVMAX. It is important to connect the far end of the RCS+ resistor directly to the drain of the high-side FET. This
should be made with a separate, non-current-carrying trace. This ensures that only the RDS(on) of the FET
influences the fault threshold voltage and not the resistance of the PC board traces.
The blanking time for the output comparator is identical to the input comparator. The output comparator threshold
is calculated in Equation 9.
V
ILIM
V
=
CS out
(
)
10
(9)
where
•
•
VCS(out) is the threshold of allowed voltage between the POS and NEG pins
VILIM is the voltage on the ILIM pin
Note that the ILIM is internally connected to 0.5 V through a 42-kΩ resistor. Any voltage between 0.25 V and
1.0 V can be applied to ILIM. For voltages above 1.0 V, the maximum VCS(OUT) threshold is clamped to 0.1 V.
Possible methods for setting ILIM are shown in Figure 9.
When using the output comparator to monitor the voltage on the parallel sensing capacitor across the inductor,
the same caveats apply as described for the current sense amplifier.
Figure 9 through Figure 12 show different methods of setting the current limit voltage. Table 1 lists the current
limit value settings when using the GPIO outputs as show in Figure 9 only.
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UCD7230A
3V3
UCD7230A
Digital Controller
Digital Controller
VCC
1
2
1
2
3V3
VCC
GND
AGND
ILIM
AGND
GND
R
40 kW
20 kW
10 kW
2.5 kW
F
4
4
ILIM
GPIO1
GPIO2
GPIO3
GPIO4
PWM
UDG-09168
UDG-09167
Figure 9. Setting the ILIM Voltage GPIO Outputs
Figure 10. Setting the ILIM Voltage Using a PWM
Output
UCD7230A
Digital Controller
UCD7230A
1
2
3V3
VCC
GND
1
2
3V3
AGND
AGND
R2
R1
4
ILIM
C
F
4
ILIM
UDG-09169
UDG-09170
Figure 11. Setting the ILIM Voltage Using a
Resistor Divider
Figure 12. Setting the ILIM Voltage Using an
Internal Setpoint
Table 1. Current Limit Value Settings
CURRENT LIMIT (ILIM) SETPOINT
(mV)
GPIO3
GPIO2
GPIO1
GPIO4
ILIM (open)
ILIM0
500
0
OPEN
OPEN
OPEN
OPEN
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
0
ILIM1
140
290
430
570
720
860
1000
ILIM2
ILIM3
ILIM4
ILIM5
ILIM6
ILIM7
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If either comparator threshold is exceeded, OUT1 is immediately turned off for the remainder of the cycle and
CLF is asserted true. Upon the rising edge of IN, the switches resume normal operation, but the CLF assertion is
maintained. If a fault is not detected in this switching cycle, then the next rising edge of IN removes the CLF
assertion. However, if one of the comparators detects a fault, then CLF assertion continues. The control device
monitors CLF and decides how to handle the fault condition. During this monitoring period, the protection
comparators protect the power MOSFET switches on a cycle-by-cycle basis. If the output-sense comparator
(POS - NEG) detects continuous overcurrent, then the driver assumes 0% duty cycle until the current drops to a
safe value. Note that when a fault condition causes OUT1 to be driven low, OUT2 behaves as if the input pulse
had been terminated normally. In some fault conditions, it is advantageous to drive OUT2 low. SRE can be used
to cause OUT2 to remain low at the discretion of the control chip. This can be used to achieve faster discharge
of the inductor and also to fully disconnect the converter from the output voltage.
Startup Handshaking
The UCD7230A has a built-in handshaking feature to facilitate efficient start-up of the digitally controlled power
supply. At start-up the CLF flag is held high until all the internal and external supply voltages of the device are
within their operating range. Once the supply voltages are within acceptable limits, CLF goes low and the device
processes input commands. The digital controller should monitor CLF at start-up and wait for CLF to go low
before sending pwm information to the UCD7230A.
Thermal Management
The usefulness of a driver is greatly affected by the drive power requirements of the load and the thermal
characteristics of the device package. In order for a power driver to be used over a particular temperature range,
the package must allow for the efficient removal of the heat while keeping the junction temperature (TJ) within
rated limits. The UCD7230A is available in the QFN package with an exposed pad that removes thermal energy
from the semiconductor junction.
As illustrated in Reference [3 & 4], the QFN package offers a lead-frame die pad that is exposed at the base of
the package. This pad is soldered to the copper on the PC board (PCB) directly underneath the device package,
reducing the θJA. The PC board must be designed with thermal lands and thermal vias to complete the heat
removal subsystem, as summarized in Reference [3].
Note that the PowerPAD™ is not directly connected to any leads of the package. However, it is electrically and
thermally connected to the substrate which is the ground of the device. The PowerPAD™ should be connected to
the quiet ground (AGND) of the circuit.
REFERENCES
1. Power Supply Seminar SEM-1600 Topic 6: A Practical Introduction to Digital Power Supply Control, by
Laszlo Balogh, Texas Instruments Literature No. SLUP224
2. Power Supply Seminar SEM–1400 Topic 2: Design and Application Guide for High Speed MOSFET Gate
Drive Circuits, by Laszlo Balogh, Texas Instruments Literature No. SLUP133.
3. Application Report, Quad Flatpack No-Lead Logic Packages, Texas Instruments Literature No. SCBA017
4. Application Report, QFN/SON PCB Attachment, Texas Instruments Literature No. SLUA271
RELATED PRODUCTS
DEVICE
DESCRIPTION
Literature Number
SLUS766C
UCD9240
UCD9220
UCD9112
Digital PWM System Controller
Digital PWM System Controller
Digital Dual-Phase Synchronous Buck Controller
SLUS904
SLVS711
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PACKAGE OPTION ADDENDUM
www.ti.com
18-Dec-2009
PACKAGING INFORMATION
Orderable Device
UCD7230ARGWR
UCD7230ARGWT
Status (1)
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
VQFN
RGW
20
3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
VQFN
RGW
20
250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
UCD7230ARGWR
UCD7230ARGWR
UCD7230ARGWT
UCD7230ARGWT
VQFN
VQFN
VQFN
VQFN
RGW
RGW
RGW
RGW
20
20
20
20
3000
3000
250
330.0
330.0
180.0
180.0
12.4
12.4
12.4
12.4
5.3
5.25
5.25
5.3
5.3
5.25
5.25
5.3
1.5
1.1
1.1
1.5
8.0
8.0
8.0
8.0
12.0
12.0
12.0
12.0
Q2
Q2
Q2
Q2
250
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
UCD7230ARGWR
UCD7230ARGWR
UCD7230ARGWT
UCD7230ARGWT
VQFN
VQFN
VQFN
VQFN
RGW
RGW
RGW
RGW
20
20
20
20
3000
3000
250
367.0
370.0
195.0
210.0
367.0
355.0
200.0
185.0
35.0
55.0
45.0
35.0
250
Pack Materials-Page 2
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UCD7230A 替代型号
| 型号 | 制造商 | 描述 | 替代类型 | 文档 |
| UCD7232 | TI | Digital Control Compatible Synchronous-Buck Gate Driver With Current | 功能相似 |
|
UCD7230A 相关器件
| 型号 | 制造商 | 描述 | 价格 | 文档 |
| UCD7230ARGWR | TI | Digital Control Compatible Synchronous Buck Gate Driver with Current Sense Conditioning Amplifier | 获取价格 |
|
| UCD7230ARGWT | TI | Digital Control Compatible Synchronous Buck Gate Driver with Current Sense Conditioning Amplifier | 获取价格 |
|
| UCD7230PWP | TI | Digital Control Compatible Synchronous Buck 【4-A Drivers with Current Sense Conditioning Amplifier | 获取价格 |
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| UCD7230PWPG4 | TI | Digital Power Compatible Synchronous Buck Driver 20-HTSSOP -40 to 105 | 获取价格 |
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| UCD7230PWPR | TI | Digital Control Compatible Synchronous Buck Gate Drivers with Current Sense Conditioning Amplifier | 获取价格 |
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| UCD7230RG | TI | IC 0.02 A BUF OR INV BASED MOSFET DRIVER, QCC20, GREEN, QFN-20, MOSFET Driver | 获取价格 |
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| UCD7230RGW | TI | Digital Control Compatible Synchronous Buck 【4-A Drivers with Current Sense Conditioning Amplifier | 获取价格 |
|
| UCD7230RGWR | TI | Digital Control Compatible Synchronous Buck Gate Drivers with Current Sense Conditioning Amplifier | 获取价格 |
|
| UCD7230RGWRG4 | TI | Digital Power Compatible Synchronous Buck Driver 20-VQFN -40 to 105 | 获取价格 |
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| UCD7230RGWT | TI | Digital Control Compatible Synchronous Buck Gate Drivers with Current Sense Conditioning Amplifier | 获取价格 |
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