AD53500JRPZ [ADI]
IC 0.4 A BUF OR INV BASED PRPHL DRVR, PDSO20, POWER, SOIC-20, Peripheral Driver;
| 型号： | AD53500JRPZ |
| 厂家： | 
ADI |
| 描述： | IC 0.4 A BUF OR INV BASED PRPHL DRVR, PDSO20, POWER, SOIC-20, Peripheral Driver 驱动 光电二极管 接口集成电路 |
| 文件： | 总7页 (文件大小：100K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
High Speed, High Current
Capability Pin Driver
a
AD53500
FUNCTIONAL BLOCK DIAGRAM
FEATURES
–2 V to +6 V Output Range
2.5 ⍀ Output Resistance
2.5 ns Tr/Tf for a 3 V Step
300 MHz Toggle Rate
V
V
V
EE
CC
CC
V
EE
39nF
39nF
Can Drive 25 ⍀ Lines and Lower
Peak Dynamic Current Capability of 400 mA
Inhibit Leakage <1 A
V
H
V
DATA
HDCPL
2⍀
DATA
INH
On-Chip Temperature Sensor
DRIVER
V
OUT
INH
APPLICATIONS
V
L
V
Automatic Test Equipment
Semiconductor Test Systems
Board Test Systems
LDCPL
TV
CC
AD53500
Instrumentation and Characterization Equipment
THERM
1.0A/K
GND
GND
GND
GND
GND
PRODUCT DESCRIPTION:
of less than 10 ns with a 1000 pF capacitance. To test I/O
The AD53500 is a complete high speed driver designed for use
in digital or mixed signal test systems where high speed and high
output drive capabilities are needed. Combining a high speed
monolithic process and a unique surface mount package, this
product attains superb electrical performance while preserving
optimum packing densities and long-term reliability thanks to an
ultrasmall 20-lead, PSOP package with built-in heat sink.
devices, the pin driver can be switched into a high impedance
state (Inhibit Mode), electrically removing the driver from the
path. The pin driver leakage current in inhibit is typically less
than 1 µA and output capacitance is typically less than 18 pF.
Transitions from HI/LO or to inhibit are controlled through the
data and inhibit inputs. The input circuitry utilizes high-speed
differential inputs with a common-mode range of –2 V to +5 V.
This allows for direct interface to the precision of differential
ECL timing or the simplicity of stimulating the pin driver from a
single-ended CMOS or TTL logic source or any combination
over the common-mode range. The analog logic HI/LO inputs
are equally easy to interface, typically requiring 50 µA of bias
current.
High and low reference levels can be set within a –2 V to +6 V
range with low offset voltage and high gain accuracy. A 2.5 Ω
output resistance allows use of an external backmatch resistor for
application to 50 Ω, 25 Ω or other complex impedance load
requirements. Without a backmatch resistor it is also capable of
driving highly capacitive loads, typically achieving a rise/fall time
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
World Wide Web Site: http://www.analog.com
© Analog Devices, Inc., 1999
(All specifications are at T = +85؇C ؎ 5؇C, +V = +10 V ؎ 3%, –V = +6 V ؎ 3%
AD53500–SPECIFICATIONS
J
S
S
unless otherwise noted. All temperature coefficients are measured over T = 75؇C–95؇C). (In test figures, voltmeter loading is 1 M⍀ or greater,
J
scope probe loading is 100 k⍀ in parallel with 5 pF.) 39 nF capacitors must be connected between VCC and VHDCPL and between VEE and VLDCPL
.
Parameter
Min
Typ
Max Units
Test Conditions
DIFFERENTIAL INPUT CHARACTERISTICS
(DATA to DATA, INH to INH)
Common-Mode Input Voltage
Differential Input Range
–2
+5
Volts
ECL or TTL
ECL = –0.8 V/–1.8 V, TTL = 0 V/5 V
VCM = –2 V, +5 V
Bias Current
±100
µA
REFERENCE INPUTS
Bias Currents
–50
+50
µA
VL, VH = 5 V
OUTPUT CHARACTERISTICS
Logic High Range
Logic Low Range
+1
–2
0.1
+6
+2
8
Volts
Volts
Volts
DATA = H, VL = –2 V, VH = +1 V to +6 V
DATA = L, VL = –2 V to +2 V, VH = +6 V
VL = –0.05 V, VH = +0.05 V and
VL = –2 V, VH = +6 V
Amplitude (VH and VL)
VH, VL Interaction
Absolute Accuracy
VH Offset
VH Gain + Linearity Error
VL Offset
–10
+10
mV
100 mV Output Amplitude
–100
–100
+100 mV
DATA = H, VH = 0 V, VL = –2 V
±0.3 ±5
% of VH + mV DATA = H, VL = –2 V, VH = +1 V to +6 V
+100 mV
DATA = L, VL = 0 V, VH = +6 V
VL Gain + Linearity Error
Offset TC, VH or VL
Output Resistance
±0.3 ±5
0.5
2.5
% of VL + mV DATA = L, VL = –2 V to +2 V, VH = +6 V
mV/°C
VL, VH = 0 V, +5 V and –2 V, 0 V
VH = +3 V, VL = 0 V, IOUT = 0, –30 mA,
+30 mA
1.5
5.5
Ω
Dynamic Current Limit
Static Current Limit
400
mA
CBYP = 39 nF, VH = +5 V, VL = 0 V
CLOAD = 1000 pF, Tr/Tf = 10 ns
Output to –2 V, VH = +6 V, VL = –1 V,
DATA = H and Output to +6 V, VH = +6 V,
VL = –2 V, DATA = L
60
–180
180
–60
mA
mA
DYNAMIC PERFORMANCE, DRIVE
(VH and VL)
Propagation Delay Time
2.5
1
ns
Measured at 50%, VH = +400 mV,
VL = –400 mV
Measured at 50%, VH = +400 mV,
VL = –400 mV
Measured at 50%, VH = +400 mV,
VL = –400 mV
Propagation Delay TC
ps/°C
ps
Delay Matching, Edge-to-Edge
100
Rise and Fall Time
1 V Swing
3 V Swing
0.85
2.5
4.0
ns
ns
ns
Measured 20%–80%, VL = 0 V, VH = 1 V
Measured 10%–90%, VL = 0 V, VH = 3 V
Measured 10%–90%, VL = 2 V, VH = 3 V
5 V Swing
Rise and Fall Time TC
1 V Swing
3 V Swing
±1
±2
±3
ps/°C
ps/°C
ps/°C
Measured 20%–80%, VL = 0 V, VH = 1 V
Measured 10%–90%, VL = 0 V, VH = 3 V
Measured 10%–90%, VL = 0 V, VH = 5 V
5 V Swing
Overshoot, Undershoot and Preshoot
Settling Time
+5.0 +30
% of Step + mV VH–VL = 0.5 V, 1 V, 3 V, 8 V
to 15 mV
to 4 mV
Delay Change vs. Pulsewidth
40
8
100
ns
µs
ps
VL = 0 V, VH = 0.5 V
VL = 0 V, VH = 0.5 V
VL = 0 V, VH = 2 V, Pulsewidth = 2.5 ns/
Period = 10 ns and Pulsewidth = 30 ns/
Period = 120 ns
Minimum Pulsewidth
3 V Swing
3.8
5.5
300
ns
VL = 0 V, VH = 3 V, Output = 2.7 V p-p,
Measure at 50%
VL = 0 V, VH = 5 V, Output = 4.5 V p-p,
Measure at 50%
5 V Swing
ns
Toggle Rate
MHz
VL = –1.8 V, VH = –0.8 V, VOUT > 600 mV p-p
REV. 0
–2–
AD53500
Parameter
Min
Typ
Max Units
Test Conditions
DYNAMIC PERFORMANCE, INHIBIT
Delay Time, Active to Inhibit
2
2
10
10
ns
Measured at 50%, VH = +2 V,
VL = –2 V, 50 Ω Terminated to Ground
Measured at 50%, VH = +2 V,
VL = –2 V, 50 Ω Terminated to Ground
VH = 0 V, VL = 0 V
Delay Time, Inhibit to Active
ns
I/O Spike
<200
mV, p-p
Output Leakage
Output Capacitance
PSRR, Drive Mode
–1.0
+1.0 µA
VOUT = –2 V to +6 V
Driver Inhibited
VS = VS ± 3%
18
35
pF
dB
POWER SUPPLIES
Total Supply Range
Positive Supply
16
+10
–6
V
V
V
Negative Supply
Positive Supply Current
Negative Supply Current
Total Power Dissipation
Temperature Sensor Gain Factor
85
88
1.37
1.0
95
98
1.54
mA
mA
W
µA/K
RLOAD = 10 kΩ, VSOURCE = +10 V
NOTES
Connecting or shorting the decoupling capacitors to ground will result in the destruction of the device.
Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS1
V
OUT
V
= (MAX) = +7V
OUT
Power Supply Voltage
7
+VS to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +11 V
–VS to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –7 V
+VS to –VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +18 V
Inputs
6
5
4
3
2
1
DATA, DATA, INH, INH . . . . . . . . . . . . . . . . +5 V, –3 V
DATA to DATA, INH to INH . . . . . . . . . . . . . . . . ±3 V
VH, VL to GND . . . . . . . . . . . . . . . . . . . . . . . . . +7 V, –3 V
VH to VL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +10 V, 0 V
Outputs
V
, V
L
H
VOUT Short Circuit Duration to Ground . . . . . . .Indefinite2
VOUT Range in Inhibit Mode . . . . . . . . . . . . . See Figure 1
–2 –1
1
2
3
4
5
6
–1
–2
–3
3
VHDCPL . . . . . . . . Do Not Connect Except for Cap to VCC
VLDCPL . . . . . . . . . Do Not Connect Except for Cap to VEE
3
V
= (MIN) = –3V
OUT
THERM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +VS, 0 V
Environmental
Operating Temperature (Junction) . . . . . . . . . . . . . .+175°C
Storage Temperature . . . . . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 10 sec)4 . . . . . . . . . .+260°C
FIGURE 1 SHOWS THE MAXIMUM ALLOWABLE LIMITS FOR V
AS A FUNCTION
OUT
OF V
AND V
WHEN THE DRIVER IS OPERATING IN INHIBIT MODE. THE
HIGH
LOW
LIMITS, AS STATED BEFORE, ARE MAXIMUM RATINGS ONLY, AND SHOULD NOT
BE USED AS THE PART'S NORMAL OPERATING RANGE. THIS RANGE APPLIES
ONLY TO SUPPLIES OF +V = +10V AND –V = –6V AND SHOULD BE DERATED
S
S
PROPORTIONALLY FOR LOWER SUPPLIES.
NOTES
V
/ V
HIGH
LOW
1Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Absolute maximum limits apply
individually, not in combination. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.
Figure 1. Absolute Maximum Ratings for VOUT
2Output short circuit protection is guaranteed as long as proper heat sinking is
employed to ensure compliance with the operating temperature limits.
3The VHDCPL and VLDCPL capacitors may be replaced by a low value resistor for higher
dc-current drive capability.
4To ensure lead coplanarity (±0.002 inches) and solderability, handling with bare
hands should be avoided and the device should be stored in environments at 24°C
± 5°C (75°F ± 10°F) with relative humidity not to exceed 65%.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD53500 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. 0
–3–
AD53500
PIN CONFIGURATION
Table I. Pin Driver Truth Table
Output
State
1
2
THERM
20
V
V
CC
DATA
DATA
INH
INH
19 TV
CC
CC
0
1
0
1
1
0
1
0
0
0
1
1
1
1
0
0
VL
VH
Hi-Z
Hi-Z
3
V
H
18
17
V
HDCPL
4
GND
GND
5
16 GND
V
OUT
AD53500
TOP VIEW
(Not to Scale)
6
15
14
13
12
V
L
GND
7
GND
V
LDCPL
Table II. Package Thermal Characteristics
8
DATA
DATA
V
V
EE
EE
9
Air Flow, FM
JC, ؇C/W
JA, ؇C/W
10
11 INH
INH
50
400
3.28
3.91
49.1
33.74
PIN FUNCTION DESCRIPTIONS
Pin Name
Pin Number
Description
VCC
1, 2
Positive Power Supply. Both pins should be connected to minimize inductance and allow
maximum speed of operation. VCC should be decoupled to GND with a low inductance
0.1 µF capacitor.
VEE
8, 9
Negative Power Supply. Both pins should be connected to keep the inductance down and
allow maximum speed of operation. VEE should be decoupled to GND with a low inductance
0.1 µF capacitor.
GND
VL
4, 6, 14, 16, 17
Device Ground. These pins should be connected to the circuit board’s ground plane at the
pins.
Analog input that sets the voltage level of a Logic 0 of the driver. Determines the driver out-
put for DATA > DATA.
Analog input that sets the voltage level of a Logic 1 of the driver. Determines the driver out-
15
18
VH
put for DATA > DATA.
VOUT
VHDCPL
5
3
The Driver Output.
Internal supply decoupling for the output stage. This pin is connected to VCC through a
39 nF (minimum) capacitor.
VLDCPL
7
Internal supply decoupling for the output stage. This pin is connected to VEE through a
39 nF (minimum) capacitor.
INH, INH
DATA, DATA
10, 11
13, 12
Differential inputs that control the high impedance state of the driver. When INH > INH, the
driver goes into a high impedance state.
Differential inputs that determine the high and low state of the driver. Driver output is high
for DATA > DATA.
TVCC
THERM
19
20
Temperature Sensor Startup Pin. This pin should be connected to VCC.
Temperature sensor output pin. A resistor (10 kΩ) should be connected between THERM
and VCC. The approximate die temperature can be determined by measuring the current
through the resistor. The typical scale factor is 1 µA/K.
ORDERING GUIDE
Shipment Method,
Package
Quantity Per
Package
Model
Description
Shipping Container Option
AD53500JRP 20-Lead Power SOIC Tube, 38 Pieces
RP-20
REV. 0
–4–
AD53500
APPLICATION INFORMATION
capacitor to the positive supply (and the VLDCPL capacitor to the
negative supply)—failure to do so causes considerable thermal
stress in the current-limiting resistor(s) during normal supply
sequencing and may ultimately cause them to fail, rendering the
part nonfunctional. Finally, the AD53500 may appear to func-
tion normally for small output steps (less than 3 V or so) if one
or both of these caps is absent, but it may exhibit excessive rise
or fall times for steps of larger amplitude.
Power Supply Distribution, Bypassing and Sequencing
The AD53500 draws substantial transient currents from its
power supplies when switching between states and careful de-
sign of the power distribution and bypassing is key to obtaining
specified performance. Supplies should be distributed using
broad, low inductance traces or (preferably) planes in a multi-
layered board with a dedicated ground-plane layer. All of the
device’s power supply pins should be used to minimize the inter-
nal inductance presented by the part’s bond wires. Each supply
must be bypassed to ground with at least one 0.1 µF capacitor;
chip-style capacitors are preferable as they minimize inductance.
One or more 10 µF (or greater) Tantalum capacitors per board
are also advisable to provide additional local energy storage.
The AD53500 does not require special power-supply sequenc-
ing. However, good design practice dictates that digital and
analog control signals not be applied to the part before the sup-
plies are stable. Violating this guideline will not normally de-
stroy the part, but the active inputs can draw considerable
current until the main supplies are applied.
The AD53500’s current-limit circuitry also requires external
bypass capacitors. Figure 2 shows a simplified schematic of the
positive current-limit circuit. Excessive collector current in
output transistor Q49 creates a voltage drop across the 5 Ω
resistor, which turns on PNP transistor Q48. Q48 diverts the
rising-edge slew current, shutting down the current mirror and
removing the output stage’s base drive. The VHDCPL pin should
be bypassed to the positive supply with a 0.039 µF capacitor,
while the VLDCPL pin (not shown) requires a similar capacitor to
the negative supply. These capacitors ensure that the AD53500
does not current-limit during normal output transitions up its
full 8 V rated step size. Both capacitors must have minimum-
length connections to the AD53500. Here again, chip capacitors
are ideal.
V+
5⍀
Q48
V
HDCPL
RISING-EDGE SLEW
CONTROL CURRENT
LEVEL-SHIFTED
LOGIC DRIVE
V
H
V–
Q49
Q50
OUT
Several points about the current-limit circuitry should be noted.
First, the limiting currents are not tightly controlled, as they are
functions of both absolute transistor VBE and junction tempera-
ture; higher dc output current is available at lower junction
temperatures. Second, it is essential to connect the VHDCPL
Figure 2. Simplified Schematic of the AD53500 Output
Stage and Positive Current-Limit Circuitry
REV. 0
–5–
AD53500
Figure 3. Evaluation Board Schematic
REV. 0
–6–
AD53500
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
20-Lead Thermally Enhanced Small Outline Package (PSOP)
(RP-20)
0.5118 (13.00)
0.4961 (12.60)
20
11
0.1890 (4.80) 0.4193 (10.65)
0.1791 (4.55) 0.3937 (10.00)
HEAT
SINK
0.2992 (7.60)
0.2914 (7.40)
1
10
PIN 1
0.3340 (8.61)
0.3287 (8.35)
0.1043 (2.65)
0.0926 (2.35)
8؇
0؇
0.0201 (0.51)
0.0130 (0.33)
0.0500
(1.27)
BSC
0.0118 (0.30)
0.0295 (0.75)
0.0098 (0.25)
SEATING
PLANE
0.0500 (1.27)
0.0057 (0.40)
؋
45؇ 0.0040 (0.10)
STANDOFF
REV. 0
–7–
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