AD53508JP [ADI]
PPMU Circuit; PPMU电路
| 型号： | AD53508JP |
| 厂家： | 
ADI |
| 描述： | PPMU Circuit |
| 文件： | 总8页 (文件大小：127K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
a
PPMU Circuit
AD53508
FEATURES
Dual Measurement Channels
Precision Four-Quadrant-Per-Pin V/I Source
Programmable Current Force Ranges
؎204.8 A and ؎2.048 mA
Five Current Measurement Ranges
204.8 nA to ؎2.048 mA
Output Voltage Range: –4 V to +9 V
Power Supplies: +15 V, +5 V, and –10 V
44-Lead Plastic J-Leaded Chip Carrier Package
The device provides a remote force/sense capability to ensure
accuracy at the tester pin. A guard output is available to drive
the shield of a force/sense pair.
Two input references per channel permit controlled switching to
different voltage or current levels. The forced voltage or current
levels can be switched back to the measurement system to read
back the analog levels for system calibration.
The circuit is powered by +15 V, +5 V and –10 V supplies and
dissipates 230 mW nominally.
Recommended Use of the PPMU with AD53032 DCL
The PPMU can be used with the AD53032 DCL to extend the
Current Force Range beyond 2 mA VCOM can be set to the
maximum spec allowance of 8 V, which would allow the maxi-
mum Current Force of IOL of 35 mA. The combination of the
PPMU and the DCL would have a few benefits including:
APPLICATIONS
Can Be Used with the AD53032 DCL to Extend Current
Force Range to 35 mA
GENERAL DESCRIPTION
The AD53508 is a custom dual-channel parametric measure-
ment circuit for use in semiconductor automatic test equipment.
It contains programmable modes to force a pin voltage and
measure its current or to integrate and hold a current value.
Alternatively, a current can be forced and the compliance volt-
age measured.
1. Accurately measuring low currents.
2. Can take parallel measurements by using one PMU per pin.
FUNCTIONAL BLOCK DIAGRAM
S8
S9
SENSE
SENSE
FORCE
AD53508
EXT RC
MAIN
40pF
S6
DAC1
C1
R1
R2
S7
INT/IM
S10
S11
S12
S13
S14
S15
S16
DAC2
VF
IF
S4
S5
ENABLE
INTEGRATE
1.25R
DIFF
1k⍀
2mA
+2.5V
S17
DSR
VM
IM
S2
S3
10k⍀
200A
R
R
OUTPUT
UNITY
S1
MEAS OUT
CON
1.25R
GUARD
S18
GUARD
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
World Wide Web Site: http://www.analog.com
© Analog Devices, Inc., 1999
AD53508–SPECIFICATIONS (TA = 25؇C, rated power supplies unless otherwise noted)
Parameter
Condition
Min
Typ
Max
Unit1
VOLTAGE FORCE/MEASURE MODE
Voltage Swing, 2 mA Range
2 mA Drive
–4
–5
+9
+12
V
V
100 µA Drive
ACCURACY
Gain ( 0.1% Tolerance)
Offset Error
0.999
1.001
15
V/V
mV
Gain Nonlinearity (Relative to Endpoints)
Current Measure CMRR (at MEAS_OUT)
0.02
0.31
% of Span
mV/V
DRIFT
Gain Error Temperature Coefficient
20
ppm (PV
or MV)/°C
µV/°C
Offset Drift
100
CURRENT FORCE/MEASURE MODE RANGES
0 (High)
1 (Low)
2.0
200
mA
µA
ACCURACY—HIGH RANGE
Transconductance ( 3% Tolerance)
Transresistance ( 3% Tolerance)
Offset Error
Gain Nonlinearity (Relative to Endpoints)
Output Compliance Voltage-Induced
Transconductance/Error
Force Mode
Measure Mode
0.776
1.21
0.8
1.25
0.824
1.29
40
mA/V
V/mA
µA
0.05
% of Span
Force Mode
–0.2
+0.4
µA/V
DRIFT—HIGH RANGE
Gain Error Temperature Coefficient
+10/–60
400
ppm (PV
or MV)/°C
nA/°C
Offset Drift
ACCURACY—LOW RANGE
Transconductance ( 3% Tolerance)
Transresistance ( 3% Tolerance)
Offset Error
Gain Nonlinearity (Relative to Endpoints)
Output Compliance Voltage-Induced
Transconductance/Error
Force Mode
Measure Mode
77.6
12.1
80
12.5
82.4
12.9
4
µA/V
V/mA
µA
0.05
% of Span
Force Mode
–0.02
+0.04
µA/V
DRIFT—LOW RANGE
Gain Error Temperature Coefficient
+10/–60
40
ppm (PV
or MV)/°C
nA/°C
Offset Drift
CURRENT MEASURE INTEGRATE MODE RANGES
High
Medium
Low
20.0
2.0
200
µA
µA
nA
ACCURACY—HIGH RANGE
Transresistance Error ( 3% Tolerance)
Offset Error
0.121
0.125
0.129
400
V/µA
nA
Gain Nonlinearity (Relative to Endpoints)
Output Compliance Voltage-Induced Transresistance Error
0.05
2.5
% of Span
nA/V of Output
DRIFT—HIGH RANGE
Gain Error Temperature Coefficient
Offset Drift
20
2
ppm MV/°C
nA/°C
ACCURACY—MEDIUM RANGE
Transresistance Error ( 3% Tolerance)
Offset Error
1.21
1.25
1.29
40
V/µA
nA
Gain Nonlinearity (Relative to Endpoints)
Output Compliance Voltage-Induced Transresistance Error
0.05
0.25
% of Span
nA/V of Output
DRIFT— MEDIUM RANGE
Gain Error Temperature Coefficient
Offset Drift
20
250
ppm MV/°C
pA/°C
–2–
REV. 0
AD53508
Parameter
Condition
Min
Typ
Max
Unit1
ACCURACY—LOW RANGE
Transresistance Error ( 3% Tolerance)
Offset Error
0.0121 0.0125 0.0129
V/nA
nA
4
Gain Nonlinearity (Relative to Endpoints)
Output Compliance Voltage-Induced Transresistance Error
0.05
0.025
% of Span
nA/V of Output
DRIFT—LOW RANGE
Gain Error Temperature Coefficient
Offset Drift
20
70
ppm MV/°C
pA/°C
DISABLE MODE2
Voltage Swing, 2 mA Range
2 mA Drive
–4
–5
+9
+12
V
V
100 µA Drive
ACCURACY
Gain ( 0.1% Tolerance)
Offset Error
0.999
1.001
15
V/V
mV
Gain Nonlinearity (Relative to Endpoints)
Current Measure CMRR (at MEAS_OUT)
0.02
0.31
% of Span
mV/V
DRIFT
Gain Error Temperature Coefficient
20
ppm (PV or
MV)/°C
µV/°C
Offset Drift
100
OTHER SPECIFICATIONS
Power Supply Rejection Ratio
f < 40 Hz, VCC
f < 40 Hz, VEE
f = 40 kHz, VCC
f = 40 kHz, VEE
70
60
35
25
dB
dB
dB
dB
CURRENT MEASURE HOLD MODE LEAKAGE
CROSSTALK3
TAMB = +70°C
1.2
nA
0.02
% of Span
SETTLING TIMES TO 0.01%
Voltage Force and Guard Voltage
CLOAD = 100 pF
20
2
50
2
µs
C
LOAD = 2000 pF
ms
µs
Current Force (200 µA Range)
MEAS_OUT Pin
ZLOAD = 100 pFʈ50 kΩ
CLOAD = 20 pF
µs
SHORT CIRCUIT CURRENT LIMIT MAGNITUDE
GUARD SCC LIMIT MAGNITUDE
Any Output Except Guards 8.5
20
10
0
mA
mA
mV
µA
2.5
GUARD OFFSET (FROM SENSE INPUT PIN)
IB (DAC1, DAC2) CURRENT
–65
–25
1.0
DIGITAL INPUTS
VIH
2.4
V
VIL
0.8
10
V
µA
IIN (Input leakage current)
POWER SUPPLIES
VCC (Positive Analog Supply Voltage)
VEE (Negative Analog Supply Voltage)
14.0
–10.5
4.75
5
15.0
–10.0
5.0
15.75
–9.0
5.25
15
V
V
V
mA
mA
V
DD (Logic Supply Voltage)
ICC (Positive Analog Supply Current)
EE (Negative Analog Supply Current)
IDD (Logic Supply Current Is 0 with Inputs at Rails,
Worst Case @ 2.4 VIN
I
–15
–5
)
8
mA
NOTES
1PV = Programmed Value, MV = Measured Value, FSR = Full-Scale Range = span.
2Output connected: DAC2 and 2 mA range selected, unconditionally.
3f < 40 Hz, both channels in current force mode; other channel output voltage swinging rail to rail.
Specifications subject to change without notice.
REV. 0
–3–
AD53508
ABSOLUTE MAXIMUM RATINGS*
(TA = 25°C unless otherwise noted)
PIN FUNCTION DESCRIPTIONS
Pin Name
Description
Min
Max
Unit Condition
1
2
3
4
5
6
7
8
9
DSR_2.5
2.5 V Reference Input
VDD to VEE
VCC to VEE
VDD to DGND
–0.3
–0.3
–0.3
+26.4
+26.4
+6
VCC+0.3
700
V
V
V
V
DAC2_A
DAC1_A
EXT_RC_A
C1_A
First of Two Switchable Inputs
Second of Two Switchable Inputs
External RS and C Common
External Capacitor
Digital Inputs to DGND –0.3
Power Dissipation
mW TA ≤ +75°C
R1_A
External Resistor
Operating Temperature
Range
Storage Temperature
Lead Temperature
Force/Sense Outputs
R2_A
External Resistor
25
–60
70
+125
+300
°C
°C
SENSE_A
FORCE_A
Sense Input
°C
Soldering (10 sec)
Force Output
VEE–0.8 VCC+0.8
V
Or 75 mA,
10 GUARD_A
11 MEAS_OUT_A
12 VCC
Guard Drive Output
Whichever Is Less
Measurement Output
+15 V Analog Supply
Connect Measure Output to Bus
–10 V Analog Supply
*
Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. These are stress ratings only; functional operation of
the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
13 M_CON_A*
14 VEE
15 FORCE_I_A*
16 FORCE_EN_A*
17 DAC1_SEL_A*
18 INTEG_A*
19 HOLD_A*
20 I_RANGE0_A*
21 I_RANGE1_A*
22 VERIFY*
Force V (When Hi) or I (When Lo)
Control Input
Select DAC1 (When Lo) or DAC2
Control Input
ORDERING GUIDE
Temperature
Range
Package
Description
Package
Option
Control Input
Model
Select 2 mA Range (Active Lo)
Select 200 µA Range (Active Lo)
Measure Forced Voltage or Current
AD53508JP 25°C to 70°C
Plastic Leaded
Chip Carrier
P-44A
23 OUTPUT_CON_A* Connect Pin Drive (Active Lo)
24 OUTPUT_CON_B* Connect Pin Drive (Active Lo)
PIN CONFIGURATION
25 I_RANGE1_B*
26 I_RANGE0_B*
27 HOLD_B*
28 INTEG_B*
29 DAC1_SEL_B*
30 FORCE_EN_B*
31 FORCE_I_B*
32 DIGGND
33 M_CON_B*
34 VDD
Select 200 µA Range (Active Lo)
Select 2 mA Range (Active Lo)
Control Input
Control Input
6
5
4
3
2
1
44 43 42 41 40
Select DAC1 (When Lo) or DAC2
Control Input
PIN 1
IDENTIFIER
7
8
R2 A
SENSE A
FORCE A
GUARD A
39 R2
B
Force V (When Hi) or I (When Lo)
Digital Ground
38 SENSE B
9
37
FORCE B
10
36
35
34
33
GUARD B
MEAS OUT B
VDD
Connect Measure Output to Bus
+5 V Digital Supply
MEAS OUT A 11
VCC 12
AD53508
TOP VIEW
13
(Not to Scale)
M CON B*
M CON A*
35 MEAS_OUT_B
36 GUARD_B
37 FORCE_B
38 SENSE_B
39 R2_B
Measurement Output
Guard Drive Output
VEE 14
32 DIGGND
31
15
16
FORCE I A*
FORCE I B*
30
29
FORCE EN B*
DAC1 SEL B*
FORCE EN A*
Force Output
DAC1 SEL A* 17
Sense Input
External Resistor
18 19 20 21 22 23 24 25 26 27 28
40 R1_B
External Resistor
41 C1_B
External Capacitor
* = ACTIVE LO
42 EXT_RC_B
43 DAC1_B
External RS and C Common
Second of Two Switchable Inputs
First of Two Switchable Inputs
44 DAC2_B
*
= Active Lo
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD53508 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
–4–
REV. 0
AD53508
Table I. Data Table
Data Latch Bits
S1 S2
S13,
S10
S15,
S14
S3
S4
S5
S6
S7
S9
S17
S8
S16
S11
S12
S18
Voltage Force/Current Measure
Irange 0
On
Irange 1
On
Integrate Range
On
Integrate
On
Off
On
On
On
On
On
On
On
On
On
On
Off
Off
Off
Off
Off
On
On
On
On
On
Off
Off
Off
Off
Off
Off
Off
Off
Off
On
Off
Off
Off
Off
On
On
On
On
On
Off
On
On
On
Off
Off
On
Off
Off
Off
Off
Off
On
Off
Off
Off
Off
Off
On
On
Off
Off
Off
On
On
On
On
On
On
On
On
Off
Off
Off
Hold/Measure
On Off
Current Force/Voltage Measure
Irange 0
On
Irange 1
On
On
Off
Off
On
On
On
On
Off
Off
Off
Off
Off
Off
On
On
On
On
On
Off
Off
On
Off
Off
Off
Off
On
On
On
Off
Off
Disable Mode: Output Connected
X
X
X
On
On
Off
On
X
Off
Off
On
Off
X
Off
On
On
X
On
Off
Off
X
Off
Off
Off
On
X
Off
Off
Off
Off
X
On
On
On
Off
X
X
On
On
On
Off
X
Off
Off
Off
Off
X
Off
Off
Off
Off
X
Off
Off
Off
On
X
On
On
On
Off
X
Verify/Voltage Force
On On Off
On
On
On
X
Verify/Current Force
On
Off
On
Disconnect
X
X
X
DAC2 Select: Enabled
X
X
X
Off
On
CAPACITOR
CHARGE
INTEGRATE*
HOLD*
DISCHARGE
CAPACITOR
INTEGRATE
HOLD
* = ACTIVE LO
Figure 1. Integrate/Current Measure Timing Diagram
Table II. Truth Table
* = Active LO
FV/MI 2 mA
FV/MI 200 mA
FV/MI Integrate DAC1
Voltage Inte-
FV/MI Integrate DAC 2
Voltage Inte-
FI/MV 2 mA
FI/MV 200 µA
FV/Verify
FI/Verify
Disconnect
Disable
Control
Input
Output
DAC1
LO
HI
DAC2
DAC1
LO
HI
DAC2
Settle
LO
HI
grate
LO
HI
Hold
LO
HI
Settle
LO
HI
grate
LO
HI
Hold
LO
HI
DAC1
LO
HI
DAC2
DAC1
LO
HI
DAC2
DAC1
LO
LO
HI
DAC2
DAC1
LO
LO
LO
LO
LO
HI
DAC2
LO
LO
LO
LO
HI
Connected
M_CON*
LO
HI
HI
LO
HI
HI
HI
LO
HI
LO
LO
HI
HI
LO
HI
HI
HI
HI
LO
LO
LO
HI
LO
HI
LO
LO
HI
LO
HI
HI
HI
X
X
X
X
X
X
X
X
X
X
HI
X
VERIFY*
X
FORCE_I*
FORCE_EN*
DAC1_SEL*
INTEG*
HI
HI
HI
HI
HI
HI
HI
HI
LO
LO
LO
HI
LO
LO
HI
LO
LO
LO
HI
LO
LO
HI
X
LO
LO
HI
LO
LO
HI
LO
LO
HI
LO
LO
LO
HI
LO
LO
LO
LO
HI
LO
HI
LO
HI
LO
HI
LO
LO
HI
HI
X
HI
LO
HI
LO
LO
HI
HI
HI
HI
X
HOLD*
HI
HI
HI
HI
HI
HI
HI
HI
HI
HI
HI
X
I_RANGE0*
I_RANGE1*
LO
HI
HI
HI
HI
HI
HI
LO
HI
LO
HI
HI
HI
X
X
X
X
LO
LO
HI
HI
HI
HI
HI
HI
LO
LO
LO
LO
X
X
X
X
X
OUTPUT_CON* LO
LO
LO
LO
LO
LO
LO
LO
LO
LO
LO
LO
LO
LO
REV. 0
–5–
AD53508
4. Computations for F1 are:
PPMU APPLICATION NOTES
F1 × 0.25 = LOW + 1 × (HIGH – LOW)/4
F1 × 0.50 = LOW + 2 × (HIGH – LOW)/4
F1 × 0.75 = LOW + 3 × (HIGH – LOW)/4
The PPMU can be used in two modes: 1. VOLTAGE FORCE
with CURRENT MEASURE or VERIFY CURRENT FORCE;
2. CURRENT FORCE with VOLTAGE MEASURE or
VERIFY VOLTAGE FORCE. In both modes the following
setup is recommended:
Where LOW = –Full Scale and HIGH = +Full Scale.
The linearity tests for measuring current are as follows (at the
MEAS_OUT pin):
1. The value of the external integrate capacitor (EXT_RC to
C1) is 10 nF.
1. The voltage is constant for these measurements.
2. MEAS_OUT pin is loaded with 1 MΩ to ground.
2. The four ranges (M1, M2, M3, M4) correspond to
CURRENT MEASURE ranges (200 nA, 20 µA, 200 µA,
and 2 mA respectively).
3. VCC = +15.0 V, VDD = +4.5 V, DIGGND = 0.0 V,
V
EE = –10 V, DSR = 2.5 V unless otherwise stated.
4. A 10 Ω resistor in series with the FORCE pin.
5. A 1 kΩ resistor in series with the SENSE pin.
3. The endpoints of the linearity curve are determined by the
–full scale (or LOW), and the +full scale (or HIGH) read-
ings at the same FORCE pin voltage.
IN VOLTAGE FORCE WITH CURRENT MEASURE OR
VERIFY CURRENT FORCE
4. Using these endpoints, gain nonlinearity is computed and
tested at the 1/4 scale, 1/2 scale, and 3/4 scale points.
To measure the leakage in the current measure and hold mode,
the PPMU has to be into the Force Voltage/Measure Current
Integrate mode.
5. Computations for M1 are:
M1 × 0.25 = LOW + 1 × (HIGH – LOW)/4
M1 × 0.50 = LOW + 2 × (HIGH – LOW)/4
M1 × 0.75 = LOW + 3 × (HIGH – LOW)/4
1. The FORCE_A (Force Output) pin has to be programmed
to +9 V.
Where LOW = –Full Scale, and HIGH = +Full Scale.
2. The PPMU has to be programmed to INTEGRATE mode.
3. The PPMU has to be programmed to HOLD mode.
4. Sample MEAS_OUT.
The M_CON pin can be used for disconnecting the MEAS_OUT
pin by:
1. Raising M_CON to 2.4 V.
2. Measuring MEAS_OUT (which is loaded with 100 kΩ).
3. MEAS_OUT should ideally be 0 V.
5. Wait 100 ms.
6. Sample MEAS_OUT again.
The OUTPUT_CON pin can be used for disconnecting the
DUT by:
7. The difference between 2 and 4 must be less than 15 mV.
The linearity tests for forcing voltage are as follows (at the
FORCE pin):
1. Disabling the SENSE pin (OUTPUT_CON = 2.4 V).
2. Loading FORCE_OUT with 2 kΩ to ground.
1. The four ranges of CURRENT MEASURE ranges (200 nA,
20 µA, 200 µA, and 2 mA) correspond to F1, F2, F3, and F4.
3. Programming the DAC1 input to +FS (+9 V) and measuring
the FORCE_OUT voltage (FV1).
2. The endpoints of the linearity curve are determined by –full
scale (or LOW), and the +full scale (or HIGH) readings at
the same FORCE pin current.
4. Programming the DAC1 input to –FS (–4 V) and measur-
ing the FORCE_OUT voltage (FV2).
3. Using these endpoints, gain nonlinearity is computed and
tested at the 1/4 scale, 1/2 scale, and 3/4 scale points.
5. FV1–FV2 < 1.3 mV.
6. A change of 1.3 mV implies a switch off-resistance of 20 MΩ.
1k⍀
S8
S9
SENSE
SENSE
AD53508
FORCING
EXT RC
VOLTAGE
DAC1
40pF
S6
S7
MAIN
C1
R1
R2
INT/IM
S10
10⍀
DAC2
S11
S12
S13
S14
S15
S16
FORCE
TO DUT
S4
S5
VF
IF
ENABLE
INTEGRATE
1k⍀
1.25R
2.5V
S17
2mA
DSR
VM
IM
S2
S3
10k⍀
DIFF
R
R
OUTPUT
200A
UNITY
S1
MEAS OUT
CON
1.25R
GUARD
S18
GUARD
Figure 2. Guarded Voltage Force/Current Measure, IRANGE 1: I ≤ 2 mA
–6–
REV. 0
AD53508
IN CURRENT FORCE WITH VOLTAGE MEASURE OR
VERIFY CURRENT FORCE
7. Measure voltage at MEAS_OUT and compare to 4.
8. VCC = 15 V.
The linearity tests for forcing current at the FORCE pin:
1. The FORCE pin is loaded with a voltage source.
9. DAC1 = 0 V.
10. FORCE pin loaded with –4 V source.
11. Measure current at FORCE.
12. Measure voltage at MEAS_OUT.
13. VEE = –9.5 V.
2. The two ranges of CURRENT FORCE ranges (2 mA and
200 µA) correspond to F1 and F2. The endpoints of the
linearity curve are determined by full scale (or LOW), and
the full scale (or HIGH) readings at the same FORCE pin
voltage.
14. Measure current at FORCE and compare to 11.
15. Measure voltage at MEAS_OUT and compare to 12.
16. VEE = –10 V.
3. Using these endpoints, gain nonlinearity is computed and
tested at the 1/4 scale, 1/2 scale, and 3/4 scale points.
4. Computations for F1 are:
F1 × 0.25 = LOW + 1 × (HIGH – LOW)/4
F1 × 0.50 = LOW + 2 × (HIGH – LOW)/4
F1 × 0.75 = LOW + 3 × (HIGH – LOW)/4
VOLTAGE FORCE WITH CURRENT MEASURE
(2 mA RANGE)
1. DAC1 = 9 V.
Where LOW = –Full Scale and HIGH = +Full Scale.
2. FORCE pin loaded with 2 mA current source.
3. Measure voltage at FORCE.
4. Measure current at MEAS_OUT.
5. VCC = 14.25 V.
The linearity test for measuring voltage is as follows (at the
MEAS_OUT pin):
1. The endpoints of the linearity curve are determined by the
–full scale (or LOW), and the +full scale (or HIGH) readings.
2. Using these endpoints, gain nonlinearity is computed and
tested at the 1/4 scale, 1/2 scale, and 3/4 scale points.
6. Measure voltage at FORCE and compare to 3:
Limit = 237 µV.
3. Computations for M1 are:
7. Measure current at MEAS_OUT and compare to 4:
M1 × 0.25 = LOW + 1 × (HIGH – LOW)/4
M1 × 0.50 = LOW + 2 × (HIGH – LOW)/4
M1 × 0.75 = LOW + 3 × (HIGH – LOW)/4
Limit = 237 µV.
8. VCC = 15 V.
9. DAC1 = –4 V.
Where LOW = –Full Scale, and HIGH = +Full Scale.
10. FORCE pin loaded with 2 mA current sink.
11. Measure voltage at FORCE.
12. Measure current at MEAS_OUT.
13. VEE = –9.5 V.
CURRENT FORCE WITH VOLTAGE MEASURE
(2 mA RANGE)
1. DAC1 = 5 V.
2. FORCE pin loaded with 9 V source.
3. Measure current at FORCE.
4. Measure voltage at MEAS_OUT.
5. VCC = 15 V.
14. Measure voltage at FORCE and compare to 11:
Limit = 474 µV.
15. Measure current at MEAS_OUT and compare to 12.
16. VEE = –10 V.
6. Measure current at FORCE and compare to 3.
S8
SENSE
SENSE
AD53508
S9
FORCING
EXT RC
VOLTAGE
40pF
S6
DAC1
MAIN
C1
R1
R2
S7
INT/IM
S10
DAC2
S11
S12
S13
S14
S15
S16
FORCE
VF
IF
S4
S5
ENABLE
INTEGRATE
1k⍀
2mA
1.25R
2.5V
S17
DSR
VM
IM
S2
S3
10k⍀
200A
DIFF
R
R
OUTPUT
UNITY
S1
MEAS OUT
CON
1.25R
GUARD
S18
GUARD
Figure 3. Guarded Current Force/Voltage Measure, IRANGE 1: I ≤ 2 mA
–7–
REV. 0
AD53508
1
51
52
34
39
40
41
32
V
V
EE
CC
39nF
CHDCPL
47
VH
45
37
38
43
42
49
50
VTERM
DATA
DATA
IOD
AD53032
39nF
CLDCPL
VHDCPL
25
30
22
50⍀
VOUT
TO DUT
DRIVER
IOD
VLDCPL
TO DUT (SENSE)
RLD
GUARD
RLD
VL 31
16
HCOMP
13
12
7
LEH
LEH
QH
6
QHB
COMPARATOR
4
QL
QL
"CONNECT TO HIGH QUALITY,
LOW NOISE SIGNAL (GND)"
3
11
10
17
LEL
LEL
LCOMP
ACTIVE LOAD
+1
24
23
25
30
22
VCOMS
VCOMI
IOLC
DSR
IOL
V/I
V/I
FORCE
SENSE
IOLRTN
*
27
36
35
IOHRTN
INHL
PPMU
26
IOH
15
14
THERM
NC
INHL
DAC1
DAC2
1.0A/K
IOHC 29
GUARD*
9, 33, 44, 46, 48
PWRGND
2, 5, 8
19
28
MEAS_OUT
ECLGND HQGND2 HQGND
TO V/I DAC
(PER CHANNEL)
TO SYSTEM
VOLTMETER
FROM OTHER PMUs
Figure 4. Recommended Use of the PPMU with a DCL
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
44-Lead Plastic Leaded Chip Carrier (PLCC)
(P-44A)
0.180 (4.57)
0.165 (4.19)
0.056 (1.42)
0.042 (1.07)
0.048 (1.21)
0.042 (1.07)
0.025 (0.63)
0.015 (0.38)
0.048 (1.21)
0.042 (1.07)
6
40
39
7
PIN 1
IDENTIFIER
0.050
(1.27)
BSC
0.63 (16.00)
0.59 (14.99)
0.021 (0.53)
0.013 (0.33)
TOP VIEW
(PINS DOWN)
0.032 (0.81)
0.026 (0.66)
17
29
28
18
0.040 (1.01)
0.025 (0.64)
0.020
(0.50)
R
0.656 (16.66)
0.650 (16.51)
SQ
SQ
0.110 (2.79)
0.085 (2.16)
0.695 (17.65)
0.685 (17.40)
–8–
REV. 0
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