AD8381JSTZ [ADI]
Fast, High Voltage Drive, 6-Channel Output DecDriver Decimating LCD Panel Driver; 快速，高电压驱动， 6声道输出DecDriver抽取LCD面板驱动
| 型号： | AD8381JSTZ |
| 厂家： | 
ADI |
| 描述： | Fast, High Voltage Drive, 6-Channel Output DecDriver Decimating LCD Panel Driver |
| 文件： | 总16页 (文件大小：290K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Fast, High Voltage Drive, 6-Channel Output
®
a
DecDriver Decimating LCD Panel Driver
AD8381
FEATURES
FUNCTIONAL BLOCK DIAGRAM
High Voltage Drive:
Rated Settling Time to within 1.3 V of Supply Rails
Output Overload Protection
High Update Rates:
Fast, 100 Ms/s 10-Bit Input Word Rate
Low Power Dissipation: 570 mW
Includes STBY Function
Voltage Controlled Video Reference (Brightness) and
Full-Scale (Contrast) Output Levels
3.3 V or 5 V Logic and 9 V to 18 V Analog Supplies
High Accuracy:
Laser Trimming Eliminates External Calibration
Flexible Logic:
INV Reverses Polarity of Video Signal
STSQ/XFR for Parallel AD8381 Operation in
12-Channel Systems
10
10
10
10
10
10
10
10
10
10
10
10
10
2-STAGE
LATCH
DB (0:9)
DAC
DAC
DAC
DAC
DAC
DAC
VID0
VID1
VID2
VID3
VID4
VID5
2-STAGE
LATCH
AD8381
2-STAGE
LATCH
STBY
BYP
BIAS
2-STAGE
LATCH
E/O
R/L
2-STAGE
LATCH
Drives Capacitive Loads:
27 ns Settling Time to 1% into 150 pF Load
Slew Rate 265 V/s with 150 pF Load
Available in 48-Lead LQFP
CLK
2-STAGE
LATCH
SEQUENCE
CONTROL
STSQ
XFR
APPLICATIONS
LCD Analog Column Driver
SCALING
CONTROL
VREFHI
VREFLO
INV VMID
PRODUCT DESCRIPTION
The AD8381 provides a fast, 10-bit latched decimating digital
input, which drives six high voltage outputs. Ten-bit input
words are sequentially loaded into six separate high speed, bipolar
DACs. Flexible digital input format allows several AD8381s to be
used in parallel for higher resolution displays. STSQ synchronizes
sequential input loading, XFR controls synchronous output
updating and R/L controls the direction of loading as either
left-to-right or right-to-left. Six channels of high voltage
output drivers drive to within 1.3 V of the rail in rated settling
time. The output signal can be adjusted for brightness, signal
inversion, and contrast for maximum flexibility.
The AD8381 is fabricated on ADI’s proprietary, fast bipolar
24 V process, providing fast input logic, bipolar DACs with
trimmed accuracy and fast settling, high voltage precision drive
amplifiers on the same chip.
The AD8381 dissipates 570 mW nominal static power. The
STBY pin reduces power to a minimum, with fast recovery.
The AD8381 is offered in a 48-lead 7 mm ¥ 7 mm ¥ 1.4 mm
LQFP package and operates over the commercial temperature
range of 0∞C to 85∞C.
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, norforanyinfringementsofpatentsorotherrightsofthirdpartiesthat
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
www.analog.com
© 2003 Analog Devices, Inc. All rights reserved.
(@ 25؇C, AVCC = 15.5 V, DVCC = 3.3 V, VREFLO = VMID = 7 V, VREFHI = 9.5 V,
MIN = 0؇C, TMAX = 85؇C, unless otherwise noted.)
T
AD8381–SPECIFICATIONS
Model
Conditions
Min
Typ
Max
Unit
VIDEO DC PERFORMANCE1
TMIN to TMAX
VDE
VCME
DAC Code 450 to 800
DAC Code 450 to 800
–7.5
–3.5
+1.0
+0.5
+7.5
+3.5
mV
mV
REFERENCE INPUTS
VMID Range2
(VREFHI – VREFLO) = 2.5 V
6.25
9.25
V
VMID Bias Current
VREFHI
VREFLO
35
77
AVCC
VREFHI
mA
V
V
VREFLO
VMID – 0.5
VREFHI Input Resistance
VREFLO Bias Current
VREFHI Input Current
VFS Range3
to VREFLO
20
0.01
125
kW
mA
mA
V
0.07
165
5.75
0
RESOLUTION
Coding
Binary
10
Bits
DIGITAL INPUT CHARACTERISTICS
Input Data Update Rate
CLK Rise and Fall Time = 5 ns
NRZ
100
Ms/s
ns
ns
ns
ns
ns
ns
ns
ns
pF
mA
mA
V
CLK to Data Setup Time: t1
0
CLK to STSQ Setup Time: t3
0
CLK to XFR Setup Time: t5
0
CLK to Data Hold Time: t2
5
CLK to STSQ Hold Time: t4
5
CLK to XFR Hold Time: t6
5
tCLK HIGH
tCLK LOW
CIN
E/O = HIGH
4.5
3.5
3
0.7
0.16
IIH
0.6
IIL
0.05
VIH
2.0
VIL
0.8
V
VTH
Threshold Voltage
1.4
V
VIDEO OUTPUT CHARACTERISTICS
Output Voltage Swing
CLK to VID Delay4: t7
INV to VID Delay
Output Current
Output Resistance
AVCC – VOH, VOL – AGND
50% of VIDx
50% of VIDx
1
1.3
17.5
16
V
13.5
12
30
15.5
14
75
29
ns
ns
mA
W
VIDEO OUTPUT DYNAMIC PERFORMANCE TMIN to TMAX, VO = 5 V Step, CL = 150 pF
Data Switching Slew Rate
Invert Switching Slew Rate
265
410
27
50
33
55
5
V/ms
V/ms
ns
ns
ns
Data Switching Settling Time to 1%
Data Switching Settling Time to 0.25%
Invert Switching Settling Time to 1%
Invert Switching Settling Time to 0.25%
CLK and Data Feedthrough5
32
75
40
100
ns
mV p-p
All-Hostile Crosstalk6
Amplitude
Glitch Duration
50
45
mV p-p
ns
POWER SUPPLY
Supply Rejection (VDE)
DVCC, Operating Range
DVCC, Quiescent Current
AVCC, Operating Range
Total AVCC Quiescent Current
STBY AVCC Current
AVCCx = +15.5 V ± 1 V
0.6
18
mV/V
V
mA
V
mA
mA
mA
3
9
5.5
25
18
40
3
33
1.8
0.03
STBY = H
STBY = H
STBY DVCC Current
0.1
OPERATING TEMPERATURE RANGE
NOTES
0
85
∞C
1VDE = Differential error voltage. VCME = Common-mode error voltage. See the Theory of Operation section.
2See Figure 6 in Theory of Operation section.
3VFS = 2 ¥ (VREFHI – VREFLO). See the Theory of Operation section.
4Measured from 50% of falling CLK edge to 50% of output change. Measurement is made for both states of INV.
5Measured on one output as CLK is driven and STSQ and XFR are held low.
6Measured on one output as the other five are changing from 0x000 to 0x3FF for both states of INV.
Specifications subject to change without notice.
–2–
REV. B
AD8381
TIMING CHARACTERISTICS
Parameter
Conditions
Min
Typ
Max
Unit
t1 CLK to Data Setup Time
t2 CLK to Data Hold Time
t3 CLK to STSQ Setup Time
t4 CLK to STSQ Hold Time
t5 CLK to XFR Setup Time
t6 CLK to XFR Hold Time
t7 CLK to VID Delay
CLK Rise and Fall Time = 5 ns
CLK Rise and Fall Time = 5 ns
CLK Rise and Fall Time = 5 ns
CLK Rise and Fall Time = 5 ns
CLK Rise and Fall Time = 5 ns
CLK Rise and Fall Time = 5 ns
0
5
0
5
0
5
13.5
ns
ns
ns
ns
ns
ns
ns
15.5
17.5
–1
0
DB (0:9)
t1
t2
CLK
t3,t5
t4,t6
STSQ, XFR
Figure 1. Timing Requirement E/O = High
–1
DB (0:9)
0
t1
t2
CLK
t3
t4
STSQ
t5
t6
XFR
Figure 2. Timing Requirements E/O = Low
CLK
XFR
t7
VIDx
Figure 3. Output Timing
–3–
REV. B
AD8381
ABSOLUTE MAXIMUM RATINGS1
MAXIMUM POWER DISSIPATION
Supply Voltages
The maximum power that can be safely dissipated by the AD8381
is limited by its junction temperature. The maximum safe junc-
tion temperature for plastic encapsulated devices is determined
by the glass transition temperature of the plastic, approximately
150∞C. Exceeding this limit temporarily may cause a shift in the
parametric performance due to a change in the stresses exerted
on the die by the package. Exceeding a junction temperature of
175∞C for an extended period can result in device failure.
AVCCx – AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 V
DVCC – DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Input Voltages
Maximum Digital Input Voltages . . . . . . . . DVCC + 0.5 V
Minimum Digital Input Voltages . . . . . . . . DGND – 0.5 V
Maximum Analog Input Voltages . . . . . . . . . AVCC + 0.5 V
Minimum Analog Input Voltages . . . . . . . . AGND – 0.5 V
Internal Power Dissipation2
LQFP Package @ 25∞C Ambient . . . . . . . . . . . . . . . . 2.7 W
Output Short Circuit Duration . . . . . . . . . . . . . . . . . . Infinite
Operating Temperature Range . . . . . . . . . . . . . . 0∞C to 85∞C
Storage Temperature Range . . . . . . . . . . . . –65∞C to +125∞C
Lead Temperature Range (Soldering 10 sec) . . . . . . . . 300∞C
To ensure proper operation within the specified operating tem-
perature range, it is necessary to limit the maximum power
dissipation as follows:
P
DMAX = (TJMAX – TA)/qJA
where:
NOTES
TJMAX = 150∞C.
1Stresses above those listed under the Absolute Maximum Ratings may cause
permanent damage to the device. This is a stress rating only; functional operation
of the device at these or any other conditions above those indicated in the
operational section of this specification is not implied. Exposure to the absolute
maximum ratings for extended periods may reduce device reliability.
248-lead LQFP Package:
3.5
3.0
2.5
2.0
1.5
1.0
0.5
q
q
JA = 45∞C/W (Still Air, 4-Layer PCB)
JC = 19∞C/W
Overload Protection
The AD8381 employs a two-stage overload protection circuit
that consists of an output current limiter and a thermal shutdown.
The maximum current at any one output of the AD8381 is
internally limited to 100 mA average. In the event of a momen-
tary short circuit between a video output and a power supply rail
(VCC or AGND), the output current limit is sufficiently low to
provide temporary protection.
0
10
20
30
40
50
60
70
80
90
The thermal shutdown debiases the output amplifier when the
junction temperature reaches the internally set trip point. In the
event of an extended short circuit between a video output and a
power supply rail, the output amplifier current continues to
switch between 0 mA and 100 mA typ with a period determined by
the thermal time constant and the hysteresis of the thermal trip
point. The thermal shutdown provides long term protection by
limiting the average junction temperature to a safe level.
AMBIENTTEMPERATURE – ؇C
Figure 4. Maximum Power Dissipation vs. Temperature
ORDERING GUIDE
Temperature Package
Range
Package
Option
Model
Description
Recovery from a momentary short circuit is fast, approximately
100 ns. Recovery from a thermal shutdown is slow and is
dependent on the ambient temperature.
AD8381JST
AD8381-EB
0∞C to 85∞C
48-Lead LQFP
Evaluation Board
ST-48
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD8381 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
–4–
REV. B
AD8381
PIN CONFIGURATION
48
47 46 45 44 43 42 41 40 39 38 37
1
2
3
4
5
6
7
8
9
NC
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
36
35
34
33
32
VID0
PIN 1
IDENTIFIER
AVCC0, 1
VID1
AGND1, 2
VID2
AD8381
31 AVCC2, 3
TOP VIEW
30
VID3
(Not to Scale)
29
28
27
26
25
AGND3, 4
VID4
DB8 10
DB9 11
NC 12
AVCC4, 5
VID5
AGND5
13 14 15 16 17 18
21 22 23 24
19 20
NC = NO CONNECT
PIN FUNCTION DESCRIPTIONS
Description
Pin No.
Mnemonic
Function
1, 12, 19, 23, NC
24, 43–45
No Connect
2–11
13
DB (0:9)
E/O
Data Input
Even/Odd Select
10-Bit Data Input MSB = DB (9).
The active CLK edge is the rising edge when this input is held high,
and it is the falling edge when this input is held low.
Data is loaded sequentially on the rising edges of CLK when this input
is high and loaded on the falling edges when this input is low.
A new data loading sequence begins on the left, with Channel 0, when this
input is low, and on the right, with Channel 5, when this input is high.
When this pin is high, the analog output voltages are above VMID.
When low, the analog output voltages are below VMID.
This pin is normally connected to the analog ground plane.
Digital Power Supply.
14
15
R/L
Right/Left Select
Invert
INV
16
17
DGND
DVCC
AVCCx
Digital Supply Return
Digital Power Supply
18, 27, 31
35, 42
20
Analog Power Supplies Analog Power Supplies.
STBY
BYP
Standby
Bypass
When high, the internal circuits are debiased and the power
dissipation drops to a minimum.
A 0.1 mF capacitor connected between this pin and AGND ensures
optimum settling time.
21
22, 25, 29
33, 37, 41
26, 28, 30,
32, 34, 36
38
AGNDx
Analog Supply Returns These pins are normally connected to the analog ground plane.
VID5, VID4, VID3,
VID2, VID1, VID0
VMID
Analog Outputs
These pins are directly connected to the analog inputs of the LCD panel.
Midpoint Reference
The voltage applied between this pin and AGND sets the midpoint
reference of the analog outputs. This pin is normally connected to VCOM.
The voltage applied between Pins 39 and 40 sets the full-scale output voltage.
The voltage applied between Pins 39 and 40 sets the full-scale output voltage.
A new data loading sequence begins on the rising edge of CLK when
this input was high on the preceding rising edge of CLK and the E/O
input is held high.
39
40
46
VREFLO
VREFHI
STSQ
Full-Scale Reference
Full-Scale Reference
Start Sequence
A new data loading sequence begins on the falling edge of CLK when
this input was high on the preceding falling edge of CLK and the E/O
input is held low.
47
XFR
CLK
Data Transfer
Clock
Data is transferred to the outputs on the immediately following falling
edge of CLK when this input is high on the rising edge of CLK.
Clock Input.
48
REV. B
–5–
–Typical Performance Characteristics
AD8381
12V
12V
VMID = 7V
VFS = 5V
VMID = 7V
VFS = 5V
VIDx
VIDx
C
L
150pF
C
L
150pF
2V
2V
20ns/DIV
20ns/DIV
TPC 1. Invert Switching 10 V Step Response (Rise) at CL
TPC 4. Invert Switching 10 V Step Response (Fall) at CL
7V
7V
VMID = 7V
VFS = 5V
VMID = 7V
VFS = 5V
VIDx
VIDx
C
L
150pF
C
L
150pF
2V
2V
10ns/DIV
10ns/DIV
TPC 2. Data Switching 5 V Step Response (Rise)
at CL, INV = L
TPC 5. Data Switching 5 V Step Response (Fall)
at CL, INV = L
12V
12V
VMID = 7V
VFS = 5V
VMID = 7V
VFS = 5V
VIDx
VIDx
C
L
150pF
C
L
150pF
7V
7V
20ns/DIV
20ns/DIV
TPC 3. Data Switching 5 V Step Response (Rise)
at CL, INV = H
TPC 6. Data Switching 5 V Step Response (Fall)
at CL, INV = H
–6–
REV. B
AD8381
1.00%
0.75%
0.25%
0.00%
7V
0.50%
–0.25%
–0.50%
–0.75%
–1.00%
VMID = 7V
VFS = 5V
0.25%
2V
0.00%
VIDx
C
L
150pF
–0.25%
–0.50%
–0.75%
–1.00%
VMID = 7V
VFS = 5V
VIDx
C
L
150pF
t = 0
t = 0
10ns/DIV
10ns/DIV
TPC 7. Output Settling Time (Rising Edge) at CL,
5 V Step, INV = Low
TPC 10. Output Settling Time (Falling Edge) at CL,
5 V Step, INV = Low
VMID = 7V
VFS = 5V
1.00%
0.75%
VIDx
C
L
150pF
0.00% 12V
–0.25%
0.50%
0.25%
–0.50%
VMID = 7V
VFS = 5V
0.00%
–0.25%
–0.50%
–0.75%
–0.75%
7V
VIDx
C
–1.00%
L
150pF
t = 0
t = 0
10ns/DIV
10ns/DIV
TPC 8. Output Settling Time (Rising Edge) at CL,
5 V Step, INV = High
TPC 11. Output Settling Time (Falling Edge) at CL,
5 V Step, INV = High
+30mV
+20mV
+10mV
VID5
VMID = 7V
–10mV
–20mV
+10mV
VMID = 7V
–10mV
VID0 – VID4
5V
DB (0:9)
20ns/DIV
20ns/DIV
TPC 9. All-Hostile Crosstalk at CL
TPC 12. Data Switching Transient (Feedthrough) at CL
REV. B
–7–
AD8381
0.5
0.4
0.5
0.4
0.3
0.3
0.2
0.2
0.1
0.1
0.0
0.0
–0.1
–0.2
–0.3
–0.4
–0.5
–0.1
–0.2
–0.3
–0.4
–0.5
0
0
256
512
768
1023
256
512
768
1023
INPUT CODE
INPUT CODE
TPC 16. Differential Nonlinearity (DNL) vs. Code, INV = L
TPC 13. Differential Nonlinearity (DNL) vs. Code, INV = H
0.5
0.4
0.5
0.4
0.3
0.3
0.2
0.2
0.1
0.1
0.0
0.0
–0.1
–0.2
–0.3
–0.4
–0.5
–0.1
–0.2
–0.3
–0.4
–0.5
0
256
512
768
1023
0
256
512
768
1023
INPUT CODE
INPUT CODE
TPC 17. Integral Nonlinearity (INL) vs. Code, INV = L
TPC 14. Integral Nonlinearity (INL) vs. Code, INV = H
0
5
0
–20
CODE 512, INV = LOW
–5
–40
CODE 512, INV = HIGH
–10
–15
–20
–25
–60
–80
10k
100k
1M
5M
5
6
7
8
9
10
11
FREQUENCY – Hz
VMID –V
TPC 18. AVCC Power Supply Rejection vs. Frequency
TPC 15. Normalized VDE at Code 0 vs. VMID, AVCC = 15.5 V
–8–
REV. B
AD8381
3.50
1.75
7.5
5.0
2.5
0.00
0.0
–2.5
–5.0
–7.5
–1.75
–3.50
0
256
512
768
1023
0
256
512
768
1023
INPUT CODE
INPUT CODE
TPC 21. Common-Mode Error Voltage (VCME) vs. Code
TPC 19. Differential Error Voltage (VDE) vs. Code
3.50
7.5
5.0
1.75
2.5
CODE 512
CODE 512
0.00
0.0
–2.5
–5.0
–7.5
–1.75
–3.50
0
20
40
60
80
100
0
20
40
60
80
100
TEMPERATURE – ؇C
TEMPERATURE – ؇C
TPC 22. Common-Mode Error (VCME) vs. Temperature
TPC 20. Differential Error Voltage (VDE) vs. Temperature
REV. B
–9–
AD8381
FUNCTIONAL DESCRIPTION
Data Transfer to Outputs (XFR Control)
The AD8381 is a system building block designed to directly
drive the columns of LCD panels of the type popularized for use
in data projectors. It comprises six channels of precision 10-bit
digital-to-analog converters loaded from a single, high speed,
10-bit-wide input. Precision current feedback amplifiers, provid-
ing well-damped pulse response and rapid voltage settling into
large capacitive loads, buffer the six outputs. Laser trimming at
the wafer level ensure low absolute output errors and tight channel-
to-channel matching. In addition, tight part-to-part matching
in high channel count systems is guaranteed by the use of an
external voltage reference.
Data transfer to all outputs is initiated by the XFR control input.
When XFR is held high during a rising CLK edge, data is
simultaneously transferred to all outputs on the immediately
following falling CLK edge.
VCOM Reference (VMID Reference Input)
An external analog reference voltage connected to this input
sets the reference level at the outputs. This input is normally
connected to VCOM.
Full-Scale Output (VREFHI, VREFLO Reference Inputs)
The difference between two external analog reference voltages,
connected to these inputs, sets the full-scale output voltage at
the outputs. VREFLO is normally tied to VMID.
Input Data Loading (STart SeQuence Control—STSQ)
A valid STSQ control input initiates a new six-clock pulse
loading cycle, during which six input data words are loaded
sequentially into six internal channels. A new loading sequence
begins on the current active CLK edge only when STSQ was
held high at the preceding active CLK edge.
Analog Voltage Inversion (INVert Control)
To facilitate systems that use column, row or pixel inversion,
the analog output voltage inversion is controlled by the INV
control input. While INV is high, the analog voltage equivalent
of the input code is subtracted from (VMID + VFS) at each
output. While INV is low, the analog voltage equivalent of the
input code is added to (VMID – VFS) at each output.
Data Loading—Expanded Systems (Even/Odd Control)
To facilitate expanded, even/odd systems, the active CLK edge, at
which input data is loaded, is set with the E/O control input.
Standby Mode (STBY Control)
Input data is loaded on rising CLK edges while the E/O input is
held high and loaded on falling CLK edges while the E/O input
is held low.
A high applied to the STBY input debiases the internal
circuitry, dropping the quiescent power dissipation to a few
milliwatts. Since both digital and analog circuits are debiased,
all stored data will be lost. Upon returning STBY to low, nor-
mal operation is restored.
Data Loading—Inverted Images (Right/Left Control)
To facilitate image mirroring, the order in which input data is
loaded is set with the R/L input.
A new loading sequence begins at Channel 0 and proceeds
to Channel 5 when the R/L input is held high and begins at
Channel 5 and proceeding to Channel 0 when the R/L input
is held low.
–10–
REV. B
AD8381
TRANSFER FUNCTION
VDE, the differential error voltage, measures the deviation of the
rms value of the output from the rms value of the ideal. It is depen-
dent on the difference between the output amplitudes VOUTN(n)
and VOUTP(n) at a particular code. The defining expression is
The AD8381 has two regions of operation, selected by the INV
input, where the video output voltages are either above or below
a reference voltage, applied externally at the VMID input.
The transfer function defines the analog output voltage as the
function of the digital input code as follows:
Ê
ˆ
1
2
Ê
Ë
n
ˆ
˜
VDE = ¥ VOUTN(n) –VOUTP(n) – VFS ¥ 1–
(
)
Á
Á
˜
1023¯
Ë
¯
where:
1
2
Ê
Ë
n
ˆ
˜
VOUT =VMID ±VFS ¥ 1–
Á
1023¯
¥ VOUTN(n) –VOUTP(n)
(
)
is the rms value of the output.
where:
(VFS ¥ (1 – n/1023)) is the rms value of the ideal.
n = input code
VCME, the common-mode error voltage, measures the devia-
tion of the average value of the output from the average value of
the ideal. It is dependent on the average between the output
amplitudes VOUTN(n) and VOUTP(n) at a particular code.
VFS = 2 ¥ (VREFHI – VREFLO)
VOUT (V)
AVCC
The defining expression is:
(VMID + VFS)
1
2
Ê 1
Ë 2
ˆ
VCME =
where:
¥
¥ VOUTN(n)+VOUTP(n) –VMID
(
)
Á
˜
¯
INV = HIGH
VOUTN(n)
VMID
1
2
¥ VOUTN(n)+VOUTP(n)
(
)
is the average value of the output.
VMID is the average value of the ideal.
INV = LOW
VOUTP(n)
MAXIMUM FULL-SCALE OUTPUT VOLTAGE
(VMID –VFS)
The following conditions limit the range of usable output voltages:
AGND
∑
∑
∑
∑
The internal DACs limit the minimum allowed voltage at
the VMID input to 5.3 V.
INPUT CODE
0
1023
The scale factor control loop limits the maximum full-scale
output voltage to 5.75 V.
Figure 5. Transfer Function
The region over which the output voltage varies with input code
is selected by the INV input. When INV is low, the output volt-
age increases from (VMID – VFS), (where VFS = the full-scale
output voltage), to VMID as the input code increases from 0 to
1023. When INV is high, the output voltage decreases from
(VMID + VFS) to VMID with increasing input code.
The output amplifiers settle cleanly at voltages within 1.3 V
from the supply rails.
The common-mode range of the output amplifiers limit the
maximum value of VMID to AVCC – 3.
At any given valid value of VMID, the voltage required to reach
any one of the above limits defines the maximum usable full-
scale output voltage VFSMAX.
For each value of input code there are then two possible values
of output voltage. When INV is low, the output is defined as
VOUTP(n) where n is the input code and P indicates the oper-
ating region where the slope of the transfer function is positive.
When INV is high, the output is defined as VOUTN(n) where N
indicates the operating region where the slope of the transfer
function is negative.
VFSMAX is the envelope in Figure 6. The valid range of VMID
is the shaded area.
VFS (V)
AVCC/2
AVCC/2–1.3
5.75
ACCURACY
To best correlate transfer function errors to image artifacts, the
overall accuracy of the AD8381 is defined by two parameters,
VDE and VCME.
4.3
VALID VMID
2
5.3
7
AVCC–7
AVCC/2
VMID (V)
AVCC–3
AVCC
0
Figure 6. VFSMAX vs. VMID
REV. B
–11–
AD8381
Operating Modes—6-Channel Systems
PIXEL CLK
The simplest full color LCD based system is characterized by an
image processor with a single 10-bit-wide data bus and a 6-channel
LCD per color.
15 16 17 18 19 20 21 22 23 24
–3 –2 –1
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14
DB (0:9)
CLK
Such systems usually have VGA or SVGA resolution and require a
single AD8381 per color.
STSQ
EVEN
STSQ
ODD
The INV input facilitates column and row inversion for
these systems.
XFR
R/L
–1
0
1
2
3
4
5
6
7
8
9
10 11
12
DB(0:9)
CLK
E/O
EVEN
E/O
ODD
STSQ
XFR
12
0
CH0
CH1
2
14
CH 0
CH 1
CH 2
CH 3
CH 4
CH 5
12
0
6
16
CH2
CH3
CH4
CH5
4
1
7
18
6
2
8
20
8
3
9
22
–2
10
4
10
–1
5
11
–12
VID0
VID1
VID2
VID3
0
2
12
14
–10
–8
–6
–4
–2
VID0
VID1
VID2
VID3
VID4
VID5
–6
0
1
2
3
4
5
6
4
16
18
20
22
–5
–4
–3
–2
–1
7
6
8
VID4
VID5
8
9
10
10
11
13
CH0
CH1
CH2
CH3
1
3
15
17
5
Figure 7. 6-Channel System Timing Diagram,
E/O = H, R/L = Low
19
7
21
CH4 –3
9
Operating Modes—12-Channel Systems
Single and dual data bus type 12-channel systems are com-
monly in use.
23
–1
11
CH5
–11
–9
13
15
1
3
VID0
VID1
VID2
VID3
VID4
VID5
The single data bus 12-channel system is characterized by an
image processor with a single, 10-bit data bus and a 12-channel
LCD per color. The maximum resolution of such a system is
usually up to 85 Hz XGA or 75 Hz SXGA and requires two
AD8381s per color.
–7
–5
5
17
19
21
7
–3
–1
9
11
23
One AD8381 is set to run in even mode while the other is in
odd mode. Both AD8381s share the same data bus and CLK.
The timing diagram of such system is shown in Figure 8.
Figure 8. Twelve-Channel Even/Odd System
Timing Diagram
The dual data bus 12-channel system is characterized by an
image processor with two 10-bit parallel data buses and a
12-channel LCD. The maximum resolution of such system is
usually up to 75 Hz UXGA and requires two AD8381s per color.
Operating Modes—Large Channel Count Systems
To facilitate 18, 24, or higher channel systems, any number of
required AD8381s may be cascaded.
Both AD8381s may be set to run in Even mode and may share
the same CLK. The timing diagram of each AD8381 in such
system is identical to that of the 6-channel system.
The INV input facilitates column, row, and pixel inversion for
both types of 12-channel systems.
–12–
REV. B
AD8381
IMAGE PROCESSOR
DB(0:9)
DB(0:9)
AD8381
CH 0
CH 2
CH 4
CH 6
CH 8
CH 10
VID0
VID1
VID2
VID3
VID4
VID5
CLK
XFR
R/L
CLK
XFR
R/L
PIXEL CLK
+2
STSQ2
STSQ1
CLK
CLK
،6 COUNTER
STSQ1
INV1
E/O1
STSQ
INV
E/O
H. REVERSE
CLK
CLK
STSQ2
INV2
E/O2
،6 COUNTER
VREFHI
VMID
VREFLO
HSTART
12-CHANNEL
LCD
HSYNC
VSYNC
INV1
INV2
DB(0:9)
CH 1
CH 3
CH 5
CH 7
CH 9
CH 11
VID0
VID1
AD8381
CLK
XFR
R/L
VID2
VID3
VID4
VID5
STSQ
INV
E/O
REFERENCES
VREFHI
VMID
VREFHI
VCOM
VREFLO
Figure 9. Single Data Bus 12-Channel Even/Odd System Block Diagram
IMAGE PROCESSOR
D(0:9) ODD
D(0:9) EVEN
DB1(0:9)
DB(0:9) AD8381
CLK
XFR
R/L
CH 0
VID0
CLK
XFR
R/L
PIXEL CLK
+2
VID1
VID2
VID3
VID4
VID5
CH 2
CH 4
CH 6
CH 8
CH 10
H. REVERSE
CLK
،6 COUNTER
STSQ
INV1
E/O
STSQ
INV
E/O
“1”
HSTART
VREFHI
VMID
INV2
VREFLO
12-CHANNEL
LCD
D(0:9) EVEN
D(0:9) ODD
DB2(0:9)
DB(0:9) AD8381
CLK
XFR
R/L
CH 1
CH 3
CH 5
CH 7
CH 9
CH 11
VID0
VID1
VID2
VID3
VID4
VID5
HSYNC
VSYNC
INV1
INV2
STSQ
INV
E/O
REFERENCES
VREFHI
VCOM
VREFHI
VMID
VREFLO
Figure 10. Dual Parallel Data Bus 12-Channel System Block Diagram
REV. B
–13–
AD8381
LAYOUT CONSIDERATIONS
Each reference voltage should be distributed to each AD8381
directly from the source of the reference voltage with approxi-
mately equal trace lengths.
The AD8381 is a mixed-signal, high speed, very accurate
device. In order to realize its specifications, it is essential to use
a properly designed printed circuit board.
A 0.1 mF chip capacitor should be placed as close to each refer-
ence input pin as possible and directly connected between the
reference input pin and the analog ground plane.
Layout and Grounding
The analog outputs and the digital inputs of the AD8381 are
pinned out on opposite sides of the package. When laying out
the circuit board, keep these sections separate from each other
to minimize crosstalk and noise and the coupling of the digital
input signals into the analog outputs.
All signal trace lengths should be made as short and direct as
possible to prevent signal degradation due to parasitic effects.
Note that digital signals should not cross or be routed near
analog signals.
36 VID0
AVCC0,1
1
2
3
4
5
6
7
8
DB0
DB1
DB2
DB3
DB4
DB5
DB6
It is imperative to provide a solid analog ground plane under
and around the AD8381. All of the ground pins of the part
should be connected directly to the ground plane with no extra
signal path length. For conventional operation this includes the
pins DGND, AGNDDAC, AGNDBIAS, AGND0, AGND1,2,
AGND3,4, and AGND5. The return traces for any of the
signals should be routed close to the ground pin for that section
to prevent stray signals from coupling into other ground pins.
VID1
34
32
30
28
26
AGND1,2
VID2
AVCC2,3
VID3
AGND3,4
VID4
DB7
9
DB8 10
DB9 11
AVCC4,5
VID5
Power Supply Bypassing
AGND5
12
All power supply and reference pins of the AD8381 must be
properly bypassed to the analog ground plane for optimum
performance.
All analog supply pins may be connected directly to an analog
supply plane located as close to the part as possible. A 0.1 mF
chip capacitor should be placed as close to each analog supply
pin as possible and connected directly between each analog
supply pin and the analog ground plane.
TO ANALOG GROUND PLANE
TO ANALOG SUPPLY PLANE
A minimum of 47 mF tantalum capacitor should be placed near
the analog supply plane and connected directly between the
supply and analog ground planes.
Figure 11.
A minimum of 10 mF tantalum capacitor should be placed near the
digital supply pin and connected directly to the analog ground
plane. A 0.1 mF chip capacitor should be connected between the
digital supply pin and the analog ground.
VREFHI, VMID, VREFLO Reference Distribution
To ensure well-matched video outputs, all AD8381s must oper-
ate from equal reference voltages.
–14–
REV. B
AD8381
OUTLINE DIMENSIONS
48-Lead Low Profile Quad Flat Package [LQFP]
(ST-48)
Dimensions shown in millimeters
0.75
0.60
0.45
9.00 BSC
SQ
1.60
MAX
37
48
36
1
PIN 1
SEATING
PLANE
10؇
6؇
2؇
7.00
BSC SQ
TOP VIEW
(PINS DOWN)
1.45
1.40
1.35
0.20
0.09
VIEW A
7؇
3.5؇
0؇
25
12
0.15
0.05
13
24
SEATING
PLANE
0.08 MAX
COPLANARITY
0.27
0.22
0.17
0.50
BSC
VIEW A
ROTATED 90؇ CCW
COMPLIANT TO JEDEC STANDARDS MS-026BBC
REV. B
–15–
AD8381
Revision History
Location
Page
10/03—Change from REV. A to REV. B.
Changes to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
9/03—Change from REV. 0 to REV. A.
Changes to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Changes to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
–16–
REV. B
相关型号：
AD8383ACPZ
LIQUID CRYSTAL DISPLAY DRIVER, QCC48, 7 X 7 MM, 0.85 MM HEIGHT, MO-220VKKD-2, LFCSP-48
ROCHESTER
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