EVAL-AD7606-6SDZ_技术文档

8-/6-/4-Channel DAS with 16-Bit, Bipolar

Input, Simultaneous Sampling ADC

Data Sheet

AD7606/AD7606-6/AD7606-4

FEATURES

APPLICATIONS

8/6/4 simultaneously sampled inputs

True bipolar analog input ranges: ±10 V, ±± V

Single ± V analog supply and 2.3 V to ± V V_DRIVE

Fully integrated data acquisition solution

Analog input clamp protection

Power-line monitoring and protection systems

Multiphase motor control

Instrumentation and control systems

Multiaxis positioning systems

Data acquisition systems (DAS)

Input buffer with 1 MΩ analog input impedance

Second-order antialiasing analog filter

On-chip accurate reference and reference buffer

16-bit ADC with 200 kSPS on all channels

Oversampling capability with digital filter

Flexible parallel/serial interface

SPI/QSPI™/MICROWIRE™/DSP compatible

Performance

7 kV ESD rating on analog input channels

9±.± dB SNR, −107 dB THD

Table 1. High Resolution, Bipolar Input, Simultaneous

Sampling DAS Solutions

Single-

Ended

Inputs

True

Number of

Differential Simultaneous

Inputs

Resolution

18 Bits

Sampling Channels

AD7608

AD7606

AD7606-6

AD7606-4

AD7607

AD7609

8

6

4

8

16 Bits

14 Bits

±0.± LSB INL, ±0.± LSB DNL

Low power: 100 mW

Standby mode: 2± mW

Temperature range: −40°C to +8±°C

64-lead LQFP package

FUNCTIONAL BLOCK DIAGRAM

AV_CC

REGCAP REGCAP

REFCAPB REFCAPA

R_FB

1MΩ

V1

CLAMP

T/H

SECOND-

ORDER LPF

V1GND

2.5V

LDO

2.5V

LDO

R_FB

1MΩ

REFIN/REFOUT

V2

CLAMP

T/H

SECOND-

V2GND

ORDER LPF

R_FB

1MΩ

REF SELECT

AGND

2.5V

REF

V3

CLAMP

OS 2

OS 1

OS 0

SECOND-

ORDER LPF

V3GND

R_FB

1MΩ

V4

CLAMP

D_OUT

A

B

SECOND-

ORDER LPF

V4GND

SERIAL

R_FB

1MΩ

D_OUT

8:1

MUX

PARALLEL/

SERIAL

RD/SCLK

CS

DIGITAL

16-BIT

SAR

V5

CLAMP

FILTER

INTERFACE

SECOND-

ORDER LPF

V5GND

R_FB

1MΩ

PAR/SER/BYTE SEL

V_DRIVE

V6

CLAMP

SECOND-

ORDER LPF

PARALLEL

DB[15:0]

V6GND

R_FB

1MΩ

AD7606

V7

CLAMP

SECOND-

ORDER LPF

V7GND

CLK OSC

R_FB

1MΩ

BUSY

CONTROL

INPUTS

V8

CLAMP

SECOND-

ORDER LPF

FRSTDATA

V8GND

R_FB

1MΩ

AGND

CONVST A CONVST B RESET RANGE

Figure 1.

Rev. D

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AD7606/AD7606-6/AD7606-4

Data Sheet

TABLE OF CONTENTS

Features .............................................................................................. 1

Analog Input............................................................................... 22

ADC Transfer Function............................................................. 23

Internal/External Reference...................................................... 24

Typical Connection Diagram ................................................... 25

Power-Down Modes .................................................................. 25

Conversion Control ................................................................... 26

Digital Interface.............................................................................. 27

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

General Description......................................................................... 3

Specifications..................................................................................... 4

Timing Specifications .................................................................. 7

Absolute Maximum Ratings.......................................................... 11

Thermal Resistance .................................................................... 11

ESD Caution................................................................................ 11

Pin Configurations and Function Descriptions ......................... 12

Typical Performance Characteristics ........................................... 17

Terminology .................................................................................... 21

Theory of Operation ...................................................................... 22

Converter Details........................................................................ 22

PAR

Parallel Interface (

/SER/BYTE SEL = 0).......................... 27

/SER/BYTE SEL = 1, DB15 = 1)............... 27

PAR

Parallel Byte (

Serial Interface (

/SER/BYTE SEL = 1)............................. 27

Reading During Conversion..................................................... 28

Digital Filter ................................................................................ 29

Layout Guidelines....................................................................... 32

Outline Dimensions....................................................................... 34

Ordering Guide .......................................................................... 34

REVISION HISTORY

11/2017—Rev. C to Rev. D

Changes to Features Section............................................................ 1

Changes to Specifications Table Summary ................................... 3

Deleted Endnote 1, Table 1; Renumbered Sequentially .............. 6

Change to Table 6 ........................................................................... 14

Changes to Typical Performance Characteristics Section......... 17

Changes to Terminology Section.................................................. 21

Changes to Ordering Guide .......................................................... 34

1/2012—Rev. B to Rev. C

Changes to Analog Input Ranges Section ................................... 22

10/2011—Rev. A to Rev. B

Changes to Input High Voltage (V_INH) and Input Low Voltage

(V_INL) Parameters and Endnote 6, Table 2..................................... 4

Changes to Table 3............................................................................ 7

Changes to Table 4.......................................................................... 11

Changes to Pin 32 Description, Table 6....................................... 13

Changes to Analog Input Clamp Protection Section................. 22

Changes to Typical Connection Diagram Section..................... 25

8/2010—Rev. 0 to Rev. A

Changes to Note 1, Table 2 .............................................................. 6

5/2010—Revision 0: Initial Version

Rev. D | Page 2 of 36

Data Sheet

AD7606/AD7606-6/AD7606-4

GENERAL DESCRIPTION

The AD7606¹/AD7606-6/AD7606-4 are 16-bit, simultaneous

sampling, analog-to-digital data acquisition systems (DAS) with

eight, six, and four channels, respectively. Each part contains

analog input clamp protection, a second-order antialiasing filter,

a track-and-hold amplifier, a 16-bit charge redistribution successive

approximation analog-to-digital converter (ADC), a flexible

digital filter, a 2.5 V reference and reference buffer, and high

speed serial and parallel interfaces.

all channels. The input clamp protection circuitry can tolerate

voltages up to 16.5 V. The AD7606 has 1 MΩ analog input

impedance regardless of sampling frequency. The single supply

operation, on-chip filtering, and high input impedance eliminate

the need for driver op amps and external bipolar supplies. The

AD7606/AD7606-6/AD7606-4 antialiasing filter has a 3 dB cutoff

frequency of 22 kHz and provides 40 dB antialias rejection when

sampling at 200 kSPS. The flexible digital filter is pin driven, yields

improvements in SNR, and reduces the 3 dB bandwidth.

The AD7606/AD7606-6/AD7606-4 operate from a single 5 V

supply and can accommodate 10 V and 5 V true bipolar input

signals while sampling at throughput rates up to 200 kSPS for

¹Patent pending.

Rev. D | Page 3 of 36

AD7606/AD7606-6/AD7606-4

SPECIFICATIONS

Data Sheet

V_REF= 2.5 V external/internal, AV_CC= 4.75 V to 5.25 V, V_DRIVE= 2.3 V to 5.25 V, f_SAMPLE= 200 kSPS, T_A= −40°C to +85°C, unless otherwise noted.

Table 2.

Parameter

Test Conditions/Comments

Min

Typ

Max

Unit

DYNAMIC PERFORMANCE

Signal-to-Noise Ratio (SNR)^{1, 2}

f_IN= 1 kHz sine wave unless otherwise noted

Oversampling by 16; 10 V range; f_IN= 130 Hz 94

Oversampling by 16; 5 V range; f_IN= 130 Hz 93

No oversampling; 10 V Range

No oversampling; 5 V range

No oversampling; 10 V range

No oversampling; 5 V range

No oversampling; 10 V range

No oversampling; 5 V range

95.5

94.5

90

89

90

89

90.5

90

−107

−108

dB

88.5

87.5

88

Signal-to-(Noise + Distortion) (SINAD)¹

Dynamic Range

87

Total Harmonic Distortion (THD)¹

Peak Harmonic or Spurious Noise (SFDR)¹

Intermodulation Distortion (IMD)¹

Second-Order Terms

Third-Order Terms

Channel-to-Channel Isolation¹

−95

fa = 1 kHz, fb = 1.1 kHz

−110

−106

−95

dB

f_INon unselected channels up to 160 kHz

ANALOG INPUT FILTER

Full Power Bandwidth

−3 dB, 10 V range

−3 dB, 5 V range

−0.1 dB, 10 V range

−0.1 dB, 5 V range

10 V Range

23

15

10

5

11

15

kHz

µs

t_{GROUP DELAY}

5 V Range

µs

DC ACCURACY

Resolution

No missing codes

16

Bits

Differential Nonlinearity¹

Integral Nonlinearity¹

Total Unadjusted Error (TUE)

0.5

6

0.99

2

LSB³

LSB

10 V range

5 V range

12

8

2

7

LSB

ppm/°C

LSB

Positive Full-Scale Error^{1, 4}

External reference

Internal reference

External reference

Internal reference

10 V range

32

Positive Full-Scale Error Drift

Positive Full-Scale Error Matching¹

Bipolar Zero Code Error^{1, 5}

5

32

40

6

5 V range

10 V range

16

1

5 V range

3

12

LSB

Bipolar Zero Code Error Drift

Bipolar Zero Code Error Matching¹

Negative Full-Scale Error^{1, 4}

10 V range

5 V range

10 V range

5 V range

External reference

Internal reference

External reference

Internal reference

10 V range

10

5

1

µV/°C

LSB

8

22

6

8

4

8

5

16

32

LSB

Negative Full-Scale Error Drift

Negative Full-Scale Error Matching¹

ppm/°C

LSB

32

40

5 V range

LSB

Rev. D | Page 4 of 36

Data Sheet

AD7606/AD7606-6/AD7606-4

Parameter

Test Conditions/Comments

Min

Typ

Max

Unit

ANALOG INPUT

Input Voltage Ranges

RANGE = 1

RANGE = 0

10

5

V

Analog Input Current

10 V; see Figure 31

5 V; see Figure 31

5.4

2.5

5

µA

pF

MΩ

Input Capacitance⁶

Input Impedance

See the Analog Input section

1

REFERENCE INPUT/OUTPUT

Reference Input Voltage Range

DC Leakage Current

See the ADC Transfer Function section

2.475

2.5

7.5

2.49/

2.505

2.525

1

V

µA

pF

V

Input Capacitance⁶

REF SELECT = 1

REFIN/REFOUT

Reference Output Voltage

Reference Temperature Coefficient

LOGIC INPUTS

10

ppm/°C

Input High Voltage (V_INH

)

0.7 × V_DRIVE

V

Input Low Voltage (V_INL

Input Current (I_IN)

Input Capacitance (C_IN)⁶

LOGIC OUTPUTS

)

0.3 × V_DRIVE

2

V

µA

pF

5

Output High Voltage (V_OH

)

I_SOURCE= 100 µA

I_SINK= 100 µA

V_DRIVE− 0.2

V

µA

pF

Output Low Voltage (V_OL

)

0.2

20

Floating-State Leakage Current

Floating-State Output Capacitance⁶

Output Coding

1

5

Twos complement

CONVERSION RATE

Conversion Time

Track-and-Hold Acquisition Time

Throughput Rate

All eight channels included; see Table 3

Per channel, all eight channels included

4

1

µs

kSPS

200

POWER REQUIREMENTS

AV_CC

V_DRIVE

4.75

2.3

5.25

V

I_TOTAL

Digital inputs = 0 V or V_DRIVE

AD7606

Normal Mode (Static)

16

14

12

22

20

17

mA

AD7606-6

AD7606-4

f_SAMPLE= 200 kSPS

AD7606

AD7606-6

Normal Mode (Operational)⁷

20

18

15

5

27

24

21

8

mA

µA

AD7606-4

Standby Mode

Shutdown Mode

2

6

Rev. D | Page 5 of 36

AD7606/AD7606-6/AD7606-4

Data Sheet

Parameter

Test Conditions/Comments

Min

Typ

Max

Unit

Power Dissipation

Normal Mode (Static)

Normal Mode (Operational)⁷

AD7606

f_SAMPLE= 200 kSPS

AD7606

AD7606-6

AD7606-4

80

115.5

mW

100

90

75

25

10

142

126

111

42

mW

µW

Standby Mode

Shutdown Mode

31.5

¹See the Terminology section.

²This specification applies when reading during a conversion or after a conversion. If reading during a conversion in parallel mode with V_DRIVE= 5 V, SNR typically reduces by 1.5 dB

and THD by 3 dB.

³LSB means least significant bit. With 5 V input range, 1 LSB = 152.58 µV. With 10 V input range, 1 LSB = 305.175 µV.

⁴These specifications include the full temperature range variation and contribution from the internal reference buffer but do not include the error contribution from

the external reference.

⁵Bipolar zero code error is calculated with respect to the analog input voltage. See the Analog Input Clamp Protection section.

⁶Sample tested during initial release to ensure compliance.

⁷Operational power/current figure includes contribution when running in oversampling mode.

Rev. D | Page 6 of 36

Data Sheet

AD7606/AD7606-6/AD7606-4

TIMING SPECIFICATIONS

AV_CC= 4.75 V to 5.25 V, V_DRIVE= 2.3 V to 5.25 V, V_REF= 2.5 V external reference/internal reference, T_A= T_MINto T_MAX, unless otherwise noted.¹

Table 3.

Limit at T_MIN, T_MAX

(0.1 × V_DRIVEand

0.9 × V_DRIVE

Limit at T_MIN, T_MAX

(0.3 × V_DRIVEand

0.7 × V_DRIVE

Logic Input Levels)

Parameter

Min

Typ

Max

Min

Typ Max Unit

Description

PARALLEL/SERIAL/BYTE MODE

t_CYCLE

1/throughput rate

5

µs

Parallel mode, reading during or after conversion; or

serial mode: V_DRIVE= 3.3 V to 5.25 V, reading during a

conversion using D_OUTA and D_OUTB lines

9.4

Serial mode reading after a conversion; V_DRIVE= 2.7 V

9.7

10.7 µs

Serial mode reading after a conversion; V_DRIVE= 2.3 V,

D_OUTA and D_OUTB lines

2

t_CONV

Conversion time

3.45

4

3

2

4.15

3.45

4

3

2

4.15 µs

Oversampling off; AD7606

Oversampling off; AD7606-6

Oversampling off; AD7606-4

Oversampling by 2; AD7606

Oversampling by 4; AD7606

Oversampling by 8; AD7606

Oversampling by 16; AD7606

Oversampling by 32; AD7606

Oversampling by 64; AD7606

µs

7.87

16.05

33

66

133

257

9.1

18.8

39

7.87

16.05

33

66

133

257

9.1

µs

18.8 µs

39

78

158

315

100

µs

78

158

315

100

t_{WAKE-UP STANDBY}

STBY

rising edge to CONVST x rising edge; power-up

time from standby mode

t_{WAKE-UP SHUTDOWN}

Internal Reference

30

13

30

13

ms

STBY

rising edge to CONVST x rising edge; power-up

time from shutdown mode

STBY

External Reference

rising edge to CONVST x rising edge; power-up

time from shutdown mode

t_RESET

t_{OS_SETUP}

t_{OS_HOLD}

50

20

50

20

ns

ms

RESET high pulse width

BUSY to OS x pin setup time

BUSY to OS x pin hold time

CONVST x high to BUSY high

Minimum CONVST x low pulse

Minimum CONVST x high pulse

t₁

t₂

t₃

t₄

40

45

25

0

25

0

CS

BUSY falling edge to falling edge setup time

3

t₅

0.5

25

0.5

25

Maximum delay allowed between CONVST A, CONVST

B rising edges

t₆

ns

CS

Maximum time between last rising edge and BUSY

falling edge

Minimum delay between RESET low to CONVST x high

t₇

25

PARALLEL/BYTE READ

OPERATION

t₈

0

ns

CS RD

to

setup time

hold time

t₉

CS RD

to

t₁₀

RD

low pulse width

16

21

25

32

15

22

19

24

30

37

15

22

ns

V_DRIVEabove 4.75 V

V_DRIVEabove 3.3 V

V_DRIVEabove 2.7 V

V_DRIVEabove 2.3 V

t₁₁

t₁₂

RD

CS

high pulse width

high pulse width (see Figure 5); and

CS

RD

linked

Rev. D | Page 7 of 36

AD7606/AD7606-6/AD7606-4

Data Sheet

Limit at T_MIN, T_MAX

(0.1 × V_DRIVEand

0.9 × V_DRIVE

Limit at T_MIN, T_MAX

(0.3 × V_DRIVEand

0.7 × V_DRIVE

Logic Input Levels)

Parameter

Min

Typ

Max

Min

Typ Max Unit

Description

t₁₃

CS

Delay from until DB[15:0] three-state disabled

V_DRIVEabove 4.75 V

16

20

25

30

19

24

30

37

ns

V_DRIVEabove 3.3 V

V_DRIVEabove 2.7 V

V_DRIVEabove 2.3 V

4

t₁₄

RD

falling edge

Data access time after

V_DRIVEabove 4.75 V

V_DRIVEabove 3.3 V

V_DRIVEabove 2.7 V

V_DRIVEabove 2.3 V

16

21

25

32

19

24

30

37

ns

t₁₅

t₁₆

t₁₇

6

RD

Data hold time after

falling edge

CS

to DB[15:0] hold time

22

CS

Delay from rising edge to DB[15:0] three-state

enabled

SERIAL READ OPERATION

f_SCLK

Frequency of serial read clock

V_DRIVEabove 4.75 V

V_DRIVEabove 3.3 V

23.5

17

20

15

MHz

14.5

11.5

12.5 MHz

V_DRIVEabove 2.7 V

V_DRIVEabove 2.3 V

10

MHz

t₁₈

CS

Delay from until D_OUTA/D_OUTB three-state

CS

disabled/delay from until MSB valid

15

20

30

18

23

35

ns

V_DRIVEabove 4.75 V

V_DRIVEabove 3.3 V

V_DRIVE= 2.3 V to 2.7 V

Data access time after SCLK rising edge

V_DRIVEabove 4.75 V

V_DRIVEabove 3.3 V

V_DRIVEabove 2.7 V

V_DRIVEabove 2.3 V

4

t₁₉

17

23

27

34

20

26

32

39

ns

t₂₀

t₂₁

t₂₂

t₂₃

0.4 t_SCLK

7

0.4 t_SCLK

7

SCLK low pulse width

SCLK high pulse width

SCLK rising edge to D_OUTA/D_OUTB valid hold time

22

ns

CS

rising edge to D_OUTA/D_OUTB three-state enabled

FRSTDATA OPERATION

t₂₄

CS

Delay from falling edge until FRSTDATA three-

state disabled

15

20

25

30

18

23

30

35

ns

V_DRIVEabove 4.75 V

V_DRIVEabove 3.3 V

V_DRIVEabove 2.7 V

V_DRIVEabove 2.3 V

t₂₅

CS

Delay from falling edge until FRSTDATA high,

serial mode

15

20

25

30

18

23

30

35

ns

V_DRIVEabove 4.75 V

V_DRIVEabove 3.3 V

V_DRIVEabove 2.7 V

V_DRIVEabove 2.3 V

t₂₆

RD

falling edge to FRSTDATA high

Delay from

16

20

25

30

19

23

30

35

ns

V_DRIVEabove 4.75 V

V_DRIVEabove 3.3 V

V_DRIVEabove 2.7 V

V_DRIVEabove 2.3 V

Rev. D | Page 8 of 36

Data Sheet

AD7606/AD7606-6/AD7606-4

Limit at T_MIN, T_MAX

(0.1 × V_DRIVEand

0.9 × V_DRIVE

Limit at T_MIN, T_MAX

(0.3 × V_DRIVEand

0.7 × V_DRIVE

Logic Input Levels)

Parameter

Min

Typ

Max

Min

Typ Max Unit

Description

t₂₇

RD

falling edge to FRSTDATA low

Delay from

19

24

22

29

ns

V_DRIVE= 3.3 V to 5.25V

V_DRIVE= 2.3 V to 2.7V

Delay from 16^thSCLK falling edge to FRSTDATA low

V_DRIVE= 3.3 V to 5.25V

t₂₈

17

22

24

20

27

29

ns

V_DRIVE= 2.3 V to 2.7V

t₂₉

CS

Delay from rising edge until FRSTDATA three-

state enabled

¹Sample tested during initial release to ensure compliance. All input signals are specified with t_R= t_F= 5 ns (10% to 90% of V_DRIVE) and timed from a voltage level of 1.6 V.

²In oversampling mode, typical t_CONVfor the AD7606-6 and AD7606-4 can be calculated using ((N × t_CONV) + ((N − 1) × 1 µs)). N is the oversampling ratio. For the AD7606-6,

t_CONV= 3 µs; and for the AD7606-4, t_CONV= 2 µs.

³The delay between the CONVST x signals was measured as the maximum time allowed while ensuring a <10 LSB performance matching between channel sets.

⁴A buffer is used on the data output pins for these measurements, which is equivalent to a load of 20 pF on the output pins.

Timing Diagrams

t₅

CONVST A,

CONVST B

t_CYCLE

t₂

CONVST A,

CONVST B

t₃

t_CONV

t₁

BUSY

t₄

CS

t₇

t_RESET

RESET

Figure 2. CONVST Timing—Reading After a Conversion

t₅

CONVST A,

CONVST B

t_CYCLE

t₂

CONVST A,

CONVST B

t₃

t_CONV

t₁

BUSY

t₆

CS

t₇

t_RESET

RESET

Figure 3. CONVST Timing—Reading During a Conversion

Rev. D | Page 9 of 36

AD7606/AD7606-6/AD7606-4

Data Sheet

CS

t₉

t₈

t₁₁

t₁₀

t₁₆

t₁₇

RD

t₁₃

t₁₄

V3

t₁₅

V7

DATA:

INVALID

DB[15:0]

V1

V2

t₂₇

V4

V8

t₂₆

t₂₉

t₂₄

FRSTDATA

CS

RD

Pulses

Figure 4. Parallel Mode, Separate and

t₁₂

CS AND RD

t₁₆

t₁₃

t₁₇

DATA:

V1

V2

V3

V4

V5

V6

V7

V8

DB[15:0]

FRSTDATA

CS

RD

Figure 5. and , Linked Parallel Mode

CS

t₂₁

t₂₀

SCLK

t₁₉

t₂₂

DB1

t₂₃

t₁₈

D

A,

OUT

DB15

t₂₅

DB14

DB13

DB0

t₂₈

D

B

OUT

t₂₉

FRSTDATA

Figure 6. Serial Read Operation (Channel 1)

CS

RD

t₈

t₉

t₁₀

t₁₁

t₁₆

t₁₇

t₁₃

t₁₅

t₁₄

HIGH

LOW

BYTE V1

HIGH

BYTE V8

LOW

DATA: DB[7:0]

FRSTDATA

INVALID

BYTE V1

BYTE V8

t₂₆

t₂₉

t₂₇

t₂₄

Figure 7. BYTE Mode Read Operation

Rev. D | Page 10 of 36

Data Sheet

AD7606/AD7606-6/AD7606-4

ABSOLUTE MAXIMUM RATINGS

T_A= 25°C, unless otherwise noted.

THERMAL RESISTANCE

Table 4.

θ_JAis specified for the worst-case conditions, that is, a device

soldered in a circuit board for surface-mount packages. These

specifications apply to a 4-layer board.

Parameter

Rating

AV_CCto AGND

V_DRIVEto AGND

−0.3 V to +7 V

−0.3 V to AV_CC+ 0.3 V

16.5 V

−0.3 V to V_DRIVE+ 0.3 V

−0.3 V to AV_CC+ 0.3 V

10 mA

Analog Input Voltage to AGND¹

Digital Input Voltage to AGND

Digital Output Voltage to AGND

REFIN to AGND

Input Current to Any Pin Except Supplies¹

Operating Temperature Range

B Version

Table 5. Thermal Resistance

Package Type

θ_JA

θ_JC

Unit

64-Lead LQFP

45

11

°C/W

ESD CAUTION

−40°C to +85°C

−65°C to +150°C

150°C

Storage Temperature Range

Junction Temperature

Pb/SN Temperature, Soldering

Reflow (10 sec to 30 sec)

Pb-Free Temperature, Soldering Reflow

ESD (All Pins Except Analog Inputs)

ESD (Analog Input Pins Only)

240 (+0)°C

260 (+0)°C

2 kV

7 kV

¹Transient currents of up to 100 mA do not cause SCR latch-up.

Stresses at or above those listed under Absolute Maximum

Ratings may cause permanent damage to the product. This is a

stress rating only; functional operation of the product at these

or any other conditions above those indicated in the operational

section of this specification is not implied. Operation beyond

the maximum operating conditions for extended periods may

affect product reliability.

Rev. D | Page 11 of 36

AD7606/AD7606-6/AD7606-4

Data Sheet

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49

1

AV

48

AV

CC

ANALOG INPUT

DECOUPLING CAP PIN

POWER SUPPLY

GROUND PIN

PIN 1

2

3

47 AGND

46

AGND

OS 0

REFGND

4

5

45

44

43

42

41

40

39

38

37

36

OS 1

OS 2

REFCAPB

REFCAPA

REFGND

REFIN/REFOUT

AGND

6

DATA OUTPUT

PAR/SER/BYTE SEL

AD7606

7

STBY

TOP VIEW

DIGITAL OUTPUT

DIGITAL INPUT

(Not to Scale)

8

RANGE

9

AGND

CONVST A

REFERENCE INPUT/OUTPUT

10

11

12

13

REGCAP

CONVST B

RESET

RD/SCLK

CS

AV

CC

AV

CC

REGCAP

BUSY 14

35 AGND

FRSTDATA 15

34 REF SELECT

33 DB15/BYTE SEL

DB0

16

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

Figure 8. AD7606 Pin Configuration

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49

1

AV

48

AV

CC

ANALOG INPUT

DECOUPLING CAP PIN

POWER SUPPLY

GROUND PIN

PIN 1

2

3

47 AGND

46

AGND

OS 0

REFGND

4

5

45

44

43

42

41

40

39

38

37

36

OS 1

OS 2

REFCAPB

REFCAPA

REFGND

REFIN/REFOUT

AGND

6

DATA OUTPUT

DIGITAL OUTPUT

DIGITAL INPUT

PAR/SER/BYTE SEL

AD7606-6

7

STBY

TOP VIEW

(Not to Scale)

8

RANGE

9

AGND

CONVST A

REFERENCE INPUT/OUTPUT

10

11

12

13

REGCAP

CONVST B

RESET

RD/SCLK

CS

AV

CC

AV

CC

REGCAP

BUSY 14

35 AGND

FRSTDATA 15

34 REF SELECT

33 DB15/BYTE SEL

DB0

16

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

Figure 9. AD7606-6 Pin Configuration

Rev. D | Page 12 of 36

Data Sheet

AD7606/AD7606-6/AD7606-4

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49

1

AV

48

AV

CC

ANALOG INPUT

DECOUPLING CAP PIN

POWER SUPPLY

GROUND PIN

PIN 1

2

3

47 AGND

46

AGND

OS 0

REFGND

4

5

45

44

43

42

41

40

39

38

37

36

OS 1

OS 2

REFCAPB

REFCAPA

REFGND

REFIN/REFOUT

AGND

6

DATA OUTPUT

PAR/SER/BYTE SEL

AD7606-4

7

STBY

TOP VIEW

DIGITAL OUTPUT

DIGITAL INPUT

(Not to Scale)

8

RANGE

9

AGND

CONVST A

REFERENCE INPUT/OUTPUT

10

11

12

13

REGCAP

CONVST B

RESET

RD/SCLK

CS

AV

CC

AV

CC

REGCAP

BUSY 14

35 AGND

FRSTDATA 15

34 REF SELECT

33 DB15/BYTE SEL

DB0

16

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

Figure 10. AD7606-4 Pin Configuration

Table 6. Pin Function Descriptions

Mnemonic

AD7606-6 AD7606-4 Description

Pin No.

Type¹

AD7606

AV_CC

1, 37, 38,

48

P

AV_CC

Analog Supply Voltage, 4.75 V to 5.25 V. This supply voltage is applied to

the internal front-end amplifiers and to the ADC core. These supply pins

should be decoupled to AGND.

2, 26, 35,

40, 41, 47

P

AGND

Analog Ground. These pins are the ground reference points for all analog

circuitry on the AD7606. All analog input signals and external reference

signals should be referred to these pins. All six of these AGND pins should

connect to the AGND plane of a system.

5, 4, 3

DI

OS [2:0]

Oversampling Mode Pins. Logic inputs. These inputs are used to select the

oversampling ratio. OS 2 is the MSB control bit, and OS 0 is the LSB control

bit. See the Digital Filter section for more details about the oversampling

mode of operation and Table 9 for oversampling bit decoding.

Parallel/Serial/Byte Interface Selection Input. Logic input. If this pin is tied to

a logic low, the parallel interface is selected. If this pin is tied to a logic high,

the serial interface is selected. Parallel byte interface mode is selected when

this pin is logic high and DB15/BYTE SEL is logic high (see Table 8).

In serial mode, the RD/SCLK pin functions as the serial clock input. The

DB7/D_OUTA pin and the DB8/D_OUTB pin function as serial data outputs. When

the serial interface is selected, the DB[15:9] and DB[6:0] pins should be tied to

ground.

6

PAR/SER/

BYTE SEL

PAR/SER/

BYTE SEL

PAR/SER/

BYTE SEL

In byte mode, DB15, in conjunction with PAR/SER/BYTE SEL, is used to select

the parallel byte mode of operation (see Table 8). DB14 is used as the HBEN

pin. DB[7:0] transfer the 16-bit conversion results in two RD operations,

with DB0 as the LSB of the data transfers.

7

DI

STBY

Standby Mode Input. This pin is used to place the AD7606/AD7606-6/

AD7606-4 into one of two power-down modes: standby mode or shutdown

mode. The power-down mode entered depends on the state of the RANGE

pin, as shown in Table 7. When in standby mode, all circuitry, except the on-

chip reference, regulators, and regulator buffers, is powered down. When

in shutdown mode, all circuitry is powered down.

Rev. D | Page 13 of 36

AD7606/AD7606-6/AD7606-4

Data Sheet

Mnemonic

AD7606-6 AD7606-4 Description

RANGE RANGE

Pin No.

Type¹

AD7606

8

DI

RANGE

Analog Input Range Selection. Logic input. The polarity on this pin deter-

mines the input range of the analog input channels. If this pin is tied to a

logic high, the analog input range is 10 V for all channels. If this pin is tied to

a logic low, the analog input range is 5 V for all channels. A logic change

on this pin has an immediate effect on the analog input range. Changing

this pin during a conversion is not recommended for fast throughput rate

applications. See the Analog Input section for more information.

9, 10

DI

CONVST A, CONVST A, CONVST A,

Conversion Start Input A, Conversion Start Input B. Logic inputs. These

logic inputs are used to initiate conversions on the analog input channels.

For simultaneous sampling of all input channels, CONVST A and CONVST B

can be shorted together, and a single convert start signal can be applied.

Alternatively, CONVST A can be used to initiate simultaneous sampling: V1,

V2, V3, and V4 for the AD7606; V1, V2, and V3 for the AD7606-6; and V1

and V2 for the AD7606-4. CONVST B can be used to initiate simultaneous

sampling on the other analog inputs: V5, V6, V7, and V8 for the AD7606;

V4, V5, and V6 for the AD7606-6; and V3 and V4 for the AD7606-4. This is

possible only when oversampling is not switched on. When the CONVST A or

CONVST B pin transitions from low to high, the front-end track-and-hold

circuitry for the respective analog inputs is set to hold.

CONVST B

11

12

DI

RESET

Reset Input. When set to logic high, the rising edge of RESET resets the

AD7606/AD7606-6/AD7606-4. The device should receive a RESET pulse

directly after power-up. The RESET high pulse should typically be 50 ns

wide. If a RESET pulse is applied during a conversion, the conversion is

aborted. If a RESET pulse is applied during a read, the contents of the

output registers reset to all zeros.

Parallel Data Read Control Input When the Parallel Interface Is Selected (RD)/

Serial Clock Input When the Serial Interface Is Selected (SCLK). When both

CS and RD are logic low in parallel mode, the output bus is enabled.

In serial mode, this pin acts as the serial clock input for data transfers.

The CS falling edge takes the D_OUTA and D_OUTB data output lines out

of three-state and clocks out the MSB of the conversion result. The rising

RD/SCLK

edge of SCLK clocks all subsequent data bits onto the D_OUTA and D_OUT

B

serial data outputs. For more information, see the Conversion Control

section.

13

14

DI

CS

Chip Select. This active low logic input frames the data transfer. When

both CS and RD are logic low in parallel mode, the DB[15:0] output bus is

enabled and the conversion result is output on the parallel data bus lines.

In serial mode, CS is used to frame the serial read transfer and clock out

the MSB of the serial output data.

Busy Output. This pin transitions to a logic high after both CONVST A and

CONVST B rising edges and indicates that the conversion process has started.

The BUSY output remains high until the conversion process for all channels

is complete. The falling edge of BUSY signals that the conversion data is

being latched into the output data registers and is available to read after

a Time t₄. Any data read while BUSY is high must be completed before the

falling edge of BUSY occurs. Rising edges on CONVST A or CONVST B have

no effect while the BUSY signal is high.

DO

BUSY

15

DO

FRSTDATA

Digital Output. The FRSTDATA output signal indicates when the first channel,

V1, is being read back on the parallel, byte, or serial interface. When the

CS input is high, the FRSTDATA output pin is in three-state. The falling

edge of CS takes FRSTDATA out of three-state. In parallel mode, the falling

edge of RD corresponding to the result of V1 then sets the FRSTDATA pin

high, indicating that the result from V1 is available on the output data bus.

The FRSTDATA output returns to a logic low following the next falling edge

of RD. In serial mode, FRSTDATA goes high on the falling edge of CS because

this clocks out the MSB of V1 on D_OUTA. It returns low on the 16^thSCLK

falling edge after the CS falling edge. See the Conversion Control section

for more details.

Rev. D | Page 14 of 36

Data Sheet

AD7606/AD7606-6/AD7606-4

Mnemonic

Pin No.

Type¹

AD7606

AD7606-6 AD7606-4 Description

22 to 16

DO

DB[6:0]

Parallel Output Data Bits, DB6 to DB0. When PAR/SER/BYTE SEL = 0, these

pins act as three-state parallel digital input/output pins. When CS and RD

are low, these pins are used to output DB6 to DB0 of the conversion result.

When PAR/SER/BYTE SEL = 1, these pins should be tied to AGND. When

operating in parallel byte interface mode, DB[7:0] outputs the 16-bit con-

version result in two RD operations. DB7 (Pin 24) is the MSB; DB0 is the LSB.

23

24

P

V_DRIVE

Logic Power Supply Input. The voltage (2.3 V to 5.25 V) supplied at this pin

determines the operating voltage of the interface. This pin is nominally at the

same supply as the supply of the host interface (that is, DSP and FPGA).

Parallel Output Data Bit 7 (DB7)/Serial Interface Data Output Pin (D_OUTA).

When PAR/SER/BYTE SEL = 0, this pins acts as a three-state parallel digital

input/output pin. When CS and RD are low, this pin is used to output DB7

of the conversion result. When PAR/SER/BYTE SEL = 1, this pin functions

as D_OUTA and outputs serial conversion data (see the Conversion Control

section for more details). When operating in parallel byte mode, DB7 is

the MSB of the byte.

Parallel Output Data Bit 8 (DB8)/Serial Interface Data Output Pin (D_OUTB).

When PAR/SER/BYTE SEL = 0, this pin acts as a three-state parallel digital

input/output pin. When CS and RD are low, this pin is used to output

DB8 of the conversion result. When PAR/SER/BYTE SEL = 1, this pin functions

as D_OUTB and outputs serial conversion data (see the Conversion Control

section for more details).

Parallel Output Data Bits, DB13 to DB9. When PAR/SER/BYTE SEL = 0, these

pins act as three-state parallel digital input/output pins. When CS and RD

are low, these pins are used to output DB13 to DB9 of the conversion result.

When PAR/SER/BYTE SEL = 1, these pins should be tied to AGND.

DO

DB7/D_OUT

A

DB7/D_OUT

A

B

DB7/D_OUT

A

B

25

DO

DB8/D_OUT

DB[13:9]

B

DB8/D_OUT

DB[13:9]

DB8/D_OUT

DB[13:9]

31 to 27

32

DO

DO/DI

DB14/

HBEN

DB14/

HBEN

DB14/

HBEN

Parallel Output Data Bit 14 (DB14)/High Byte Enable (HBEN). When PAR/

SER/BYTE SEL = 0, this pin acts as a three-state parallel digital output pin.

When CS and RD are low, this pin is used to output DB14 of the conversion

result. When PAR/SER/BYTE SEL = 1 and DB15/BYTE SEL = 1, the AD7606/

AD7606-6/AD7606-4 operate in parallel byte interface mode. In parallel

byte mode, the HBEN pin is used to select whether the most significant byte

(MSB) or the least significant byte (LSB) of the conversion result is output first.

When HBEN = 1, the MSB is output first, followed by the LSB.

When HBEN = 0, the LSB is output first, followed by the MSB.

In serial mode, this pin should be tied to GND.

33

DO/DI

DB15/

BYTE SEL

DB15/

BYTE SEL

DB15/

BYTE SEL

Parallel Output Data Bit 15 (DB15)/Parallel Byte Mode Select (BYTE SEL).

When PAR/SER/BYTE SEL = 0, this pin acts as a three-state parallel digital

output pin. When CS and RD are low, this pin is used to output DB15 of the

conversion result. When PAR/SER/BYTE SEL = 1, the BYTE SEL pin is used to

select between serial interface mode and parallel byte interface mode

(see Table 8). When PAR/SER/BYTE SEL = 1 and DB15/BYTE SEL = 0, the

AD7606 operates in serial interface mode. When PAR/SER/BYTE SEL = 1

and DB15/BYTE SEL = 1, the AD7606 operates in parallel byte interface mode.

34

DI

P

REF SELECT REF SELECT REF SELECT Internal/External Reference Selection Input. Logic input. If this pin is set to

logic high, the internal reference is selected and enabled. If this pin is set to

logic low, the internal reference is disabled and an external reference

voltage must be applied to the REFIN/REFOUT pin.

36, 39

REGCAP

Decoupling Capacitor Pin for Voltage Output from Internal Regulator.

These output pins should be decoupled separately to AGND using a 1 μF

capacitor. The voltage on these pins is in the range of 2.5 V to 2.7 V.

Rev. D | Page 15 of 36

AD7606/AD7606-6/AD7606-4

Data Sheet

Mnemonic

AD7606-6 AD7606-4 Description

Pin No.

Type¹

AD7606

42

REF

REFIN/

REFOUT

REFIN/

REFOUT

REFIN/

REFOUT

Reference Input (REFIN)/Reference Output (REFOUT). The on-chip reference

of 2.5 V is available on this pin for external use if the REF SELECT pin is set to

logic high. Alternatively, the internal reference can be disabled by setting

the REF SELECT pin to logic low, and an external reference of 2.5 V can be

applied to this input (see the Internal/External Reference section).

Decoupling is required on this pin for both the internal and external

reference options. A 10 μF capacitor should be applied from this pin to

ground close to the REFGND pins.

43, 46

44, 45

REF

REFGND

REFCAPA,

REFCAPB

REFGND

REFCAPA,

REFCAPB

REFGND

REFCAPA,

REFCAPB

Reference Ground Pins. These pins should be connected to AGND.

Reference Buffer Output Force/Sense Pins. These pins must be connected

together and decoupled to AGND using a low ESR, 10 μF ceramic capacitor.

The voltage on these pins is typically 4.5 V.

49

AI

V1

Analog Input. This pin is a single-ended analog input. The analog input

range of this channel is determined by the RANGE pin.

50, 52

AI GND

V1GND,

V2GND

V1GND,

V2GND

V1GND,

V2GND

Analog Input Ground Pins. These pins correspond to Analog Input Pin V1

and Analog Input Pin V2. All analog input AGND pins should connect to

the AGND plane of a system.

51

AI

V2

Analog Input. This pin is a single-ended analog input. The analog input

range of this channel is determined by the RANGE pin.

53

54

AI/GND

AI GND/ V3GND

GND

V3

V3GND

AGND

Analog Input 3. For the AD7606-4, this is an AGND pin.

Analog Input Ground Pin. For the AD7606-4, this is an AGND pin.

55

56

AI/GND

AI GND/ V4GND

GND

V4

AGND

Analog Input 4. For the AD7606-6 and the AD7606-4, this is an AGND pin.

Analog Input Ground Pin. For the AD7606-6 and AD7606-4, this is an

AGND pin.

57

58

AI

V5

V4

V3

Analog Inputs. These pins are single-ended analog inputs. The analog

input range of these channels is determined by the RANGE pin.

Analog Input Ground Pins. All analog input AGND pins should connect to

the AGND plane of a system.

AI GND

V5GND

V4GND

V3GND

59

60

AI

AI GND

V6

V6GND

V5

V5GND

V4

V4GND

Analog Inputs. These pins are single-ended analog inputs.

Analog Input Ground Pins. All analog input AGND pins should connect to

the AGND plane of a system.

61

62

AI/GND

AI GND/ V7GND

GND

V7

V6

V6GND

AGND

Analog Input Pins. For the AD7606-4, this is an AGND pin.

Analog Input Ground Pins. For the AD7606-4, this is an AGND pin.

63

64

AI/GND

AI GND/ V8GND

GND

V8

AGND

Analog Input Pin. For the AD7606-4 and AD7606-6, this is an AGND pin.

Analog Input Ground Pin. For the AD7606-4 and AD7606-6, this is an

AGND pin.

¹P is power supply, DI is digital input, DO is digital output, REF is reference input/output, AI is analog input, GND is ground.

Rev. D | Page 16 of 36

Data Sheet

AD7606/AD7606-6/AD7606-4

TYPICAL PERFORMANCE CHARACTERISTICS

Temperature range is from −40°C to +85°C. The AD7606 is functional up to 105°C with throughput rates < 160 kSPS. Specifications are

guaranteed for the operating temperature range of −40°C to +85°C only.

0

2.0

AV , V

CC DRIVE

= 5V

AV , V

CC DRIVE

= 5V

INTERNAL REFERENCE

±10V RANGE

F

= 200kSPS

SAMPLE

= 25°C

–20

1.5

T

A

F

= 200kSPS

INTERNAL REFERENCE

±10V RANGE

SAMPLE

= 1kHz

–40

IN

1.0

16,384 POINT FFT

SNR = 90.17dB

THD = –106.25dB

–60

0.5

–80

0

–100

–120

–140

–160

–180

–0.5

–1.0

–1.5

–2.0

0

10k 20k 30k 40k 50k 60k 70k 80k 90k 100k

INPUT FREQUENCY (Hz)

0

10k

20k

30k

CODE

40k

50k

60k

Figure 11. AD7606 FFT, ±10 V Range

Figure 14. AD7606 Typical INL, ±10 V Range

0

–20

1.0

0.8

AV , V

CC DRIVE

INTERNAL REFERENCE

±5V RANGE

= 5V

AV , V

= 5V

= 200kSPS

CC DRIVE

F

T

SAMPLE

= 25°C

A

F

= 200kSPS

INTERNAL REFERENCE

±10V RANGE

SAMPLE

= 1kHz

0.6

–40

IN

16,384 POINT FFT

SNR = 89.48dB

THD = –108.65dB

0.4

–60

0.2

–80

0

–100

–120

–140

–160

–180

–0.2

–0.4

–0.6

–0.8

–1.0

0

10k 20k 30k 40k 50k 60k 70k 80k 90k 100k

INPUT FREQUENCY (Hz)

0

10k

20k

30k

CODE

40k

50k

60k

Figure 12. AD7606 FFT Plot, ±± V Range

Figure 1±. AD7606 Typical DNL, ±10 V Range

0

–10

–20

–30

–40

2.0

1.5

AV , V

CC DRIVE

INTERNAL REFERENCE

±10V RANGE

= 5V

AV , V

CC DRIVE

INTERNAL REFERENCE

±5V RANGE

= 5V

F

T

F

= 11.5kSPS

= 25°C

= 133Hz

F

T

= 200kSPS

SAMPLE

= 25°C

A

1.0

–50

IN

8192 POINT FFT

OS BY 16

SNR = 96.01dB

THD = –108.05dB

–60

–70

–80

–90

0.5

0

–100

–110

–120

–130

–140

–150

–160

–170

–180

–0.5

–1.0

–1.5

–2.0

0

0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

FREQUENCY (kHz)

0

8192 16,384 24,576 32,768 40,960 49,152 57,344 65,536

CODE

Figure 13. FFT Plot Oversampling By 16, ±10 V Range

Figure 16. AD7606 Typical INL, ± ± V Range

Rev. D | Page 17 of 36

AD7606/AD7606-6/AD7606-4

Data Sheet

1.00

10

8

AV , V

CC DRIVE

INTERNAL REFERENCE

±5V RANGE

= 5V

0.75

0.50

0.25

0

PFS ERROR

NFS ERROR

F

T

= 200kSPS

SAMPLE

= 25°C

6

A

4

2

0

–2

–4

–6

–9

–10

–0.25

–0.50

–0.75

–1.00

10V RANGE

AV , V

= 5V

CC DRIVE

EXTERNAL REFERENCE

0

8192 16,384 24,576 32,768 40,960 49,152 57,344 65,536

CODE

–40

–25

–10

5

20

35 50 65 80

TEMPERATURE (°C)

Figure 17. AD7606 Typical DNL, ±± V Range

Figure 20. NFS and PFS Error Matching

20

15

10

5

10

8

±10V RANGE

±5V RANGE

6

0

4

–5

–10

–15

2

AV , V

CC DRIVE

= 5V

F

= 200 kSPS

SAMPLE

= 25°C

T

A

EXTERNAL REFERENCE

SOURCE RESISTANCE IS MATCHED ON

THE VxGND INPUT

0

200kSPS

AV , V

= 5V

CC DRIVE

±10V AND ±5V RANGE

EXTERNAL REFERENCE

35 50 65 80

TEMPERATURE (°C)

–20

–40

–2

–25

–10

5

20

0

20k

40k

60k

80k

100k

120k

SOURCE RESISTANCE (Ω)

Figure 18. NFS Error vs. Temperature

Figure 21. PFS and NFS Error vs. Source Resistance

20

15

10

5

1.0

0.8

0.6

0.4

0.2

0

±5V RANGE

±10V RANGE

5V RANGE

–0.2

–0.4

–0.6

–0.8

–1.0

–5

–10

–15

10V RANGE

200kSPS

AV , V

= 5V

AV , V

= 5V

CC DRIVE

EXTERNAL REFERENCE

CC DRIVE

EXTERNAL REFERENCE

–20

–40

–25

–10

5

20

35 50 65 80

–40

–25

–10

5

20

35 50 65 80

TEMPERATURE (°C)

Figure 19. PFS Error vs. Temperature

Figure 22. Bipolar Zero Code Error vs. Temperature

Rev. D | Page 18 of 36

Data Sheet

AD7606/AD7606-6/AD7606-4

4

98

96

94

92

90

88

86

84

82

80

3

5V RANGE

2

1

10V RANGE

0

–1

–2

–3

OS BY 64

OS BY 32

OS BY 16

OS BY 8

OS BY 4

OS BY 2

NO OS

AV , V

CC DRIVE

= 5V

F

CHANGES WITH OS RATE

SAMPLE

= 25°C

200kSPS

AV , V

T

A

= 5V

INTERNAL REFERENCE

±5V RANGE

CC DRIVE

EXTERNAL REFERENCE

35 50 65 80

TEMPERATURE (°C)

–4

–40

–25

–10

5

20

10

100

1k

10k

100k

INPUT FREQUENCY (Hz)

Figure 23. Bipolar Zero Code Error Matching Between Channels

Figure 26. SNR vs. Input Frequency for Different Oversampling Rates, ±5 V Range

–40

100

98

96

94

92

90

88

±10V RANGE

AV , V

= +5V

CC DRIVE

–50

–60

F

= 200kSPS

SAMPLE

R

MATCHED ON Vx AND VxGND INPUTS

SOURCE

–70

–80

105kΩ

48.7kΩ

23.7kΩ

10kΩ

5kΩ

1.2kΩ

100Ω

51Ω

–90

86

84

82

80

OS BY 64

OS BY 32

OS BY 16

OS BY 8

OS BY 4

OS BY 2

NO OS

–100

–110

–120

AV , V

CC DRIVE

= 5V

F

CHANGES WITH OS RATE

SAMPLE

= 25°C

T

A

INTERNAL REFERENCE

±10V RANGE

0Ω

1k

10k

100k

10

100

1k

10k

100k

INPUT FREQUENCY (Hz)

Figure 24. THD vs. Input Frequency for Various Source Impedances,

±±0 V Range

Figure 27. SNR vs. Input Frequency for Different Oversampling Rates, ±±0 V Range

–40

–50

±5V RANGE

AV , V

CC DRIVE

INTERNAL REFERENCE

AD7606 RECOMMENDED DECOUPLING USED

= 5V

AV , V

= +5V

CC DRIVE

–60

–70

–50

–60

F

= 200kSPS

SAMPLE

R

MATCHED ON Vx AND VxGND INPUTS

F

T

= 150kSPS

SOURCE

SAMPLE

= 25°C

A

INTERFERER ON ALL UNSELECTED CHANNELS

–80

–70

–90

±10V RANGE

±5V RANGE

–80

–100

–110

–120

–130

–140

105kΩ

48.7kΩ

23.7kΩ

10kΩ

5kΩ

1.2kΩ

100Ω

51Ω

–90

–100

–110

–120

0Ω

1k

10k

100k

0

20

40

60

80

100

120

140

160

INPUT FREQUENCY (Hz)

NOISE FREQUENCY (kHz)

Figure 25. THD vs. Input Frequency for Various Source Impedances,

±5 V Range

Figure 28. Channel-to-Channel Isolation

Rev. D | Page 19 of 36

AD7606/AD7606-6/AD7606-4

Data Sheet

100

22

20

18

16

14

12

10

8

98

±10V RANGE

96

94

±5V RANGE

92

90

88

86

AV , V

= 5V

AV , V = 5V

CC DRIVE

84

82

80

CC DRIVE

= 25°C

T

T = 25°C

A

INTERNAL REFERENCE

F VARIES WITH OS RATE

SAMPLE

F

SCALES WITH OS RATIO

SAMPLE

OFF

OS2

OS4

OS8

OS16

OS32

OS64

NO OS

OS2

OS4

OS8

OS16

OS32

OS64

OVERSAMPLING RATIO

Figure 29. Dynamic Range vs. Oversampling Rate

Figure 32. Supply Current vs. Oversampling Rate

2.5010

2.5005

2.5000

2.4995

2.4990

2.4985

2.4980

140

130

120

110

100

90

AV

= 5.25V

CC

AV

= 5V

CC

±10V RANGE

±5V RANGE

= 4.75V

80

AV , V

CC DRIVE

INTERNAL REFERENCE

AD7606 RECOMMENDED DECOUPLING USED

= 5V

70

F

T

= 200kSPS

SAMPLE

= 25°C

A

60

–40

–25

–10

5

20

35

50

65

80

0

100 200 300 400 500 600 700 800 900 1000 1100

AV NOISE FREQUENCY (kHz)

TEMPERATURE (°C)

CC

Figure 30. Reference Output Voltage vs. Temperature for

Different Supply Voltages

Figure 33. PSRR

8

6

AV , V

CC DRIVE

= 5V

F

= 200kSPS

SAMPLE

4

2

0

–2

–4

–6

–8

–10

+85°C

+25°C

–40°C

–10

–8

–6

–4

–2

0

2

4

6

8

10

INPUT VOLTAGE (V)

Figure 31. Analog Input Current vs. Temperature for Various Supply Voltages

Rev. D | Page 20 of 36

Data Sheet

AD7606/AD7606-6/AD7606-4

TERMINOLOGY

Integral Nonlinearity

Total Harmonic Distortion (THD)

The maximum deviation from a straight line passing through

the endpoints of the ADC transfer function. The endpoints of

the transfer function are zero scale, at ½ LSB below the first

code transition; and full scale, at ½ LSB above the last code

transition.

The ratio of the rms sum of the harmonics to the fundamental.

For the AD7606/AD7606-6/AD7606-4, it is defined as

THD (dB) =

2

V₂²+V₃²+V₄²+V₅²+V₆²+V₇²+V₈²+V₉

20log

V₁

Differential Nonlinearity

The difference between the measured and the ideal 1 LSB

change between any two adjacent codes in the ADC.

where:

V₁is the rms amplitude of the fundamental.

V₂to V₉are the rms amplitudes of the second through ninth

harmonics.

Peak Harmonic or Spurious Noise

The ratio of the rms value of the next largest component in the

ADC output spectrum (up to f_S/2, excluding dc) to the rms value

of the fundamental. Normally, the value of this specification is

determined by the largest harmonic in the spectrum, but for

ADCs where the harmonics are buried in the noise floor, it is

determined by a noise peak.

Bipolar Zero Code Error

The deviation of the midscale transition (all 1s to all 0s) from

the ideal, which is 0 V − ½ LSB.

Bipolar Zero Code Error Match

The absolute difference in bipolar zero code error between any

two input channels.

Positive Full-Scale Error

The deviation of the actual last code transition from the ideal

last code transition (10 V − 1½ LSB (9.99954) and 5 V − 1½ LSB

(4.99977)) after bipolar zero code error is adjusted out. The

positive full-scale error includes the contribution from the

internal reference buffer.

Intermodulation Distortion

With inputs consisting of sine waves at two frequencies, fa and fb,

any active device with nonlinearities creates distortion products

at sum and difference frequencies of mfa nfb, where m, n = 0,

1, 2, 3. Intermodulation distortion terms are those for which

neither m nor n is equal to 0. For example, the second-order

terms include (fa + fb) and (fa − fb), and the third-order terms

include (2fa + fb), (2fa − fb), (fa + 2fb), and (fa − 2fb).

The calculation of the intermodulation distortion is per the

THD specification, where it is the ratio of the rms sum of the

individual distortion products to the rms amplitude of the sum

of the fundamentals expressed in decibels (dB).

Positive Full-Scale Error Match

The absolute difference in positive full-scale error between any

two input channels.

Negative Full-Scale Error

The deviation of the first code transition from the ideal first

code transition (−10 V + ½ LSB (−9.99984) and −5 V + ½ LSB

(−4.99992)) after the bipolar zero code error is adjusted out.

The negative full-scale error includes the contribution from the

internal reference buffer.

Power Supply Rejection Ratio (PSRR)

Variations in power supply affect the full-scale transition but not

the converter’s linearity. PSR is the maximum change in full-

scale transition point due to a change in power supply voltage

from the nominal value. The PSR ratio (PSRR) is defined as the

ratio of the power in the ADC output at full-scale frequency, f,

to the power of a 100 mV p-p sine wave applied to the ADC’s

Negative Full-Scale Error Match

The absolute difference in negative full-scale error between any

two input channels.

Total Unadjusted Error (TUE)

TUE is a comprehensive specification that includes the gain

linearity and offset errors.

Signal-to-(Noise + Distortion) Ratio

The measured ratio of signal-to-(noise + distortion) at the

output of the ADC. The signal is the rms amplitude of the

fundamental. Noise is the sum of all nonfundamental signals

up to half the sampling frequency (f_S/2, excluding dc).

V

_DDand V_SSsupplies of Frequency f_S.

PSRR (dB) = 10 log (Pf/Pf_S)

where:

Pf is equal to the power at Frequency f in the ADC output.

Pf_Sis equal to the power at Frequency f_Scoupled onto the AV_CC

supply.

Channel-to-Channel Isolation

The ratio depends on the number of quantization levels in

the digitization process: the more levels, the smaller the

quantization noise.

Channel-to-channel isolation is a measure of the level of crosstalk

between all input channels. It is measured by applying a full-scale

sine wave signal, up to 160 kHz, to all unselected input channels

and then determining the degree to which the signal attenuates

in the selected channel with a 1 kHz sine wave signal applied (see

Figure 28).

The theoretical signal-to-(noise + distortion) ratio for an ideal

N-bit converter with a sine wave input is given by

Signal-to-(Noise + Distortion) = (6.02 N + 1.76) dB

Thus, for a 16-bit converter, the signal-to-(noise + distortion)

is 98 dB.

Rev. D | Page 21 of 36

AD7606/AD7606-6/AD7606-4

Data Sheet

THEORY OF OPERATION

Analog Input Clamp Protection

CONVERTER DETAILS

Figure 34 shows the analog input structure of the AD7606/

AD7606-6/AD7606-4. Each analog input of the AD7606/

AD7606-6/AD7606-4 contains clamp protection circuitry.

Despite single ꢀ V supply operation, this analog input clamp

protection allows for an input over voltage of up to ±±6.ꢀ V.

The AD7606/AD7606-6/AD7606-4 are data acquisition systems

that employ a high speed, low power, charge redistribution,

successive approximation analog-to-digital converter (ADC)

and allow the simultaneous sampling of eight/six/four analog input

channels. The analog inputs on the AD7606/AD7606-6/AD7606-4

can accept true bipolar input signals. The RANGE pin is used to

select either ±±0 V or ±ꢀ V as the input range. The AD7606/

AD7606-6/AD7606-4 operate from a single ꢀ V supply.

R

FB

1MΩ

Vx

CLAMP

1MΩ

VxGND

The AD7606/AD7606-6/AD7606-4 contain input clamp

protection, input signal scaling amplifiers, a second-order anti-

aliasing filter, track-and-hold amplifiers, an on-chip reference,

reference buffers, a high speed ADC, a digital filter, and high

speed parallel and serial interfaces. Sampling on the AD7606/

AD7606-6/AD7606-4 is controlled using the CONVST signals.

SECOND-

ORDER

LPF

R

FB

Figure 34. Analog Input Circuitry

Figure 3ꢀ shows the voltage vs. current characteristic of the

clamp circuit. For input voltages of up to ±±6.ꢀ V, no current

flows in the clamp circuit. For input voltages that are above ±±6.ꢀ V,

the AD7606/AD7606-6/AD7606-4 clamp circuitry turns on.

ANALOG INPUT

Analog Input Ranges

AV , V

CC DRIVE

= 5V

30

20

T

= 25°C

A

The AD7606/AD7606-6/AD7606-4 can handle true bipolar,

single-ended input voltages. The logic level on the RANGE pin

determines the analog input range of all analog input channels.

If this pin is tied to a logic high, the analog input range is ±±0 V

for all channels. If this pin is tied to a logic low, the analog input

range is ±ꢀ V for all channels. A logic change on this pin has an

immediate effect on the analog input range; however, there is

typically a settling time of approximately 80 μs, in addition to

the normal acquisition time requirement. The recommended

practice is to hardwire the RANGE pin according to the desired

input range for the system signals.

10

0

–10

–20

–30

–40

–50

–20

–15

–10

–5

0

5

10

15

20

During normal operation, the applied analog input voltage

should remain within the analog input range selected via the

RANGE pin. A RESET pulse must be applied after power up to

ensure the analog input channels are configured for the range

selected.

SOURCE VOLTAGE (V)

Figure 35. Input Protection Clamp Profile

A series resistor should be placed on the analog input channels

to limit the current to ±±0 mA for input voltages above ±±6.ꢀ V.

In an application where there is a series resistance on an analog

input channel, Vx, a corresponding resistance is required on the

analog input GND channel, VxGND (see Figure 36). If there is

no corresponding resistor on the VxGND channel, an offset

error occurs on that channel. It is recommended that the input

overvoltage clamp protection circuitry be used to protect the

AD7606/AD7606-6/AD7606-4 against transient overvoltage

events. It is not recommended to leave the AD7606/AD7606-6/

AD7606-4 in a condition where the clamp protection circuitry

is active in normal or power-down conditions for extended

periods because this may degrade the bipolar zero code error

performance of the AD7606/AD7606-6/AD7606-4.

When in a power-down mode, it is recommended to tie the

analog inputs to GND. Per the Analog Input Clamp Protection

section, the overvoltage clamp protection is recommended for

use in transient overvoltage conditions and should not remain

active for extended periods. Stressing the analog inputs outside

of the conditions mentioned here may degrade the bipolar zero

code error and THD performance of the AD7606/AD7606-6/

AD7606-4.

Analog Input Impedance

The analog input impedance of the AD7606/AD7606-6/

AD7606-4 is ± MΩ. This is a fixed input impedance that does

not vary with the AD7606 sampling frequency. This high analog

input impedance eliminates the need for a driver amplifier in

front of the AD7606/AD7606-6/AD7606-4, allowing for direct

connection to the source or sensor. With the need for a driver

amplifier eliminated, bipolar supplies (which are often a source

of noise in a system) can be removed from the signal chain.

Rev. D | Page 22 of 36

Data Sheet

AD7606/AD7606-6/AD7606-4

R

hold (that is, the delay time between the external CONꢀST x

signal and the track-and-hold actually going into hold) is well

matched, by design, across all eight track-and-holds on one

device and from device to device. This matching allows more

than one AD7606/AD7606-6/AD7606-4 device to be sampled

simultaneously in a system.

FB

AD7606

ANALOG

INPUT

R

1MΩ

Vx

CLAMP

SIGNAL

C

VxGND

FB

Figure 36. Input Resistance Matching on the Analog Input of the

AD7606/AD7606-6/AD7606-4

The end of the conversion process across all eight channels is

indicated by the falling edge of BUSY; and it is at this point that the

track-and-holds return to track mode, and the acquisition time

for the next set of conversions begins.

Analog Input Antialiasing Filter

An analog antialiasing filter (a second-order Butterworth) is also

provided on the AD7606/AD7606-6/AD7606-4. Figure 37 and

Figure 38 show the frequency and phase response, respectively,

of the analog antialiasing filter. In the ±± ꢀ range, the −3 dB

frequency is typically 1± kHz. In the ±10 ꢀ range, the −3 dB

frequency is typically 23 kHz.

The conversion clock for the part is internally generated, and

the conversion time for all channels is 4 μs on the AD7606,

3 μs on the AD7606-6, and 2 μs on the AD7606-4. On the AD7606,

the BUSY signal returns low after all eight conversions to indicate

the end of the conversion process. On the falling edge of BUSY,

the track-and-hold amplifiers return to track mode. New data

can be read from the output register via the parallel, parallel

byte, or serial interface after BUSY goes low; or, alternatively,

data from the previous conversion can be read while BUSY is

high. Reading data from the AD7606/AD7606-6/AD7606-4

while a conversion is in progress has little effect on performance

and allows a faster throughput to be achieved. In parallel mode

at ꢀ_DRIꢀE> 3.3 ꢀ, the SNR is reduced by ~1.± dB when reading

during a conversion.

5

0

±10V RANGE

AV , V

CC DRIVE

= 5V

–5

–10

–15

–20

–25

–30

–35

–40

F

T

= 200kSPS

SAMPLE

= 25°C

±5V RANGE

A

±10V RANGE 0.1dB

3dB

–40 10,303 24,365Hz

+25 9619

+85 9326

23,389Hz

22,607Hz

±5V RANGE

0.1dB

–40 5225

+25 5225

+85 4932

3dB

ADC TRANSFER FUNCTION

16,162Hz

15,478Hz

14,990Hz

The output coding of the AD7606/AD7606-6/AD7606-4 is

twos complement. The designed code transitions occur midway

between successive integer LSB values, that is, 1/2 LSB and 3/2 LSB.

The LSB size is FSR/6±,±36 for the AD7606. The ideal transfer

characteristic for the AD7606/AD7606-6/AD7606-4 is shown

in Figure 39.

100

1k

10k

100k

INPUT FREQUENCY (Hz)

Figure 37. Analog Antialiasing Filter Frequency Response

18

VIN

10V

VIN

5V

REF

2.5V

REF

2.5V

±10V CODE =

× 32,768 ×

16

14

12

10

8

±5V RANGE

±10V RANGE

±5V CODE =

× 32,768 ×

011...111

011...110

+FS – (–FS)

2¹⁶

000...001

000...000

111...111

LSB =

6

4

2

100...010

100...001

100...000

0

–2

–4

–6

–8

–FS + 1/2LSB 0V – 1/2LSB +FS – 3/2LSB

AV , V

= 5V

= 200kSPS

CC DRIVE

ANALOG INPUT

F

T

SAMPLE

= 25°C

A

+FS

±10V RANGE +10V

±5V RANGE +5V

MIDSCALE –FS

LSB

305µV

152µV

0V

–10V

–5V

10

1k

10k

100k

INPUT FREQUENCY (Hz)

Figure 39. AD7606/AD7606-6/AD7606-4 Transfer Characteristics

Figure 38. Analog Antialias Filter Phase Response

The LSB size is dependent on the analog input range selected.

Track-and-Hold Amplifiers

The track-and-hold amplifiers on the AD7606/AD7606-6/

AD7606-4 allow the ADC to accurately acquire an input sine wave

of full-scale amplitude to 16-bit resolution. The track-and-hold

amplifiers sample their respective inputs simultaneously on the

rising edge of CONꢀST x. The aperture time for the track-and-

Rev. D | Page 23 of 36

AD7606/AD7606-6/AD7606-4

Data Sheet

Internal Reference Mode

INTERNAL/EXTERNAL REFERENCE

One AD7606/AD7606-6/AD7606-4 device, configured to operate

in the internal reference mode, can be used to drive the remaining

AD7606/AD7606-6/AD7606-4 devices, which are configured to

operate in external reference mode (see Figure 42). The REFIN/

REFOUT pin of the AD7606/AD7606-6/AD7606-4, configured

in internal reference mode, should be decoupled using a 10 µF

ceramic decoupling capacitor. The other AD7606/AD7606-6/

AD7606-4 devices, configured in external reference mode,

should use at least a 100 nF decoupling capacitor on their

REFIN/REFOUT pins.

The AD7606/AD7606-6/AD7606-4 contain an on-chip 2.5 V

band gap reference. The REFIN/REFOUT pin allows access to

the 2.5 V reference that generates the on-chip 4.5 V reference

internally, or it allows an external reference of 2.5 V to be applied

to the AD7606/AD7606-6/AD7606-4. An externally applied

reference of 2.5 V is also gained up to 4.5 V, using the internal

buffer. This 4.5 V buffered reference is the reference used by the

SAR ADC.

The REF SELECT pin is a logic input pin that allows the user to

select between the internal reference and an external reference.

If this pin is set to logic high, the internal reference is selected

and enabled. If this pin is set to logic low, the internal reference

is disabled and an external reference voltage must be applied

to the REFIN/REFOUT pin. The internal reference buffer is

always enabled. After a reset, the AD7606/AD7606-6/AD7606-4

operate in the reference mode selected by the REF SELECT pin.

Decoupling is required on the REFIN/REFOUT pin for both

the internal and external reference options. A 10 µF ceramic

capacitor is required on the REFIN/REFOUT pin.

REFIN/REFOUT

SAR

REFCAPA

BUF

10µF

REFCAPB

2.5V

REF

Figure 40. Reference Circuitry

The AD7606/AD7606-6/AD7606-4 contain a reference buffer

configured to gain the REF voltage up to ~4.5 V, as shown in

Figure 40. The REFCAPA and REFCAPB pins must be shorted

together externally, and a ceramic capacitor of 10 μF applied to

REFGND, to ensure that the reference buffer is in closed-loop

operation. The reference voltage available at the REFIN/REFOUT

pin is 2.5 V.

AD7606

REF SELECT

REFIN/REFOUT

100nF

ADR421

0.1µF

When the AD7606/AD7606-6/AD7606-4 are configured in

external reference mode, the REFIN/REFOUT pin is a high

input impedance pin. For applications using multiple AD7606

devices, the following configurations are recommended,

depending on the application requirements.

Figure 41. Single External Reference Driving Multiple AD7606/AD7606-6/

AD7606-4 REFIN Pins

V

DRIVE

External Reference Mode

AD7606

REF SELECT

One ADR421 external reference can be used to drive the

REFIN/REFOUT pins of all AD7606 devices (see Figure 41).

In this configuration, each REFIN/REFOUT pin of the

AD7606/AD7606-6/AD7606-4 should be decoupled with at

least a 100 nF decoupling capacitor.

REFIN/REFOUT

+

10µF

100nF

Figure 42. Internal Reference Driving Multiple AD7606/AD7606-6/AD7606-4

REFIN Pins

Rev. D | Page 24 of 36

Data Sheet

AD7606/AD7606-6/AD7606-4

The power-down mode is selected through the state of the

TYPICAL CONNECTION DIAGRAM

STBY

RANGE pin when the

pin is low. Table 7 shows the

Figure 43 shows the typical connection diagram for the AD7606/

AD7606-6/AD7606-4. There are four AV_CCsupply pins on the

part, and each of the four pins should be decoupled using a 100 nF

capacitor at each supply pin and a 10 µF capacitor at the supply

source. The AD7606/AD7606-6/AD7606-4 can operate with the

internal reference or an externally applied reference. In this

configuration, the AD7606 is configured to operate with the

internal reference. When using a single AD7606/AD7606-6/

AD7606-4 device on the board, the REFIN/REFOUT pin

should be decoupled with a 10 µF capacitor. Refer to the

Internal/External Reference section when using an application

with multiple AD7606/AD7606-6/AD7606-4 devices. The

REFCAPA and REFCAPB pins are shorted together and

decoupled with a 10 µF ceramic capacitor.

configurations required to choose the desired power-down mode.

When the AD7606/AD7606-6/AD7606-4 are placed in standby

mode, the current consumption is 8 mA maximum and power-

up time is approximately 100 µs because the capacitor on the

REFCAPA and REFCAPB pins must charge up. In standby mode,

the on-chip reference and regulators remain powered up, and

the amplifiers and ADC core are powered down.

When the AD7606/AD7606-6/AD7606-4 are placed in shutdown

mode, the current consumption is 6 µA maximum and power-up

time is approximately 13 ms (external reference mode). In shut-

down mode, all circuitry is powered down. When the AD7606/

AD7606-6/AD7606-4 are powered up from shutdown mode,

a RESET signal must be applied to the AD7606/AD7606-6/

AD7606-4 after the required power-up time has elapsed.

The V_DRIVEsupply is connected to the same supply as the

processor. The V_DRIVEvoltage controls the voltage value of the

output logic signals. For layout, decoupling, and grounding

hints, see the Layout Guidelines section.

Table 7. Power-Down Mode Selection

STBY

Power-Down Mode

Standby

Shutdown

RANGE

0

1

0

After supplies are applied to the AD7606/AD7606-6/AD7606-4,

a reset should be applied to the AD7606/AD7606-6/AD7606-4

to ensure that it is configured for the correct mode of operation.

POWER-DOWN MODES

Two power-down modes are available on the AD7606/AD7606-6/

STBY

AD7606-4: standby mode and shutdown mode. The

controls whether the AD7606/AD7606-6/AD7606-4 are in

normal mode or in one of the two power-down modes.

ANALOG SUPPLY

VOLTAGE 5V¹

DIGITAL SUPPLY

VOLTAGE +2.3V TO +5.25V

+

1µF

10µF

100nF

2

AV

V

DRIVE

REFIN/REFOUT

REFCAPA

REGCAP

CC

PARALLEL

INTERFACE

+

DB0 TO DB15

10µF

REFCAPB

REFGND

CONVST A, CONVST B

CS

RD

BUSY

V1

V1GND

V2

V2GND

V3

V3GND

V4

AD7606

RESET

OS 2

OS 1

OS 0

OVERSAMPLING

EIGHT ANALOG

INPUTS V1 TO V8

V4GND

V5

REF SELECT

PAR/SER SEL

V

DRIVE

V5GND

V6

V6GND

V7

V7GND

V8

V8GND

RANGE

STBY

V

DRIVE

AGND

1

DECOUPLING SHOWN ON THE AV PIN APPLIES TO EACH AV PIN (PIN 1, PIN 37, PIN 38, PIN 48).

CC

DECOUPLING CAPACITOR CAN BE SHARED BETWEEN AV

PIN 37 AND PIN 38.

CC

2

DECOUPLING SHOWN ON THE REGCAP PIN APPLIES TO EACH REGCAP PIN (PIN 36, PIN 39).

Figure 43. AD7606 Typical Connection Diagram

Rev. D | Page 25 of 36

AD7606/AD7606-6/AD7606-4

Data Sheet

transformers. In a 50 Hz system, this allows for up to 9° of phase

compensation; and in a 60 Hz system, it allows for up to 10° of

phase compensation.

CONVERSION CONTROL

Simultaneous Sampling on All Analog Input Channels

The AD7606/AD7606-6/AD7606-4 allow simultaneous sampling

of all analog input channels. All channels are sampled simul-

taneously when both CONVST pins (CONVST A, CONVST B)

are tied together. A single CONVST signal is used to control both

CONVST x inputs. The rising edge of this common CONVST

signal initiates simultaneous sampling on all analog input channels

(V1 to V8 for the AD7606, V1 to V6 for the AD7606-6, and V1

to V4 for the AD7606-4).

This is accomplished by pulsing the two CONVST pins

independently and is possible only if oversampling is not in use.

CONVST A is used to initiate simultaneous sampling of the

first set of channels (V1 to V4 for the AD7606, V1 to V3 for the

AD7606-6, and V1 and V2 for the AD7606-4); and CONVST B

is used to initiate simultaneous sampling on the second set of

analog input channels (V5 to V8 for the AD7606, V4 to V6 for

the AD7606-6, and V3 and V4 for the AD7606-4), as illustrated

in Figure 44. On the rising edge of CONVST A, the track-and-

hold amplifiers for the first set of channels are placed into hold

mode. On the rising edge of CONVST B, the track-and-hold

amplifiers for the second set of channels are placed into hold

mode. The conversion process begins once both rising edges

of CONVST x have occurred; therefore BUSY goes high on the

rising edge of the later CONVST x signal. In Table 3, Time t₅

indicates the maximum allowable time between CONVST x

sampling points.

The AD7606 contains an on-chip oscillator that is used to

perform the conversions. The conversion time for all ADC

channels is t_CONV. The BUSY signal indicates to the user when

conversions are in progress, so when the rising edge of CONVST

is applied, BUSY goes logic high and transitions low at the end

of the entire conversion process. The falling edge of the BUSY

signal is used to place all eight track-and-hold amplifiers back

into track mode. The falling edge of BUSY also indicates that

the new data can now be read from the parallel bus (DB[15:0]),

the D_OUTA and D_OUTB serial data lines, or the parallel byte bus,

DB[7:0].

There is no change to the data read process when using two

separate CONVST x signals.

Simultaneously Sampling Two Sets of Channels

Connect all unused analog input channels to AGND. The results

for any unused channels are still included in the data read because

all channels are always converted.

The AD7606/AD7606-6/AD7606-4 also allow the analog input

channels to be sampled simultaneously in two sets. This can be

used in power-line protection and measurement systems to

compensate for phase differences introduced by PT and CT

V1 TO V4 TRACK-AND-HOLD

ENTER HOLD

V5 TO V8 TRACK-AND-HOLD

ENTER HOLD

t₅

CONVST A

CONVST B

BUSY

AD7606 CONVERTS

ON ALL 8 CHANNELS

t_CONV

CS/RD

V1

V2

V3

V7

V8

DATA: DB[15:0]

FRSTDATA

Figure 44. AD7606 Simultaneous Sampling on Channel Sets While Using Independent CONVST A and CONVST B Signals—Parallel Mode

Rev. D | Page 26 of 36

Data Sheet

AD7606/AD7606-6/AD7606-4

DIGITAL INTERFACE

The AD7606/AD7606-6/AD7606-4 provide three interface

options: a parallel interface, a high speed serial interface, and

a parallel byte interface. The required interface mode is selected

RD

signal is logic low, it enables the data conversion

result from each channel to be transferred to the digital host

(DSP, FPGA).

When the

PAR

via the

/SER/BYTE SEL and DB15/BYTE SEL pins.

When there is only one AD7606/AD7606-6/AD7606-4 in

a system/board and it does not share the parallel bus, data can

be read using just one control signal from the digital host. The

Table 8. Interface Mode Selection

PAR/SER/BYTE SEL

DB1±

Interface Mode

CS

RD

and

In this case, the data bus comes out of three-state on the falling

CS RD CS RD

signal allows the data

signals can be tied together, as shown in Figure 5.

0

1

0

1

Parallel interface mode

Serial interface mode

Parallel byte interface mode

edge of

/

. The combined

and

to be clocked out of the AD7606/AD7606-6/AD7606-4 and to

Operation of the interface modes is discussed in the following

sections.

CS

be read by the digital host. In this case,

data transfer of each data channel.

is used to frame the

PARALLEL INTERFACE (PAR/SER/BYTE SEL = 0)

PARALLEL BYTE (PAR/SER/BYTE SEL = 1, DB1± = 1)

Data can be read from the AD7606/AD7606-6/AD7606-4 via

Parallel byte interface mode operates much like the parallel

interface mode, except that each channel conversion result is read

CS

RD

the parallel data bus with standard

PAR

and

signals. To read the

data over the parallel bus, the

CS RD

/SER/BYTE SEL pin should

input signals are internally gated to

RD

out in two 8-bit transfers. Therefore, 16

to read all eight conversion results from the AD7606. For the

RD

pulses are required

be tied low. The

and

enable the conversion result onto the data bus. The data lines,

CS

AD7606-6, 12

pulses are required; and on the AD7606-4,

pulses are required to read all the channel results.

To configure the AD7606/AD76706-6/AD7606-4 to operate in

PAR

DB15 to DB0, leave their high impedance state when both

RD

eight

and

are logic low.

parallel byte mode, the

/SER/BYTE SEL and BYTE SEL/

AD7606

INTERRUPT

BUSY 14

DB15 pins should be tied to logic high (see Table 8). In parallel

byte mode, DB[7:0] are used to transfer the data to the digital

host. DB0 is the LSB of the data transfer, and DB7 is the MSB of

the data transfer. In parallel byte mode, DB14 acts as an HBEN

pin. When DB14/HBEN is tied to logic high, the most

significant byte (MSB) of the conversion result is output first,

followed by the LSB of the conversion result. When DB14 is tied

to logic low, the LSB of the conversion result is output first,

followed by the MSB of the conversion result. The FRSTDATA

pin remains high until the entire 16 bits of the conversion result

from V1 are read from the AD7606/AD7606-6/AD7606-4.

13

12

CS

RD/SCLK

DB[15:0]

DIGITAL

HOST

[33:24]

[22:16]

Figure 4±. AD7606 Interface Diagram—One AD7606 Using the Parallel Bus,

CS RD

with and

Shorted Together

CS

The rising edge of the

the falling edge of the

high impedance state.

input signal three-states the bus, and

input signal takes the bus out of the

is the control signal that enables the

data lines; it is the function that allows multiple AD7606/

AD7606-6/ AD7606-4 devices to share the same parallel

data bus.

SERIAL INTERFACE (PAR/SER/BYTE SEL = 1)

To read data back from the AD7606 over the serial interface, the

CS

RD

signal

The

signal can be permanently tied low, and the

PAR

CS

/SER/BYTE SEL pin must be tied high. The

and SCLK

can be used to access the conversion results as shown in Figure 4.

A read operation of new data can take place after the BUSY

signal goes low (see Figure 2); or, alternatively, a read operation

of data from the previous conversion process can take place

while BUSY is high (see Figure 3).

signals are used to transfer data from the AD7606. The AD7606/

AD7606-6/AD7606-4 have two serial data output pins, D_OUTA

and D_OUTB. Data can be read back from the AD7606/AD76706-

6/AD7606-4 using one or both of these D_OUTlines. For the

AD7606, conversion results from Channel V1 to Channel V4

first appear on D_OUTA, and conversion results from Channel V5

to Channel V8 first appear on D_OUTB. For the AD7606-6,

conversion results from Channel V1 to Channel V3 first appear

on D_OUTA, and conversion results from Channel V4 to Channel

V6 first appear on D_OUTB. For the AD7606-4, conversion results

from Channel V1 and Channel V2 first appear on D_OUTA, and

conversion results from Channels V3 and Channel V4 first

appear on D_OUTB.

RD

The

results register. Applying a sequence of

of the AD7606/AD7606-6/AD7606-4 clocks the conversion

pin is used to read data from the output conversion

RD RD

pulses to the

results out from each channel onto the Parallel Bus DB[15:0] in

RD

ascending order. The first

falling edge after BUSY goes low

RD

clocks out the conversion result from Channel V1. The next

falling edge updates the bus with the V2 conversion result, and so

on. On the AD7606, the eighth falling edge of

conversion result for Channel V8.

RD

clocks out the

Rev. D | Page 27 of 36

AD7606/AD7606-6/AD7606-4

Data Sheet

CS

takes the bus out of three-state and clocks

The falling edge takes the data output lines, D_OUTA and D_OUTB,

The falling edge of

out of three-state and clocks out the MSB of the conversion

result. The rising edge of SCLK clocks all subsequent data bits

out the MSB of the 16-bit conversion result. This MSB is valid

CS

on the first falling edge of the SCLK after the

falling edge.

CS

onto the serial data outputs, D_OUTA and D_OUTB. The

input

The subsequent 15 data bits are clocked out of the AD7606/

AD7606-6/AD7606-4 on the SCLK rising edge. Data is valid on

the SCLK falling edge. To access each conversion result, 16 clock

cycles must be provided to the AD7606/AD7606-6/AD7606-4.

can be held low for the entire serial read operation, or it can be

pulsed to frame each channel read of 16 SCLK cycles. Figure 46

shows a read of eight simultaneous conversion results using two

D

_OUTlines on the AD7606. In this case, a 64 SCLK transfer is used

The FRSTDATA output signal indicates when the first channel,

CS

to access data from the AD7606, and is held low to frame the

entire 64 SCLK cycles. Data can also be clocked out using just

one D_OUTline, in which case it is recommended that D_OUTA be

used to access all conversion data because the channel data is

output in ascending order. For the AD7606 to access all eight

conversion results on one D_OUTline, a total of 128 SCLK cycles

CS

V1, is being read back. When the input is high, the FRSTDATA

output pin is in three-state. In serial mode, the falling edge of

CS

takes FRSTDATA out of three-state and sets the FRSTDATA

pin high, indicating that the result from V1 is available on the

D_OUTA output data line. The FRSTDATA output returns to

a logic low following the 16^thSCLK falling edge. If all channels

are read on D_OUTB, the FRSTDATA output does not go high when

V1 is being output on this serial data output pin. It goes high

only when V1 is available on D_OUTA (and this is when V5 is

available on D_OUTB for the AD7606).

CS

is required. These 128 SCLK cycles can be framed by one

signal, or each group of 16 SCLK cycles can be individually

CS

framed by the

signal. The disadvantage of using just one

D_OUTline is that the throughput rate is reduced if reading occurs

after conversion. The unused D_OUTline should be left unconnected

in serial mode. For the AD7606, if D_OUTB is to be used as a single

READING DURING CONVERSION

Data can be read from the AD7606/AD7606-6/AD7606-4 while

BUSY is high and the conversions are in progress. This has little

effect on the performance of the converter, and it allows a faster

throughput rate to be achieved. A parallel, parallel byte, or serial

read can be performed during conversions and when oversampling

may or may not be in use. Figure 3 shows the timing diagram for

reading while BUSY is high in parallel or serial mode. Reading

during conversions allows the full throughput rate to be achieved

when using the serial interface with V_DRIVEabove 4.75 V.

D

_OUTline, the channel results are output in the following order:

V5, V6, V7, V8, V1, V2, V3, and V4; however, the FRSTDATA

indicator returns low after V5 is read on D_OUTB. For the AD7606-6

and the AD7606-4, if D_OUTB is to be used as a single D_OUTline,

the channel results are output in the following order: V4, V5, V6,

V1, V2, and V3 for the AD7606-6; and V3, V4, V1, and V2 for

the AD7606-4.

Figure 6 shows the timing diagram for reading one channel of

CS

data, framed by the

AD7606-4 in serial mode. The SCLK input signal provides the

CS

signal, from the AD7606/AD7606-6/

Data can be read from the AD7606 at any time other than on

the falling edge of BUSY because this is when the output data

registers are updated with the new conversion data. Time t₆, as

outlined in Table 3, should be observed in this condition.

clock source for the serial read operation. The

goes low to

access the data from the AD7606/AD7606-6/AD7606-4.

CS

64

SCLK

D

A

B

V1

V5

V2

V6

V3

V7

V4

V8

OUT

Figure 46. AD7606 Serial Interface with Two D_OUTLines

Rev. D | Page 28 of 36

Data Sheet

AD7606/AD7606-6/AD7606-4

t_CYCLE

DIGITAL FILTER

CONVST A

AND

The AD7606/AD7606-6/AD7606-4 contain an optional digital

first-order sinc filter that should be used in applications where

slower throughput rates are used or where higher signal-to-noise

ratio or dynamic range is desirable. The oversampling ratio of the

digital filter is controlled using the oversampling pins, OS [2:0] (see

Table 9). OS 2 is the MSB control bit, and OS 0 is the LSB control

bit. Table 9 provides the oversampling bit decoding to select the

different oversample rates. The OS pins are latched on the falling

edge of BUSY. This sets the oversampling rate for the next

conversion (see Figure 48). In addition to the oversampling

function, the output result is decimated to 16-bit resolution.

t_CONV

19µs

CONVST B

9µs

4µs

OS = 0 OS = 2 OS = 4

BUSY

t₄

CS

RD

DATA:

DB[15:0]

If the OS pins are set to select an OS ratio of eight, the next

CONVST x rising edge takes the first sample for each channel,

and the remaining seven samples for all channels are taken with

an internally generated sampling signal. These samples are then

averaged to yield an improvement in SNR performance. Table 9

shows typical SNR performance for both the 10 V and the 5 V

range. As Table 9 shows, there is an improvement in SNR as the

OS ratio increases. As the OS ratio increases, the 3 dB frequency

is reduced, and the allowed sampling frequency is also reduced.

In an application where the required sampling frequency is

10 kSPS, an OS ratio of up to 16 can be used. In this case, the

application sees an improvement in SNR, but the input 3 dB

bandwidth is limited to ~6 kHz.

Figure 47. AD7606—No Oversampling, Oversampling × 2, and

Oversampling × 4 While Using Read After Conversion

Figure 47 shows that the conversion time extends as the over-

sampling rate is increased, and the BUSY signal lengthens for the

different oversampling rates. For example, a sampling frequency

of 10 kSPS yields a cycle time of 100 µs. Figure 47 shows OS × 2

and OS × 4; for a 10 kSPS example, there is adequate cycle time to

further increase the oversampling rate and yield greater improve-

ments in SNR performance. In an application where the initial

sampling or throughput rate is at 200 kSPS, for example, and

oversampling is turned on, the throughput rate must be reduced

to accommodate the longer conversion time and to allow for the

read. To achieve the fastest throughput rate possible when over-

sampling is turned on, the read can be performed during the

BUSY high time. The falling edge of BUSY is used to update the

output data registers with the new conversion data; therefore, the

reading of conversion data should not occur on this edge.

The CONVST A and CONVST B pins must be tied/driven

together when oversampling is turned on. When the over-

sampling function is turned on, the BUSY high time for the

conversion process extends. The actual BUSY high time

depends on the oversampling rate that is selected: the higher the

oversampling rate, the longer the BUSY high, or total conversion

time (see Table 3).

CONVST A

AND

CONVST B

OVERSAMPLE RATE

LATCHED FOR CONVERSION N + 1

CONVERSION N

CONVERSION N + 1

BUSY

t_{OS_HOLD}

t_{OS_SETUP}

OS x

Figure 48. OS x Pin Timing

Table 9. Oversample Bit Decoding

Maximum Throughput

OS

SNR ± V Range SNR 10 V Range

3 dB BW ± V Range 3 dB BW 10 V Range

OS[2:0] Ratio

(dB)

(kHz)

CONVST Frequency (kHz)

000

001

010

011

100

101

110

111

No OS

2

4

8

16

32

64

Invalid

89

90

92

93.6

95

96

15

13.7

10.3

6

22

18.5

11.9

6

200

100

50

91.2

92.6

94.2

95.5

96.4

96.9

25

12.5

6.25

3.125

96.7

97

3

1.5

3

1.5

Rev. D | Page 29 of 36

AD7606/AD7606-6/AD7606-4

Data Sheet

1400

1200

1000

800

600

400

200

0

Figure 49 to Figure 55 illustrate the effect of oversampling on

the code spread in a dc histogram plot. As the oversample rate

is increased, the spread of the codes is reduced.

1000

OVERSAMPLING BY 8

= 25kSPS

1263

F

SAMPLE

AV = 5V

CC

V

= 2.5V

DRIVE

NO OVERSAMPLING

= 200kSPS

928

887

783

F

SAMPLE

AV = 5V

900

800

700

600

500

400

300

200

100

0

CC

V

= 2.5V

DRIVE

0

2

0

2

0

3

–3

–2

–1

0

1

CODE (LSB)

131

–1

97

2

Figure ±2. Histogram of Codes—OS × 8 (Three Codes)

0

3

2

3

1400

OVERSAMPLING BY 16

= 12.5kSPS

–3

–2

0

1

1453

F

SAMPLE

AV = 5V

CODE (LSB)

1200

1000

800

600

400

200

0

CC

V

= 2.5V

DRIVE

Figure 49. Histogram of Codes—No OS (Six Codes)

1400

OVERSAMPLING BY 2

= 100kSPS

F

SAMPLE

AV = 5V

1200

1000

800

600

400

200

0

CC

1148

V

= 2.5V

DRIVE

595

804

0

2

0

3

–3

–2

–1

0

1

CODE (LSB)

Figure ±3. Histogram of Codes—OS × 16 (Two Codes)

80

–1

1600

16

2

0

3

OVERSAMPLING BY 32

= 6.125kSPS

1417

F

–3

–2

0

1

SAMPLE

AV = 5V

1400

1200

1000

800

600

400

200

0

CC

CODE (LSB)

V

= 2.5V

DRIVE

Figure ±0. Histogram of Codes—OS × 2 (Four Codes)

1400

OVERSAMPLING BY 4

= 50kSPS

1262

F

SAMPLE

AV = 5V

1200

1000

800

600

400

200

0

CC

631

V

= 2.5V

DRIVE

764

0

2

0

3

–3

–2

–1

0

1

CODE (LSB)

Figure ±4. Histogram of Codes—OS × 32 (Two Codes)

1600

OVERSAMPLING BY 64

= 3kSPS

1679

19

–1

0

3

2

0

3

F

SAMPLE

AV = 5V

1400

1200

1000

800

600

400

200

0

–3

–2

0

1

CC

V

= 2.5V

DRIVE

CODE (LSB)

Figure ±1. Histogram of Codes—OS × 4 (Four Codes)

369

0

2

0

3

–3

–2

–1

0

1

CODE (LSB)

Figure ±±. Histogram of Codes—OS × 64 (Two Codes)

Rev. D | Page 30 of 36

Data Sheet

AD7606/AD7606-6/AD7606-4

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

When the oversampling mode is selected for the AD7606/

AD7606-6/AD7606-4, it has the effect of adding a digital filter

function after the ADC. The different oversampling rates and

the CONVST sampling frequency produce different digital filter

frequency profiles.

AV

= 5V

CC

V

DRIVE

= 25°C

T

A

10V RANGE

OS BY 16

Figure 56 to Figure 61 show the digital filter frequency profiles for

the different oversampling rates. The combination of the analog

antialiasing filter and the oversampling digital filter can be used

to eliminate and reduce the complexity of the design of any filter

before the AD7606/AD7606-6/AD7606-4. The digital filtering

combines steep roll-off and linear phase response.

100

1k

10k

100k

1M

10M

0

AV

= 5V

CC

FREQUENCY (Hz)

V

= 5V

DRIVE

= 25°C

–10

–20

–30

–40

–50

–60

–70

–80

–90

T

A

Figure ±9. Digital Filter Response for OS 16

10V RANGE

OS BY 2

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

AV

= 5V

CC

V

DRIVE

= 25°C

T

A

10V RANGE

OS BY 32

100

1k

10k

100k

1M

10M

FREQUENCY (Hz)

Figure ±6. Digital Filter Response for OS 2

100

1k

10k

100k

1M

10M

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

AV

= 5V

CC

FREQUENCY (Hz)

V

DRIVE

= 25°C

T

A

Figure 60. Digital Filter Response for OS 32

10V RANGE

OS BY 4

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

AV

= 5V

CC

V

T

= 5V

DRIVE

= 25°C

A

10V RANGE

OS BY 64

100

1k

10k

100k

1M

10M

FREQUENCY (Hz)

Figure ±7. Digital Filter Response for OS 4

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

100

1k

10k

100k

1M

10M

AV

= 5V

CC

FREQUENCY (Hz)

V

DRIVE

= 25°C

T

A

Figure 61. Digital Filter Response for OS 64

10V RANGE

OS BY 8

100

1k

10k

100k

1M

10M

FREQUENCY (Hz)

Figure ±8. Digital Filter Response for OS 8

Rev. D | Page 31 of 36

AD7606/AD7606-6/AD7606-4

Data Sheet

Figure 62 shows the recommended decoupling on the top layer

of the AD7606 board. Figure 63 shows bottom layer decoupling,

which is used for the four AV_CCpins and the V_DRIVEpin decoupling.

Where the ceramic 100 nF caps for the AV_CCpins are placed

close to their respective device pins, a single 100 nF capacitor

can be shared between Pin 37 and Pin 38.

LAYOUT GUIDELINES

The printed circuit board that houses the AD7606/AD7606-6/

AD7606-4 should be designed so that the analog and digital

sections are separated and confined to different areas of the board.

At least one ground plane should be used. It can be common or

split between the digital and analog sections. In the case of the

split plane, the digital and analog ground planes should be

joined in only one place, preferably as close as possible to the

AD7606/AD7606-6/AD7606-4.

If the AD7606/AD7606-6/AD7606-4 are in a system where

multiple devices require analog-to-digital ground connections,

the connection should still be made at only one point: a star

ground point that should be established as close as possible to the

AD7606/AD7606-6/AD7606-4. Good connections should be

made to the ground plane. Avoid sharing one connection for

multiple ground pins. Use individual vias or multiple vias to the

ground plane for each ground pin.

Avoid running digital lines under the devices because doing so

couples noise onto the die. The analog ground plane should be

allowed to run under the AD7606/AD7606-6/AD7606-4 to

avoid noise coupling. Fast switching signals like CONVST A,

CONVST B, or clocks should be shielded with digital ground

to avoid radiating noise to other sections of the board, and they

should never run near analog signal paths. Avoid crossover of

digital and analog signals. Traces on layers in close proximity on

the board should run at right angles to each other to reduce the

effect of feedthrough through the board.

Figure 62. Top Layer Decoupling REFIN/REFOUT,

REFCAPA, REFCAPB, and REGCAP Pins

The power supply lines to the AV_CCand V_DRIVEpins on the

AD7606/AD7606-6/AD7606-4 should use as large a trace as

possible to provide low impedance paths and reduce the effect

of glitches on the power supply lines. Where possible, use supply

planes and make good connections between the AD7606 supply

pins and the power tracks on the board. Use a single via or multiple

vias for each supply pin.

Good decoupling is also important to lower the supply impedance

presented to the AD7606/AD7606-6/AD7606-4 and to reduce

the magnitude of the supply spikes. The decoupling capacitors

should be placed close to (ideally, right up against) these pins

and their corresponding ground pins. Place the decoupling

capacitors for the REFIN/REFOUT pin and the REFCAPA and

REFCAPB pins as close as possible to their respective AD7606/

AD7606-6/AD7606-4 pins; and, where possible, they should be

placed on the same side of the board as the AD7606 device.

Figure 63. Bottom Layer Decoupling

Rev. D | Page 32 of 36

Data Sheet

AD7606/AD7606-6/AD7606-4

To ensure good device-to-device performance matching in

a system that contains multiple AD7606/AD7606-6/AD7606-4

devices, a symmetrical layout between the AD7606/AD7606-6/

AD7606-4 devices is important.

AVCC

Figure 64 shows a layout with two AD7606/AD7606-6/AD7606-4

devices. The AV_CCsupply plane runs to the right of both devices,

and the V_DRIVEsupply track runs to the left of the two devices.

The reference chip is positioned between the two devices, and

the reference voltage track runs north to Pin 42 of U1 and south

to Pin 42 of U2. A solid ground plane is used.

U2

These symmetrical layout principles can also be applied to a system

that contains more than two AD7606/AD7606-6/AD7606-4

devices. The AD7606/AD7606-6/AD7606-4 devices can be placed

in a north-south direction, with the reference voltage located

midway between the devices and the reference track running in

the north-south direction, similar to Figure 64.

U1

Figure 64. Layout for Multiple AD7606 Devices—Top Layer and

Supply Plane Layer

Rev. D | Page 33 of 36

AD7606/AD7606-6/AD7606-4

OUTLINE DIMENSIONS

Data Sheet

12.20

12.00 SQ

11.80

0.75

0.60

0.45

1.60

MAX

64

49

1

48

PIN 1

10.20

10.00 SQ

9.80

TOP VIEW

(PINS DOWN)

1.45

1.40

1.35

0.20

0.09

7°

3.5°

0°

0.08

COPLANARITY

16

33

0.15

0.05

SEATING

17

32

PLANE

VIEW A

0.27

0.22

0.17

0.50

BSC

LEAD PITCH

VIEW A

ROTATED 90° CCW

COMPLIANT TO JEDEC STANDARDS MS-026-BCD

Figure 65. 64-Lead Low Profile Quad Flat Package [LQFP]

(ST-64-2)

Dimensions shown in millimetres

ORDERING GUIDE

Model^{1, 2, 3}

AD7606BSTZ

AD7606BSTZ-RL

AD7606BSTZ-6

AD7606BSTZ-6RL

AD7606BSTZ-4

AD7606BSTZ-4RL

EVAL-AD7606SDZ

EVAL-AD7606-6SDZ

EVAL-AD7606-4SDZ

EVAL-SDP-CB1Z

Temperature Range

−40°C to +85°C

Package Description

Package Option

64-Lead Low Profile Quad Flat Package [LQFP]

Evaluation Board for the AD7606

Evaluation Board for the AD7606-6

Evaluation Board for the AD7606-4

Evaluation Controller Board

ST-64-2

¹Z = RoHS Compliant Part.

²The EVAL-AD7606SDZ, EVAL-AD7606-6SDZ, and EVAL-AD7606-4SDZ can be used as standalone evaluation boards or in conjunction with the EVAL-SDP-CB1Z for

evaluation/demonstration purposes.

³The EVAL-SDP-CB1Z allows the PC to control and communicate with all Analog Devices, Inc., evaluation boards ending in the SDZ designator.

Rev. D | Page 34 of 36

Data Sheet

NOTES

AD7606/AD7606-6/AD7606-4

Rev. D | Page 35 of 36

AD7606/AD7606-6/AD7606-4

NOTES

Data Sheet

registered trademarks are the property of their respective owners.

D08479-0-11/17(D)

Rev. D | Page 36 of 36


型号：	EVAL-AD7606-6SDZ
厂家：	ADI
描述：	8-/6-/4-Channel DAS with 16-Bit, Bipolar Input, Simultaneous Sampling ADC
文件：	总36页 (文件大小：955K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

EVAL-AD7606-6SDZ [ADI]

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