APW7062BKC-TUL [ANPEC]
Synchronous Buck PWM Controller; 同步降压PWM控制器
| 型号： | APW7062BKC-TUL |
| 厂家： | 
ANPEC ELECTRONICS COROPRATION |
| 描述： | Synchronous Buck PWM Controller |
| 文件： | 总18页 (文件大小：230K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
APW7062B
Synchronous Buck PWM Controller
Features
General Description
The APW7062B is a voltage mode, synchronous PWM
controller which drives dual N-Channel MOSFETs. It
integrates the control, monitoring and protection func-
tions into a single package, provides one controlled
power outputs with under-voltage and over-current
protection.
APW7062B provide excellent regulation for output load
variation. An internal 0.8V temperature-compensated
reference voltage is designed to meet the requirement
of low output voltage applications. It includes a 200kHz
free-running triangle-wave oscillator that is adjustable
from 70kHz to 800kHz.
The power-on-reset (POR) circuit monitors the VCC,
EN, OCSET input voltage to start-up or shutdown the
IC. The over-current protection (OCP) monitors the
output current by using the voltage drop across the
upper MOSFET’s RDS(ON), eliminating the need for a
current sensing resistor. The under-voltage protection
(UVP) monitors the voltage of FB pin for short-circuit
protection.
•
•
•
Simple Single-Loop Control Design
- Voltage-Mode PWM Control
Fast Transient Response
- Full 0–100% Duty Ratio
Excellent Output Voltage Regulation
- 0.8V Internal Reference
- ± 1% Over Line Voltage and Temperature
•
Over Current Fault Monitor
- Uses Upper MOSFETs RDS (ON)
Converter Can Source and Sink Current
Small Converter Size
•
•
- 200kHz Free-Running Oscillator
- Programmable from 70kHz to 800kHz
14-Lead SOIC Package
•
•
Lead Free Available (RoHS Compliant)
Applications
The over-current protection trip cycle the soft-start func-
tion until the fault events be removed. Under-voltage
protection will shutdown the IC directly.
•
•
•
•
Graphic Cards
DDR Memory Power Supply
DDR Memory Termination Voltage
Low-Voltage Distributed Power Supplies
Pinouts
RT
OCSET
SS
1
2
3
4
5
6
7
VCC
14
13
PVCC
12
11
10
9
LGATE
PGND
BOOT
COMP
FB
UGATE
PHASE
EN
8
GND
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise
customers to obtain the latest version of relevant information to verify before placing orders.
Copyright ANPEC Electronics Corp.
Rev. A.3 - Mar., 2005
1
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APW7062B
Ordering and Marking Information
P ackage C ode
APW 7062B
K : S O P -14
O perating Junction Tem p. R ange
C : 0 to 70°C
Lead Free C ode
H andling C ode
Tem p. R ange
P ackage C ode
H andling C ode
TU : Tube
TR : Tape & R eel
Lead Free C ode
L : Lead Free D evice
B lank : O riginal D evice
A P W 7062B
XXXXX
A P W 7062B K :
XXXXX - D ate C ode
Notes： ANPEC lead-free products contain molding compounds/die attach materials and 100% matte in plate
termination finish; which are fully compliant with RoHS and compatible with both SnPb and lead-free soldiering
operations. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J STD-020C for
MSL classification at lead-free peak reflow temperature.
Block Diagram
VCC
OCSET
GND
Power-On
Reset
EN
SS
OCSET
I
200uA
BOOT
vcc
SS
I
UGATE
10uA
O.C.P
Comparator
Soft Start
PHASE
5.8V
U.V.P
Comparator
:
2
R EF
50% V
PVCC
PW M
Comparator
Gate Control
LGATE
Error Amp
PGND
R EF
V
Oscillator
Triangle
W ave
COMP
FB
RT
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APW7062B
Application Cicuit
12V
C1
R1
10R
1uF
D1
1N4148
12V
L1
R3
1K
R2
10K
1uH
U1
C3
C6
C4
+
+
+
APW7062B
8
7
6
5
C5
470uF
16V
470uF
16V
100uF
16V
R4
1
2
3
4
5
6
7
14
13
12
11
10
9
4.7uF
RT
VCC
C2
1nF
4
30mR
30mR
NC
OCSET
SS
PV CC
LGATE
PGND
BOOT
COMP
FB
Q1
R5
2R2
APM4220
EN
UGA TE
PHA SE
8
1
2
3
GND
1.2V
C8
0.1uF
C7
L2
0.1uF
8
7
6
5
R10
15K
2.2uH
SHDN
R7
NC
C9
C10
+
+
C13
D2
1000uF
6.3V
30mR
1000uF
6.3V
C11
47pF
Q2
SR24
4.7uF
R6
0R
C12
4
APM4220
2A/40V
30mR
8200pF
1
2
3
R8
1KF
1%
C12
NC
R9
2KF
1%
R8
R9
OUT
REF
V
= V × 1+
Absolute Maximum Ratings
Symbol
Parameter
Rating
30
Unit
V
CC
V
VCC to GND
BOOT
V
BOOT to GND
PHASE to GND
30
V
PHASE
V
30
V
Operating Junction Temperature
Storage Temperature
0~150
-65 ~ 150
300
oC
oC
oC
KV
STG
T
SDR
T
Soldering Temperature (10 Seconds)
Minimum ESD Rating
ESD
V
±2
Copyright ANPEC Electronics Corp.
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APW7062B
Electrical Characteristics
APW7062B
Unit
Symbol
Parameter
Test Conditions
Min Typ Max
VCC SUPPLY CURRENT
CC
EN=V ; UGATE and LGATE
CC
I
Nominal Supply
2
mA
Open
Shutdown Supply
EN=0V
250 350
µA
POWER-ON-RESET
CC
OCSET
OCSET
DC
DC
Rising V Threshold
V
V
=4.5V
=4.5V
10.4
8.8
V
V
CC
Falling V Threshold
Enable-Input Threshold
OCSET
DC
V
=4.5V
0.8
2.0
V
V
Voltage
OCSET
Rising V
OSCILLATOR
Threshold
1.27
T
CC
Free Running Frequency
Total Variation
R =OPEN, V =12
170 200 230 kHz
-15
+15
6KΩ < RT to GND < 200KΩ
%
T
P-P
Ramp Amplitude
R =OPEN
1.9
V
OSC
∆V
REFERENCE VOLTAGE ACCURANCY
Reference Voltage Tolerance
-1
+1
REF
∆V
%
REF
V
PWM Error Amplifier
0.80
V
GATE DRIVERS
UGATE
BOOT
UGATE
I
Upper Gate Source
V
=12V, V
=6V
650 800
4
mA
Ω
UGATE
ILGATE=0.3A
PVCC=12V, VLGATE=6V
ILGATE=0.3A
R
Upper Gate Sink
Lower Gate Source
Lower Gate Sink
Dead Time
7
7
LGATE
700
4
mA
Ω
I
550
LGATE
R
D
VOUT=2.5V, IOUT=1A, RT=OPEN
50
ns
T
PROTECTION
FB Under Voltage
50
%
OCSET
OCSET
DC
I
OCSET Current Source
Soft-Start Current
V
=4.5V
170 200 230
10 12
µA
µA
SS
I
8
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APW7062B
Functional Pin Description
RT (Pin1)
SS (Pin3)
This pin can adjust the switching frequency. Connect
a resistor from RT to GND for increasing the switching
frequency:
Connect a capacitor from the pin to GND to set the
soft-start interval of the converter. An internal 10uA
current source charges this capacitor to 5.8V. The
SS voltage clamps the error amplifier output, and Fig-
ure1 shows the soft-start interval. At t1, the SS volt-
age reaches the valley of the oscillator’s triangle wave.
The PWM comparator starts to generate a PWM sig-
nal to control logic, and the output is rising rapidly.
Until the output is in regulation at t2, the clamp on the
COMP is released. This method provides a rapid and
controlled output voltage rise.
When over current protection occurs, the VOUT is
shutdown, and re-soft-start again, if the over current
condition still exists in soft-start , the VOUT is
shutdowned again, after the SS reaches 4.5V, the SS
is discharged to zero. The soft-start is recurring until
the over current condition is eliminated.
4.15×106
FS = 200kHz +
RT
(RT to GND,F
S =
200kHz to 400kHz)
Conversely, connect a resistor from RT to VCC for de-
creasing the switching frequency:
3.51×107
FS = 200kHz -
RT
(RT to VCC,FS = 200kHz to 75kHz)
OCSET (Pin2)
This pin serves two functions: a shutdown control and
the setting of over current limit threshold. Pulling this
pin below 1.27V will shutdown the controller, forcing
the UGATE and LGATE signals to be at 0V.
A resistor (Rocset) connected between this pin and the
drain of the high side MOSFET will determine the over
current limit. An internal 200uA current source will
flow through this resistor, creating a voltage drop,
which will be compared with the voltage across the
high side MOSFET. The threshold of the over current
limit is therefore given by:
VOLTAGE
VSOFT START
VOUT
Error Am p
Output
VOSC(MIN)
VSS=1.2V
OCSET
(
)
×
OCSET
I
200uA
R
PEAK =
I
DS(ON)
R
TIME
t0
t1
t2
t3
To avoid noise interference from switching transient, a
delay time is designed in the OCP comparator.
The over current protection is active only when the
high side MOSFET is turned on longer than 300ns.
FIGURE1. SOFT-START INTERVAL
C
I
SS
=
SS ×(VOSC(MIN)+t1)
t2
VOUT
CSS
SS
I
SoftStart
=
3
t
−
2
t
=
×
SteadyState×∆ OSC
t
V
IN
V
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APW7062B
Functional Pin Description (Cont.)
Where :
LGATE pins are held low. The EN pin is the open-
collector, it will not be floating.
t1=1.2V
CSS = Soft Start Capacitor
GND (Pin7)
ISS = Soft Start Current = 10µA
VOSC(MIN) = Bottom of Oscillator = 1.35V
VIN = Input Voltage
∆Vosc = Peak to Peak Oscillator Voltage = 1.9V
∆VOUTSteadyState = Steady State Output Voltage
Signal ground for the IC.
PHASE (Pin8)
This pin is connected to the source of the high-side
MOSFETandisusedtomonitorthevoltagedropacross
the high-side MOSFET for over-current protection.
COMP (Pin4)
This pin is the output of the error amplifier. Add an
external resistor and capacitor network to provide the
loop compensation for the PWM converter (see Appli-
cation Information).
UGATE (Pin9)
Connect the pin to external MOSFET, and provides
the gate drive for the upper MOSFET.
FB (Pin5)
BOOT (Pin 10)
FB pin is the inverter input of the error amplifier. and it
receives the feedback voltage from an external resis-
This pin provides the supply voltage to the high side
MOSFET driver. For driving logic level N-channel
MOSEFT, a bootstrap circuit can be used to create a
suitable driver’s supply.
tive divider across the output (VOUT). The output volt-
age is determined by:
OUT
R
PGND (Pin11)
OUT =
V
×
+
0.8V
1
GND
R
Power ground for the gate diver. Connect the lower
MOSFET source to this pin.
where ROUT is the resistor connected from VOUT to FB
and RGND is the resistor connected from FB to GND.
LGATE (Pin 12)
Connect the pin to external MOSFET, and provides
the gate drive signal for the lower MOSFET.
If the FB voltage is under 50% VREF, because of the
short circuit or other influence , it will cause the under
voltage protection, and the device is shutdowned. Re-
move the error condition and restart the VCC voltage
or pull the EN from low to high once, the device can
be enabled again.
PVCC (Pin13)
This pin provides a supply voltage for the lower gate
drive, connect it to VCC pin in common use.
VCC (Pin14)
EN (Pin6)
This pin provides a supply voltage for the device, when
VCC is above the rising threshold 10.4V, the device is
turned on, conversely, VCC is below the falling
threshold, the device is turned off.
Pull the pin higher than 2V to enable the device, and
pull the pin lower than 0.8V to shutdown the device. In
shutdown, the SS is discharged and the UGATE and
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APW7062B
Typical Characteristics
Power Up
Power Down
VCC=12V, VIN=12V
VOUT=2.5V, L=2.2uH
VCC=12V, VIN=12V
VOUT=2.5V, L=2.2uH
VCC(5V/div)
SS(2V/div)
VCC(5V/div)
SS(2V/div)
VOUT(1V/div)
VOUT(1V/div)
Time(10ms/div)
Time(10ms/div)
Enable (EN = VCC)
Shutdown (EN=GND)
VCC=12V, VIN=12V
VOUT=2.5V, L=2.2uH
EN(10V/div)
SS(2V/div)
EN(10V/div)
VCC=12V, VIN=12V
VOUT=2.5V, L=2.2uH
SS(2V/div)
VOUT(1V/div)
VOUT(1V/div)
Time(10ms/div)
Time(2ms/div)
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APW7062B
Typical Characteristics (Cont.)
Load Transient Response
Under Voltage Protection
VCC=12V, VIN=12V
VCC=12V, VIN=12V
VOUT(100mV/div)
VOUT=2.5V, RT=Open
VOUT=2.5V, L=2.2uH
L=2.2uH
VOUT(2V/div)
SS(5V/div)
IL(10A/div)
IOUT(2A/div)
UGATE(20V/div)
Time(20us/div)
Time(20us/div)
UGATE Falling
UGATE Rising
VCC=12V, VIN=12V
VOUT=2.5V, RT=Open
VCC=12V, VIN=12V
VOUT=2.5V, RT=Open
UGATE(10V/div)
UGATE(10V/div)
LGATE(10V/div)
Phase(10V/div)
LGATE(10V/div)
Phase(10V/div)
Time(50ns/div)
Time(50ns/div)
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APW7062B
Typical Characteristics (Cont.)
UGATE Source Current vs. UGATE Voltage
UGATE Sink Current vs. UGATE Voltage
1.2
1.4
VBOOT=12V
VBOOT=12V
1.2
1
1
0.8
0.6
0.4
0.2
0
0.8
0.6
0.4
0.2
0
0
2
4
6
8
10
12
0
2
4
6
8
10
12
UGATE Voltage (V)
UGATE Voltage (V)
LGATE Source Current vs. LGATE Voltage
LGATE Sink Current vs. LGATE Voltage
1.2
1
1.4
PVCC=12V
PVCC=12V
1.2
1
0.8
0.6
0.4
0.2
0
0.8
0.6
0.4
0.2
0
0
2
4
6
8
10
12
0
2
4
6
8
10
12
LGATE Voltage (V)
LGATE Voltage (V)
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APW7062B
Typical Characteristics (Cont.)
Over Current Protection
RT Resistance vs. Switching Frequency
VCC=12V, VIN=12V, VOUT=2.5V,
ROCEST=1KΩ, RT=Open, RDS(ON)=14mΩ,
IOUT=16.3A, L=2.2uH, LOUT=16.3A
10000
1000
100
10
VOUT(1V/div)
RT pull up to 12V
SS(5V/div)
IL(10A/div)
RT pull down to GND
UGATE(20V/div)
1
10
100
1000
Switching Frequency (kHz)
Time(20ms/div)
Switching Frequency vs. Junction Temperature
Reference Voltage vs. Junction Temperature
0.8
220
VCC=12V
RT=Open
210
0.798
0.796
0.794
0.792
0.79
200
190
180
170
160
-40 -20
0
20 40 60 80 100 120
-40 -20
0
20 40 60 80 100 120
Junction Temperature (°C)
Junction Temperature (°C)
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APW7062B
Application Information
∆VOUT = IRIPPLE x ESR
Component Selection Guidelines
where Fs is the switching frequency of the regulator.
Output Capacitor Selection
The selection of COUT is determined by the required
effective series resistance (ESR) and voltage rating
rather than the actual capacitance requirement. There-
fore select high performance low ESR capacitors that
are intended for switching regulator applications. In
some applications, multiple capacitors have to be
paralled to achieve the desired ESR value. If tantalum
capacitors are used, make sure they are surge tested
by the manufactures. If in doubt, consult the capaci-
tors manufacturer.
There is a tradeoff exists between the inductor’s ripple
current and the regulator load transient response time
A smaller inductor will give the regulator a faster load
transient response at the expense of higher ripple cur-
rent and vice versa. The maximum ripple current oc-
curs at the maximum input voltage. A good starting
point is to choose the ripple current to be approxi-
mately 30% of the maximum output current.
Once the inductance value has been chosen, select
an inductor that is capable of carrying the required
peak current without going into saturation. In some
type of inductors, especially core that is make of
ferrite, the ripple current will increase abruptly when it
saturates. This will result in a larger output ripple
voltage.
Input Capacitor Selection
The input capacitor is chosen based on the voltage
rating and the RMS current rating. For reliable
operation, select the capacitor voltage rating to be at
least 1.3 times higher than the maximum input voltage.
The maximum RMS current rating requirement is ap-
proximately IOUT/2 , where IOUT is the load current.
During power up, the input capacitors have to handle
large amount of surge current. If tantalum capacitors
are used, make sure they are surge tested by the
manufactures. If in doubt, consult the capacitors
manufacturer.
Compensation
The output LC filter introduces a double pole, which
contributes with –40dB/decade gain slope and 180
degrees phase shift in the control loop. A compensa-
tion network between COMP pin and ground should
be added. The simplest loop compensation network
is shown in Fig. 4.
For high frequency decoupling, a ceramic capacitor
between 0.1uF to 1uF can be connected between VCC
and ground pin.
The output LC filter consists of the output inductor
and output capacitors. The transfer function of the LC
filter is given by:
Inductor Selection
The inductance of the inductor is determined by the
output voltage requirement. The larger the inductance,
the lower the inductor’s current ripple. This will trans-
late into lower output ripple voltage. The ripple current
and ripple voltage can be approximated by:
1+ s×ESR×COUT
GAINLC
=
2
OUT
s ×L ×C + s×ESR +1
VIN - VOUT VOUT
x
IRIPPLE
=
VIN
Fs x L
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APW7062B
Application Information (Cont.)
Compensation (Cont.)
The poles and zero of this transfer function are:
IN
V
V
GAINPWM =
PWM
∆
OSC
IN
V
1
FLC
=
2× π ×
2 × π ×
×
OUT
L C
Driver
1
Comparator
FESR
=
×
OUT
ESR C
OSC
V
The FLC is the double poles of the LC filter, and FESR is
the zero introduced by the ESR of the output capacitor.
Output of
Error
PHASE
Amplifier
L
Output
PHASE
Driver
Figure 3. The PWM Modulator
OUT
C
ESR
The compensation circuit is shown in Figure 4. R3
and C1 introduce a zero and C2 introduces a pole to
reduce the switching noise. The transfer function of
error amplifier is given by:
Figure 1. The Output LC Filter
LC
F
1
sC1
1
sC2
-40dB/dec
gm × R3 +
//
GAINAMP = gm× Zo =
ESR
F
Gain
(
R3sC1+1
C1+ C2
R3×C1× C2
)
gm×
=
s× s +
-20dB/dec
The poles and zero of the compensation network are:
1
Frequency
FP =
C1×C2
Figure 2. The Output LC Filter Gain & Frequency
2× π ×R3×
C1+ C2
1
The PWM modulator is shown in Figure. 3. The input
is the output of the error amplifier and the output is the
PHASE node. The transfer function of the PWM modu-
lator is given by:
FZ
=
2× π ×R3× C1
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APW7062B
Application Information (Cont.)
Compensation (Cont.)
Calculate the C2 by the equation:
C1
VOUT
C2 =
S
π × R3 × C1 × F − 1
Error
R1
Amplifier
FB
Z
LC
F =0.75F
-
COMP
P
S
F =0.5F
20 log(gm R3)
R2
+
R3
C1
Compensation
Gain
VREF
C2
LC
O
F
F
VIN
20 log
Figure 4. Compensation Network
ΔVOSC
Converter
Gain
ESR
F
PWM &
The closed loop gain of the converter can be written
as:
Filter Gain
R2
R1+ R2
Frequency
Figure 5. Converter Gain & Frequency
x GAINAMP
GAINLC x GAINPWM x
Figure 5 shows the converter gain and the following
guidelines will help to design the compensation
network.
1.Select the desired zero crossover frequency FO:
(1/5 ~ 1/10) x FS >FO>FZ
MOSFET Selection
The selection of the N-channel power MOSFETs are
determined by the RDS(ON), reverse transfer capacitance
(CRSS) and maximum output current requirement.The
losses in the MOSFETs have two components: con-
duction loss and transition loss. For the upper and
lower MOSFET, the losses are approximately given
by the following :
Use the following equation to calculate R3:
OSC
IN
ESR
O
∆V
V
F
R1+ R2
F
R3 =
×
×
×
LC 2
R2
gm
F
Where:
P
UPPER = Iou2t (1+ TC)(RDS(ON))D + (0.5)(Iout)(VIN)(tsw)FS
gm=900uA/V
2.Place the zero FZ before the LC filter double poles
FLC:
PLOWER = Iout2(1+ TC)(RDS(ON))(1-D)
FZ = 0.75 x FLC
Calculate the C1 by the equation:
where IOUT is the load current
TC is the temperature dependency of RDS(ON)
FS is the switching frequency
tsw is the switching interval
10
=
C1
× π ×
× LC
2
R1 F
D is the duty cycle
3. Set the pole at the half the switching frequency:
FP = 0.5xFS
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APW7062B
Application Information (Cont.)
Note that both MOSFETs have conduction losses while
the upper MOSFET include an additional transition
loss.The switching internal, tsw, is a function of the
reverse transfer capacitance CRSS. Figure 3 illustrates
the switching waveform internal of the MOSFET.
The (1+TC) term is to factor in the temperature depen-
dency of the RDS(ON) and can be extracted from the
“RDS(ON) vs Temperature” curve of the power MOSFET.
single point grounding. Figure 4 illustrates the layout,
with bold lines indicating high current paths. Compo-
nents along the bold lines should be placed close
together. Below is a checklist for your layout:
• Keep the switching nodes (UGATE, LGATE and
PHASE) away from sensitive small signal nodes
since these nodes are fast moving signals. There
fore keep traces to these nodes as short as
possible.
Layout Considerations
• The ground return of CIN must return to the combine
In high power switching regulator, a correct layout is
important to ensure proper operation of the regulator.
In general, interconnecting impedances should be mini-
mized by using short, wide printed circuit traces. Sig-
nal and power grounds are to be kept separate and
finally combined using ground plane construction or
COUT (-) terminal.
• Capacitor CBOOT should be connected as close to
the BOOT and PHASE pins as possible.
V DS
VIN
C IN
APW 7062B
+
11
P GND
12
L
O
A
D
LG ATE
C OU T
9
8
UGATE
P HAS E
Q1
Q2
+
L1
t
VOU T
Time
sw
Figure 4. Recomm ended Layout Diagram
Figure 3. Switching waveform across MOSFET
Copyright ANPEC Electronics Corp.
Rev. A.3 - Mar., 2005
14
www.anpec.com.tw
APW7062B
Package Information
SOP – 14 (150mil)
A
D
Ee
B
L
Millimeters
Inches
Dim
Min.
1.477
0.102
0.331
0.191
8.558
3.82
Max.
1.732
0.255
0.509
Min.
Max.
0.068
0.010
0.020
0.0098
0.344
0.157
A
A1
B
0.058
0.004
0.013
C
D
E
0.2496
8.762
3.999
0.0075
0.336
0.150
e
1.274
0.050
H
L
5.808
0.382
6.215
1.274
0.228
0.015
0.244
0.050
°
0
8
0
8
θ
°
°
°
°
Copyright ANPEC Electronics Corp.
Rev. A.3 - Mar., 2005
15
www.anpec.com.tw
APW7062B
Physical Specifications
Terminal Material
Lead Solderability
Packaging
Solder-Plated Copper (Solder Material : 90/10 or 63/37 SnPb
Meets EIA Specification RSI86-91, ANSI/J-STD-002 Category 3.
2500 devices per reel
Reflow Condition (IR/Convection or VPR Reflow)
tp
TP
Critical Zone
TL to TP
Ramp-up
TL
tL
Tsmax
Tsmin
Ramp-down
ts
Preheat
25
°
t 25 C to Peak
Time
Classificatin Reflow Profiles
Profile Feature
Sn-Pb Eutectic Assembly
Pb-Free Assembly
Average ramp-up rate
3°C/second max.
3°C/second max.
(TL to TP)
Preheat
100°C
150°C
150°C
200°C
- Temperature Min (Tsmin)
- Temperature Max (Tsmax)
- Time (min to max) (ts)
Time maintained above:
- Temperature (TL)
60-120 seconds
60-180 seconds
183°C
217°C
60-150 seconds
60-150 seconds
- Time (tL)
Peak/Classificatioon Temperature (Tp)
See table 1
See table 2
Time within 5°C of actual
10-30 seconds
20-40 seconds
Peak Temperature (tp)
Ramp-down Rate
6°C/second max.
6°C/second max.
6 minutes max.
8 minutes max.
Time 25°C to Peak Temperature
Notes: All temperatures refer to topside of the package .Measured on the body surface.
Copyright ANPEC Electronics Corp.
Rev. A.3 - Mar., 2005
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APW7062B
Classificatin Reflow Profiles(Cont.)
Table 1. SnPb Entectic Process – Package Peak Reflow Temperatures
Package Thickness
Volume mm3
<350
Volume mm3
≥350
<2.5 mm
≥2.5 mm
240 +0/-5°C
225 +0/-5°C
225 +0/-5°C
225 +0/-5°C
Table 2. Pb-free Process – Package Classification Reflow Temperatures
Package Thickness
Volume mm3
<350
Volume mm3
350-2000
Volume mm3
>2000
<1.6 mm
1.6 mm – 2.5 mm
≥2.5 mm
260 +0°C*
260 +0°C*
250 +0°C*
260 +0°C*
250 +0°C*
245 +0°C*
260 +0°C*
245 +0°C*
245 +0°C*
*Tolerance: The device manufacturer/supplier shall assure process compatibility up to and
including the stated classification temperature (this means Peak reflow temperature +0°C.
For example 260°C+0°C) at the rated MSL level.
Reliability Test Program
Test item
SOLDERABILITY
Method
MIL-STD-883D-2003
MIL-STD-883D-1005.7
JESD-22-B,A102
MIL-STD-883D-1011.9
MIL-STD-883D-3015.7
JESD 78
Description
245°C, 5 SEC
1000 Hrs Bias @125°C
168 Hrs, 100%RH, 121°C
-65°C~150°C, 200 Cycles
VHBM > 2KV, VMM > 200V
10ms, 1tr > 100mA
HOLT
PCT
TST
ESD
Latch-Up
Carrier Tape & Reel Dimension
t
D
P
Po
E
P1
F
W
Ao
D1
Ko
Copyright ANPEC Electronics Corp.
Rev. A.3 - Mar., 2005
17
www.anpec.com.tw
APW7062B
Carrier Tape & Reel Dimension
T2
J
C
A
B
T1
A
B
C
J
T1
T2
W
P
8
t
E
Application
13.0 + 0.5
16.0 ± 0.3
330REF 100REF
2 ± 0.5 16.5REF 2.5 ± 025
1.75
- 0.2
SOP-14
(150mil)
F
D
D1
Po
P1
Ao
Ko
0.50 +
1.50
φ
φ
7.5
4.0
2.0
6.5
2.10
0.3 0.05
±
0.1
(MIN)
(mm)
Cover Tape Dimensions
Application
SOP- 14
Carrier Width
Cover Tape Width
Devices Per Reel
24
21.3
2500
Customer Service
Anpec Electronics Corp.
Head Office :
5F, No. 2 Li-Hsin Road, SBIP,
Hsin-Chu, Taiwan, R.O.C.
Tel : 886-3-5642000
Fax : 886-3-5642050
Taipei Branch :
7F, No. 137, Lane 235, Pac Chiao Rd.,
Hsin Tien City, Taipei Hsien, Taiwan, R. O. C.
Tel : 886-2-89191368
Fax : 886-2-89191369
Copyright ANPEC Electronics Corp.
Rev. A.3 - Mar., 2005
18
www.anpec.com.tw
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